qemu-char: append opt to stop truncation of serial file
[qemu/ar7.git] / hw / arm / virt.c
blobacc1fcbdd19195ed76681ee82b6cc8786bba9a52
1 /*
2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "hw/sysbus.h"
32 #include "hw/arm/arm.h"
33 #include "hw/arm/primecell.h"
34 #include "hw/arm/virt.h"
35 #include "hw/devices.h"
36 #include "net/net.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/device_tree.h"
39 #include "sysemu/sysemu.h"
40 #include "sysemu/kvm.h"
41 #include "hw/boards.h"
42 #include "hw/loader.h"
43 #include "exec/address-spaces.h"
44 #include "qemu/bitops.h"
45 #include "qemu/error-report.h"
46 #include "hw/pci-host/gpex.h"
47 #include "hw/arm/virt-acpi-build.h"
48 #include "hw/arm/sysbus-fdt.h"
49 #include "hw/platform-bus.h"
50 #include "hw/arm/fdt.h"
51 #include "hw/intc/arm_gic_common.h"
52 #include "kvm_arm.h"
53 #include "hw/smbios/smbios.h"
54 #include "qapi/visitor.h"
55 #include "standard-headers/linux/input.h"
57 /* Number of external interrupt lines to configure the GIC with */
58 #define NUM_IRQS 256
60 #define PLATFORM_BUS_NUM_IRQS 64
62 static ARMPlatformBusSystemParams platform_bus_params;
64 typedef struct VirtBoardInfo {
65 struct arm_boot_info bootinfo;
66 const char *cpu_model;
67 const MemMapEntry *memmap;
68 const int *irqmap;
69 int smp_cpus;
70 void *fdt;
71 int fdt_size;
72 uint32_t clock_phandle;
73 uint32_t gic_phandle;
74 uint32_t v2m_phandle;
75 } VirtBoardInfo;
77 typedef struct {
78 MachineClass parent;
79 VirtBoardInfo *daughterboard;
80 } VirtMachineClass;
82 typedef struct {
83 MachineState parent;
84 bool secure;
85 bool highmem;
86 int32_t gic_version;
87 } VirtMachineState;
89 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
90 #define VIRT_MACHINE(obj) \
91 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
92 #define VIRT_MACHINE_GET_CLASS(obj) \
93 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
94 #define VIRT_MACHINE_CLASS(klass) \
95 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
97 /* Addresses and sizes of our components.
98 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
99 * 128MB..256MB is used for miscellaneous device I/O.
100 * 256MB..1GB is reserved for possible future PCI support (ie where the
101 * PCI memory window will go if we add a PCI host controller).
102 * 1GB and up is RAM (which may happily spill over into the
103 * high memory region beyond 4GB).
104 * This represents a compromise between how much RAM can be given to
105 * a 32 bit VM and leaving space for expansion and in particular for PCI.
106 * Note that devices should generally be placed at multiples of 0x10000,
107 * to accommodate guests using 64K pages.
109 static const MemMapEntry a15memmap[] = {
110 /* Space up to 0x8000000 is reserved for a boot ROM */
111 [VIRT_FLASH] = { 0, 0x08000000 },
112 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
113 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
114 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
115 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
116 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
117 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
118 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
119 /* This redistributor space allows up to 2*64kB*123 CPUs */
120 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
121 [VIRT_UART] = { 0x09000000, 0x00001000 },
122 [VIRT_RTC] = { 0x09010000, 0x00001000 },
123 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
124 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
125 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
126 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
127 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
128 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
129 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
130 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
131 [VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
132 /* Second PCIe window, 512GB wide at the 512GB boundary */
133 [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL },
136 static const int a15irqmap[] = {
137 [VIRT_UART] = 1,
138 [VIRT_RTC] = 2,
139 [VIRT_PCIE] = 3, /* ... to 6 */
140 [VIRT_GPIO] = 7,
141 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
142 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
143 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
146 static VirtBoardInfo machines[] = {
148 .cpu_model = "cortex-a15",
149 .memmap = a15memmap,
150 .irqmap = a15irqmap,
153 .cpu_model = "cortex-a53",
154 .memmap = a15memmap,
155 .irqmap = a15irqmap,
158 .cpu_model = "cortex-a57",
159 .memmap = a15memmap,
160 .irqmap = a15irqmap,
163 .cpu_model = "host",
164 .memmap = a15memmap,
165 .irqmap = a15irqmap,
169 static VirtBoardInfo *find_machine_info(const char *cpu)
171 int i;
173 for (i = 0; i < ARRAY_SIZE(machines); i++) {
174 if (strcmp(cpu, machines[i].cpu_model) == 0) {
175 return &machines[i];
178 return NULL;
181 static void create_fdt(VirtBoardInfo *vbi)
183 void *fdt = create_device_tree(&vbi->fdt_size);
185 if (!fdt) {
186 error_report("create_device_tree() failed");
187 exit(1);
190 vbi->fdt = fdt;
192 /* Header */
193 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
194 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
195 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
198 * /chosen and /memory nodes must exist for load_dtb
199 * to fill in necessary properties later
201 qemu_fdt_add_subnode(fdt, "/chosen");
202 qemu_fdt_add_subnode(fdt, "/memory");
203 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
205 /* Clock node, for the benefit of the UART. The kernel device tree
206 * binding documentation claims the PL011 node clock properties are
207 * optional but in practice if you omit them the kernel refuses to
208 * probe for the device.
210 vbi->clock_phandle = qemu_fdt_alloc_phandle(fdt);
211 qemu_fdt_add_subnode(fdt, "/apb-pclk");
212 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
213 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
214 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
215 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
216 "clk24mhz");
217 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle);
221 static void fdt_add_psci_node(const VirtBoardInfo *vbi)
223 uint32_t cpu_suspend_fn;
224 uint32_t cpu_off_fn;
225 uint32_t cpu_on_fn;
226 uint32_t migrate_fn;
227 void *fdt = vbi->fdt;
228 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
230 qemu_fdt_add_subnode(fdt, "/psci");
231 if (armcpu->psci_version == 2) {
232 const char comp[] = "arm,psci-0.2\0arm,psci";
233 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
235 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;
236 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) {
237 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND;
238 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON;
239 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE;
240 } else {
241 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND;
242 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON;
243 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE;
245 } else {
246 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci");
248 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND;
249 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF;
250 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON;
251 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE;
254 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
255 * to the instruction that should be used to invoke PSCI functions.
256 * However, the device tree binding uses 'method' instead, so that is
257 * what we should use here.
259 qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc");
261 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn);
262 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn);
263 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn);
264 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn);
267 static void fdt_add_timer_nodes(const VirtBoardInfo *vbi, int gictype)
269 /* Note that on A15 h/w these interrupts are level-triggered,
270 * but for the GIC implementation provided by both QEMU and KVM
271 * they are edge-triggered.
273 ARMCPU *armcpu;
274 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
276 if (gictype == 2) {
277 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
278 GIC_FDT_IRQ_PPI_CPU_WIDTH,
279 (1 << vbi->smp_cpus) - 1);
282 qemu_fdt_add_subnode(vbi->fdt, "/timer");
284 armcpu = ARM_CPU(qemu_get_cpu(0));
285 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
286 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
287 qemu_fdt_setprop(vbi->fdt, "/timer", "compatible",
288 compat, sizeof(compat));
289 } else {
290 qemu_fdt_setprop_string(vbi->fdt, "/timer", "compatible",
291 "arm,armv7-timer");
293 qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts",
294 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
295 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
296 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
297 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
300 static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
302 int cpu;
303 int addr_cells = 1;
306 * From Documentation/devicetree/bindings/arm/cpus.txt
307 * On ARM v8 64-bit systems value should be set to 2,
308 * that corresponds to the MPIDR_EL1 register size.
309 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
310 * in the system, #address-cells can be set to 1, since
311 * MPIDR_EL1[63:32] bits are not used for CPUs
312 * identification.
314 * Here we actually don't know whether our system is 32- or 64-bit one.
315 * The simplest way to go is to examine affinity IDs of all our CPUs. If
316 * at least one of them has Aff3 populated, we set #address-cells to 2.
318 for (cpu = 0; cpu < vbi->smp_cpus; cpu++) {
319 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
321 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
322 addr_cells = 2;
323 break;
327 qemu_fdt_add_subnode(vbi->fdt, "/cpus");
328 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", addr_cells);
329 qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0);
331 for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) {
332 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
333 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
335 qemu_fdt_add_subnode(vbi->fdt, nodename);
336 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "cpu");
337 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible",
338 armcpu->dtb_compatible);
340 if (vbi->smp_cpus > 1) {
341 qemu_fdt_setprop_string(vbi->fdt, nodename,
342 "enable-method", "psci");
345 if (addr_cells == 2) {
346 qemu_fdt_setprop_u64(vbi->fdt, nodename, "reg",
347 armcpu->mp_affinity);
348 } else {
349 qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg",
350 armcpu->mp_affinity);
353 g_free(nodename);
357 static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi)
359 vbi->v2m_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
360 qemu_fdt_add_subnode(vbi->fdt, "/intc/v2m");
361 qemu_fdt_setprop_string(vbi->fdt, "/intc/v2m", "compatible",
362 "arm,gic-v2m-frame");
363 qemu_fdt_setprop(vbi->fdt, "/intc/v2m", "msi-controller", NULL, 0);
364 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/v2m", "reg",
365 2, vbi->memmap[VIRT_GIC_V2M].base,
366 2, vbi->memmap[VIRT_GIC_V2M].size);
367 qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->v2m_phandle);
370 static void fdt_add_gic_node(VirtBoardInfo *vbi, int type)
372 vbi->gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
373 qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", vbi->gic_phandle);
375 qemu_fdt_add_subnode(vbi->fdt, "/intc");
376 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3);
377 qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0);
378 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2);
379 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2);
380 qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0);
381 if (type == 3) {
382 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible",
383 "arm,gic-v3");
384 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg",
385 2, vbi->memmap[VIRT_GIC_DIST].base,
386 2, vbi->memmap[VIRT_GIC_DIST].size,
387 2, vbi->memmap[VIRT_GIC_REDIST].base,
388 2, vbi->memmap[VIRT_GIC_REDIST].size);
389 } else {
390 /* 'cortex-a15-gic' means 'GIC v2' */
391 qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible",
392 "arm,cortex-a15-gic");
393 qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg",
394 2, vbi->memmap[VIRT_GIC_DIST].base,
395 2, vbi->memmap[VIRT_GIC_DIST].size,
396 2, vbi->memmap[VIRT_GIC_CPU].base,
397 2, vbi->memmap[VIRT_GIC_CPU].size);
400 qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle);
403 static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic)
405 int i;
406 int irq = vbi->irqmap[VIRT_GIC_V2M];
407 DeviceState *dev;
409 dev = qdev_create(NULL, "arm-gicv2m");
410 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_V2M].base);
411 qdev_prop_set_uint32(dev, "base-spi", irq);
412 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
413 qdev_init_nofail(dev);
415 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
416 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
419 fdt_add_v2m_gic_node(vbi);
422 static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, int type, bool secure)
424 /* We create a standalone GIC */
425 DeviceState *gicdev;
426 SysBusDevice *gicbusdev;
427 const char *gictype;
428 int i;
430 gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
432 gicdev = qdev_create(NULL, gictype);
433 qdev_prop_set_uint32(gicdev, "revision", type);
434 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
435 /* Note that the num-irq property counts both internal and external
436 * interrupts; there are always 32 of the former (mandated by GIC spec).
438 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
439 if (!kvm_irqchip_in_kernel()) {
440 qdev_prop_set_bit(gicdev, "has-security-extensions", secure);
442 qdev_init_nofail(gicdev);
443 gicbusdev = SYS_BUS_DEVICE(gicdev);
444 sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base);
445 if (type == 3) {
446 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_REDIST].base);
447 } else {
448 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base);
451 /* Wire the outputs from each CPU's generic timer to the
452 * appropriate GIC PPI inputs, and the GIC's IRQ output to
453 * the CPU's IRQ input.
455 for (i = 0; i < smp_cpus; i++) {
456 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
457 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
458 int irq;
459 /* Mapping from the output timer irq lines from the CPU to the
460 * GIC PPI inputs we use for the virt board.
462 const int timer_irq[] = {
463 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
464 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
465 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
466 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
469 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
470 qdev_connect_gpio_out(cpudev, irq,
471 qdev_get_gpio_in(gicdev,
472 ppibase + timer_irq[irq]));
475 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
476 sysbus_connect_irq(gicbusdev, i + smp_cpus,
477 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
480 for (i = 0; i < NUM_IRQS; i++) {
481 pic[i] = qdev_get_gpio_in(gicdev, i);
484 fdt_add_gic_node(vbi, type);
486 if (type == 2) {
487 create_v2m(vbi, pic);
491 static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic)
493 char *nodename;
494 hwaddr base = vbi->memmap[VIRT_UART].base;
495 hwaddr size = vbi->memmap[VIRT_UART].size;
496 int irq = vbi->irqmap[VIRT_UART];
497 const char compat[] = "arm,pl011\0arm,primecell";
498 const char clocknames[] = "uartclk\0apb_pclk";
500 sysbus_create_simple("pl011", base, pic[irq]);
502 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
503 qemu_fdt_add_subnode(vbi->fdt, nodename);
504 /* Note that we can't use setprop_string because of the embedded NUL */
505 qemu_fdt_setprop(vbi->fdt, nodename, "compatible",
506 compat, sizeof(compat));
507 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
508 2, base, 2, size);
509 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts",
510 GIC_FDT_IRQ_TYPE_SPI, irq,
511 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
512 qemu_fdt_setprop_cells(vbi->fdt, nodename, "clocks",
513 vbi->clock_phandle, vbi->clock_phandle);
514 qemu_fdt_setprop(vbi->fdt, nodename, "clock-names",
515 clocknames, sizeof(clocknames));
517 qemu_fdt_setprop_string(vbi->fdt, "/chosen", "stdout-path", nodename);
518 g_free(nodename);
521 static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic)
523 char *nodename;
524 hwaddr base = vbi->memmap[VIRT_RTC].base;
525 hwaddr size = vbi->memmap[VIRT_RTC].size;
526 int irq = vbi->irqmap[VIRT_RTC];
527 const char compat[] = "arm,pl031\0arm,primecell";
529 sysbus_create_simple("pl031", base, pic[irq]);
531 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
532 qemu_fdt_add_subnode(vbi->fdt, nodename);
533 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat));
534 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
535 2, base, 2, size);
536 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts",
537 GIC_FDT_IRQ_TYPE_SPI, irq,
538 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
539 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle);
540 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk");
541 g_free(nodename);
544 static DeviceState *pl061_dev;
545 static void virt_powerdown_req(Notifier *n, void *opaque)
547 /* use gpio Pin 3 for power button event */
548 qemu_set_irq(qdev_get_gpio_in(pl061_dev, 3), 1);
551 static Notifier virt_system_powerdown_notifier = {
552 .notify = virt_powerdown_req
555 static void create_gpio(const VirtBoardInfo *vbi, qemu_irq *pic)
557 char *nodename;
558 hwaddr base = vbi->memmap[VIRT_GPIO].base;
559 hwaddr size = vbi->memmap[VIRT_GPIO].size;
560 int irq = vbi->irqmap[VIRT_GPIO];
561 const char compat[] = "arm,pl061\0arm,primecell";
563 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
565 uint32_t phandle = qemu_fdt_alloc_phandle(vbi->fdt);
566 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
567 qemu_fdt_add_subnode(vbi->fdt, nodename);
568 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
569 2, base, 2, size);
570 qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat));
571 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#gpio-cells", 2);
572 qemu_fdt_setprop(vbi->fdt, nodename, "gpio-controller", NULL, 0);
573 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts",
574 GIC_FDT_IRQ_TYPE_SPI, irq,
575 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
576 qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle);
577 qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk");
578 qemu_fdt_setprop_cell(vbi->fdt, nodename, "phandle", phandle);
580 qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys");
581 qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys", "compatible", "gpio-keys");
582 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#size-cells", 0);
583 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#address-cells", 1);
585 qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys/poweroff");
586 qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys/poweroff",
587 "label", "GPIO Key Poweroff");
588 qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys/poweroff", "linux,code",
589 KEY_POWER);
590 qemu_fdt_setprop_cells(vbi->fdt, "/gpio-keys/poweroff",
591 "gpios", phandle, 3, 0);
593 /* connect powerdown request */
594 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
596 g_free(nodename);
599 static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic)
601 int i;
602 hwaddr size = vbi->memmap[VIRT_MMIO].size;
604 /* We create the transports in forwards order. Since qbus_realize()
605 * prepends (not appends) new child buses, the incrementing loop below will
606 * create a list of virtio-mmio buses with decreasing base addresses.
608 * When a -device option is processed from the command line,
609 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
610 * order. The upshot is that -device options in increasing command line
611 * order are mapped to virtio-mmio buses with decreasing base addresses.
613 * When this code was originally written, that arrangement ensured that the
614 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
615 * the first -device on the command line. (The end-to-end order is a
616 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
617 * guest kernel's name-to-address assignment strategy.)
619 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
620 * the message, if not necessarily the code, of commit 70161ff336.
621 * Therefore the loop now establishes the inverse of the original intent.
623 * Unfortunately, we can't counteract the kernel change by reversing the
624 * loop; it would break existing command lines.
626 * In any case, the kernel makes no guarantee about the stability of
627 * enumeration order of virtio devices (as demonstrated by it changing
628 * between kernel versions). For reliable and stable identification
629 * of disks users must use UUIDs or similar mechanisms.
631 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
632 int irq = vbi->irqmap[VIRT_MMIO] + i;
633 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size;
635 sysbus_create_simple("virtio-mmio", base, pic[irq]);
638 /* We add dtb nodes in reverse order so that they appear in the finished
639 * device tree lowest address first.
641 * Note that this mapping is independent of the loop above. The previous
642 * loop influences virtio device to virtio transport assignment, whereas
643 * this loop controls how virtio transports are laid out in the dtb.
645 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
646 char *nodename;
647 int irq = vbi->irqmap[VIRT_MMIO] + i;
648 hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size;
650 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
651 qemu_fdt_add_subnode(vbi->fdt, nodename);
652 qemu_fdt_setprop_string(vbi->fdt, nodename,
653 "compatible", "virtio,mmio");
654 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
655 2, base, 2, size);
656 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts",
657 GIC_FDT_IRQ_TYPE_SPI, irq,
658 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
659 g_free(nodename);
663 static void create_one_flash(const char *name, hwaddr flashbase,
664 hwaddr flashsize)
666 /* Create and map a single flash device. We use the same
667 * parameters as the flash devices on the Versatile Express board.
669 DriveInfo *dinfo = drive_get_next(IF_PFLASH);
670 DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
671 const uint64_t sectorlength = 256 * 1024;
673 if (dinfo) {
674 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
675 &error_abort);
678 qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength);
679 qdev_prop_set_uint64(dev, "sector-length", sectorlength);
680 qdev_prop_set_uint8(dev, "width", 4);
681 qdev_prop_set_uint8(dev, "device-width", 2);
682 qdev_prop_set_bit(dev, "big-endian", false);
683 qdev_prop_set_uint16(dev, "id0", 0x89);
684 qdev_prop_set_uint16(dev, "id1", 0x18);
685 qdev_prop_set_uint16(dev, "id2", 0x00);
686 qdev_prop_set_uint16(dev, "id3", 0x00);
687 qdev_prop_set_string(dev, "name", name);
688 qdev_init_nofail(dev);
690 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, flashbase);
693 static void create_flash(const VirtBoardInfo *vbi)
695 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
696 * Any file passed via -bios goes in the first of these.
698 hwaddr flashsize = vbi->memmap[VIRT_FLASH].size / 2;
699 hwaddr flashbase = vbi->memmap[VIRT_FLASH].base;
700 char *nodename;
702 if (bios_name) {
703 char *fn;
704 int image_size;
706 if (drive_get(IF_PFLASH, 0, 0)) {
707 error_report("The contents of the first flash device may be "
708 "specified with -bios or with -drive if=pflash... "
709 "but you cannot use both options at once");
710 exit(1);
712 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
713 if (!fn) {
714 error_report("Could not find ROM image '%s'", bios_name);
715 exit(1);
717 image_size = load_image_targphys(fn, flashbase, flashsize);
718 g_free(fn);
719 if (image_size < 0) {
720 error_report("Could not load ROM image '%s'", bios_name);
721 exit(1);
725 create_one_flash("virt.flash0", flashbase, flashsize);
726 create_one_flash("virt.flash1", flashbase + flashsize, flashsize);
728 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
729 qemu_fdt_add_subnode(vbi->fdt, nodename);
730 qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash");
731 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
732 2, flashbase, 2, flashsize,
733 2, flashbase + flashsize, 2, flashsize);
734 qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4);
735 g_free(nodename);
738 static void create_fw_cfg(const VirtBoardInfo *vbi, AddressSpace *as)
740 hwaddr base = vbi->memmap[VIRT_FW_CFG].base;
741 hwaddr size = vbi->memmap[VIRT_FW_CFG].size;
742 char *nodename;
744 fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
746 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
747 qemu_fdt_add_subnode(vbi->fdt, nodename);
748 qemu_fdt_setprop_string(vbi->fdt, nodename,
749 "compatible", "qemu,fw-cfg-mmio");
750 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
751 2, base, 2, size);
752 g_free(nodename);
755 static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle,
756 int first_irq, const char *nodename)
758 int devfn, pin;
759 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
760 uint32_t *irq_map = full_irq_map;
762 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
763 for (pin = 0; pin < 4; pin++) {
764 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
765 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
766 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
767 int i;
769 uint32_t map[] = {
770 devfn << 8, 0, 0, /* devfn */
771 pin + 1, /* PCI pin */
772 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
774 /* Convert map to big endian */
775 for (i = 0; i < 10; i++) {
776 irq_map[i] = cpu_to_be32(map[i]);
778 irq_map += 10;
782 qemu_fdt_setprop(vbi->fdt, nodename, "interrupt-map",
783 full_irq_map, sizeof(full_irq_map));
785 qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupt-map-mask",
786 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
787 0x7 /* PCI irq */);
790 static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
791 bool use_highmem)
793 hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base;
794 hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size;
795 hwaddr base_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].base;
796 hwaddr size_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].size;
797 hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base;
798 hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size;
799 hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base;
800 hwaddr size_ecam = vbi->memmap[VIRT_PCIE_ECAM].size;
801 hwaddr base = base_mmio;
802 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
803 int irq = vbi->irqmap[VIRT_PCIE];
804 MemoryRegion *mmio_alias;
805 MemoryRegion *mmio_reg;
806 MemoryRegion *ecam_alias;
807 MemoryRegion *ecam_reg;
808 DeviceState *dev;
809 char *nodename;
810 int i;
812 dev = qdev_create(NULL, TYPE_GPEX_HOST);
813 qdev_init_nofail(dev);
815 /* Map only the first size_ecam bytes of ECAM space */
816 ecam_alias = g_new0(MemoryRegion, 1);
817 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
818 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
819 ecam_reg, 0, size_ecam);
820 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
822 /* Map the MMIO window into system address space so as to expose
823 * the section of PCI MMIO space which starts at the same base address
824 * (ie 1:1 mapping for that part of PCI MMIO space visible through
825 * the window).
827 mmio_alias = g_new0(MemoryRegion, 1);
828 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
829 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
830 mmio_reg, base_mmio, size_mmio);
831 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
833 if (use_highmem) {
834 /* Map high MMIO space */
835 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
837 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
838 mmio_reg, base_mmio_high, size_mmio_high);
839 memory_region_add_subregion(get_system_memory(), base_mmio_high,
840 high_mmio_alias);
843 /* Map IO port space */
844 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
846 for (i = 0; i < GPEX_NUM_IRQS; i++) {
847 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
850 nodename = g_strdup_printf("/pcie@%" PRIx64, base);
851 qemu_fdt_add_subnode(vbi->fdt, nodename);
852 qemu_fdt_setprop_string(vbi->fdt, nodename,
853 "compatible", "pci-host-ecam-generic");
854 qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "pci");
855 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#address-cells", 3);
856 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#size-cells", 2);
857 qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0,
858 nr_pcie_buses - 1);
860 if (vbi->v2m_phandle) {
861 qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent",
862 vbi->v2m_phandle);
865 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
866 2, base_ecam, 2, size_ecam);
868 if (use_highmem) {
869 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges",
870 1, FDT_PCI_RANGE_IOPORT, 2, 0,
871 2, base_pio, 2, size_pio,
872 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
873 2, base_mmio, 2, size_mmio,
874 1, FDT_PCI_RANGE_MMIO_64BIT,
875 2, base_mmio_high,
876 2, base_mmio_high, 2, size_mmio_high);
877 } else {
878 qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges",
879 1, FDT_PCI_RANGE_IOPORT, 2, 0,
880 2, base_pio, 2, size_pio,
881 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
882 2, base_mmio, 2, size_mmio);
885 qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 1);
886 create_pcie_irq_map(vbi, vbi->gic_phandle, irq, nodename);
888 g_free(nodename);
891 static void create_platform_bus(VirtBoardInfo *vbi, qemu_irq *pic)
893 DeviceState *dev;
894 SysBusDevice *s;
895 int i;
896 ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1);
897 MemoryRegion *sysmem = get_system_memory();
899 platform_bus_params.platform_bus_base = vbi->memmap[VIRT_PLATFORM_BUS].base;
900 platform_bus_params.platform_bus_size = vbi->memmap[VIRT_PLATFORM_BUS].size;
901 platform_bus_params.platform_bus_first_irq = vbi->irqmap[VIRT_PLATFORM_BUS];
902 platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS;
904 fdt_params->system_params = &platform_bus_params;
905 fdt_params->binfo = &vbi->bootinfo;
906 fdt_params->intc = "/intc";
908 * register a machine init done notifier that creates the device tree
909 * nodes of the platform bus and its children dynamic sysbus devices
911 arm_register_platform_bus_fdt_creator(fdt_params);
913 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
914 dev->id = TYPE_PLATFORM_BUS_DEVICE;
915 qdev_prop_set_uint32(dev, "num_irqs",
916 platform_bus_params.platform_bus_num_irqs);
917 qdev_prop_set_uint32(dev, "mmio_size",
918 platform_bus_params.platform_bus_size);
919 qdev_init_nofail(dev);
920 s = SYS_BUS_DEVICE(dev);
922 for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) {
923 int irqn = platform_bus_params.platform_bus_first_irq + i;
924 sysbus_connect_irq(s, i, pic[irqn]);
927 memory_region_add_subregion(sysmem,
928 platform_bus_params.platform_bus_base,
929 sysbus_mmio_get_region(s, 0));
932 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
934 const VirtBoardInfo *board = (const VirtBoardInfo *)binfo;
936 *fdt_size = board->fdt_size;
937 return board->fdt;
940 static void virt_build_smbios(VirtGuestInfo *guest_info)
942 FWCfgState *fw_cfg = guest_info->fw_cfg;
943 uint8_t *smbios_tables, *smbios_anchor;
944 size_t smbios_tables_len, smbios_anchor_len;
945 const char *product = "QEMU Virtual Machine";
947 if (!fw_cfg) {
948 return;
951 if (kvm_enabled()) {
952 product = "KVM Virtual Machine";
955 smbios_set_defaults("QEMU", product,
956 "1.0", false, true, SMBIOS_ENTRY_POINT_30);
958 smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len,
959 &smbios_anchor, &smbios_anchor_len);
961 if (smbios_anchor) {
962 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
963 smbios_tables, smbios_tables_len);
964 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
965 smbios_anchor, smbios_anchor_len);
969 static
970 void virt_guest_info_machine_done(Notifier *notifier, void *data)
972 VirtGuestInfoState *guest_info_state = container_of(notifier,
973 VirtGuestInfoState, machine_done);
974 virt_acpi_setup(&guest_info_state->info);
975 virt_build_smbios(&guest_info_state->info);
978 static void machvirt_init(MachineState *machine)
980 VirtMachineState *vms = VIRT_MACHINE(machine);
981 qemu_irq pic[NUM_IRQS];
982 MemoryRegion *sysmem = get_system_memory();
983 int gic_version = vms->gic_version;
984 int n, max_cpus;
985 MemoryRegion *ram = g_new(MemoryRegion, 1);
986 const char *cpu_model = machine->cpu_model;
987 VirtBoardInfo *vbi;
988 VirtGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
989 VirtGuestInfo *guest_info = &guest_info_state->info;
990 char **cpustr;
992 if (!cpu_model) {
993 cpu_model = "cortex-a15";
996 /* We can probe only here because during property set
997 * KVM is not available yet
999 if (!gic_version) {
1000 gic_version = kvm_arm_vgic_probe();
1001 if (!gic_version) {
1002 error_report("Unable to determine GIC version supported by host");
1003 error_printf("KVM acceleration is probably not supported\n");
1004 exit(1);
1008 /* Separate the actual CPU model name from any appended features */
1009 cpustr = g_strsplit(cpu_model, ",", 2);
1011 vbi = find_machine_info(cpustr[0]);
1013 if (!vbi) {
1014 error_report("mach-virt: CPU %s not supported", cpustr[0]);
1015 exit(1);
1018 /* The maximum number of CPUs depends on the GIC version, or on how
1019 * many redistributors we can fit into the memory map.
1021 if (gic_version == 3) {
1022 max_cpus = vbi->memmap[VIRT_GIC_REDIST].size / 0x20000;
1023 } else {
1024 max_cpus = GIC_NCPU;
1027 if (smp_cpus > max_cpus) {
1028 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1029 "supported by machine 'mach-virt' (%d)",
1030 smp_cpus, max_cpus);
1031 exit(1);
1034 vbi->smp_cpus = smp_cpus;
1036 if (machine->ram_size > vbi->memmap[VIRT_MEM].size) {
1037 error_report("mach-virt: cannot model more than 30GB RAM");
1038 exit(1);
1041 create_fdt(vbi);
1043 for (n = 0; n < smp_cpus; n++) {
1044 ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
1045 CPUClass *cc = CPU_CLASS(oc);
1046 Object *cpuobj;
1047 Error *err = NULL;
1048 char *cpuopts = g_strdup(cpustr[1]);
1050 if (!oc) {
1051 error_report("Unable to find CPU definition");
1052 exit(1);
1054 cpuobj = object_new(object_class_get_name(oc));
1056 /* Handle any CPU options specified by the user */
1057 cc->parse_features(CPU(cpuobj), cpuopts, &err);
1058 g_free(cpuopts);
1059 if (err) {
1060 error_report_err(err);
1061 exit(1);
1064 if (!vms->secure) {
1065 object_property_set_bool(cpuobj, false, "has_el3", NULL);
1068 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, "psci-conduit",
1069 NULL);
1071 /* Secondary CPUs start in PSCI powered-down state */
1072 if (n > 0) {
1073 object_property_set_bool(cpuobj, true, "start-powered-off", NULL);
1076 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
1077 object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base,
1078 "reset-cbar", &error_abort);
1081 object_property_set_bool(cpuobj, true, "realized", NULL);
1083 g_strfreev(cpustr);
1084 fdt_add_timer_nodes(vbi, gic_version);
1085 fdt_add_cpu_nodes(vbi);
1086 fdt_add_psci_node(vbi);
1088 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
1089 machine->ram_size);
1090 memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram);
1092 create_flash(vbi);
1094 create_gic(vbi, pic, gic_version, vms->secure);
1096 create_uart(vbi, pic);
1098 create_rtc(vbi, pic);
1100 create_pcie(vbi, pic, vms->highmem);
1102 create_gpio(vbi, pic);
1104 /* Create mmio transports, so the user can create virtio backends
1105 * (which will be automatically plugged in to the transports). If
1106 * no backend is created the transport will just sit harmlessly idle.
1108 create_virtio_devices(vbi, pic);
1110 create_fw_cfg(vbi, &address_space_memory);
1111 rom_set_fw(fw_cfg_find());
1113 guest_info->smp_cpus = smp_cpus;
1114 guest_info->fw_cfg = fw_cfg_find();
1115 guest_info->memmap = vbi->memmap;
1116 guest_info->irqmap = vbi->irqmap;
1117 guest_info->use_highmem = vms->highmem;
1118 guest_info->gic_version = gic_version;
1119 guest_info_state->machine_done.notify = virt_guest_info_machine_done;
1120 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
1122 vbi->bootinfo.ram_size = machine->ram_size;
1123 vbi->bootinfo.kernel_filename = machine->kernel_filename;
1124 vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline;
1125 vbi->bootinfo.initrd_filename = machine->initrd_filename;
1126 vbi->bootinfo.nb_cpus = smp_cpus;
1127 vbi->bootinfo.board_id = -1;
1128 vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base;
1129 vbi->bootinfo.get_dtb = machvirt_dtb;
1130 vbi->bootinfo.firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
1131 arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo);
1134 * arm_load_kernel machine init done notifier registration must
1135 * happen before the platform_bus_create call. In this latter,
1136 * another notifier is registered which adds platform bus nodes.
1137 * Notifiers are executed in registration reverse order.
1139 create_platform_bus(vbi, pic);
1142 static bool virt_get_secure(Object *obj, Error **errp)
1144 VirtMachineState *vms = VIRT_MACHINE(obj);
1146 return vms->secure;
1149 static void virt_set_secure(Object *obj, bool value, Error **errp)
1151 VirtMachineState *vms = VIRT_MACHINE(obj);
1153 vms->secure = value;
1156 static bool virt_get_highmem(Object *obj, Error **errp)
1158 VirtMachineState *vms = VIRT_MACHINE(obj);
1160 return vms->highmem;
1163 static void virt_set_highmem(Object *obj, bool value, Error **errp)
1165 VirtMachineState *vms = VIRT_MACHINE(obj);
1167 vms->highmem = value;
1170 static char *virt_get_gic_version(Object *obj, Error **errp)
1172 VirtMachineState *vms = VIRT_MACHINE(obj);
1173 const char *val = vms->gic_version == 3 ? "3" : "2";
1175 return g_strdup(val);
1178 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
1180 VirtMachineState *vms = VIRT_MACHINE(obj);
1182 if (!strcmp(value, "3")) {
1183 vms->gic_version = 3;
1184 } else if (!strcmp(value, "2")) {
1185 vms->gic_version = 2;
1186 } else if (!strcmp(value, "host")) {
1187 vms->gic_version = 0; /* Will probe later */
1188 } else {
1189 error_report("Invalid gic-version option value");
1190 error_printf("Allowed gic-version values are: 3, 2, host\n");
1191 exit(1);
1195 static void virt_instance_init(Object *obj)
1197 VirtMachineState *vms = VIRT_MACHINE(obj);
1199 /* EL3 is disabled by default on virt: this makes us consistent
1200 * between KVM and TCG for this board, and it also allows us to
1201 * boot UEFI blobs which assume no TrustZone support.
1203 vms->secure = false;
1204 object_property_add_bool(obj, "secure", virt_get_secure,
1205 virt_set_secure, NULL);
1206 object_property_set_description(obj, "secure",
1207 "Set on/off to enable/disable the ARM "
1208 "Security Extensions (TrustZone)",
1209 NULL);
1211 /* High memory is enabled by default */
1212 vms->highmem = true;
1213 object_property_add_bool(obj, "highmem", virt_get_highmem,
1214 virt_set_highmem, NULL);
1215 object_property_set_description(obj, "highmem",
1216 "Set on/off to enable/disable using "
1217 "physical address space above 32 bits",
1218 NULL);
1219 /* Default GIC type is v2 */
1220 vms->gic_version = 2;
1221 object_property_add_str(obj, "gic-version", virt_get_gic_version,
1222 virt_set_gic_version, NULL);
1223 object_property_set_description(obj, "gic-version",
1224 "Set GIC version. "
1225 "Valid values are 2, 3 and host", NULL);
1228 static void virt_class_init(ObjectClass *oc, void *data)
1230 MachineClass *mc = MACHINE_CLASS(oc);
1232 mc->desc = "ARM Virtual Machine",
1233 mc->init = machvirt_init;
1234 /* Start max_cpus at the maximum QEMU supports. We'll further restrict
1235 * it later in machvirt_init, where we have more information about the
1236 * configuration of the particular instance.
1238 mc->max_cpus = MAX_CPUMASK_BITS;
1239 mc->has_dynamic_sysbus = true;
1240 mc->block_default_type = IF_VIRTIO;
1241 mc->no_cdrom = 1;
1242 mc->pci_allow_0_address = true;
1245 static const TypeInfo machvirt_info = {
1246 .name = TYPE_VIRT_MACHINE,
1247 .parent = TYPE_MACHINE,
1248 .instance_size = sizeof(VirtMachineState),
1249 .instance_init = virt_instance_init,
1250 .class_size = sizeof(VirtMachineClass),
1251 .class_init = virt_class_init,
1254 static void machvirt_machine_init(void)
1256 type_register_static(&machvirt_info);
1259 machine_init(machvirt_machine_init);