target/riscv/csr.c

   1 /*
   2  * RISC-V Control and Status Registers.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "cpu.h"
  23 #include "qemu/main-loop.h"
  24 #include "exec/exec-all.h"
  25
  26 /* CSR function table */
  27 static riscv_csr_operations csr_ops[];
  28
  29 /* CSR function table constants */
  30 enum {
  31     CSR_TABLE_SIZE = 0x1000
  32 };
  33
  34 /* CSR function table public API */
  35 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
  36 {
  37     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
  38 }
  39
  40 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
  41 {
  42     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
  43 }
  44
  45 /* Predicates */
  46 static int fs(CPURISCVState *env, int csrno)
  47 {
  48 #if !defined(CONFIG_USER_ONLY)
  49     /* loose check condition for fcsr in vector extension */
  50     if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
  51         return 0;
  52     }
  53     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
  54         return -RISCV_EXCP_ILLEGAL_INST;
  55     }
  56 #endif
  57     return 0;
  58 }
  59
  60 static int vs(CPURISCVState *env, int csrno)
  61 {
  62     if (env->misa & RVV) {
  63         return 0;
  64     }
  65     return -1;
  66 }
  67
  68 static int ctr(CPURISCVState *env, int csrno)
  69 {
  70 #if !defined(CONFIG_USER_ONLY)
  71     CPUState *cs = env_cpu(env);
  72     RISCVCPU *cpu = RISCV_CPU(cs);
  73
  74     if (!cpu->cfg.ext_counters) {
  75         /* The Counters extensions is not enabled */
  76         return -RISCV_EXCP_ILLEGAL_INST;
  77     }
  78
  79     if (riscv_cpu_virt_enabled(env)) {
  80         switch (csrno) {
  81         case CSR_CYCLE:
  82             if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
  83                 get_field(env->mcounteren, HCOUNTEREN_CY)) {
  84                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  85             }
  86             break;
  87         case CSR_TIME:
  88             if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
  89                 get_field(env->mcounteren, HCOUNTEREN_TM)) {
  90                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  91             }
  92             break;
  93         case CSR_INSTRET:
  94             if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
  95                 get_field(env->mcounteren, HCOUNTEREN_IR)) {
  96                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  97             }
  98             break;
  99         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
 100             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
 101                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
 102                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 103             }
 104             break;
 105         }
 106         if (riscv_cpu_is_32bit(env)) {
 107             switch (csrno) {
 108             case CSR_CYCLEH:
 109                 if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
 110                     get_field(env->mcounteren, HCOUNTEREN_CY)) {
 111                     return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 112                 }
 113                 break;
 114             case CSR_TIMEH:
 115                 if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
 116                     get_field(env->mcounteren, HCOUNTEREN_TM)) {
 117                     return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 118                 }
 119                 break;
 120             case CSR_INSTRETH:
 121                 if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
 122                     get_field(env->mcounteren, HCOUNTEREN_IR)) {
 123                     return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 124                 }
 125                 break;
 126             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
 127                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
 128                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
 129                     return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 130                 }
 131                 break;
 132             }
 133         }
 134     }
 135 #endif
 136     return 0;
 137 }
 138
 139 static int ctr32(CPURISCVState *env, int csrno)
 140 {
 141     if (!riscv_cpu_is_32bit(env)) {
 142         return -RISCV_EXCP_ILLEGAL_INST;
 143     }
 144
 145     return ctr(env, csrno);
 146 }
 147
 148 #if !defined(CONFIG_USER_ONLY)
 149 static int any(CPURISCVState *env, int csrno)
 150 {
 151     return 0;
 152 }
 153
 154 static int any32(CPURISCVState *env, int csrno)
 155 {
 156     if (!riscv_cpu_is_32bit(env)) {
 157         return -RISCV_EXCP_ILLEGAL_INST;
 158     }
 159
 160     return any(env, csrno);
 161
 162 }
 163
 164 static int smode(CPURISCVState *env, int csrno)
 165 {
 166     return -!riscv_has_ext(env, RVS);
 167 }
 168
 169 static int hmode(CPURISCVState *env, int csrno)
 170 {
 171     if (riscv_has_ext(env, RVS) &&
 172         riscv_has_ext(env, RVH)) {
 173         /* Hypervisor extension is supported */
 174         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 175             env->priv == PRV_M) {
 176             return 0;
 177         } else {
 178             return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 179         }
 180     }
 181
 182     return -RISCV_EXCP_ILLEGAL_INST;
 183 }
 184
 185 static int hmode32(CPURISCVState *env, int csrno)
 186 {
 187     if (!riscv_cpu_is_32bit(env)) {
 188         return 0;
 189     }
 190
 191     return hmode(env, csrno);
 192
 193 }
 194
 195 static int pmp(CPURISCVState *env, int csrno)
 196 {
 197     return -!riscv_feature(env, RISCV_FEATURE_PMP);
 198 }
 199 #endif
 200
 201 /* User Floating-Point CSRs */
 202 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
 203 {
 204 #if !defined(CONFIG_USER_ONLY)
 205     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 206         return -RISCV_EXCP_ILLEGAL_INST;
 207     }
 208 #endif
 209     *val = riscv_cpu_get_fflags(env);
 210     return 0;
 211 }
 212
 213 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
 214 {
 215 #if !defined(CONFIG_USER_ONLY)
 216     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 217         return -RISCV_EXCP_ILLEGAL_INST;
 218     }
 219     env->mstatus |= MSTATUS_FS;
 220 #endif
 221     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
 222     return 0;
 223 }
 224
 225 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
 226 {
 227 #if !defined(CONFIG_USER_ONLY)
 228     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 229         return -RISCV_EXCP_ILLEGAL_INST;
 230     }
 231 #endif
 232     *val = env->frm;
 233     return 0;
 234 }
 235
 236 static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
 237 {
 238 #if !defined(CONFIG_USER_ONLY)
 239     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 240         return -RISCV_EXCP_ILLEGAL_INST;
 241     }
 242     env->mstatus |= MSTATUS_FS;
 243 #endif
 244     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
 245     return 0;
 246 }
 247
 248 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
 249 {
 250 #if !defined(CONFIG_USER_ONLY)
 251     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 252         return -RISCV_EXCP_ILLEGAL_INST;
 253     }
 254 #endif
 255     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
 256         | (env->frm << FSR_RD_SHIFT);
 257     if (vs(env, csrno) >= 0) {
 258         *val |= (env->vxrm << FSR_VXRM_SHIFT)
 259                 | (env->vxsat << FSR_VXSAT_SHIFT);
 260     }
 261     return 0;
 262 }
 263
 264 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
 265 {
 266 #if !defined(CONFIG_USER_ONLY)
 267     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 268         return -RISCV_EXCP_ILLEGAL_INST;
 269     }
 270     env->mstatus |= MSTATUS_FS;
 271 #endif
 272     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 273     if (vs(env, csrno) >= 0) {
 274         env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
 275         env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
 276     }
 277     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
 278     return 0;
 279 }
 280
 281 static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
 282 {
 283     *val = env->vtype;
 284     return 0;
 285 }
 286
 287 static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
 288 {
 289     *val = env->vl;
 290     return 0;
 291 }
 292
 293 static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
 294 {
 295     *val = env->vxrm;
 296     return 0;
 297 }
 298
 299 static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
 300 {
 301     env->vxrm = val;
 302     return 0;
 303 }
 304
 305 static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
 306 {
 307     *val = env->vxsat;
 308     return 0;
 309 }
 310
 311 static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
 312 {
 313     env->vxsat = val;
 314     return 0;
 315 }
 316
 317 static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
 318 {
 319     *val = env->vstart;
 320     return 0;
 321 }
 322
 323 static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
 324 {
 325     env->vstart = val;
 326     return 0;
 327 }
 328
 329 /* User Timers and Counters */
 330 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
 331 {
 332 #if !defined(CONFIG_USER_ONLY)
 333     if (icount_enabled()) {
 334         *val = icount_get();
 335     } else {
 336         *val = cpu_get_host_ticks();
 337     }
 338 #else
 339     *val = cpu_get_host_ticks();
 340 #endif
 341     return 0;
 342 }
 343
 344 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
 345 {
 346 #if !defined(CONFIG_USER_ONLY)
 347     if (icount_enabled()) {
 348         *val = icount_get() >> 32;
 349     } else {
 350         *val = cpu_get_host_ticks() >> 32;
 351     }
 352 #else
 353     *val = cpu_get_host_ticks() >> 32;
 354 #endif
 355     return 0;
 356 }
 357
 358 #if defined(CONFIG_USER_ONLY)
 359 static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
 360 {
 361     *val = cpu_get_host_ticks();
 362     return 0;
 363 }
 364
 365 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
 366 {
 367     *val = cpu_get_host_ticks() >> 32;
 368     return 0;
 369 }
 370
 371 #else /* CONFIG_USER_ONLY */
 372
 373 static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
 374 {
 375     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 376
 377     if (!env->rdtime_fn) {
 378         return -RISCV_EXCP_ILLEGAL_INST;
 379     }
 380
 381     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
 382     return 0;
 383 }
 384
 385 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
 386 {
 387     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 388
 389     if (!env->rdtime_fn) {
 390         return -RISCV_EXCP_ILLEGAL_INST;
 391     }
 392
 393     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
 394     return 0;
 395 }
 396
 397 /* Machine constants */
 398
 399 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
 400 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
 401 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
 402
 403 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
 404                                            VS_MODE_INTERRUPTS;
 405 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
 406                                      VS_MODE_INTERRUPTS;
 407 static const target_ulong delegable_excps =
 408     (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) |
 409     (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) |
 410     (1ULL << (RISCV_EXCP_ILLEGAL_INST)) |
 411     (1ULL << (RISCV_EXCP_BREAKPOINT)) |
 412     (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) |
 413     (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) |
 414     (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) |
 415     (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) |
 416     (1ULL << (RISCV_EXCP_U_ECALL)) |
 417     (1ULL << (RISCV_EXCP_S_ECALL)) |
 418     (1ULL << (RISCV_EXCP_VS_ECALL)) |
 419     (1ULL << (RISCV_EXCP_M_ECALL)) |
 420     (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) |
 421     (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) |
 422     (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
 423     (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
 424     (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
 425     (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
 426     (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
 427 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
 428     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
 429     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 430 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
 431 static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 432 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 433
 434 static const char valid_vm_1_10_32[16] = {
 435     [VM_1_10_MBARE] = 1,
 436     [VM_1_10_SV32] = 1
 437 };
 438
 439 static const char valid_vm_1_10_64[16] = {
 440     [VM_1_10_MBARE] = 1,
 441     [VM_1_10_SV39] = 1,
 442     [VM_1_10_SV48] = 1,
 443     [VM_1_10_SV57] = 1
 444 };
 445
 446 /* Machine Information Registers */
 447 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
 448 {
 449     return *val = 0;
 450 }
 451
 452 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val)
 453 {
 454     *val = env->mhartid;
 455     return 0;
 456 }
 457
 458 /* Machine Trap Setup */
 459 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
 460 {
 461     *val = env->mstatus;
 462     return 0;
 463 }
 464
 465 static int validate_vm(CPURISCVState *env, target_ulong vm)
 466 {
 467     if (riscv_cpu_is_32bit(env)) {
 468         return valid_vm_1_10_32[vm & 0xf];
 469     } else {
 470         return valid_vm_1_10_64[vm & 0xf];
 471     }
 472 }
 473
 474 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
 475 {
 476     uint64_t mstatus = env->mstatus;
 477     uint64_t mask = 0;
 478     int dirty;
 479
 480     /* flush tlb on mstatus fields that affect VM */
 481     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
 482             MSTATUS_MPRV | MSTATUS_SUM)) {
 483         tlb_flush(env_cpu(env));
 484     }
 485     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
 486         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
 487         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
 488         MSTATUS_TW;
 489
 490     if (!riscv_cpu_is_32bit(env)) {
 491         /*
 492          * RV32: MPV and GVA are not in mstatus. The current plan is to
 493          * add them to mstatush. For now, we just don't support it.
 494          */
 495         mask |= MSTATUS_MPV | MSTATUS_GVA;
 496     }
 497
 498     mstatus = (mstatus & ~mask) | (val & mask);
 499
 500     dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
 501             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
 502     mstatus = set_field(mstatus, MSTATUS_SD, dirty);
 503     env->mstatus = mstatus;
 504
 505     return 0;
 506 }
 507
 508 static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
 509 {
 510     *val = env->mstatus >> 32;
 511     return 0;
 512 }
 513
 514 static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
 515 {
 516     uint64_t valh = (uint64_t)val << 32;
 517     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
 518
 519     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
 520         tlb_flush(env_cpu(env));
 521     }
 522
 523     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
 524
 525     return 0;
 526 }
 527
 528 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
 529 {
 530     *val = env->misa;
 531     return 0;
 532 }
 533
 534 static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
 535 {
 536     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
 537         /* drop write to misa */
 538         return 0;
 539     }
 540
 541     /* 'I' or 'E' must be present */
 542     if (!(val & (RVI | RVE))) {
 543         /* It is not, drop write to misa */
 544         return 0;
 545     }
 546
 547     /* 'E' excludes all other extensions */
 548     if (val & RVE) {
 549         /* when we support 'E' we can do "val = RVE;" however
 550          * for now we just drop writes if 'E' is present.
 551          */
 552         return 0;
 553     }
 554
 555     /* Mask extensions that are not supported by this hart */
 556     val &= env->misa_mask;
 557
 558     /* Mask extensions that are not supported by QEMU */
 559     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 560
 561     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
 562     if ((val & RVD) && !(val & RVF)) {
 563         val &= ~RVD;
 564     }
 565
 566     /* Suppress 'C' if next instruction is not aligned
 567      * TODO: this should check next_pc
 568      */
 569     if ((val & RVC) && (GETPC() & ~3) != 0) {
 570         val &= ~RVC;
 571     }
 572
 573     /* misa.MXL writes are not supported by QEMU */
 574     val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
 575
 576     /* flush translation cache */
 577     if (val != env->misa) {
 578         tb_flush(env_cpu(env));
 579     }
 580
 581     env->misa = val;
 582
 583     return 0;
 584 }
 585
 586 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
 587 {
 588     *val = env->medeleg;
 589     return 0;
 590 }
 591
 592 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val)
 593 {
 594     env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
 595     return 0;
 596 }
 597
 598 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
 599 {
 600     *val = env->mideleg;
 601     return 0;
 602 }
 603
 604 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
 605 {
 606     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
 607     if (riscv_has_ext(env, RVH)) {
 608         env->mideleg |= VS_MODE_INTERRUPTS;
 609     }
 610     return 0;
 611 }
 612
 613 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
 614 {
 615     *val = env->mie;
 616     return 0;
 617 }
 618
 619 static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
 620 {
 621     env->mie = (env->mie & ~all_ints) | (val & all_ints);
 622     return 0;
 623 }
 624
 625 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
 626 {
 627     *val = env->mtvec;
 628     return 0;
 629 }
 630
 631 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
 632 {
 633     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
 634     if ((val & 3) < 2) {
 635         env->mtvec = val;
 636     } else {
 637         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
 638     }
 639     return 0;
 640 }
 641
 642 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
 643 {
 644     *val = env->mcounteren;
 645     return 0;
 646 }
 647
 648 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
 649 {
 650     env->mcounteren = val;
 651     return 0;
 652 }
 653
 654 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 655 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
 656 {
 657     if (env->priv_ver < PRIV_VERSION_1_11_0) {
 658         return -RISCV_EXCP_ILLEGAL_INST;
 659     }
 660     *val = env->mcounteren;
 661     return 0;
 662 }
 663
 664 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 665 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
 666 {
 667     if (env->priv_ver < PRIV_VERSION_1_11_0) {
 668         return -RISCV_EXCP_ILLEGAL_INST;
 669     }
 670     env->mcounteren = val;
 671     return 0;
 672 }
 673
 674 /* Machine Trap Handling */
 675 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
 676 {
 677     *val = env->mscratch;
 678     return 0;
 679 }
 680
 681 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val)
 682 {
 683     env->mscratch = val;
 684     return 0;
 685 }
 686
 687 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val)
 688 {
 689     *val = env->mepc;
 690     return 0;
 691 }
 692
 693 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val)
 694 {
 695     env->mepc = val;
 696     return 0;
 697 }
 698
 699 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val)
 700 {
 701     *val = env->mcause;
 702     return 0;
 703 }
 704
 705 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
 706 {
 707     env->mcause = val;
 708     return 0;
 709 }
 710
 711 static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
 712 {
 713     *val = env->mbadaddr;
 714     return 0;
 715 }
 716
 717 static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 718 {
 719     env->mbadaddr = val;
 720     return 0;
 721 }
 722
 723 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 724                    target_ulong new_value, target_ulong write_mask)
 725 {
 726     RISCVCPU *cpu = env_archcpu(env);
 727     /* Allow software control of delegable interrupts not claimed by hardware */
 728     target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
 729     uint32_t old_mip;
 730
 731     if (mask) {
 732         old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
 733     } else {
 734         old_mip = env->mip;
 735     }
 736
 737     if (ret_value) {
 738         *ret_value = old_mip;
 739     }
 740
 741     return 0;
 742 }
 743
 744 /* Supervisor Trap Setup */
 745 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
 746 {
 747     target_ulong mask = (sstatus_v1_10_mask);
 748     *val = env->mstatus & mask;
 749     return 0;
 750 }
 751
 752 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
 753 {
 754     target_ulong mask = (sstatus_v1_10_mask);
 755     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
 756     return write_mstatus(env, CSR_MSTATUS, newval);
 757 }
 758
 759 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
 760 {
 761     if (riscv_cpu_virt_enabled(env)) {
 762         /* Tell the guest the VS bits, shifted to the S bit locations */
 763         *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
 764     } else {
 765         *val = env->mie & env->mideleg;
 766     }
 767     return 0;
 768 }
 769
 770 static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 771 {
 772     target_ulong newval;
 773
 774     if (riscv_cpu_virt_enabled(env)) {
 775         /* Shift the guests S bits to VS */
 776         newval = (env->mie & ~VS_MODE_INTERRUPTS) |
 777                  ((val << 1) & VS_MODE_INTERRUPTS);
 778     } else {
 779         newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
 780     }
 781
 782     return write_mie(env, CSR_MIE, newval);
 783 }
 784
 785 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
 786 {
 787     *val = env->stvec;
 788     return 0;
 789 }
 790
 791 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
 792 {
 793     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
 794     if ((val & 3) < 2) {
 795         env->stvec = val;
 796     } else {
 797         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
 798     }
 799     return 0;
 800 }
 801
 802 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
 803 {
 804     *val = env->scounteren;
 805     return 0;
 806 }
 807
 808 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
 809 {
 810     env->scounteren = val;
 811     return 0;
 812 }
 813
 814 /* Supervisor Trap Handling */
 815 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val)
 816 {
 817     *val = env->sscratch;
 818     return 0;
 819 }
 820
 821 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val)
 822 {
 823     env->sscratch = val;
 824     return 0;
 825 }
 826
 827 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val)
 828 {
 829     *val = env->sepc;
 830     return 0;
 831 }
 832
 833 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val)
 834 {
 835     env->sepc = val;
 836     return 0;
 837 }
 838
 839 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val)
 840 {
 841     *val = env->scause;
 842     return 0;
 843 }
 844
 845 static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
 846 {
 847     env->scause = val;
 848     return 0;
 849 }
 850
 851 static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
 852 {
 853     *val = env->sbadaddr;
 854     return 0;
 855 }
 856
 857 static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 858 {
 859     env->sbadaddr = val;
 860     return 0;
 861 }
 862
 863 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 864                    target_ulong new_value, target_ulong write_mask)
 865 {
 866     int ret;
 867
 868     if (riscv_cpu_virt_enabled(env)) {
 869         /* Shift the new values to line up with the VS bits */
 870         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
 871                       (write_mask & sip_writable_mask) << 1 & env->mideleg);
 872         ret &= vsip_writable_mask;
 873         ret >>= 1;
 874     } else {
 875         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
 876                       write_mask & env->mideleg & sip_writable_mask);
 877     }
 878
 879     *ret_value &= env->mideleg;
 880     return ret;
 881 }
 882
 883 /* Supervisor Protection and Translation */
 884 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
 885 {
 886     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
 887         *val = 0;
 888         return 0;
 889     }
 890
 891     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
 892         return -RISCV_EXCP_ILLEGAL_INST;
 893     } else {
 894         *val = env->satp;
 895     }
 896
 897     return 0;
 898 }
 899
 900 static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
 901 {
 902     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
 903         return 0;
 904     }
 905     if (validate_vm(env, get_field(val, SATP_MODE)) &&
 906         ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
 907     {
 908         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
 909             return -RISCV_EXCP_ILLEGAL_INST;
 910         } else {
 911             if ((val ^ env->satp) & SATP_ASID) {
 912                 tlb_flush(env_cpu(env));
 913             }
 914             env->satp = val;
 915         }
 916     }
 917     return 0;
 918 }
 919
 920 /* Hypervisor Extensions */
 921 static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
 922 {
 923     *val = env->hstatus;
 924     if (!riscv_cpu_is_32bit(env)) {
 925         /* We only support 64-bit VSXL */
 926         *val = set_field(*val, HSTATUS_VSXL, 2);
 927     }
 928     /* We only support little endian */
 929     *val = set_field(*val, HSTATUS_VSBE, 0);
 930     return 0;
 931 }
 932
 933 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
 934 {
 935     env->hstatus = val;
 936     if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
 937         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
 938     }
 939     if (get_field(val, HSTATUS_VSBE) != 0) {
 940         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
 941     }
 942     return 0;
 943 }
 944
 945 static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
 946 {
 947     *val = env->hedeleg;
 948     return 0;
 949 }
 950
 951 static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
 952 {
 953     env->hedeleg = val;
 954     return 0;
 955 }
 956
 957 static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
 958 {
 959     *val = env->hideleg;
 960     return 0;
 961 }
 962
 963 static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
 964 {
 965     env->hideleg = val;
 966     return 0;
 967 }
 968
 969 static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 970                    target_ulong new_value, target_ulong write_mask)
 971 {
 972     int ret = rmw_mip(env, 0, ret_value, new_value,
 973                       write_mask & hip_writable_mask);
 974
 975     *ret_value &= hip_writable_mask;
 976
 977     return ret;
 978 }
 979
 980 static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 981                    target_ulong new_value, target_ulong write_mask)
 982 {
 983     int ret = rmw_mip(env, 0, ret_value, new_value,
 984                       write_mask & hip_writable_mask);
 985
 986     *ret_value &= hip_writable_mask;
 987
 988     return ret;
 989 }
 990
 991 static int read_hie(CPURISCVState *env, int csrno, target_ulong *val)
 992 {
 993     *val = env->mie & VS_MODE_INTERRUPTS;
 994     return 0;
 995 }
 996
 997 static int write_hie(CPURISCVState *env, int csrno, target_ulong val)
 998 {
 999     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
1000     return write_mie(env, CSR_MIE, newval);
1001 }
1002
1003 static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val)
1004 {
1005     *val = env->hcounteren;
1006     return 0;
1007 }
1008
1009 static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
1010 {
1011     env->hcounteren = val;
1012     return 0;
1013 }
1014
1015 static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
1016 {
1017     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1018     return 0;
1019 }
1020
1021 static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
1022 {
1023     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1024     return 0;
1025 }
1026
1027 static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
1028 {
1029     *val = env->htval;
1030     return 0;
1031 }
1032
1033 static int write_htval(CPURISCVState *env, int csrno, target_ulong val)
1034 {
1035     env->htval = val;
1036     return 0;
1037 }
1038
1039 static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
1040 {
1041     *val = env->htinst;
1042     return 0;
1043 }
1044
1045 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
1046 {
1047     return 0;
1048 }
1049
1050 static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
1051 {
1052     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1053     return 0;
1054 }
1055
1056 static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
1057 {
1058     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1059     return 0;
1060 }
1061
1062 static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
1063 {
1064     *val = env->hgatp;
1065     return 0;
1066 }
1067
1068 static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
1069 {
1070     env->hgatp = val;
1071     return 0;
1072 }
1073
1074 static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
1075 {
1076     if (!env->rdtime_fn) {
1077         return -RISCV_EXCP_ILLEGAL_INST;
1078     }
1079
1080     *val = env->htimedelta;
1081     return 0;
1082 }
1083
1084 static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
1085 {
1086     if (!env->rdtime_fn) {
1087         return -RISCV_EXCP_ILLEGAL_INST;
1088     }
1089
1090     if (riscv_cpu_is_32bit(env)) {
1091         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1092     } else {
1093         env->htimedelta = val;
1094     }
1095     return 0;
1096 }
1097
1098 static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
1099 {
1100     if (!env->rdtime_fn) {
1101         return -RISCV_EXCP_ILLEGAL_INST;
1102     }
1103
1104     *val = env->htimedelta >> 32;
1105     return 0;
1106 }
1107
1108 static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
1109 {
1110     if (!env->rdtime_fn) {
1111         return -RISCV_EXCP_ILLEGAL_INST;
1112     }
1113
1114     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1115     return 0;
1116 }
1117
1118 /* Virtual CSR Registers */
1119 static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
1120 {
1121     *val = env->vsstatus;
1122     return 0;
1123 }
1124
1125 static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
1126 {
1127     uint64_t mask = (target_ulong)-1;
1128     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1129     return 0;
1130 }
1131
1132 static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
1133                     target_ulong new_value, target_ulong write_mask)
1134 {
1135     int ret = rmw_mip(env, 0, ret_value, new_value,
1136                       write_mask & env->mideleg & vsip_writable_mask);
1137     return ret;
1138 }
1139
1140 static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
1141 {
1142     *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
1143     return 0;
1144 }
1145
1146 static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
1147 {
1148     target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
1149     return write_mie(env, CSR_MIE, newval);
1150 }
1151
1152 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1153 {
1154     *val = env->vstvec;
1155     return 0;
1156 }
1157
1158 static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val)
1159 {
1160     env->vstvec = val;
1161     return 0;
1162 }
1163
1164 static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val)
1165 {
1166     *val = env->vsscratch;
1167     return 0;
1168 }
1169
1170 static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val)
1171 {
1172     env->vsscratch = val;
1173     return 0;
1174 }
1175
1176 static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val)
1177 {
1178     *val = env->vsepc;
1179     return 0;
1180 }
1181
1182 static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val)
1183 {
1184     env->vsepc = val;
1185     return 0;
1186 }
1187
1188 static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val)
1189 {
1190     *val = env->vscause;
1191     return 0;
1192 }
1193
1194 static int write_vscause(CPURISCVState *env, int csrno, target_ulong val)
1195 {
1196     env->vscause = val;
1197     return 0;
1198 }
1199
1200 static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val)
1201 {
1202     *val = env->vstval;
1203     return 0;
1204 }
1205
1206 static int write_vstval(CPURISCVState *env, int csrno, target_ulong val)
1207 {
1208     env->vstval = val;
1209     return 0;
1210 }
1211
1212 static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val)
1213 {
1214     *val = env->vsatp;
1215     return 0;
1216 }
1217
1218 static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val)
1219 {
1220     env->vsatp = val;
1221     return 0;
1222 }
1223
1224 static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
1225 {
1226     *val = env->mtval2;
1227     return 0;
1228 }
1229
1230 static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
1231 {
1232     env->mtval2 = val;
1233     return 0;
1234 }
1235
1236 static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
1237 {
1238     *val = env->mtinst;
1239     return 0;
1240 }
1241
1242 static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
1243 {
1244     env->mtinst = val;
1245     return 0;
1246 }
1247
1248 /* Physical Memory Protection */
1249 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
1250 {
1251     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1252     return 0;
1253 }
1254
1255 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val)
1256 {
1257     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1258     return 0;
1259 }
1260
1261 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val)
1262 {
1263     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1264     return 0;
1265 }
1266
1267 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
1268 {
1269     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1270     return 0;
1271 }
1272
1273 #endif
1274
1275 /*
1276  * riscv_csrrw - read and/or update control and status register
1277  *
1278  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
1279  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
1280  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
1281  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
1282  */
1283
1284 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
1285                 target_ulong new_value, target_ulong write_mask)
1286 {
1287     int ret;
1288     target_ulong old_value;
1289     RISCVCPU *cpu = env_archcpu(env);
1290
1291     /* check privileges and return -1 if check fails */
1292 #if !defined(CONFIG_USER_ONLY)
1293     int effective_priv = env->priv;
1294     int read_only = get_field(csrno, 0xC00) == 3;
1295
1296     if (riscv_has_ext(env, RVH) &&
1297         env->priv == PRV_S &&
1298         !riscv_cpu_virt_enabled(env)) {
1299         /*
1300          * We are in S mode without virtualisation, therefore we are in HS Mode.
1301          * Add 1 to the effective privledge level to allow us to access the
1302          * Hypervisor CSRs.
1303          */
1304         effective_priv++;
1305     }
1306
1307     if ((write_mask && read_only) ||
1308         (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
1309         return -RISCV_EXCP_ILLEGAL_INST;
1310     }
1311 #endif
1312
1313     /* ensure the CSR extension is enabled. */
1314     if (!cpu->cfg.ext_icsr) {
1315         return -RISCV_EXCP_ILLEGAL_INST;
1316     }
1317
1318     /* check predicate */
1319     if (!csr_ops[csrno].predicate) {
1320         return -RISCV_EXCP_ILLEGAL_INST;
1321     }
1322     ret = csr_ops[csrno].predicate(env, csrno);
1323     if (ret < 0) {
1324         return ret;
1325     }
1326
1327     /* execute combined read/write operation if it exists */
1328     if (csr_ops[csrno].op) {
1329         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1330     }
1331
1332     /* if no accessor exists then return failure */
1333     if (!csr_ops[csrno].read) {
1334         return -RISCV_EXCP_ILLEGAL_INST;
1335     }
1336
1337     /* read old value */
1338     ret = csr_ops[csrno].read(env, csrno, &old_value);
1339     if (ret < 0) {
1340         return ret;
1341     }
1342
1343     /* write value if writable and write mask set, otherwise drop writes */
1344     if (write_mask) {
1345         new_value = (old_value & ~write_mask) | (new_value & write_mask);
1346         if (csr_ops[csrno].write) {
1347             ret = csr_ops[csrno].write(env, csrno, new_value);
1348             if (ret < 0) {
1349                 return ret;
1350             }
1351         }
1352     }
1353
1354     /* return old value */
1355     if (ret_value) {
1356         *ret_value = old_value;
1357     }
1358
1359     return 0;
1360 }
1361
1362 /*
1363  * Debugger support.  If not in user mode, set env->debugger before the
1364  * riscv_csrrw call and clear it after the call.
1365  */
1366 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
1367                 target_ulong new_value, target_ulong write_mask)
1368 {
1369     int ret;
1370 #if !defined(CONFIG_USER_ONLY)
1371     env->debugger = true;
1372 #endif
1373     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
1374 #if !defined(CONFIG_USER_ONLY)
1375     env->debugger = false;
1376 #endif
1377     return ret;
1378 }
1379
1380 /* Control and Status Register function table */
1381 static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
1382     /* User Floating-Point CSRs */
1383     [CSR_FFLAGS] =              { fs,   read_fflags,      write_fflags      },
1384     [CSR_FRM] =                 { fs,   read_frm,         write_frm         },
1385     [CSR_FCSR] =                { fs,   read_fcsr,        write_fcsr        },
1386     /* Vector CSRs */
1387     [CSR_VSTART] =              { vs,   read_vstart,      write_vstart      },
1388     [CSR_VXSAT] =               { vs,   read_vxsat,       write_vxsat       },
1389     [CSR_VXRM] =                { vs,   read_vxrm,        write_vxrm        },
1390     [CSR_VL] =                  { vs,   read_vl                             },
1391     [CSR_VTYPE] =               { vs,   read_vtype                          },
1392     /* User Timers and Counters */
1393     [CSR_CYCLE] =               { ctr,  read_instret                        },
1394     [CSR_INSTRET] =             { ctr,  read_instret                        },
1395     [CSR_CYCLEH] =              { ctr32,  read_instreth                     },
1396     [CSR_INSTRETH] =            { ctr32,  read_instreth                     },
1397
1398     /* In privileged mode, the monitor will have to emulate TIME CSRs only if
1399      * rdtime callback is not provided by machine/platform emulation */
1400     [CSR_TIME] =                { ctr,  read_time                           },
1401     [CSR_TIMEH] =               { ctr32,  read_timeh                        },
1402
1403 #if !defined(CONFIG_USER_ONLY)
1404     /* Machine Timers and Counters */
1405     [CSR_MCYCLE] =              { any,  read_instret                        },
1406     [CSR_MINSTRET] =            { any,  read_instret                        },
1407     [CSR_MCYCLEH] =             { any32,  read_instreth                     },
1408     [CSR_MINSTRETH] =           { any32,  read_instreth                     },
1409
1410     /* Machine Information Registers */
1411     [CSR_MVENDORID] =           { any,  read_zero                           },
1412     [CSR_MARCHID] =             { any,  read_zero                           },
1413     [CSR_MIMPID] =              { any,  read_zero                           },
1414     [CSR_MHARTID] =             { any,  read_mhartid                        },
1415
1416     /* Machine Trap Setup */
1417     [CSR_MSTATUS] =             { any,  read_mstatus,     write_mstatus     },
1418     [CSR_MISA] =                { any,  read_misa,        write_misa        },
1419     [CSR_MIDELEG] =             { any,  read_mideleg,     write_mideleg     },
1420     [CSR_MEDELEG] =             { any,  read_medeleg,     write_medeleg     },
1421     [CSR_MIE] =                 { any,  read_mie,         write_mie         },
1422     [CSR_MTVEC] =               { any,  read_mtvec,       write_mtvec       },
1423     [CSR_MCOUNTEREN] =          { any,  read_mcounteren,  write_mcounteren  },
1424
1425     [CSR_MSTATUSH] =            { any32,  read_mstatush,    write_mstatush  },
1426
1427     [CSR_MSCOUNTEREN] =         { any,  read_mscounteren, write_mscounteren },
1428
1429     /* Machine Trap Handling */
1430     [CSR_MSCRATCH] =            { any,  read_mscratch,    write_mscratch    },
1431     [CSR_MEPC] =                { any,  read_mepc,        write_mepc        },
1432     [CSR_MCAUSE] =              { any,  read_mcause,      write_mcause      },
1433     [CSR_MBADADDR] =            { any,  read_mbadaddr,    write_mbadaddr    },
1434     [CSR_MIP] =                 { any,  NULL,     NULL,     rmw_mip         },
1435
1436     /* Supervisor Trap Setup */
1437     [CSR_SSTATUS] =             { smode, read_sstatus,     write_sstatus     },
1438     [CSR_SIE] =                 { smode, read_sie,         write_sie         },
1439     [CSR_STVEC] =               { smode, read_stvec,       write_stvec       },
1440     [CSR_SCOUNTEREN] =          { smode, read_scounteren,  write_scounteren  },
1441
1442     /* Supervisor Trap Handling */
1443     [CSR_SSCRATCH] =            { smode, read_sscratch,    write_sscratch    },
1444     [CSR_SEPC] =                { smode, read_sepc,        write_sepc        },
1445     [CSR_SCAUSE] =              { smode, read_scause,      write_scause      },
1446     [CSR_SBADADDR] =            { smode, read_sbadaddr,    write_sbadaddr    },
1447     [CSR_SIP] =                 { smode, NULL,     NULL,     rmw_sip         },
1448
1449     /* Supervisor Protection and Translation */
1450     [CSR_SATP] =                { smode, read_satp,        write_satp        },
1451
1452     [CSR_HSTATUS] =             { hmode,   read_hstatus,     write_hstatus    },
1453     [CSR_HEDELEG] =             { hmode,   read_hedeleg,     write_hedeleg    },
1454     [CSR_HIDELEG] =             { hmode,   read_hideleg,     write_hideleg    },
1455     [CSR_HVIP] =                { hmode,   NULL,     NULL,     rmw_hvip       },
1456     [CSR_HIP] =                 { hmode,   NULL,     NULL,     rmw_hip        },
1457     [CSR_HIE] =                 { hmode,   read_hie,         write_hie        },
1458     [CSR_HCOUNTEREN] =          { hmode,   read_hcounteren,  write_hcounteren },
1459     [CSR_HGEIE] =               { hmode,   read_hgeie,       write_hgeie      },
1460     [CSR_HTVAL] =               { hmode,   read_htval,       write_htval      },
1461     [CSR_HTINST] =              { hmode,   read_htinst,      write_htinst     },
1462     [CSR_HGEIP] =               { hmode,   read_hgeip,       write_hgeip      },
1463     [CSR_HGATP] =               { hmode,   read_hgatp,       write_hgatp      },
1464     [CSR_HTIMEDELTA] =          { hmode,   read_htimedelta,  write_htimedelta },
1465     [CSR_HTIMEDELTAH] =         { hmode32,   read_htimedeltah, write_htimedeltah},
1466
1467     [CSR_VSSTATUS] =            { hmode,   read_vsstatus,    write_vsstatus   },
1468     [CSR_VSIP] =                { hmode,   NULL,     NULL,     rmw_vsip       },
1469     [CSR_VSIE] =                { hmode,   read_vsie,        write_vsie       },
1470     [CSR_VSTVEC] =              { hmode,   read_vstvec,      write_vstvec     },
1471     [CSR_VSSCRATCH] =           { hmode,   read_vsscratch,   write_vsscratch  },
1472     [CSR_VSEPC] =               { hmode,   read_vsepc,       write_vsepc      },
1473     [CSR_VSCAUSE] =             { hmode,   read_vscause,     write_vscause    },
1474     [CSR_VSTVAL] =              { hmode,   read_vstval,      write_vstval     },
1475     [CSR_VSATP] =               { hmode,   read_vsatp,       write_vsatp      },
1476
1477     [CSR_MTVAL2] =              { hmode,   read_mtval2,      write_mtval2     },
1478     [CSR_MTINST] =              { hmode,   read_mtinst,      write_mtinst     },
1479
1480     /* Physical Memory Protection */
1481     [CSR_PMPCFG0  ... CSR_PMPCFG3]   = { pmp,   read_pmpcfg,  write_pmpcfg   },
1482     [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp,   read_pmpaddr, write_pmpaddr  },
1483
1484     /* Performance Counters */
1485     [CSR_HPMCOUNTER3   ... CSR_HPMCOUNTER31] =    { ctr,  read_zero          },
1486     [CSR_MHPMCOUNTER3  ... CSR_MHPMCOUNTER31] =   { any,  read_zero          },
1487     [CSR_MHPMEVENT3    ... CSR_MHPMEVENT31] =     { any,  read_zero          },
1488     [CSR_HPMCOUNTER3H  ... CSR_HPMCOUNTER31H] =   { ctr32,  read_zero        },
1489     [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] =  { any32,  read_zero        },
1490 #endif /* !CONFIG_USER_ONLY */
1491 };