hw/arm/s3c24xx_memc.c

   1 /* hw/s3c24xx_memc.c
   2  *
   3  * Samsung S3C24XX memory controller emulation.
   4  *
   5  * The SDRAM controller on several S3C SOC is generic, the emulation needs to
   6  * be little more than backing the registers.
   7  *
   8  * Copyright 2006, 2007 Daniel Silverstone and Vincent Sanders
   9  *
  10  * Copyright 2010, 2013 Stefan Weil
  11  *
  12  * This file is under the terms of the GNU General Public License Version 2.
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "cpu.h"
  17 #include "hw/hw.h"
  18 #include "exec/address-spaces.h" /* get_system_memory */
  19 #include "migration/register.h"  /* register_savevm_live */
  20
  21 #include "s3c24xx.h"
  22
  23 /* Memory controller state */
  24 struct s3c24xx_memc_state_s {
  25     MemoryRegion mmio;
  26     uint32_t memc_reg[13];
  27 };
  28
  29 static void s3c24xx_memc_write(void *opaque, hwaddr addr_,
  30                                uint64_t value, unsigned size)
  31 {
  32     struct s3c24xx_memc_state_s *s = opaque;
  33     int addr = (addr_ & 0x3f) >> 2;
  34
  35     if (addr < 0 || addr > 12)
  36         addr = 12;
  37
  38     s->memc_reg[addr] = value;
  39 }
  40
  41 static uint64_t s3c24xx_memc_read(void *opaque, hwaddr addr_,
  42                                   unsigned size)
  43 {
  44     struct s3c24xx_memc_state_s *s = opaque;
  45     int addr = (addr_ & 0x3f) >> 2;
  46
  47     if (addr < 0 || addr > 12)
  48         addr = 12;
  49
  50     return s->memc_reg[addr];
  51 }
  52
  53 static const MemoryRegionOps s3c24xx_memc_ops = {
  54     .read = s3c24xx_memc_read,
  55     .write = s3c24xx_memc_write,
  56     .endianness = DEVICE_NATIVE_ENDIAN,
  57     .valid = {
  58         .min_access_size = 1,
  59         .max_access_size = 4
  60     }
  61 };
  62
  63 static void s3c24xx_memc_save(QEMUFile *f, void *opaque)
  64 {
  65     struct s3c24xx_memc_state_s *s = opaque;
  66     int i;
  67
  68     for (i = 0; i < 13; i ++)
  69         qemu_put_be32s(f, &s->memc_reg[i]);
  70 }
  71
  72 static int s3c24xx_memc_load(QEMUFile *f, void *opaque, int version_id)
  73 {
  74     struct s3c24xx_memc_state_s *s = opaque;
  75     int i;
  76
  77     for (i = 0; i < 13; i ++)
  78         qemu_get_be32s(f, &s->memc_reg[i]);
  79
  80     return 0;
  81 }
  82
  83 static SaveVMHandlers savevm_s3c24xx_memc = {
  84     .save_state = s3c24xx_memc_save,
  85     .load_state = s3c24xx_memc_load
  86 };
  87
  88 struct s3c24xx_memc_state_s *
  89 s3c24xx_memc_init(hwaddr base_addr)
  90 {
  91     /* Memory controller is simple SDRAM control. As SDRAM is emulated and
  92      * requires no setup the emulation needs to be nothing more than memory
  93      * backing the registers.
  94      *
  95      * There are 13 registers, each 4 bytes.
  96      */
  97     struct s3c24xx_memc_state_s *s = g_new0(struct s3c24xx_memc_state_s, 1);
  98
  99     memory_region_init_io(&s->mmio, OBJECT(s), &s3c24xx_memc_ops, s,
 100                           "s3c24xx.memc", 13 * 4);
 101     memory_region_add_subregion(get_system_memory(), base_addr, &s->mmio);
 102     register_savevm_live(NULL, "s3c24xx_memc", 0, 0, &savevm_s3c24xx_memc, s);
 103
 104     return s;
 105 }