hw/arm/s3c24xx_memc.c

   1 /* hw/s3c24xx_memc.c
   2  *
   3  * Samsung S3C24XX memory controller emulation.
   4  *
   5  * The SDRAM controller on several S3C SOC is generic, the emulation needs to
   6  * be little more than backing the registers.
   7  *
   8  * Copyright 2006, 2007 Daniel Silverstone and Vincent Sanders
   9  *
  10  * Copyright 2010, 2013, 2020 Stefan Weil
  11  *
  12  * This file is under the terms of the GNU General Public License Version 2.
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "cpu.h"
  17 #include "exec/address-spaces.h" /* get_system_memory */
  18 #include "hw/hw.h"
  19 #include "migration/qemu-file-types.h" /* qemu_put_be32s */
  20 #include "migration/register.h"  /* register_savevm_live */
  21
  22 #include "s3c24xx.h"
  23
  24 /* Memory controller state */
  25 struct s3c24xx_memc_state_s {
  26     MemoryRegion mmio;
  27     uint32_t memc_reg[13];
  28 };
  29
  30 static void s3c24xx_memc_write(void *opaque, hwaddr addr_,
  31                                uint64_t value, unsigned size)
  32 {
  33     struct s3c24xx_memc_state_s *s = opaque;
  34     int addr = (addr_ & 0x3f) >> 2;
  35
  36     if (addr < 0 || addr > 12)
  37         addr = 12;
  38
  39     s->memc_reg[addr] = value;
  40 }
  41
  42 static uint64_t s3c24xx_memc_read(void *opaque, hwaddr addr_,
  43                                   unsigned size)
  44 {
  45     struct s3c24xx_memc_state_s *s = opaque;
  46     int addr = (addr_ & 0x3f) >> 2;
  47
  48     if (addr < 0 || addr > 12)
  49         addr = 12;
  50
  51     return s->memc_reg[addr];
  52 }
  53
  54 static const MemoryRegionOps s3c24xx_memc_ops = {
  55     .read = s3c24xx_memc_read,
  56     .write = s3c24xx_memc_write,
  57     .endianness = DEVICE_NATIVE_ENDIAN,
  58     .valid = {
  59         .min_access_size = 1,
  60         .max_access_size = 4
  61     }
  62 };
  63
  64 static void s3c24xx_memc_save(QEMUFile *f, void *opaque)
  65 {
  66     struct s3c24xx_memc_state_s *s = opaque;
  67     int i;
  68
  69     for (i = 0; i < 13; i ++)
  70         qemu_put_be32s(f, &s->memc_reg[i]);
  71 }
  72
  73 static int s3c24xx_memc_load(QEMUFile *f, void *opaque, int version_id)
  74 {
  75     struct s3c24xx_memc_state_s *s = opaque;
  76     int i;
  77
  78     for (i = 0; i < 13; i ++)
  79         qemu_get_be32s(f, &s->memc_reg[i]);
  80
  81     return 0;
  82 }
  83
  84 static SaveVMHandlers savevm_s3c24xx_memc = {
  85     .save_state = s3c24xx_memc_save,
  86     .load_state = s3c24xx_memc_load
  87 };
  88
  89 struct s3c24xx_memc_state_s *
  90 s3c24xx_memc_init(hwaddr base_addr)
  91 {
  92     /* Memory controller is simple SDRAM control. As SDRAM is emulated and
  93      * requires no setup the emulation needs to be nothing more than memory
  94      * backing the registers.
  95      *
  96      * There are 13 registers, each 4 bytes.
  97      */
  98     struct s3c24xx_memc_state_s *s = g_new0(struct s3c24xx_memc_state_s, 1);
  99
 100     memory_region_init_io(&s->mmio, OBJECT(s), &s3c24xx_memc_ops, s,
 101                           "s3c24xx.memc", 13 * 4);
 102     memory_region_add_subregion(get_system_memory(), base_addr, &s->mmio);
 103     register_savevm_live("s3c24xx_memc", 0, 0, &savevm_s3c24xx_memc, s);
 104
 105     return s;
 106 }