target/ppc/gdbstub.c

   1 /*
   2  * PowerPC gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2013 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu/osdep.h"
  21 #include "qemu-common.h"
  22 #include "cpu.h"
  23 #include "exec/gdbstub.h"
  24
  25 static int ppc_gdb_register_len_apple(int n)
  26 {
  27     switch (n) {
  28     case 0 ... 31:
  29         /* gprs */
  30         return 8;
  31     case 32 ... 63:
  32         /* fprs */
  33         return 8;
  34     case 64 ... 95:
  35         return 16;
  36     case 64 + 32: /* nip */
  37     case 65 + 32: /* msr */
  38     case 67 + 32: /* lr */
  39     case 68 + 32: /* ctr */
  40     case 70 + 32: /* fpscr */
  41         return 8;
  42     case 66 + 32: /* cr */
  43     case 69 + 32: /* xer */
  44         return 4;
  45     default:
  46         return 0;
  47     }
  48 }
  49
  50 static int ppc_gdb_register_len(int n)
  51 {
  52     switch (n) {
  53     case 0 ... 31:
  54         /* gprs */
  55         return sizeof(target_ulong);
  56     case 32 ... 63:
  57         /* fprs */
  58         if (gdb_has_xml) {
  59             return 0;
  60         }
  61         return 8;
  62     case 66:
  63         /* cr */
  64     case 69:
  65         /* xer */
  66         return 4;
  67     case 64:
  68         /* nip */
  69     case 65:
  70         /* msr */
  71     case 67:
  72         /* lr */
  73     case 68:
  74         /* ctr */
  75         return sizeof(target_ulong);
  76     case 70:
  77         /* fpscr */
  78         if (gdb_has_xml) {
  79             return 0;
  80         }
  81         return sizeof(target_ulong);
  82     default:
  83         return 0;
  84     }
  85 }
  86
  87 /*
  88  * We need to present the registers to gdb in the "current" memory
  89  * ordering.  For user-only mode we get this for free;
  90  * TARGET_WORDS_BIGENDIAN is set to the proper ordering for the
  91  * binary, and cannot be changed.  For system mode,
  92  * TARGET_WORDS_BIGENDIAN is always set, and we must check the current
  93  * mode of the chip to see if we're running in little-endian.
  94  */
  95 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
  96 {
  97 #ifndef CONFIG_USER_ONLY
  98     if (!msr_le) {
  99         /* do nothing */
 100     } else if (len == 4) {
 101         bswap32s((uint32_t *)mem_buf);
 102     } else if (len == 8) {
 103         bswap64s((uint64_t *)mem_buf);
 104     } else {
 105         g_assert_not_reached();
 106     }
 107 #endif
 108 }
 109
 110 /*
 111  * Old gdb always expects FP registers.  Newer (xml-aware) gdb only
 112  * expects whatever the target description contains.  Due to a
 113  * historical mishap the FP registers appear in between core integer
 114  * regs and PC, MSR, CR, and so forth.  We hack round this by giving
 115  * the FP regs zero size when talking to a newer gdb.
 116  */
 117
 118 int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
 119 {
 120     PowerPCCPU *cpu = POWERPC_CPU(cs);
 121     CPUPPCState *env = &cpu->env;
 122     int r = ppc_gdb_register_len(n);
 123
 124     if (!r) {
 125         return r;
 126     }
 127
 128     if (n < 32) {
 129         /* gprs */
 130         gdb_get_regl(mem_buf, env->gpr[n]);
 131     } else if (n < 64) {
 132         /* fprs */
 133         stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32));
 134     } else {
 135         switch (n) {
 136         case 64:
 137             gdb_get_regl(mem_buf, env->nip);
 138             break;
 139         case 65:
 140             gdb_get_regl(mem_buf, env->msr);
 141             break;
 142         case 66:
 143             {
 144                 uint32_t cr = 0;
 145                 int i;
 146                 for (i = 0; i < 8; i++) {
 147                     cr |= env->crf[i] << (32 - ((i + 1) * 4));
 148                 }
 149                 gdb_get_reg32(mem_buf, cr);
 150                 break;
 151             }
 152         case 67:
 153             gdb_get_regl(mem_buf, env->lr);
 154             break;
 155         case 68:
 156             gdb_get_regl(mem_buf, env->ctr);
 157             break;
 158         case 69:
 159             gdb_get_reg32(mem_buf, env->xer);
 160             break;
 161         case 70:
 162             gdb_get_reg32(mem_buf, env->fpscr);
 163             break;
 164         }
 165     }
 166     ppc_maybe_bswap_register(env, mem_buf, r);
 167     return r;
 168 }
 169
 170 int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
 171 {
 172     PowerPCCPU *cpu = POWERPC_CPU(cs);
 173     CPUPPCState *env = &cpu->env;
 174     int r = ppc_gdb_register_len_apple(n);
 175
 176     if (!r) {
 177         return r;
 178     }
 179
 180     if (n < 32) {
 181         /* gprs */
 182         gdb_get_reg64(mem_buf, env->gpr[n]);
 183     } else if (n < 64) {
 184         /* fprs */
 185         stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32));
 186     } else if (n < 96) {
 187         /* Altivec */
 188         stq_p(mem_buf, n - 64);
 189         stq_p(mem_buf + 8, 0);
 190     } else {
 191         switch (n) {
 192         case 64 + 32:
 193             gdb_get_reg64(mem_buf, env->nip);
 194             break;
 195         case 65 + 32:
 196             gdb_get_reg64(mem_buf, env->msr);
 197             break;
 198         case 66 + 32:
 199             {
 200                 uint32_t cr = 0;
 201                 int i;
 202                 for (i = 0; i < 8; i++) {
 203                     cr |= env->crf[i] << (32 - ((i + 1) * 4));
 204                 }
 205                 gdb_get_reg32(mem_buf, cr);
 206                 break;
 207             }
 208         case 67 + 32:
 209             gdb_get_reg64(mem_buf, env->lr);
 210             break;
 211         case 68 + 32:
 212             gdb_get_reg64(mem_buf, env->ctr);
 213             break;
 214         case 69 + 32:
 215             gdb_get_reg32(mem_buf, env->xer);
 216             break;
 217         case 70 + 32:
 218             gdb_get_reg64(mem_buf, env->fpscr);
 219             break;
 220         }
 221     }
 222     ppc_maybe_bswap_register(env, mem_buf, r);
 223     return r;
 224 }
 225
 226 int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 227 {
 228     PowerPCCPU *cpu = POWERPC_CPU(cs);
 229     CPUPPCState *env = &cpu->env;
 230     int r = ppc_gdb_register_len(n);
 231
 232     if (!r) {
 233         return r;
 234     }
 235     ppc_maybe_bswap_register(env, mem_buf, r);
 236     if (n < 32) {
 237         /* gprs */
 238         env->gpr[n] = ldtul_p(mem_buf);
 239     } else if (n < 64) {
 240         /* fprs */
 241         *cpu_fpr_ptr(env, n - 32) = ldfq_p(mem_buf);
 242     } else {
 243         switch (n) {
 244         case 64:
 245             env->nip = ldtul_p(mem_buf);
 246             break;
 247         case 65:
 248             ppc_store_msr(env, ldtul_p(mem_buf));
 249             break;
 250         case 66:
 251             {
 252                 uint32_t cr = ldl_p(mem_buf);
 253                 int i;
 254                 for (i = 0; i < 8; i++) {
 255                     env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
 256                 }
 257                 break;
 258             }
 259         case 67:
 260             env->lr = ldtul_p(mem_buf);
 261             break;
 262         case 68:
 263             env->ctr = ldtul_p(mem_buf);
 264             break;
 265         case 69:
 266             env->xer = ldl_p(mem_buf);
 267             break;
 268         case 70:
 269             /* fpscr */
 270             store_fpscr(env, ldtul_p(mem_buf), 0xffffffff);
 271             break;
 272         }
 273     }
 274     return r;
 275 }
 276 int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
 277 {
 278     PowerPCCPU *cpu = POWERPC_CPU(cs);
 279     CPUPPCState *env = &cpu->env;
 280     int r = ppc_gdb_register_len_apple(n);
 281
 282     if (!r) {
 283         return r;
 284     }
 285     ppc_maybe_bswap_register(env, mem_buf, r);
 286     if (n < 32) {
 287         /* gprs */
 288         env->gpr[n] = ldq_p(mem_buf);
 289     } else if (n < 64) {
 290         /* fprs */
 291         *cpu_fpr_ptr(env, n - 32) = ldfq_p(mem_buf);
 292     } else {
 293         switch (n) {
 294         case 64 + 32:
 295             env->nip = ldq_p(mem_buf);
 296             break;
 297         case 65 + 32:
 298             ppc_store_msr(env, ldq_p(mem_buf));
 299             break;
 300         case 66 + 32:
 301             {
 302                 uint32_t cr = ldl_p(mem_buf);
 303                 int i;
 304                 for (i = 0; i < 8; i++) {
 305                     env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
 306                 }
 307                 break;
 308             }
 309         case 67 + 32:
 310             env->lr = ldq_p(mem_buf);
 311             break;
 312         case 68 + 32:
 313             env->ctr = ldq_p(mem_buf);
 314             break;
 315         case 69 + 32:
 316             env->xer = ldl_p(mem_buf);
 317             break;
 318         case 70 + 32:
 319             /* fpscr */
 320             store_fpscr(env, ldq_p(mem_buf), 0xffffffff);
 321             break;
 322         }
 323     }
 324     return r;
 325 }
 326
 327 #ifndef CONFIG_USER_ONLY
 328 void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu)
 329 {
 330     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 331     CPUPPCState *env = &cpu->env;
 332     GString *xml;
 333     char *spr_name;
 334     unsigned int num_regs = 0;
 335     int i;
 336
 337     if (pcc->gdb_spr_xml) {
 338         return;
 339     }
 340
 341     xml = g_string_new("<?xml version=\"1.0\"?>");
 342     g_string_append(xml, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 343     g_string_append(xml, "<feature name=\"org.qemu.power.spr\">");
 344
 345     for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
 346         ppc_spr_t *spr = &env->spr_cb[i];
 347
 348         if (!spr->name) {
 349             continue;
 350         }
 351
 352         spr_name = g_ascii_strdown(spr->name, -1);
 353         g_string_append_printf(xml, "<reg name=\"%s\"", spr_name);
 354         g_free(spr_name);
 355
 356         g_string_append_printf(xml, " bitsize=\"%d\"", TARGET_LONG_BITS);
 357         g_string_append(xml, " group=\"spr\"/>");
 358
 359         /*
 360          * GDB identifies registers based on the order they are
 361          * presented in the XML. These ids will not match QEMU's
 362          * representation (which follows the PowerISA).
 363          *
 364          * Store the position of the current register description so
 365          * we can make the correspondence later.
 366          */
 367         spr->gdb_id = num_regs;
 368         num_regs++;
 369     }
 370
 371     g_string_append(xml, "</feature>");
 372
 373     pcc->gdb_num_sprs = num_regs;
 374     pcc->gdb_spr_xml = g_string_free(xml, false);
 375 }
 376
 377 const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name)
 378 {
 379     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
 380
 381     if (strcmp(xml_name, "power-spr.xml") == 0) {
 382         return pcc->gdb_spr_xml;
 383     }
 384     return NULL;
 385 }
 386 #endif