hw/ide/cmd646.c

   1 /*
   2  * QEMU IDE Emulation: PCI cmd646 support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "qemu/osdep.h"
  26 #include "hw/hw.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/isa/isa.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/dma.h"
  31
  32 #include "hw/ide/pci.h"
  33 #include "trace.h"
  34
  35 /* CMD646 specific */
  36 #define CFR             0x50
  37 #define   CFR_INTR_CH0  0x04
  38 #define CNTRL           0x51
  39 #define   CNTRL_EN_CH0  0x04
  40 #define   CNTRL_EN_CH1  0x08
  41 #define ARTTIM23        0x57
  42 #define    ARTTIM23_INTR_CH1    0x10
  43 #define MRDMODE         0x71
  44 #define   MRDMODE_INTR_CH0      0x04
  45 #define   MRDMODE_INTR_CH1      0x08
  46 #define   MRDMODE_BLK_CH0       0x10
  47 #define   MRDMODE_BLK_CH1       0x20
  48 #define UDIDETCR0       0x73
  49 #define UDIDETCR1       0x7B
  50
  51 static void cmd646_update_irq(PCIDevice *pd);
  52
  53 static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
  54                                 unsigned size)
  55 {
  56     CMD646BAR *cmd646bar = opaque;
  57
  58     if (addr != 2 || size != 1) {
  59         return ((uint64_t)1 << (size * 8)) - 1;
  60     }
  61     return ide_status_read(cmd646bar->bus, addr + 2);
  62 }
  63
  64 static void cmd646_cmd_write(void *opaque, hwaddr addr,
  65                              uint64_t data, unsigned size)
  66 {
  67     CMD646BAR *cmd646bar = opaque;
  68
  69     if (addr != 2 || size != 1) {
  70         return;
  71     }
  72     ide_cmd_write(cmd646bar->bus, addr + 2, data);
  73 }
  74
  75 static const MemoryRegionOps cmd646_cmd_ops = {
  76     .read = cmd646_cmd_read,
  77     .write = cmd646_cmd_write,
  78     .endianness = DEVICE_LITTLE_ENDIAN,
  79 };
  80
  81 static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
  82                                  unsigned size)
  83 {
  84     CMD646BAR *cmd646bar = opaque;
  85
  86     if (size == 1) {
  87         return ide_ioport_read(cmd646bar->bus, addr);
  88     } else if (addr == 0) {
  89         if (size == 2) {
  90             return ide_data_readw(cmd646bar->bus, addr);
  91         } else {
  92             return ide_data_readl(cmd646bar->bus, addr);
  93         }
  94     }
  95     return ((uint64_t)1 << (size * 8)) - 1;
  96 }
  97
  98 static void cmd646_data_write(void *opaque, hwaddr addr,
  99                              uint64_t data, unsigned size)
 100 {
 101     CMD646BAR *cmd646bar = opaque;
 102
 103     if (size == 1) {
 104         ide_ioport_write(cmd646bar->bus, addr, data);
 105     } else if (addr == 0) {
 106         if (size == 2) {
 107             ide_data_writew(cmd646bar->bus, addr, data);
 108         } else {
 109             ide_data_writel(cmd646bar->bus, addr, data);
 110         }
 111     }
 112 }
 113
 114 static const MemoryRegionOps cmd646_data_ops = {
 115     .read = cmd646_data_read,
 116     .write = cmd646_data_write,
 117     .endianness = DEVICE_LITTLE_ENDIAN,
 118 };
 119
 120 static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
 121 {
 122     IDEBus *bus = &d->bus[bus_num];
 123     CMD646BAR *bar = &d->cmd646_bar[bus_num];
 124
 125     bar->bus = bus;
 126     memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
 127                           "cmd646-cmd", 4);
 128     memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
 129                           "cmd646-data", 8);
 130 }
 131
 132 static void cmd646_update_dma_interrupts(PCIDevice *pd)
 133 {
 134     /* Sync DMA interrupt status from UDMA interrupt status */
 135     if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
 136         pd->config[CFR] |= CFR_INTR_CH0;
 137     } else {
 138         pd->config[CFR] &= ~CFR_INTR_CH0;
 139     }
 140
 141     if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
 142         pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1;
 143     } else {
 144         pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
 145     }
 146 }
 147
 148 static void cmd646_update_udma_interrupts(PCIDevice *pd)
 149 {
 150     /* Sync UDMA interrupt status from DMA interrupt status */
 151     if (pd->config[CFR] & CFR_INTR_CH0) {
 152         pd->config[MRDMODE] |= MRDMODE_INTR_CH0;
 153     } else {
 154         pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
 155     }
 156
 157     if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
 158         pd->config[MRDMODE] |= MRDMODE_INTR_CH1;
 159     } else {
 160         pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
 161     }
 162 }
 163
 164 static uint64_t bmdma_read(void *opaque, hwaddr addr,
 165                            unsigned size)
 166 {
 167     BMDMAState *bm = opaque;
 168     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 169     uint32_t val;
 170
 171     if (size != 1) {
 172         return ((uint64_t)1 << (size * 8)) - 1;
 173     }
 174
 175     switch(addr & 3) {
 176     case 0:
 177         val = bm->cmd;
 178         break;
 179     case 1:
 180         val = pci_dev->config[MRDMODE];
 181         break;
 182     case 2:
 183         val = bm->status;
 184         break;
 185     case 3:
 186         if (bm == &bm->pci_dev->bmdma[0]) {
 187             val = pci_dev->config[UDIDETCR0];
 188         } else {
 189             val = pci_dev->config[UDIDETCR1];
 190         }
 191         break;
 192     default:
 193         val = 0xff;
 194         break;
 195     }
 196
 197     trace_bmdma_read_cmd646(addr, val);
 198     return val;
 199 }
 200
 201 static void bmdma_write(void *opaque, hwaddr addr,
 202                         uint64_t val, unsigned size)
 203 {
 204     BMDMAState *bm = opaque;
 205     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 206
 207     if (size != 1) {
 208         return;
 209     }
 210
 211     trace_bmdma_write_cmd646(addr, val);
 212     switch(addr & 3) {
 213     case 0:
 214         bmdma_cmd_writeb(bm, val);
 215         break;
 216     case 1:
 217         pci_dev->config[MRDMODE] =
 218             (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
 219         cmd646_update_dma_interrupts(pci_dev);
 220         cmd646_update_irq(pci_dev);
 221         break;
 222     case 2:
 223         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
 224         break;
 225     case 3:
 226         if (bm == &bm->pci_dev->bmdma[0]) {
 227             pci_dev->config[UDIDETCR0] = val;
 228         } else {
 229             pci_dev->config[UDIDETCR1] = val;
 230         }
 231         break;
 232     }
 233 }
 234
 235 static const MemoryRegionOps cmd646_bmdma_ops = {
 236     .read = bmdma_read,
 237     .write = bmdma_write,
 238 };
 239
 240 static void bmdma_setup_bar(PCIIDEState *d)
 241 {
 242     BMDMAState *bm;
 243     int i;
 244
 245     memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
 246     for(i = 0;i < 2; i++) {
 247         bm = &d->bmdma[i];
 248         memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
 249                               "cmd646-bmdma-bus", 4);
 250         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
 251         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
 252                               &bmdma_addr_ioport_ops, bm,
 253                               "cmd646-bmdma-ioport", 4);
 254         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 255     }
 256 }
 257
 258 static void cmd646_update_irq(PCIDevice *pd)
 259 {
 260     int pci_level;
 261
 262     pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
 263                  !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
 264         ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
 265          !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
 266     pci_set_irq(pd, pci_level);
 267 }
 268
 269 /* the PCI irq level is the logical OR of the two channels */
 270 static void cmd646_set_irq(void *opaque, int channel, int level)
 271 {
 272     PCIIDEState *d = opaque;
 273     PCIDevice *pd = PCI_DEVICE(d);
 274     int irq_mask;
 275
 276     irq_mask = MRDMODE_INTR_CH0 << channel;
 277     if (level) {
 278         pd->config[MRDMODE] |= irq_mask;
 279     } else {
 280         pd->config[MRDMODE] &= ~irq_mask;
 281     }
 282     cmd646_update_dma_interrupts(pd);
 283     cmd646_update_irq(pd);
 284 }
 285
 286 static void cmd646_reset(void *opaque)
 287 {
 288     PCIIDEState *d = opaque;
 289     unsigned int i;
 290
 291     for (i = 0; i < 2; i++) {
 292         ide_bus_reset(&d->bus[i]);
 293     }
 294 }
 295
 296 static uint32_t cmd646_pci_config_read(PCIDevice *d,
 297                                        uint32_t address, int len)
 298 {
 299     return pci_default_read_config(d, address, len);
 300 }
 301
 302 static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
 303                                     int l)
 304 {
 305     uint32_t i;
 306
 307     pci_default_write_config(d, addr, val, l);
 308
 309     for (i = addr; i < addr + l; i++) {
 310         switch (i) {
 311         case CFR:
 312         case ARTTIM23:
 313             cmd646_update_udma_interrupts(d);
 314             break;
 315         case MRDMODE:
 316             cmd646_update_dma_interrupts(d);
 317             break;
 318         }
 319     }
 320
 321     cmd646_update_irq(d);
 322 }
 323
 324 /* CMD646 PCI IDE controller */
 325 static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
 326 {
 327     PCIIDEState *d = PCI_IDE(dev);
 328     uint8_t *pci_conf = dev->config;
 329     qemu_irq *irq;
 330     int i;
 331
 332     pci_conf[PCI_CLASS_PROG] = 0x8f;
 333
 334     pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
 335     if (d->secondary) {
 336         /* XXX: if not enabled, really disable the seconday IDE controller */
 337         pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */
 338     }
 339
 340     /* Set write-to-clear interrupt bits */
 341     dev->wmask[CFR] = 0x0;
 342     dev->w1cmask[CFR] = CFR_INTR_CH0;
 343     dev->wmask[ARTTIM23] = 0x0;
 344     dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
 345     dev->wmask[MRDMODE] = 0x0;
 346     dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;
 347
 348     setup_cmd646_bar(d, 0);
 349     setup_cmd646_bar(d, 1);
 350     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
 351     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
 352     pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
 353     pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
 354     bmdma_setup_bar(d);
 355     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 356
 357     /* TODO: RST# value should be 0 */
 358     pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
 359
 360     irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
 361     for (i = 0; i < 2; i++) {
 362         ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
 363         ide_init2(&d->bus[i], irq[i]);
 364
 365         bmdma_init(&d->bus[i], &d->bmdma[i], d);
 366         d->bmdma[i].bus = &d->bus[i];
 367         ide_register_restart_cb(&d->bus[i]);
 368     }
 369
 370     vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
 371     qemu_register_reset(cmd646_reset, d);
 372 }
 373
 374 static void pci_cmd646_ide_exitfn(PCIDevice *dev)
 375 {
 376     PCIIDEState *d = PCI_IDE(dev);
 377     unsigned i;
 378
 379     for (i = 0; i < 2; ++i) {
 380         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 381         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 382     }
 383 }
 384
 385 void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
 386                          int secondary_ide_enabled)
 387 {
 388     PCIDevice *dev;
 389
 390     dev = pci_create(bus, -1, "cmd646-ide");
 391     qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
 392     qdev_init_nofail(&dev->qdev);
 393
 394     pci_ide_create_devs(dev, hd_table);
 395 }
 396
 397 static Property cmd646_ide_properties[] = {
 398     DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
 399     DEFINE_PROP_END_OF_LIST(),
 400 };
 401
 402 static void cmd646_ide_class_init(ObjectClass *klass, void *data)
 403 {
 404     DeviceClass *dc = DEVICE_CLASS(klass);
 405     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 406
 407     k->realize = pci_cmd646_ide_realize;
 408     k->exit = pci_cmd646_ide_exitfn;
 409     k->vendor_id = PCI_VENDOR_ID_CMD;
 410     k->device_id = PCI_DEVICE_ID_CMD_646;
 411     k->revision = 0x07;
 412     k->class_id = PCI_CLASS_STORAGE_IDE;
 413     k->config_read = cmd646_pci_config_read;
 414     k->config_write = cmd646_pci_config_write;
 415     dc->props = cmd646_ide_properties;
 416     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 417 }
 418
 419 static const TypeInfo cmd646_ide_info = {
 420     .name          = "cmd646-ide",
 421     .parent        = TYPE_PCI_IDE,
 422     .class_init    = cmd646_ide_class_init,
 423 };
 424
 425 static void cmd646_ide_register_types(void)
 426 {
 427     type_register_static(&cmd646_ide_info);
 428 }
 429
 430 type_init(cmd646_ide_register_types)