hw/ide/cmd646.c

   1 /*
   2  * QEMU IDE Emulation: PCI cmd646 support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/qdev-properties.h"
  29 #include "migration/vmstate.h"
  30 #include "qemu/module.h"
  31 #include "hw/isa/isa.h"
  32 #include "sysemu/dma.h"
  33 #include "sysemu/reset.h"
  34
  35 #include "hw/ide/pci.h"
  36 #include "ide-internal.h"
  37 #include "trace.h"
  38
  39 /* CMD646 specific */
  40 #define CFR                  0x50
  41 #define   CFR_INTR_CH0       0x04
  42 #define CNTRL                0x51
  43 #define   CNTRL_EN_CH0       0x04
  44 #define   CNTRL_EN_CH1       0x08
  45 #define ARTTIM23             0x57
  46 #define    ARTTIM23_INTR_CH1 0x10
  47 #define MRDMODE              0x71
  48 #define   MRDMODE_INTR_CH0   0x04
  49 #define   MRDMODE_INTR_CH1   0x08
  50 #define   MRDMODE_BLK_CH0    0x10
  51 #define   MRDMODE_BLK_CH1    0x20
  52 #define UDIDETCR0            0x73
  53 #define UDIDETCR1            0x7B
  54
  55 static void cmd646_update_irq(PCIDevice *pd);
  56
  57 static void cmd646_update_dma_interrupts(PCIDevice *pd)
  58 {
  59     /* Sync DMA interrupt status from UDMA interrupt status */
  60     if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
  61         pd->config[CFR] |= CFR_INTR_CH0;
  62     } else {
  63         pd->config[CFR] &= ~CFR_INTR_CH0;
  64     }
  65
  66     if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
  67         pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1;
  68     } else {
  69         pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
  70     }
  71 }
  72
  73 static void cmd646_update_udma_interrupts(PCIDevice *pd)
  74 {
  75     /* Sync UDMA interrupt status from DMA interrupt status */
  76     if (pd->config[CFR] & CFR_INTR_CH0) {
  77         pd->config[MRDMODE] |= MRDMODE_INTR_CH0;
  78     } else {
  79         pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
  80     }
  81
  82     if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
  83         pd->config[MRDMODE] |= MRDMODE_INTR_CH1;
  84     } else {
  85         pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
  86     }
  87 }
  88
  89 static uint64_t bmdma_read(void *opaque, hwaddr addr,
  90                            unsigned size)
  91 {
  92     BMDMAState *bm = opaque;
  93     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
  94     uint32_t val;
  95
  96     if (size != 1) {
  97         return ((uint64_t)1 << (size * 8)) - 1;
  98     }
  99
 100     switch(addr & 3) {
 101     case 0:
 102         val = bm->cmd;
 103         break;
 104     case 1:
 105         val = pci_dev->config[MRDMODE];
 106         break;
 107     case 2:
 108         val = bm->status;
 109         break;
 110     case 3:
 111         if (bm == &bm->pci_dev->bmdma[0]) {
 112             val = pci_dev->config[UDIDETCR0];
 113         } else {
 114             val = pci_dev->config[UDIDETCR1];
 115         }
 116         break;
 117     default:
 118         val = 0xff;
 119         break;
 120     }
 121
 122     trace_bmdma_read_cmd646(addr, val);
 123     return val;
 124 }
 125
 126 static void bmdma_write(void *opaque, hwaddr addr,
 127                         uint64_t val, unsigned size)
 128 {
 129     BMDMAState *bm = opaque;
 130     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 131
 132     if (size != 1) {
 133         return;
 134     }
 135
 136     trace_bmdma_write_cmd646(addr, val);
 137     switch(addr & 3) {
 138     case 0:
 139         bmdma_cmd_writeb(bm, val);
 140         break;
 141     case 1:
 142         pci_dev->config[MRDMODE] =
 143             (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
 144         cmd646_update_dma_interrupts(pci_dev);
 145         cmd646_update_irq(pci_dev);
 146         break;
 147     case 2:
 148         bmdma_status_writeb(bm, val);
 149         break;
 150     case 3:
 151         if (bm == &bm->pci_dev->bmdma[0]) {
 152             pci_dev->config[UDIDETCR0] = val;
 153         } else {
 154             pci_dev->config[UDIDETCR1] = val;
 155         }
 156         break;
 157     }
 158 }
 159
 160 static const MemoryRegionOps cmd646_bmdma_ops = {
 161     .read = bmdma_read,
 162     .write = bmdma_write,
 163 };
 164
 165 static void bmdma_setup_bar(PCIIDEState *d)
 166 {
 167     BMDMAState *bm;
 168     int i;
 169
 170     memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
 171     for(i = 0;i < 2; i++) {
 172         bm = &d->bmdma[i];
 173         memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
 174                               "cmd646-bmdma-bus", 4);
 175         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
 176         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
 177                               &bmdma_addr_ioport_ops, bm,
 178                               "cmd646-bmdma-ioport", 4);
 179         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 180     }
 181 }
 182
 183 static void cmd646_update_irq(PCIDevice *pd)
 184 {
 185     int pci_level;
 186
 187     pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
 188                  !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
 189         ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
 190          !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
 191     pci_set_irq(pd, pci_level);
 192 }
 193
 194 /* the PCI irq level is the logical OR of the two channels */
 195 static void cmd646_set_irq(void *opaque, int channel, int level)
 196 {
 197     PCIIDEState *d = opaque;
 198     PCIDevice *pd = PCI_DEVICE(d);
 199     int irq_mask;
 200
 201     irq_mask = MRDMODE_INTR_CH0 << channel;
 202     if (level) {
 203         pd->config[MRDMODE] |= irq_mask;
 204     } else {
 205         pd->config[MRDMODE] &= ~irq_mask;
 206     }
 207     cmd646_update_dma_interrupts(pd);
 208     cmd646_update_irq(pd);
 209 }
 210
 211 static void cmd646_reset(DeviceState *dev)
 212 {
 213     PCIIDEState *d = PCI_IDE(dev);
 214     unsigned int i;
 215
 216     for (i = 0; i < 2; i++) {
 217         ide_bus_reset(&d->bus[i]);
 218     }
 219 }
 220
 221 static uint32_t cmd646_pci_config_read(PCIDevice *d,
 222                                        uint32_t address, int len)
 223 {
 224     return pci_default_read_config(d, address, len);
 225 }
 226
 227 static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
 228                                     int l)
 229 {
 230     uint32_t i;
 231
 232     pci_default_write_config(d, addr, val, l);
 233
 234     for (i = addr; i < addr + l; i++) {
 235         switch (i) {
 236         case CFR:
 237         case ARTTIM23:
 238             cmd646_update_udma_interrupts(d);
 239             break;
 240         case MRDMODE:
 241             cmd646_update_dma_interrupts(d);
 242             break;
 243         }
 244     }
 245
 246     cmd646_update_irq(d);
 247 }
 248
 249 /* CMD646 PCI IDE controller */
 250 static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
 251 {
 252     PCIIDEState *d = PCI_IDE(dev);
 253     DeviceState *ds = DEVICE(dev);
 254     uint8_t *pci_conf = dev->config;
 255     int i;
 256
 257     pci_conf[PCI_CLASS_PROG] = 0x8f;
 258
 259     pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
 260     if (d->secondary) {
 261         /* XXX: if not enabled, really disable the secondary IDE controller */
 262         pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */
 263     }
 264
 265     /* Set write-to-clear interrupt bits */
 266     dev->wmask[CFR] = 0x0;
 267     dev->w1cmask[CFR] = CFR_INTR_CH0;
 268     dev->wmask[ARTTIM23] = 0x0;
 269     dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
 270     dev->wmask[MRDMODE] = 0x0;
 271     dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;
 272
 273     memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
 274                           &d->bus[0], "cmd646-data0", 8);
 275     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);
 276
 277     memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
 278                           &d->bus[0], "cmd646-cmd0", 4);
 279     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);
 280
 281     memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
 282                           &d->bus[1], "cmd646-data1", 8);
 283     pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);
 284
 285     memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
 286                           &d->bus[1], "cmd646-cmd1", 4);
 287     pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);
 288
 289     bmdma_setup_bar(d);
 290     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 291
 292     /* TODO: RST# value should be 0 */
 293     pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
 294
 295     qdev_init_gpio_in(ds, cmd646_set_irq, 2);
 296     for (i = 0; i < 2; i++) {
 297         ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
 298         ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));
 299
 300         bmdma_init(&d->bus[i], &d->bmdma[i], d);
 301         ide_bus_register_restart_cb(&d->bus[i]);
 302     }
 303 }
 304
 305 static void pci_cmd646_ide_exitfn(PCIDevice *dev)
 306 {
 307     PCIIDEState *d = PCI_IDE(dev);
 308     unsigned i;
 309
 310     for (i = 0; i < 2; ++i) {
 311         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 312         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 313     }
 314 }
 315
 316 static Property cmd646_ide_properties[] = {
 317     DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
 318     DEFINE_PROP_END_OF_LIST(),
 319 };
 320
 321 static void cmd646_ide_class_init(ObjectClass *klass, void *data)
 322 {
 323     DeviceClass *dc = DEVICE_CLASS(klass);
 324     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 325
 326     dc->reset = cmd646_reset;
 327     dc->vmsd = &vmstate_ide_pci;
 328     k->realize = pci_cmd646_ide_realize;
 329     k->exit = pci_cmd646_ide_exitfn;
 330     k->vendor_id = PCI_VENDOR_ID_CMD;
 331     k->device_id = PCI_DEVICE_ID_CMD_646;
 332     k->revision = 0x07;
 333     k->class_id = PCI_CLASS_STORAGE_IDE;
 334     k->config_read = cmd646_pci_config_read;
 335     k->config_write = cmd646_pci_config_write;
 336     device_class_set_props(dc, cmd646_ide_properties);
 337     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 338 }
 339
 340 static const TypeInfo cmd646_ide_info = {
 341     .name          = "cmd646-ide",
 342     .parent        = TYPE_PCI_IDE,
 343     .class_init    = cmd646_ide_class_init,
 344 };
 345
 346 static void cmd646_ide_register_types(void)
 347 {
 348     type_register_static(&cmd646_ide_info);
 349 }
 350
 351 type_init(cmd646_ide_register_types)