2 * QEMU PowerPC PowerNV machine model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/units.h"
23 #include "qapi/error.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/numa.h"
26 #include "sysemu/reset.h"
27 #include "sysemu/runstate.h"
28 #include "sysemu/cpus.h"
29 #include "sysemu/device_tree.h"
30 #include "target/ppc/cpu.h"
32 #include "hw/ppc/fdt.h"
33 #include "hw/ppc/ppc.h"
34 #include "hw/ppc/pnv.h"
35 #include "hw/ppc/pnv_core.h"
36 #include "hw/loader.h"
37 #include "exec/address-spaces.h"
38 #include "qapi/visitor.h"
39 #include "monitor/monitor.h"
40 #include "hw/intc/intc.h"
41 #include "hw/ipmi/ipmi.h"
42 #include "target/ppc/mmu-hash64.h"
44 #include "hw/ppc/xics.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/ppc/pnv_xscom.h"
47 #include "hw/ppc/pnv_pnor.h"
49 #include "hw/isa/isa.h"
50 #include "hw/boards.h"
51 #include "hw/char/serial.h"
52 #include "hw/rtc/mc146818rtc.h"
56 #define FDT_MAX_SIZE (1 * MiB)
58 #define FW_FILE_NAME "skiboot.lid"
59 #define FW_LOAD_ADDR 0x0
60 #define FW_MAX_SIZE (4 * MiB)
62 #define KERNEL_LOAD_ADDR 0x20000000
63 #define KERNEL_MAX_SIZE (256 * MiB)
64 #define INITRD_LOAD_ADDR 0x60000000
65 #define INITRD_MAX_SIZE (256 * MiB)
67 static const char *pnv_chip_core_typename(const PnvChip
*o
)
69 const char *chip_type
= object_class_get_name(object_get_class(OBJECT(o
)));
70 int len
= strlen(chip_type
) - strlen(PNV_CHIP_TYPE_SUFFIX
);
71 char *s
= g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len
, chip_type
);
72 const char *core_type
= object_class_get_name(object_class_by_name(s
));
78 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
79 * 4 * 4 sockets * 12 cores * 8 threads = 1536
85 * Memory nodes are created by hostboot, one for each range of memory
86 * that has a different "affinity". In practice, it means one range
89 static void pnv_dt_memory(void *fdt
, int chip_id
, hwaddr start
, hwaddr size
)
92 uint64_t mem_reg_property
[2];
95 mem_reg_property
[0] = cpu_to_be64(start
);
96 mem_reg_property
[1] = cpu_to_be64(size
);
98 mem_name
= g_strdup_printf("memory@%"HWADDR_PRIx
, start
);
99 off
= fdt_add_subnode(fdt
, 0, mem_name
);
102 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
103 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
104 sizeof(mem_reg_property
))));
105 _FDT((fdt_setprop_cell(fdt
, off
, "ibm,chip-id", chip_id
)));
108 static int get_cpus_node(void *fdt
)
110 int cpus_offset
= fdt_path_offset(fdt
, "/cpus");
112 if (cpus_offset
< 0) {
113 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
115 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
116 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
124 * The PowerNV cores (and threads) need to use real HW ids and not an
125 * incremental index like it has been done on other platforms. This HW
126 * id is stored in the CPU PIR, it is used to create cpu nodes in the
127 * device tree, used in XSCOM to address cores and in interrupt
130 static void pnv_dt_core(PnvChip
*chip
, PnvCore
*pc
, void *fdt
)
132 PowerPCCPU
*cpu
= pc
->threads
[0];
133 CPUState
*cs
= CPU(cpu
);
134 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
135 int smt_threads
= CPU_CORE(pc
)->nr_threads
;
136 CPUPPCState
*env
= &cpu
->env
;
137 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
138 uint32_t servers_prop
[smt_threads
];
140 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
141 0xffffffff, 0xffffffff};
142 uint32_t tbfreq
= PNV_TIMEBASE_FREQ
;
143 uint32_t cpufreq
= 1000000000;
144 uint32_t page_sizes_prop
[64];
145 size_t page_sizes_prop_size
;
146 const uint8_t pa_features
[] = { 24, 0,
147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
153 int cpus_offset
= get_cpus_node(fdt
);
155 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, pc
->pir
);
156 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
160 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id", chip
->chip_id
)));
162 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", pc
->pir
)));
163 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,pir", pc
->pir
)));
164 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
166 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
167 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
168 env
->dcache_line_size
)));
169 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
170 env
->dcache_line_size
)));
171 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
172 env
->icache_line_size
)));
173 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
174 env
->icache_line_size
)));
176 if (pcc
->l1_dcache_size
) {
177 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
178 pcc
->l1_dcache_size
)));
180 warn_report("Unknown L1 dcache size for cpu");
182 if (pcc
->l1_icache_size
) {
183 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
184 pcc
->l1_icache_size
)));
186 warn_report("Unknown L1 icache size for cpu");
189 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
190 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
191 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size",
192 cpu
->hash64_opts
->slb_size
)));
193 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
194 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
196 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
197 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
200 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
201 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
202 segs
, sizeof(segs
))));
206 * Advertise VMX/VSX (vector extensions) if available
207 * 0 / no property == no vector extensions
208 * 1 == VMX / Altivec available
211 if (env
->insns_flags
& PPC_ALTIVEC
) {
212 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
214 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
218 * Advertise DFP (Decimal Floating Point) if available
219 * 0 / no property == no DFP
222 if (env
->insns_flags2
& PPC2_DFP
) {
223 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
226 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
227 sizeof(page_sizes_prop
));
228 if (page_sizes_prop_size
) {
229 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
230 page_sizes_prop
, page_sizes_prop_size
)));
233 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
234 pa_features
, sizeof(pa_features
))));
236 /* Build interrupt servers properties */
237 for (i
= 0; i
< smt_threads
; i
++) {
238 servers_prop
[i
] = cpu_to_be32(pc
->pir
+ i
);
240 _FDT((fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
241 servers_prop
, sizeof(servers_prop
))));
244 static void pnv_dt_icp(PnvChip
*chip
, void *fdt
, uint32_t pir
,
247 uint64_t addr
= PNV_ICP_BASE(chip
) | (pir
<< 12);
249 const char compat
[] = "IBM,power8-icp\0IBM,ppc-xicp";
250 uint32_t irange
[2], i
, rsize
;
254 irange
[0] = cpu_to_be32(pir
);
255 irange
[1] = cpu_to_be32(nr_threads
);
257 rsize
= sizeof(uint64_t) * 2 * nr_threads
;
258 reg
= g_malloc(rsize
);
259 for (i
= 0; i
< nr_threads
; i
++) {
260 reg
[i
* 2] = cpu_to_be64(addr
| ((pir
+ i
) * 0x1000));
261 reg
[i
* 2 + 1] = cpu_to_be64(0x1000);
264 name
= g_strdup_printf("interrupt-controller@%"PRIX64
, addr
);
265 offset
= fdt_add_subnode(fdt
, 0, name
);
269 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
, sizeof(compat
))));
270 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, rsize
)));
271 _FDT((fdt_setprop_string(fdt
, offset
, "device_type",
272 "PowerPC-External-Interrupt-Presentation")));
273 _FDT((fdt_setprop(fdt
, offset
, "interrupt-controller", NULL
, 0)));
274 _FDT((fdt_setprop(fdt
, offset
, "ibm,interrupt-server-ranges",
275 irange
, sizeof(irange
))));
276 _FDT((fdt_setprop_cell(fdt
, offset
, "#interrupt-cells", 1)));
277 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 0)));
281 static void pnv_chip_power8_dt_populate(PnvChip
*chip
, void *fdt
)
283 static const char compat
[] = "ibm,power8-xscom\0ibm,xscom";
286 pnv_dt_xscom(chip
, fdt
, 0,
287 cpu_to_be64(PNV_XSCOM_BASE(chip
)),
288 cpu_to_be64(PNV_XSCOM_SIZE
),
289 compat
, sizeof(compat
));
291 for (i
= 0; i
< chip
->nr_cores
; i
++) {
292 PnvCore
*pnv_core
= chip
->cores
[i
];
294 pnv_dt_core(chip
, pnv_core
, fdt
);
296 /* Interrupt Control Presenters (ICP). One per core. */
297 pnv_dt_icp(chip
, fdt
, pnv_core
->pir
, CPU_CORE(pnv_core
)->nr_threads
);
300 if (chip
->ram_size
) {
301 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
305 static void pnv_chip_power9_dt_populate(PnvChip
*chip
, void *fdt
)
307 static const char compat
[] = "ibm,power9-xscom\0ibm,xscom";
310 pnv_dt_xscom(chip
, fdt
, 0,
311 cpu_to_be64(PNV9_XSCOM_BASE(chip
)),
312 cpu_to_be64(PNV9_XSCOM_SIZE
),
313 compat
, sizeof(compat
));
315 for (i
= 0; i
< chip
->nr_cores
; i
++) {
316 PnvCore
*pnv_core
= chip
->cores
[i
];
318 pnv_dt_core(chip
, pnv_core
, fdt
);
321 if (chip
->ram_size
) {
322 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
325 pnv_dt_lpc(chip
, fdt
, 0, PNV9_LPCM_BASE(chip
), PNV9_LPCM_SIZE
);
328 static void pnv_chip_power10_dt_populate(PnvChip
*chip
, void *fdt
)
330 static const char compat
[] = "ibm,power10-xscom\0ibm,xscom";
333 pnv_dt_xscom(chip
, fdt
, 0,
334 cpu_to_be64(PNV10_XSCOM_BASE(chip
)),
335 cpu_to_be64(PNV10_XSCOM_SIZE
),
336 compat
, sizeof(compat
));
338 for (i
= 0; i
< chip
->nr_cores
; i
++) {
339 PnvCore
*pnv_core
= chip
->cores
[i
];
341 pnv_dt_core(chip
, pnv_core
, fdt
);
344 if (chip
->ram_size
) {
345 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
348 pnv_dt_lpc(chip
, fdt
, 0, PNV10_LPCM_BASE(chip
), PNV10_LPCM_SIZE
);
351 static void pnv_dt_rtc(ISADevice
*d
, void *fdt
, int lpc_off
)
353 uint32_t io_base
= d
->ioport_id
;
354 uint32_t io_regs
[] = {
356 cpu_to_be32(io_base
),
362 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
363 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
367 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
368 _FDT((fdt_setprop_string(fdt
, node
, "compatible", "pnpPNP,b00")));
371 static void pnv_dt_serial(ISADevice
*d
, void *fdt
, int lpc_off
)
373 const char compatible
[] = "ns16550\0pnpPNP,501";
374 uint32_t io_base
= d
->ioport_id
;
375 uint32_t io_regs
[] = {
377 cpu_to_be32(io_base
),
383 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
384 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
388 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
389 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
390 sizeof(compatible
))));
392 _FDT((fdt_setprop_cell(fdt
, node
, "clock-frequency", 1843200)));
393 _FDT((fdt_setprop_cell(fdt
, node
, "current-speed", 115200)));
394 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", d
->isairq
[0])));
395 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
396 fdt_get_phandle(fdt
, lpc_off
))));
398 /* This is needed by Linux */
399 _FDT((fdt_setprop_string(fdt
, node
, "device_type", "serial")));
402 static void pnv_dt_ipmi_bt(ISADevice
*d
, void *fdt
, int lpc_off
)
404 const char compatible
[] = "bt\0ipmi-bt";
406 uint32_t io_regs
[] = {
408 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
415 io_base
= object_property_get_int(OBJECT(d
), "ioport", &error_fatal
);
416 io_regs
[1] = cpu_to_be32(io_base
);
418 irq
= object_property_get_int(OBJECT(d
), "irq", &error_fatal
);
420 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
421 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
425 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
426 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
427 sizeof(compatible
))));
429 /* Mark it as reserved to avoid Linux trying to claim it */
430 _FDT((fdt_setprop_string(fdt
, node
, "status", "reserved")));
431 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
432 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
433 fdt_get_phandle(fdt
, lpc_off
))));
436 typedef struct ForeachPopulateArgs
{
439 } ForeachPopulateArgs
;
441 static int pnv_dt_isa_device(DeviceState
*dev
, void *opaque
)
443 ForeachPopulateArgs
*args
= opaque
;
444 ISADevice
*d
= ISA_DEVICE(dev
);
446 if (object_dynamic_cast(OBJECT(dev
), TYPE_MC146818_RTC
)) {
447 pnv_dt_rtc(d
, args
->fdt
, args
->offset
);
448 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_ISA_SERIAL
)) {
449 pnv_dt_serial(d
, args
->fdt
, args
->offset
);
450 } else if (object_dynamic_cast(OBJECT(dev
), "isa-ipmi-bt")) {
451 pnv_dt_ipmi_bt(d
, args
->fdt
, args
->offset
);
453 error_report("unknown isa device %s@i%x", qdev_fw_name(dev
),
461 * The default LPC bus of a multichip system is on chip 0. It's
462 * recognized by the firmware (skiboot) using a "primary" property.
464 static void pnv_dt_isa(PnvMachineState
*pnv
, void *fdt
)
466 int isa_offset
= fdt_path_offset(fdt
, pnv
->chips
[0]->dt_isa_nodename
);
467 ForeachPopulateArgs args
= {
469 .offset
= isa_offset
,
473 _FDT((fdt_setprop(fdt
, isa_offset
, "primary", NULL
, 0)));
475 phandle
= qemu_fdt_alloc_phandle(fdt
);
477 _FDT((fdt_setprop_cell(fdt
, isa_offset
, "phandle", phandle
)));
480 * ISA devices are not necessarily parented to the ISA bus so we
481 * can not use object_child_foreach()
483 qbus_walk_children(BUS(pnv
->isa_bus
), pnv_dt_isa_device
, NULL
, NULL
, NULL
,
487 static void pnv_dt_power_mgt(PnvMachineState
*pnv
, void *fdt
)
491 off
= fdt_add_subnode(fdt
, 0, "ibm,opal");
492 off
= fdt_add_subnode(fdt
, off
, "power-mgt");
494 _FDT(fdt_setprop_cell(fdt
, off
, "ibm,enabled-stop-levels", 0xc0000000));
497 static void *pnv_dt_create(MachineState
*machine
)
499 PnvMachineClass
*pmc
= PNV_MACHINE_GET_CLASS(machine
);
500 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
506 fdt
= g_malloc0(FDT_MAX_SIZE
);
507 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
510 _FDT((fdt_add_subnode(fdt
, 0, "qemu")));
513 _FDT((fdt_setprop_cell(fdt
, 0, "#address-cells", 0x2)));
514 _FDT((fdt_setprop_cell(fdt
, 0, "#size-cells", 0x2)));
515 _FDT((fdt_setprop_string(fdt
, 0, "model",
516 "IBM PowerNV (emulated by qemu)")));
517 _FDT((fdt_setprop(fdt
, 0, "compatible", pmc
->compat
, pmc
->compat_size
)));
519 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
520 _FDT((fdt_setprop_string(fdt
, 0, "vm,uuid", buf
)));
522 _FDT((fdt_property_string(fdt
, "system-id", buf
)));
526 off
= fdt_add_subnode(fdt
, 0, "chosen");
527 if (machine
->kernel_cmdline
) {
528 _FDT((fdt_setprop_string(fdt
, off
, "bootargs",
529 machine
->kernel_cmdline
)));
532 if (pnv
->initrd_size
) {
533 uint32_t start_prop
= cpu_to_be32(pnv
->initrd_base
);
534 uint32_t end_prop
= cpu_to_be32(pnv
->initrd_base
+ pnv
->initrd_size
);
536 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-start",
537 &start_prop
, sizeof(start_prop
))));
538 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-end",
539 &end_prop
, sizeof(end_prop
))));
542 /* Populate device tree for each chip */
543 for (i
= 0; i
< pnv
->num_chips
; i
++) {
544 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->dt_populate(pnv
->chips
[i
], fdt
);
547 /* Populate ISA devices on chip 0 */
548 pnv_dt_isa(pnv
, fdt
);
551 pnv_dt_bmc_sensors(pnv
->bmc
, fdt
);
554 /* Create an extra node for power management on machines that support it */
555 if (pmc
->dt_power_mgt
) {
556 pmc
->dt_power_mgt(pnv
, fdt
);
562 static void pnv_powerdown_notify(Notifier
*n
, void *opaque
)
564 PnvMachineState
*pnv
= container_of(n
, PnvMachineState
, powerdown_notifier
);
567 pnv_bmc_powerdown(pnv
->bmc
);
571 static void pnv_reset(MachineState
*machine
)
575 qemu_devices_reset();
577 fdt
= pnv_dt_create(machine
);
579 /* Pack resulting tree */
580 _FDT((fdt_pack(fdt
)));
582 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
583 cpu_physical_memory_write(PNV_FDT_ADDR
, fdt
, fdt_totalsize(fdt
));
586 static ISABus
*pnv_chip_power8_isa_create(PnvChip
*chip
, Error
**errp
)
588 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
589 return pnv_lpc_isa_create(&chip8
->lpc
, true, errp
);
592 static ISABus
*pnv_chip_power8nvl_isa_create(PnvChip
*chip
, Error
**errp
)
594 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
595 return pnv_lpc_isa_create(&chip8
->lpc
, false, errp
);
598 static ISABus
*pnv_chip_power9_isa_create(PnvChip
*chip
, Error
**errp
)
600 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
601 return pnv_lpc_isa_create(&chip9
->lpc
, false, errp
);
604 static ISABus
*pnv_chip_power10_isa_create(PnvChip
*chip
, Error
**errp
)
606 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
607 return pnv_lpc_isa_create(&chip10
->lpc
, false, errp
);
610 static ISABus
*pnv_isa_create(PnvChip
*chip
, Error
**errp
)
612 return PNV_CHIP_GET_CLASS(chip
)->isa_create(chip
, errp
);
615 static void pnv_chip_power8_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
617 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
619 ics_pic_print_info(&chip8
->psi
.ics
, mon
);
622 static void pnv_chip_power9_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
624 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
626 pnv_xive_pic_print_info(&chip9
->xive
, mon
);
627 pnv_psi_pic_print_info(&chip9
->psi
, mon
);
630 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip
*chip
,
633 return PNV_XSCOM_EX_BASE(core_id
);
636 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip
*chip
,
639 return PNV9_XSCOM_EC_BASE(core_id
);
642 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip
*chip
,
645 return PNV10_XSCOM_EC_BASE(core_id
);
648 static bool pnv_match_cpu(const char *default_type
, const char *cpu_type
)
650 PowerPCCPUClass
*ppc_default
=
651 POWERPC_CPU_CLASS(object_class_by_name(default_type
));
652 PowerPCCPUClass
*ppc
=
653 POWERPC_CPU_CLASS(object_class_by_name(cpu_type
));
655 return ppc_default
->pvr_match(ppc_default
, ppc
->pvr
);
658 static void pnv_ipmi_bt_init(ISABus
*bus
, IPMIBmc
*bmc
, uint32_t irq
)
662 obj
= OBJECT(isa_create(bus
, "isa-ipmi-bt"));
663 object_property_set_link(obj
, OBJECT(bmc
), "bmc", &error_fatal
);
664 object_property_set_int(obj
, irq
, "irq", &error_fatal
);
665 object_property_set_bool(obj
, true, "realized", &error_fatal
);
668 static void pnv_chip_power10_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
670 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
672 pnv_psi_pic_print_info(&chip10
->psi
, mon
);
675 static void pnv_init(MachineState
*machine
)
677 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
678 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
684 DriveInfo
*pnor
= drive_get(IF_MTD
, 0, 0);
688 if (machine
->ram_size
< (1 * GiB
)) {
689 warn_report("skiboot may not work with < 1GB of RAM");
692 ram
= g_new(MemoryRegion
, 1);
693 memory_region_allocate_system_memory(ram
, NULL
, "pnv.ram",
695 memory_region_add_subregion(get_system_memory(), 0, ram
);
698 * Create our simple PNOR device
700 dev
= qdev_create(NULL
, TYPE_PNV_PNOR
);
702 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(pnor
),
705 qdev_init_nofail(dev
);
706 pnv
->pnor
= PNV_PNOR(dev
);
708 /* load skiboot firmware */
709 if (bios_name
== NULL
) {
710 bios_name
= FW_FILE_NAME
;
713 fw_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
715 error_report("Could not find OPAL firmware '%s'", bios_name
);
719 fw_size
= load_image_targphys(fw_filename
, FW_LOAD_ADDR
, FW_MAX_SIZE
);
721 error_report("Could not load OPAL firmware '%s'", fw_filename
);
727 if (machine
->kernel_filename
) {
730 kernel_size
= load_image_targphys(machine
->kernel_filename
,
731 KERNEL_LOAD_ADDR
, KERNEL_MAX_SIZE
);
732 if (kernel_size
< 0) {
733 error_report("Could not load kernel '%s'",
734 machine
->kernel_filename
);
740 if (machine
->initrd_filename
) {
741 pnv
->initrd_base
= INITRD_LOAD_ADDR
;
742 pnv
->initrd_size
= load_image_targphys(machine
->initrd_filename
,
743 pnv
->initrd_base
, INITRD_MAX_SIZE
);
744 if (pnv
->initrd_size
< 0) {
745 error_report("Could not load initial ram disk '%s'",
746 machine
->initrd_filename
);
752 * Check compatibility of the specified CPU with the machine
755 if (!pnv_match_cpu(mc
->default_cpu_type
, machine
->cpu_type
)) {
756 error_report("invalid CPU model '%s' for %s machine",
757 machine
->cpu_type
, mc
->name
);
761 /* Create the processor chips */
762 i
= strlen(machine
->cpu_type
) - strlen(POWERPC_CPU_TYPE_SUFFIX
);
763 chip_typename
= g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
764 i
, machine
->cpu_type
);
765 if (!object_class_by_name(chip_typename
)) {
766 error_report("invalid chip model '%.*s' for %s machine",
767 i
, machine
->cpu_type
, mc
->name
);
772 machine
->smp
.max_cpus
/ (machine
->smp
.cores
* machine
->smp
.threads
);
774 * TODO: should we decide on how many chips we can create based
775 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
777 if (!is_power_of_2(pnv
->num_chips
) || pnv
->num_chips
> 4) {
778 error_report("invalid number of chips: '%d'", pnv
->num_chips
);
779 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n");
783 pnv
->chips
= g_new0(PnvChip
*, pnv
->num_chips
);
784 for (i
= 0; i
< pnv
->num_chips
; i
++) {
786 Object
*chip
= object_new(chip_typename
);
788 pnv
->chips
[i
] = PNV_CHIP(chip
);
791 * TODO: put all the memory in one node on chip 0 until we find a
792 * way to specify different ranges for each chip
795 object_property_set_int(chip
, machine
->ram_size
, "ram-size",
799 snprintf(chip_name
, sizeof(chip_name
), "chip[%d]", PNV_CHIP_HWID(i
));
800 object_property_add_child(OBJECT(pnv
), chip_name
, chip
, &error_fatal
);
801 object_property_set_int(chip
, PNV_CHIP_HWID(i
), "chip-id",
803 object_property_set_int(chip
, machine
->smp
.cores
,
804 "nr-cores", &error_fatal
);
805 object_property_set_int(chip
, machine
->smp
.threads
,
806 "nr-threads", &error_fatal
);
808 * The POWER8 machine use the XICS interrupt interface.
809 * Propagate the XICS fabric to the chip and its controllers.
811 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XICS_FABRIC
)) {
812 object_property_set_link(chip
, OBJECT(pnv
), "xics", &error_abort
);
814 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XIVE_FABRIC
)) {
815 object_property_set_link(chip
, OBJECT(pnv
), "xive-fabric",
818 object_property_set_bool(chip
, true, "realized", &error_fatal
);
820 g_free(chip_typename
);
822 /* Create the machine BMC simulator */
823 pnv
->bmc
= pnv_bmc_create(pnv
->pnor
);
825 /* Instantiate ISA bus on chip 0 */
826 pnv
->isa_bus
= pnv_isa_create(pnv
->chips
[0], &error_fatal
);
828 /* Create serial port */
829 serial_hds_isa_init(pnv
->isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
831 /* Create an RTC ISA device too */
832 mc146818_rtc_init(pnv
->isa_bus
, 2000, NULL
);
834 /* Create the IPMI BT device for communication with the BMC */
835 pnv_ipmi_bt_init(pnv
->isa_bus
, pnv
->bmc
, 10);
838 * OpenPOWER systems use a IPMI SEL Event message to notify the
841 pnv
->powerdown_notifier
.notify
= pnv_powerdown_notify
;
842 qemu_register_powerdown_notifier(&pnv
->powerdown_notifier
);
846 * 0:21 Reserved - Read as zeros
851 static uint32_t pnv_chip_core_pir_p8(PnvChip
*chip
, uint32_t core_id
)
853 return (chip
->chip_id
<< 7) | (core_id
<< 3);
856 static void pnv_chip_power8_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
859 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
860 Error
*local_err
= NULL
;
862 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
864 obj
= icp_create(OBJECT(cpu
), TYPE_PNV_ICP
, chip8
->xics
, &local_err
);
866 error_propagate(errp
, local_err
);
874 static void pnv_chip_power8_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
876 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
878 icp_reset(ICP(pnv_cpu
->intc
));
881 static void pnv_chip_power8_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
883 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
885 icp_destroy(ICP(pnv_cpu
->intc
));
886 pnv_cpu
->intc
= NULL
;
889 static void pnv_chip_power8_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
892 icp_pic_print_info(ICP(pnv_cpu_state(cpu
)->intc
), mon
);
896 * 0:48 Reserved - Read as zeroes
899 * 56 Reserved - Read as zero
903 * We only care about the lower bits. uint32_t is fine for the moment.
905 static uint32_t pnv_chip_core_pir_p9(PnvChip
*chip
, uint32_t core_id
)
907 return (chip
->chip_id
<< 8) | (core_id
<< 2);
910 static uint32_t pnv_chip_core_pir_p10(PnvChip
*chip
, uint32_t core_id
)
912 return (chip
->chip_id
<< 8) | (core_id
<< 2);
915 static void pnv_chip_power9_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
918 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
919 Error
*local_err
= NULL
;
921 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
924 * The core creates its interrupt presenter but the XIVE interrupt
925 * controller object is initialized afterwards. Hopefully, it's
926 * only used at runtime.
928 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_PRESENTER(&chip9
->xive
),
931 error_propagate(errp
, local_err
);
938 static void pnv_chip_power9_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
940 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
942 xive_tctx_reset(XIVE_TCTX(pnv_cpu
->intc
));
945 static void pnv_chip_power9_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
947 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
949 xive_tctx_destroy(XIVE_TCTX(pnv_cpu
->intc
));
950 pnv_cpu
->intc
= NULL
;
953 static void pnv_chip_power9_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
956 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu
)->intc
), mon
);
959 static void pnv_chip_power10_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
962 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
964 /* Will be defined when the interrupt controller is */
965 pnv_cpu
->intc
= NULL
;
968 static void pnv_chip_power10_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
973 static void pnv_chip_power10_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
975 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
977 pnv_cpu
->intc
= NULL
;
980 static void pnv_chip_power10_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
986 * Allowed core identifiers on a POWER8 Processor Chip :
995 * <EX7,8 reserved> <reserved>
1004 #define POWER8E_CORE_MASK (0x7070ull)
1005 #define POWER8_CORE_MASK (0x7e7eull)
1008 * POWER9 has 24 cores, ids starting at 0x0
1010 #define POWER9_CORE_MASK (0xffffffffffffffull)
1013 #define POWER10_CORE_MASK (0xffffffffffffffull)
1015 static void pnv_chip_power8_instance_init(Object
*obj
)
1017 Pnv8Chip
*chip8
= PNV8_CHIP(obj
);
1019 object_property_add_link(obj
, "xics", TYPE_XICS_FABRIC
,
1020 (Object
**)&chip8
->xics
,
1021 object_property_allow_set_link
,
1022 OBJ_PROP_LINK_STRONG
,
1025 object_initialize_child(obj
, "psi", &chip8
->psi
, sizeof(chip8
->psi
),
1026 TYPE_PNV8_PSI
, &error_abort
, NULL
);
1028 object_initialize_child(obj
, "lpc", &chip8
->lpc
, sizeof(chip8
->lpc
),
1029 TYPE_PNV8_LPC
, &error_abort
, NULL
);
1031 object_initialize_child(obj
, "occ", &chip8
->occ
, sizeof(chip8
->occ
),
1032 TYPE_PNV8_OCC
, &error_abort
, NULL
);
1034 object_initialize_child(obj
, "homer", &chip8
->homer
, sizeof(chip8
->homer
),
1035 TYPE_PNV8_HOMER
, &error_abort
, NULL
);
1038 static void pnv_chip_icp_realize(Pnv8Chip
*chip8
, Error
**errp
)
1040 PnvChip
*chip
= PNV_CHIP(chip8
);
1041 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1045 name
= g_strdup_printf("icp-%x", chip
->chip_id
);
1046 memory_region_init(&chip8
->icp_mmio
, OBJECT(chip
), name
, PNV_ICP_SIZE
);
1047 sysbus_init_mmio(SYS_BUS_DEVICE(chip
), &chip8
->icp_mmio
);
1050 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 1, PNV_ICP_BASE(chip
));
1052 /* Map the ICP registers for each thread */
1053 for (i
= 0; i
< chip
->nr_cores
; i
++) {
1054 PnvCore
*pnv_core
= chip
->cores
[i
];
1055 int core_hwid
= CPU_CORE(pnv_core
)->core_id
;
1057 for (j
= 0; j
< CPU_CORE(pnv_core
)->nr_threads
; j
++) {
1058 uint32_t pir
= pcc
->core_pir(chip
, core_hwid
) + j
;
1059 PnvICPState
*icp
= PNV_ICP(xics_icp_get(chip8
->xics
, pir
));
1061 memory_region_add_subregion(&chip8
->icp_mmio
, pir
<< 12,
1067 static void pnv_chip_power8_realize(DeviceState
*dev
, Error
**errp
)
1069 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1070 PnvChip
*chip
= PNV_CHIP(dev
);
1071 Pnv8Chip
*chip8
= PNV8_CHIP(dev
);
1072 Pnv8Psi
*psi8
= &chip8
->psi
;
1073 Error
*local_err
= NULL
;
1075 assert(chip8
->xics
);
1077 /* XSCOM bridge is first */
1078 pnv_xscom_realize(chip
, PNV_XSCOM_SIZE
, &local_err
);
1080 error_propagate(errp
, local_err
);
1083 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV_XSCOM_BASE(chip
));
1085 pcc
->parent_realize(dev
, &local_err
);
1087 error_propagate(errp
, local_err
);
1091 /* Processor Service Interface (PSI) Host Bridge */
1092 object_property_set_int(OBJECT(&chip8
->psi
), PNV_PSIHB_BASE(chip
),
1093 "bar", &error_fatal
);
1094 object_property_set_link(OBJECT(&chip8
->psi
), OBJECT(chip8
->xics
),
1095 ICS_PROP_XICS
, &error_abort
);
1096 object_property_set_bool(OBJECT(&chip8
->psi
), true, "realized", &local_err
);
1098 error_propagate(errp
, local_err
);
1101 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PSIHB_BASE
,
1102 &PNV_PSI(psi8
)->xscom_regs
);
1104 /* Create LPC controller */
1105 object_property_set_link(OBJECT(&chip8
->lpc
), OBJECT(&chip8
->psi
), "psi",
1107 object_property_set_bool(OBJECT(&chip8
->lpc
), true, "realized",
1109 pnv_xscom_add_subregion(chip
, PNV_XSCOM_LPC_BASE
, &chip8
->lpc
.xscom_regs
);
1111 chip
->dt_isa_nodename
= g_strdup_printf("/xscom@%" PRIx64
"/isa@%x",
1112 (uint64_t) PNV_XSCOM_BASE(chip
),
1113 PNV_XSCOM_LPC_BASE
);
1116 * Interrupt Management Area. This is the memory region holding
1117 * all the Interrupt Control Presenter (ICP) registers
1119 pnv_chip_icp_realize(chip8
, &local_err
);
1121 error_propagate(errp
, local_err
);
1125 /* Create the simplified OCC model */
1126 object_property_set_link(OBJECT(&chip8
->occ
), OBJECT(&chip8
->psi
), "psi",
1128 object_property_set_bool(OBJECT(&chip8
->occ
), true, "realized", &local_err
);
1130 error_propagate(errp
, local_err
);
1133 pnv_xscom_add_subregion(chip
, PNV_XSCOM_OCC_BASE
, &chip8
->occ
.xscom_regs
);
1135 /* OCC SRAM model */
1136 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip
),
1137 &chip8
->occ
.sram_regs
);
1140 object_property_set_link(OBJECT(&chip8
->homer
), OBJECT(chip
), "chip",
1142 object_property_set_bool(OBJECT(&chip8
->homer
), true, "realized",
1145 error_propagate(errp
, local_err
);
1148 /* Homer Xscom region */
1149 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PBA_BASE
, &chip8
->homer
.pba_regs
);
1151 /* Homer mmio region */
1152 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip
),
1153 &chip8
->homer
.regs
);
1156 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1158 addr
&= (PNV_XSCOM_SIZE
- 1);
1159 return ((addr
>> 4) & ~0xfull
) | ((addr
>> 3) & 0xf);
1162 static void pnv_chip_power8e_class_init(ObjectClass
*klass
, void *data
)
1164 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1165 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1167 k
->chip_cfam_id
= 0x221ef04980000000ull
; /* P8 Murano DD2.1 */
1168 k
->cores_mask
= POWER8E_CORE_MASK
;
1169 k
->core_pir
= pnv_chip_core_pir_p8
;
1170 k
->intc_create
= pnv_chip_power8_intc_create
;
1171 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1172 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1173 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1174 k
->isa_create
= pnv_chip_power8_isa_create
;
1175 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1176 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1177 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1178 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1179 dc
->desc
= "PowerNV Chip POWER8E";
1181 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1182 &k
->parent_realize
);
1185 static void pnv_chip_power8_class_init(ObjectClass
*klass
, void *data
)
1187 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1188 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1190 k
->chip_cfam_id
= 0x220ea04980000000ull
; /* P8 Venice DD2.0 */
1191 k
->cores_mask
= POWER8_CORE_MASK
;
1192 k
->core_pir
= pnv_chip_core_pir_p8
;
1193 k
->intc_create
= pnv_chip_power8_intc_create
;
1194 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1195 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1196 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1197 k
->isa_create
= pnv_chip_power8_isa_create
;
1198 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1199 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1200 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1201 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1202 dc
->desc
= "PowerNV Chip POWER8";
1204 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1205 &k
->parent_realize
);
1208 static void pnv_chip_power8nvl_class_init(ObjectClass
*klass
, void *data
)
1210 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1211 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1213 k
->chip_cfam_id
= 0x120d304980000000ull
; /* P8 Naples DD1.0 */
1214 k
->cores_mask
= POWER8_CORE_MASK
;
1215 k
->core_pir
= pnv_chip_core_pir_p8
;
1216 k
->intc_create
= pnv_chip_power8_intc_create
;
1217 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1218 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1219 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1220 k
->isa_create
= pnv_chip_power8nvl_isa_create
;
1221 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1222 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1223 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1224 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1225 dc
->desc
= "PowerNV Chip POWER8NVL";
1227 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1228 &k
->parent_realize
);
1231 static void pnv_chip_power9_instance_init(Object
*obj
)
1233 Pnv9Chip
*chip9
= PNV9_CHIP(obj
);
1235 object_initialize_child(obj
, "xive", &chip9
->xive
, sizeof(chip9
->xive
),
1236 TYPE_PNV_XIVE
, &error_abort
, NULL
);
1237 object_property_add_alias(obj
, "xive-fabric", OBJECT(&chip9
->xive
),
1238 "xive-fabric", &error_abort
);
1240 object_initialize_child(obj
, "psi", &chip9
->psi
, sizeof(chip9
->psi
),
1241 TYPE_PNV9_PSI
, &error_abort
, NULL
);
1243 object_initialize_child(obj
, "lpc", &chip9
->lpc
, sizeof(chip9
->lpc
),
1244 TYPE_PNV9_LPC
, &error_abort
, NULL
);
1246 object_initialize_child(obj
, "occ", &chip9
->occ
, sizeof(chip9
->occ
),
1247 TYPE_PNV9_OCC
, &error_abort
, NULL
);
1249 object_initialize_child(obj
, "homer", &chip9
->homer
, sizeof(chip9
->homer
),
1250 TYPE_PNV9_HOMER
, &error_abort
, NULL
);
1253 static void pnv_chip_quad_realize(Pnv9Chip
*chip9
, Error
**errp
)
1255 PnvChip
*chip
= PNV_CHIP(chip9
);
1258 chip9
->nr_quads
= DIV_ROUND_UP(chip
->nr_cores
, 4);
1259 chip9
->quads
= g_new0(PnvQuad
, chip9
->nr_quads
);
1261 for (i
= 0; i
< chip9
->nr_quads
; i
++) {
1263 PnvQuad
*eq
= &chip9
->quads
[i
];
1264 PnvCore
*pnv_core
= chip
->cores
[i
* 4];
1265 int core_id
= CPU_CORE(pnv_core
)->core_id
;
1267 snprintf(eq_name
, sizeof(eq_name
), "eq[%d]", core_id
);
1268 object_initialize_child(OBJECT(chip
), eq_name
, eq
, sizeof(*eq
),
1269 TYPE_PNV_QUAD
, &error_fatal
, NULL
);
1271 object_property_set_int(OBJECT(eq
), core_id
, "id", &error_fatal
);
1272 object_property_set_bool(OBJECT(eq
), true, "realized", &error_fatal
);
1274 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_EQ_BASE(eq
->id
),
1279 static void pnv_chip_power9_realize(DeviceState
*dev
, Error
**errp
)
1281 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1282 Pnv9Chip
*chip9
= PNV9_CHIP(dev
);
1283 PnvChip
*chip
= PNV_CHIP(dev
);
1284 Pnv9Psi
*psi9
= &chip9
->psi
;
1285 Error
*local_err
= NULL
;
1287 /* XSCOM bridge is first */
1288 pnv_xscom_realize(chip
, PNV9_XSCOM_SIZE
, &local_err
);
1290 error_propagate(errp
, local_err
);
1293 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV9_XSCOM_BASE(chip
));
1295 pcc
->parent_realize(dev
, &local_err
);
1297 error_propagate(errp
, local_err
);
1301 pnv_chip_quad_realize(chip9
, &local_err
);
1303 error_propagate(errp
, local_err
);
1307 /* XIVE interrupt controller (POWER9) */
1308 object_property_set_int(OBJECT(&chip9
->xive
), PNV9_XIVE_IC_BASE(chip
),
1309 "ic-bar", &error_fatal
);
1310 object_property_set_int(OBJECT(&chip9
->xive
), PNV9_XIVE_VC_BASE(chip
),
1311 "vc-bar", &error_fatal
);
1312 object_property_set_int(OBJECT(&chip9
->xive
), PNV9_XIVE_PC_BASE(chip
),
1313 "pc-bar", &error_fatal
);
1314 object_property_set_int(OBJECT(&chip9
->xive
), PNV9_XIVE_TM_BASE(chip
),
1315 "tm-bar", &error_fatal
);
1316 object_property_set_link(OBJECT(&chip9
->xive
), OBJECT(chip
), "chip",
1318 object_property_set_bool(OBJECT(&chip9
->xive
), true, "realized",
1321 error_propagate(errp
, local_err
);
1324 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_XIVE_BASE
,
1325 &chip9
->xive
.xscom_regs
);
1327 /* Processor Service Interface (PSI) Host Bridge */
1328 object_property_set_int(OBJECT(&chip9
->psi
), PNV9_PSIHB_BASE(chip
),
1329 "bar", &error_fatal
);
1330 object_property_set_bool(OBJECT(&chip9
->psi
), true, "realized", &local_err
);
1332 error_propagate(errp
, local_err
);
1335 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PSIHB_BASE
,
1336 &PNV_PSI(psi9
)->xscom_regs
);
1339 object_property_set_link(OBJECT(&chip9
->lpc
), OBJECT(&chip9
->psi
), "psi",
1341 object_property_set_bool(OBJECT(&chip9
->lpc
), true, "realized", &local_err
);
1343 error_propagate(errp
, local_err
);
1346 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip
),
1347 &chip9
->lpc
.xscom_regs
);
1349 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1350 (uint64_t) PNV9_LPCM_BASE(chip
));
1352 /* Create the simplified OCC model */
1353 object_property_set_link(OBJECT(&chip9
->occ
), OBJECT(&chip9
->psi
), "psi",
1355 object_property_set_bool(OBJECT(&chip9
->occ
), true, "realized", &local_err
);
1357 error_propagate(errp
, local_err
);
1360 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_OCC_BASE
, &chip9
->occ
.xscom_regs
);
1362 /* OCC SRAM model */
1363 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip
),
1364 &chip9
->occ
.sram_regs
);
1367 object_property_set_link(OBJECT(&chip9
->homer
), OBJECT(chip
), "chip",
1369 object_property_set_bool(OBJECT(&chip9
->homer
), true, "realized",
1372 error_propagate(errp
, local_err
);
1375 /* Homer Xscom region */
1376 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PBA_BASE
, &chip9
->homer
.pba_regs
);
1378 /* Homer mmio region */
1379 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip
),
1380 &chip9
->homer
.regs
);
1383 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1385 addr
&= (PNV9_XSCOM_SIZE
- 1);
1389 static void pnv_chip_power9_class_init(ObjectClass
*klass
, void *data
)
1391 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1392 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1394 k
->chip_cfam_id
= 0x220d104900008000ull
; /* P9 Nimbus DD2.0 */
1395 k
->cores_mask
= POWER9_CORE_MASK
;
1396 k
->core_pir
= pnv_chip_core_pir_p9
;
1397 k
->intc_create
= pnv_chip_power9_intc_create
;
1398 k
->intc_reset
= pnv_chip_power9_intc_reset
;
1399 k
->intc_destroy
= pnv_chip_power9_intc_destroy
;
1400 k
->intc_print_info
= pnv_chip_power9_intc_print_info
;
1401 k
->isa_create
= pnv_chip_power9_isa_create
;
1402 k
->dt_populate
= pnv_chip_power9_dt_populate
;
1403 k
->pic_print_info
= pnv_chip_power9_pic_print_info
;
1404 k
->xscom_core_base
= pnv_chip_power9_xscom_core_base
;
1405 k
->xscom_pcba
= pnv_chip_power9_xscom_pcba
;
1406 dc
->desc
= "PowerNV Chip POWER9";
1408 device_class_set_parent_realize(dc
, pnv_chip_power9_realize
,
1409 &k
->parent_realize
);
1412 static void pnv_chip_power10_instance_init(Object
*obj
)
1414 Pnv10Chip
*chip10
= PNV10_CHIP(obj
);
1416 object_initialize_child(obj
, "psi", &chip10
->psi
, sizeof(chip10
->psi
),
1417 TYPE_PNV10_PSI
, &error_abort
, NULL
);
1418 object_initialize_child(obj
, "lpc", &chip10
->lpc
, sizeof(chip10
->lpc
),
1419 TYPE_PNV10_LPC
, &error_abort
, NULL
);
1422 static void pnv_chip_power10_realize(DeviceState
*dev
, Error
**errp
)
1424 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1425 PnvChip
*chip
= PNV_CHIP(dev
);
1426 Pnv10Chip
*chip10
= PNV10_CHIP(dev
);
1427 Error
*local_err
= NULL
;
1429 /* XSCOM bridge is first */
1430 pnv_xscom_realize(chip
, PNV10_XSCOM_SIZE
, &local_err
);
1432 error_propagate(errp
, local_err
);
1435 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV10_XSCOM_BASE(chip
));
1437 pcc
->parent_realize(dev
, &local_err
);
1439 error_propagate(errp
, local_err
);
1443 /* Processor Service Interface (PSI) Host Bridge */
1444 object_property_set_int(OBJECT(&chip10
->psi
), PNV10_PSIHB_BASE(chip
),
1445 "bar", &error_fatal
);
1446 object_property_set_bool(OBJECT(&chip10
->psi
), true, "realized",
1449 error_propagate(errp
, local_err
);
1452 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_PSIHB_BASE
,
1453 &PNV_PSI(&chip10
->psi
)->xscom_regs
);
1456 object_property_set_link(OBJECT(&chip10
->lpc
), OBJECT(&chip10
->psi
), "psi",
1458 object_property_set_bool(OBJECT(&chip10
->lpc
), true, "realized",
1461 error_propagate(errp
, local_err
);
1464 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip
),
1465 &chip10
->lpc
.xscom_regs
);
1467 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1468 (uint64_t) PNV10_LPCM_BASE(chip
));
1471 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1473 addr
&= (PNV10_XSCOM_SIZE
- 1);
1477 static void pnv_chip_power10_class_init(ObjectClass
*klass
, void *data
)
1479 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1480 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1482 k
->chip_cfam_id
= 0x120da04900008000ull
; /* P10 DD1.0 (with NX) */
1483 k
->cores_mask
= POWER10_CORE_MASK
;
1484 k
->core_pir
= pnv_chip_core_pir_p10
;
1485 k
->intc_create
= pnv_chip_power10_intc_create
;
1486 k
->intc_reset
= pnv_chip_power10_intc_reset
;
1487 k
->intc_destroy
= pnv_chip_power10_intc_destroy
;
1488 k
->intc_print_info
= pnv_chip_power10_intc_print_info
;
1489 k
->isa_create
= pnv_chip_power10_isa_create
;
1490 k
->dt_populate
= pnv_chip_power10_dt_populate
;
1491 k
->pic_print_info
= pnv_chip_power10_pic_print_info
;
1492 k
->xscom_core_base
= pnv_chip_power10_xscom_core_base
;
1493 k
->xscom_pcba
= pnv_chip_power10_xscom_pcba
;
1494 dc
->desc
= "PowerNV Chip POWER10";
1496 device_class_set_parent_realize(dc
, pnv_chip_power10_realize
,
1497 &k
->parent_realize
);
1500 static void pnv_chip_core_sanitize(PnvChip
*chip
, Error
**errp
)
1502 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1506 * No custom mask for this chip, let's use the default one from *
1509 if (!chip
->cores_mask
) {
1510 chip
->cores_mask
= pcc
->cores_mask
;
1513 /* filter alien core ids ! some are reserved */
1514 if ((chip
->cores_mask
& pcc
->cores_mask
) != chip
->cores_mask
) {
1515 error_setg(errp
, "warning: invalid core mask for chip Ox%"PRIx64
" !",
1519 chip
->cores_mask
&= pcc
->cores_mask
;
1521 /* now that we have a sane layout, let check the number of cores */
1522 cores_max
= ctpop64(chip
->cores_mask
);
1523 if (chip
->nr_cores
> cores_max
) {
1524 error_setg(errp
, "warning: too many cores for chip ! Limit is %d",
1530 static void pnv_chip_core_realize(PnvChip
*chip
, Error
**errp
)
1532 Error
*error
= NULL
;
1533 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1534 const char *typename
= pnv_chip_core_typename(chip
);
1537 if (!object_class_by_name(typename
)) {
1538 error_setg(errp
, "Unable to find PowerNV CPU Core '%s'", typename
);
1543 pnv_chip_core_sanitize(chip
, &error
);
1545 error_propagate(errp
, error
);
1549 chip
->cores
= g_new0(PnvCore
*, chip
->nr_cores
);
1551 for (i
= 0, core_hwid
= 0; (core_hwid
< sizeof(chip
->cores_mask
) * 8)
1552 && (i
< chip
->nr_cores
); core_hwid
++) {
1555 uint64_t xscom_core_base
;
1557 if (!(chip
->cores_mask
& (1ull << core_hwid
))) {
1561 pnv_core
= PNV_CORE(object_new(typename
));
1563 snprintf(core_name
, sizeof(core_name
), "core[%d]", core_hwid
);
1564 object_property_add_child(OBJECT(chip
), core_name
, OBJECT(pnv_core
),
1566 chip
->cores
[i
] = pnv_core
;
1567 object_property_set_int(OBJECT(pnv_core
), chip
->nr_threads
,
1568 "nr-threads", &error_fatal
);
1569 object_property_set_int(OBJECT(pnv_core
), core_hwid
,
1570 CPU_CORE_PROP_CORE_ID
, &error_fatal
);
1571 object_property_set_int(OBJECT(pnv_core
),
1572 pcc
->core_pir(chip
, core_hwid
),
1573 "pir", &error_fatal
);
1574 object_property_set_link(OBJECT(pnv_core
), OBJECT(chip
), "chip",
1576 object_property_set_bool(OBJECT(pnv_core
), true, "realized",
1579 /* Each core has an XSCOM MMIO region */
1580 xscom_core_base
= pcc
->xscom_core_base(chip
, core_hwid
);
1582 pnv_xscom_add_subregion(chip
, xscom_core_base
,
1583 &pnv_core
->xscom_regs
);
1588 static void pnv_chip_realize(DeviceState
*dev
, Error
**errp
)
1590 PnvChip
*chip
= PNV_CHIP(dev
);
1591 Error
*error
= NULL
;
1594 pnv_chip_core_realize(chip
, &error
);
1596 error_propagate(errp
, error
);
1601 static Property pnv_chip_properties
[] = {
1602 DEFINE_PROP_UINT32("chip-id", PnvChip
, chip_id
, 0),
1603 DEFINE_PROP_UINT64("ram-start", PnvChip
, ram_start
, 0),
1604 DEFINE_PROP_UINT64("ram-size", PnvChip
, ram_size
, 0),
1605 DEFINE_PROP_UINT32("nr-cores", PnvChip
, nr_cores
, 1),
1606 DEFINE_PROP_UINT64("cores-mask", PnvChip
, cores_mask
, 0x0),
1607 DEFINE_PROP_UINT32("nr-threads", PnvChip
, nr_threads
, 1),
1608 DEFINE_PROP_END_OF_LIST(),
1611 static void pnv_chip_class_init(ObjectClass
*klass
, void *data
)
1613 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1615 set_bit(DEVICE_CATEGORY_CPU
, dc
->categories
);
1616 dc
->realize
= pnv_chip_realize
;
1617 dc
->props
= pnv_chip_properties
;
1618 dc
->desc
= "PowerNV Chip";
1621 PowerPCCPU
*pnv_chip_find_cpu(PnvChip
*chip
, uint32_t pir
)
1625 for (i
= 0; i
< chip
->nr_cores
; i
++) {
1626 PnvCore
*pc
= chip
->cores
[i
];
1627 CPUCore
*cc
= CPU_CORE(pc
);
1629 for (j
= 0; j
< cc
->nr_threads
; j
++) {
1630 if (ppc_cpu_pir(pc
->threads
[j
]) == pir
) {
1631 return pc
->threads
[j
];
1638 static ICSState
*pnv_ics_get(XICSFabric
*xi
, int irq
)
1640 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
1643 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1644 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
1646 if (ics_valid_irq(&chip8
->psi
.ics
, irq
)) {
1647 return &chip8
->psi
.ics
;
1653 static void pnv_ics_resend(XICSFabric
*xi
)
1655 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
1658 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1659 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
1660 ics_resend(&chip8
->psi
.ics
);
1664 static ICPState
*pnv_icp_get(XICSFabric
*xi
, int pir
)
1666 PowerPCCPU
*cpu
= ppc_get_vcpu_by_pir(pir
);
1668 return cpu
? ICP(pnv_cpu_state(cpu
)->intc
) : NULL
;
1671 static void pnv_pic_print_info(InterruptStatsProvider
*obj
,
1674 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1679 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1681 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
1682 PNV_CHIP_GET_CLASS(pnv
->chips
[0])->intc_print_info(pnv
->chips
[0], cpu
,
1686 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1687 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->pic_print_info(pnv
->chips
[i
], mon
);
1691 static int pnv_match_nvt(XiveFabric
*xfb
, uint8_t format
,
1692 uint8_t nvt_blk
, uint32_t nvt_idx
,
1693 bool cam_ignore
, uint8_t priority
,
1694 uint32_t logic_serv
,
1695 XiveTCTXMatch
*match
)
1697 PnvMachineState
*pnv
= PNV_MACHINE(xfb
);
1698 int total_count
= 0;
1701 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1702 Pnv9Chip
*chip9
= PNV9_CHIP(pnv
->chips
[i
]);
1703 XivePresenter
*xptr
= XIVE_PRESENTER(&chip9
->xive
);
1704 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
1707 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
1708 priority
, logic_serv
, match
);
1714 total_count
+= count
;
1720 static void pnv_machine_power8_class_init(ObjectClass
*oc
, void *data
)
1722 MachineClass
*mc
= MACHINE_CLASS(oc
);
1723 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
1724 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
1725 static const char compat
[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
1727 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER8";
1728 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
1730 xic
->icp_get
= pnv_icp_get
;
1731 xic
->ics_get
= pnv_ics_get
;
1732 xic
->ics_resend
= pnv_ics_resend
;
1734 pmc
->compat
= compat
;
1735 pmc
->compat_size
= sizeof(compat
);
1738 static void pnv_machine_power9_class_init(ObjectClass
*oc
, void *data
)
1740 MachineClass
*mc
= MACHINE_CLASS(oc
);
1741 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
1742 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
1743 static const char compat
[] = "qemu,powernv9\0ibm,powernv";
1745 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER9";
1746 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
1747 xfc
->match_nvt
= pnv_match_nvt
;
1749 mc
->alias
= "powernv";
1751 pmc
->compat
= compat
;
1752 pmc
->compat_size
= sizeof(compat
);
1753 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
1756 static void pnv_machine_power10_class_init(ObjectClass
*oc
, void *data
)
1758 MachineClass
*mc
= MACHINE_CLASS(oc
);
1759 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
1760 static const char compat
[] = "qemu,powernv10\0ibm,powernv";
1762 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER10";
1763 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power10_v1.0");
1765 pmc
->compat
= compat
;
1766 pmc
->compat_size
= sizeof(compat
);
1767 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
1770 static void pnv_machine_class_init(ObjectClass
*oc
, void *data
)
1772 MachineClass
*mc
= MACHINE_CLASS(oc
);
1773 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
1775 mc
->desc
= "IBM PowerNV (Non-Virtualized)";
1776 mc
->init
= pnv_init
;
1777 mc
->reset
= pnv_reset
;
1778 mc
->max_cpus
= MAX_CPUS
;
1779 /* Pnv provides a AHCI device for storage */
1780 mc
->block_default_type
= IF_IDE
;
1781 mc
->no_parallel
= 1;
1782 mc
->default_boot_order
= NULL
;
1784 * RAM defaults to less than 2048 for 32-bit hosts, and large
1785 * enough to fit the maximum initrd size at it's load address
1787 mc
->default_ram_size
= INITRD_LOAD_ADDR
+ INITRD_MAX_SIZE
;
1788 ispc
->print_info
= pnv_pic_print_info
;
1791 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1794 .class_init = class_initfn, \
1795 .parent = TYPE_PNV8_CHIP, \
1798 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1801 .class_init = class_initfn, \
1802 .parent = TYPE_PNV9_CHIP, \
1805 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
1808 .class_init = class_initfn, \
1809 .parent = TYPE_PNV10_CHIP, \
1812 static const TypeInfo types
[] = {
1814 .name
= MACHINE_TYPE_NAME("powernv10"),
1815 .parent
= TYPE_PNV_MACHINE
,
1816 .class_init
= pnv_machine_power10_class_init
,
1819 .name
= MACHINE_TYPE_NAME("powernv9"),
1820 .parent
= TYPE_PNV_MACHINE
,
1821 .class_init
= pnv_machine_power9_class_init
,
1822 .interfaces
= (InterfaceInfo
[]) {
1823 { TYPE_XIVE_FABRIC
},
1828 .name
= MACHINE_TYPE_NAME("powernv8"),
1829 .parent
= TYPE_PNV_MACHINE
,
1830 .class_init
= pnv_machine_power8_class_init
,
1831 .interfaces
= (InterfaceInfo
[]) {
1832 { TYPE_XICS_FABRIC
},
1837 .name
= TYPE_PNV_MACHINE
,
1838 .parent
= TYPE_MACHINE
,
1840 .instance_size
= sizeof(PnvMachineState
),
1841 .class_init
= pnv_machine_class_init
,
1842 .class_size
= sizeof(PnvMachineClass
),
1843 .interfaces
= (InterfaceInfo
[]) {
1844 { TYPE_INTERRUPT_STATS_PROVIDER
},
1849 .name
= TYPE_PNV_CHIP
,
1850 .parent
= TYPE_SYS_BUS_DEVICE
,
1851 .class_init
= pnv_chip_class_init
,
1852 .instance_size
= sizeof(PnvChip
),
1853 .class_size
= sizeof(PnvChipClass
),
1858 * P10 chip and variants
1861 .name
= TYPE_PNV10_CHIP
,
1862 .parent
= TYPE_PNV_CHIP
,
1863 .instance_init
= pnv_chip_power10_instance_init
,
1864 .instance_size
= sizeof(Pnv10Chip
),
1866 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10
, pnv_chip_power10_class_init
),
1869 * P9 chip and variants
1872 .name
= TYPE_PNV9_CHIP
,
1873 .parent
= TYPE_PNV_CHIP
,
1874 .instance_init
= pnv_chip_power9_instance_init
,
1875 .instance_size
= sizeof(Pnv9Chip
),
1877 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9
, pnv_chip_power9_class_init
),
1880 * P8 chip and variants
1883 .name
= TYPE_PNV8_CHIP
,
1884 .parent
= TYPE_PNV_CHIP
,
1885 .instance_init
= pnv_chip_power8_instance_init
,
1886 .instance_size
= sizeof(Pnv8Chip
),
1888 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8
, pnv_chip_power8_class_init
),
1889 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E
, pnv_chip_power8e_class_init
),
1890 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL
,
1891 pnv_chip_power8nvl_class_init
),