hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "cpu.h"
  31 #include "trace.h"
  32 #include "qemu/timer.h"
  33 #include "hw/ppc/xics.h"
  34 #include "hw/qdev-properties.h"
  35 #include "qemu/error-report.h"
  36 #include "qemu/module.h"
  37 #include "qapi/visitor.h"
  38 #include "migration/vmstate.h"
  39 #include "monitor/monitor.h"
  40 #include "hw/intc/intc.h"
  41 #include "hw/irq.h"
  42 #include "sysemu/kvm.h"
  43 #include "sysemu/reset.h"
  44
  45 void icp_pic_print_info(ICPState *icp, Monitor *mon)
  46 {
  47     int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
  48
  49     if (!icp->output) {
  50         return;
  51     }
  52
  53     if (kvm_irqchip_in_kernel()) {
  54         icp_synchronize_state(icp);
  55     }
  56
  57     monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
  58                    cpu_index, icp->xirr, icp->xirr_owner,
  59                    icp->pending_priority, icp->mfrr);
  60 }
  61
  62 void ics_pic_print_info(ICSState *ics, Monitor *mon)
  63 {
  64     uint32_t i;
  65
  66     monitor_printf(mon, "ICS %4x..%4x %p\n",
  67                    ics->offset, ics->offset + ics->nr_irqs - 1, ics);
  68
  69     if (!ics->irqs) {
  70         return;
  71     }
  72
  73     if (kvm_irqchip_in_kernel()) {
  74         ics_synchronize_state(ics);
  75     }
  76
  77     for (i = 0; i < ics->nr_irqs; i++) {
  78         ICSIRQState *irq = ics->irqs + i;
  79
  80         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
  81             continue;
  82         }
  83         monitor_printf(mon, "  %4x %s %02x %02x\n",
  84                        ics->offset + i,
  85                        (irq->flags & XICS_FLAGS_IRQ_LSI) ?
  86                        "LSI" : "MSI",
  87                        irq->priority, irq->status);
  88     }
  89 }
  90
  91 /*
  92  * ICP: Presentation layer
  93  */
  94
  95 #define XISR_MASK  0x00ffffff
  96 #define CPPR_MASK  0xff000000
  97
  98 #define XISR(icp)   (((icp)->xirr) & XISR_MASK)
  99 #define CPPR(icp)   (((icp)->xirr) >> 24)
 100
 101 static void ics_reject(ICSState *ics, uint32_t nr);
 102 static void ics_eoi(ICSState *ics, uint32_t nr);
 103
 104 static void icp_check_ipi(ICPState *icp)
 105 {
 106     if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
 107         return;
 108     }
 109
 110     trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
 111
 112     if (XISR(icp) && icp->xirr_owner) {
 113         ics_reject(icp->xirr_owner, XISR(icp));
 114     }
 115
 116     icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
 117     icp->pending_priority = icp->mfrr;
 118     icp->xirr_owner = NULL;
 119     qemu_irq_raise(icp->output);
 120 }
 121
 122 void icp_resend(ICPState *icp)
 123 {
 124     XICSFabric *xi = icp->xics;
 125     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 126
 127     if (icp->mfrr < CPPR(icp)) {
 128         icp_check_ipi(icp);
 129     }
 130
 131     xic->ics_resend(xi);
 132 }
 133
 134 void icp_set_cppr(ICPState *icp, uint8_t cppr)
 135 {
 136     uint8_t old_cppr;
 137     uint32_t old_xisr;
 138
 139     old_cppr = CPPR(icp);
 140     icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
 141
 142     if (cppr < old_cppr) {
 143         if (XISR(icp) && (cppr <= icp->pending_priority)) {
 144             old_xisr = XISR(icp);
 145             icp->xirr &= ~XISR_MASK; /* Clear XISR */
 146             icp->pending_priority = 0xff;
 147             qemu_irq_lower(icp->output);
 148             if (icp->xirr_owner) {
 149                 ics_reject(icp->xirr_owner, old_xisr);
 150                 icp->xirr_owner = NULL;
 151             }
 152         }
 153     } else {
 154         if (!XISR(icp)) {
 155             icp_resend(icp);
 156         }
 157     }
 158 }
 159
 160 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
 161 {
 162     icp->mfrr = mfrr;
 163     if (mfrr < CPPR(icp)) {
 164         icp_check_ipi(icp);
 165     }
 166 }
 167
 168 uint32_t icp_accept(ICPState *icp)
 169 {
 170     uint32_t xirr = icp->xirr;
 171
 172     qemu_irq_lower(icp->output);
 173     icp->xirr = icp->pending_priority << 24;
 174     icp->pending_priority = 0xff;
 175     icp->xirr_owner = NULL;
 176
 177     trace_xics_icp_accept(xirr, icp->xirr);
 178
 179     return xirr;
 180 }
 181
 182 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
 183 {
 184     if (mfrr) {
 185         *mfrr = icp->mfrr;
 186     }
 187     return icp->xirr;
 188 }
 189
 190 void icp_eoi(ICPState *icp, uint32_t xirr)
 191 {
 192     XICSFabric *xi = icp->xics;
 193     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 194     ICSState *ics;
 195     uint32_t irq;
 196
 197     /* Send EOI -> ICS */
 198     icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 199     trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
 200     irq = xirr & XISR_MASK;
 201
 202     ics = xic->ics_get(xi, irq);
 203     if (ics) {
 204         ics_eoi(ics, irq);
 205     }
 206     if (!XISR(icp)) {
 207         icp_resend(icp);
 208     }
 209 }
 210
 211 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
 212 {
 213     ICPState *icp = xics_icp_get(ics->xics, server);
 214
 215     trace_xics_icp_irq(server, nr, priority);
 216
 217     if ((priority >= CPPR(icp))
 218         || (XISR(icp) && (icp->pending_priority <= priority))) {
 219         ics_reject(ics, nr);
 220     } else {
 221         if (XISR(icp) && icp->xirr_owner) {
 222             ics_reject(icp->xirr_owner, XISR(icp));
 223             icp->xirr_owner = NULL;
 224         }
 225         icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 226         icp->xirr_owner = ics;
 227         icp->pending_priority = priority;
 228         trace_xics_icp_raise(icp->xirr, icp->pending_priority);
 229         qemu_irq_raise(icp->output);
 230     }
 231 }
 232
 233 static int icp_pre_save(void *opaque)
 234 {
 235     ICPState *icp = opaque;
 236
 237     if (kvm_irqchip_in_kernel()) {
 238         icp_get_kvm_state(icp);
 239     }
 240
 241     return 0;
 242 }
 243
 244 static int icp_post_load(void *opaque, int version_id)
 245 {
 246     ICPState *icp = opaque;
 247
 248     if (kvm_irqchip_in_kernel()) {
 249         Error *local_err = NULL;
 250         int ret;
 251
 252         ret = icp_set_kvm_state(icp, &local_err);
 253         if (ret < 0) {
 254             error_report_err(local_err);
 255             return ret;
 256         }
 257     }
 258
 259     return 0;
 260 }
 261
 262 static const VMStateDescription vmstate_icp_server = {
 263     .name = "icp/server",
 264     .version_id = 1,
 265     .minimum_version_id = 1,
 266     .pre_save = icp_pre_save,
 267     .post_load = icp_post_load,
 268     .fields = (VMStateField[]) {
 269         /* Sanity check */
 270         VMSTATE_UINT32(xirr, ICPState),
 271         VMSTATE_UINT8(pending_priority, ICPState),
 272         VMSTATE_UINT8(mfrr, ICPState),
 273         VMSTATE_END_OF_LIST()
 274     },
 275 };
 276
 277 static void icp_reset_handler(void *dev)
 278 {
 279     ICPState *icp = ICP(dev);
 280
 281     icp->xirr = 0;
 282     icp->pending_priority = 0xff;
 283     icp->mfrr = 0xff;
 284
 285     /* Make all outputs are deasserted */
 286     qemu_set_irq(icp->output, 0);
 287
 288     if (kvm_irqchip_in_kernel()) {
 289         Error *local_err = NULL;
 290
 291         icp_set_kvm_state(ICP(dev), &local_err);
 292         if (local_err) {
 293             error_report_err(local_err);
 294         }
 295     }
 296 }
 297
 298 static void icp_realize(DeviceState *dev, Error **errp)
 299 {
 300     ICPState *icp = ICP(dev);
 301     PowerPCCPU *cpu;
 302     CPUPPCState *env;
 303     Object *obj;
 304     Error *err = NULL;
 305
 306     obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
 307     if (!obj) {
 308         error_propagate_prepend(errp, err,
 309                                 "required link '" ICP_PROP_XICS
 310                                 "' not found: ");
 311         return;
 312     }
 313
 314     icp->xics = XICS_FABRIC(obj);
 315
 316     obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
 317     if (!obj) {
 318         error_propagate_prepend(errp, err,
 319                                 "required link '" ICP_PROP_CPU
 320                                 "' not found: ");
 321         return;
 322     }
 323
 324     cpu = POWERPC_CPU(obj);
 325     icp->cs = CPU(obj);
 326
 327     env = &cpu->env;
 328     switch (PPC_INPUT(env)) {
 329     case PPC_FLAGS_INPUT_POWER7:
 330         icp->output = env->irq_inputs[POWER7_INPUT_INT];
 331         break;
 332     case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */
 333         icp->output = env->irq_inputs[POWER9_INPUT_INT];
 334         break;
 335
 336     case PPC_FLAGS_INPUT_970:
 337         icp->output = env->irq_inputs[PPC970_INPUT_INT];
 338         break;
 339
 340     default:
 341         error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
 342         return;
 343     }
 344
 345     /* Connect the presenter to the VCPU (required for CPU hotplug) */
 346     if (kvm_irqchip_in_kernel()) {
 347         icp_kvm_realize(dev, &err);
 348         if (err) {
 349             error_propagate(errp, err);
 350             return;
 351         }
 352     }
 353
 354     qemu_register_reset(icp_reset_handler, dev);
 355     vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
 356 }
 357
 358 static void icp_unrealize(DeviceState *dev, Error **errp)
 359 {
 360     ICPState *icp = ICP(dev);
 361
 362     vmstate_unregister(NULL, &vmstate_icp_server, icp);
 363     qemu_unregister_reset(icp_reset_handler, dev);
 364 }
 365
 366 static void icp_class_init(ObjectClass *klass, void *data)
 367 {
 368     DeviceClass *dc = DEVICE_CLASS(klass);
 369
 370     dc->realize = icp_realize;
 371     dc->unrealize = icp_unrealize;
 372 }
 373
 374 static const TypeInfo icp_info = {
 375     .name = TYPE_ICP,
 376     .parent = TYPE_DEVICE,
 377     .instance_size = sizeof(ICPState),
 378     .class_init = icp_class_init,
 379     .class_size = sizeof(ICPStateClass),
 380 };
 381
 382 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
 383 {
 384     Error *local_err = NULL;
 385     Object *obj;
 386
 387     obj = object_new(type);
 388     object_property_add_child(cpu, type, obj, &error_abort);
 389     object_unref(obj);
 390     object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi),
 391                                    &error_abort);
 392     object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort);
 393     object_property_set_bool(obj, true, "realized", &local_err);
 394     if (local_err) {
 395         object_unparent(obj);
 396         error_propagate(errp, local_err);
 397         obj = NULL;
 398     }
 399
 400     return obj;
 401 }
 402
 403 /*
 404  * ICS: Source layer
 405  */
 406 static void ics_resend_msi(ICSState *ics, int srcno)
 407 {
 408     ICSIRQState *irq = ics->irqs + srcno;
 409
 410     /* FIXME: filter by server#? */
 411     if (irq->status & XICS_STATUS_REJECTED) {
 412         irq->status &= ~XICS_STATUS_REJECTED;
 413         if (irq->priority != 0xff) {
 414             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 415         }
 416     }
 417 }
 418
 419 static void ics_resend_lsi(ICSState *ics, int srcno)
 420 {
 421     ICSIRQState *irq = ics->irqs + srcno;
 422
 423     if ((irq->priority != 0xff)
 424         && (irq->status & XICS_STATUS_ASSERTED)
 425         && !(irq->status & XICS_STATUS_SENT)) {
 426         irq->status |= XICS_STATUS_SENT;
 427         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 428     }
 429 }
 430
 431 static void ics_set_irq_msi(ICSState *ics, int srcno, int val)
 432 {
 433     ICSIRQState *irq = ics->irqs + srcno;
 434
 435     trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset);
 436
 437     if (val) {
 438         if (irq->priority == 0xff) {
 439             irq->status |= XICS_STATUS_MASKED_PENDING;
 440             trace_xics_masked_pending();
 441         } else  {
 442             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 443         }
 444     }
 445 }
 446
 447 static void ics_set_irq_lsi(ICSState *ics, int srcno, int val)
 448 {
 449     ICSIRQState *irq = ics->irqs + srcno;
 450
 451     trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset);
 452     if (val) {
 453         irq->status |= XICS_STATUS_ASSERTED;
 454     } else {
 455         irq->status &= ~XICS_STATUS_ASSERTED;
 456     }
 457     ics_resend_lsi(ics, srcno);
 458 }
 459
 460 void ics_set_irq(void *opaque, int srcno, int val)
 461 {
 462     ICSState *ics = (ICSState *)opaque;
 463
 464     if (kvm_irqchip_in_kernel()) {
 465         ics_kvm_set_irq(ics, srcno, val);
 466         return;
 467     }
 468
 469     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 470         ics_set_irq_lsi(ics, srcno, val);
 471     } else {
 472         ics_set_irq_msi(ics, srcno, val);
 473     }
 474 }
 475
 476 static void ics_write_xive_msi(ICSState *ics, int srcno)
 477 {
 478     ICSIRQState *irq = ics->irqs + srcno;
 479
 480     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 481         || (irq->priority == 0xff)) {
 482         return;
 483     }
 484
 485     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 486     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 487 }
 488
 489 static void ics_write_xive_lsi(ICSState *ics, int srcno)
 490 {
 491     ics_resend_lsi(ics, srcno);
 492 }
 493
 494 void ics_write_xive(ICSState *ics, int srcno, int server,
 495                     uint8_t priority, uint8_t saved_priority)
 496 {
 497     ICSIRQState *irq = ics->irqs + srcno;
 498
 499     irq->server = server;
 500     irq->priority = priority;
 501     irq->saved_priority = saved_priority;
 502
 503     trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);
 504
 505     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 506         ics_write_xive_lsi(ics, srcno);
 507     } else {
 508         ics_write_xive_msi(ics, srcno);
 509     }
 510 }
 511
 512 static void ics_reject(ICSState *ics, uint32_t nr)
 513 {
 514     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 515
 516     trace_xics_ics_reject(nr, nr - ics->offset);
 517     if (irq->flags & XICS_FLAGS_IRQ_MSI) {
 518         irq->status |= XICS_STATUS_REJECTED;
 519     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
 520         irq->status &= ~XICS_STATUS_SENT;
 521     }
 522 }
 523
 524 void ics_resend(ICSState *ics)
 525 {
 526     int i;
 527
 528     for (i = 0; i < ics->nr_irqs; i++) {
 529         /* FIXME: filter by server#? */
 530         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
 531             ics_resend_lsi(ics, i);
 532         } else {
 533             ics_resend_msi(ics, i);
 534         }
 535     }
 536 }
 537
 538 static void ics_eoi(ICSState *ics, uint32_t nr)
 539 {
 540     int srcno = nr - ics->offset;
 541     ICSIRQState *irq = ics->irqs + srcno;
 542
 543     trace_xics_ics_eoi(nr);
 544
 545     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 546         irq->status &= ~XICS_STATUS_SENT;
 547     }
 548 }
 549
 550 static void ics_simple_reset(DeviceState *dev)
 551 {
 552     ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
 553
 554     icsc->parent_reset(dev);
 555
 556     if (kvm_irqchip_in_kernel()) {
 557         Error *local_err = NULL;
 558
 559         ics_set_kvm_state(ICS_BASE(dev), &local_err);
 560         if (local_err) {
 561             error_report_err(local_err);
 562         }
 563     }
 564 }
 565
 566 static void ics_simple_reset_handler(void *dev)
 567 {
 568     ics_simple_reset(dev);
 569 }
 570
 571 static void ics_simple_realize(DeviceState *dev, Error **errp)
 572 {
 573     ICSState *ics = ICS_SIMPLE(dev);
 574     ICSStateClass *icsc = ICS_BASE_GET_CLASS(ics);
 575     Error *local_err = NULL;
 576
 577     icsc->parent_realize(dev, &local_err);
 578     if (local_err) {
 579         error_propagate(errp, local_err);
 580         return;
 581     }
 582
 583     qemu_register_reset(ics_simple_reset_handler, ics);
 584 }
 585
 586 static void ics_simple_class_init(ObjectClass *klass, void *data)
 587 {
 588     DeviceClass *dc = DEVICE_CLASS(klass);
 589     ICSStateClass *isc = ICS_BASE_CLASS(klass);
 590
 591     device_class_set_parent_realize(dc, ics_simple_realize,
 592                                     &isc->parent_realize);
 593     device_class_set_parent_reset(dc, ics_simple_reset,
 594                                   &isc->parent_reset);
 595 }
 596
 597 static const TypeInfo ics_simple_info = {
 598     .name = TYPE_ICS_SIMPLE,
 599     .parent = TYPE_ICS_BASE,
 600     .instance_size = sizeof(ICSState),
 601     .class_init = ics_simple_class_init,
 602     .class_size = sizeof(ICSStateClass),
 603 };
 604
 605 static void ics_reset_irq(ICSIRQState *irq)
 606 {
 607     irq->priority = 0xff;
 608     irq->saved_priority = 0xff;
 609 }
 610
 611 static void ics_base_reset(DeviceState *dev)
 612 {
 613     ICSState *ics = ICS_BASE(dev);
 614     int i;
 615     uint8_t flags[ics->nr_irqs];
 616
 617     for (i = 0; i < ics->nr_irqs; i++) {
 618         flags[i] = ics->irqs[i].flags;
 619     }
 620
 621     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 622
 623     for (i = 0; i < ics->nr_irqs; i++) {
 624         ics_reset_irq(ics->irqs + i);
 625         ics->irqs[i].flags = flags[i];
 626     }
 627 }
 628
 629 static void ics_base_realize(DeviceState *dev, Error **errp)
 630 {
 631     ICSState *ics = ICS_BASE(dev);
 632     Object *obj;
 633     Error *err = NULL;
 634
 635     obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &err);
 636     if (!obj) {
 637         error_propagate_prepend(errp, err,
 638                                 "required link '" ICS_PROP_XICS
 639                                 "' not found: ");
 640         return;
 641     }
 642     ics->xics = XICS_FABRIC(obj);
 643
 644     if (!ics->nr_irqs) {
 645         error_setg(errp, "Number of interrupts needs to be greater 0");
 646         return;
 647     }
 648     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 649 }
 650
 651 static void ics_base_instance_init(Object *obj)
 652 {
 653     ICSState *ics = ICS_BASE(obj);
 654
 655     ics->offset = XICS_IRQ_BASE;
 656 }
 657
 658 static int ics_base_pre_save(void *opaque)
 659 {
 660     ICSState *ics = opaque;
 661
 662     if (kvm_irqchip_in_kernel()) {
 663         ics_get_kvm_state(ics);
 664     }
 665
 666     return 0;
 667 }
 668
 669 static int ics_base_post_load(void *opaque, int version_id)
 670 {
 671     ICSState *ics = opaque;
 672
 673     if (kvm_irqchip_in_kernel()) {
 674         Error *local_err = NULL;
 675         int ret;
 676
 677         ret = ics_set_kvm_state(ics, &local_err);
 678         if (ret < 0) {
 679             error_report_err(local_err);
 680             return ret;
 681         }
 682     }
 683
 684     return 0;
 685 }
 686
 687 static const VMStateDescription vmstate_ics_base_irq = {
 688     .name = "ics/irq",
 689     .version_id = 2,
 690     .minimum_version_id = 1,
 691     .fields = (VMStateField[]) {
 692         VMSTATE_UINT32(server, ICSIRQState),
 693         VMSTATE_UINT8(priority, ICSIRQState),
 694         VMSTATE_UINT8(saved_priority, ICSIRQState),
 695         VMSTATE_UINT8(status, ICSIRQState),
 696         VMSTATE_UINT8(flags, ICSIRQState),
 697         VMSTATE_END_OF_LIST()
 698     },
 699 };
 700
 701 static const VMStateDescription vmstate_ics_base = {
 702     .name = "ics",
 703     .version_id = 1,
 704     .minimum_version_id = 1,
 705     .pre_save = ics_base_pre_save,
 706     .post_load = ics_base_post_load,
 707     .fields = (VMStateField[]) {
 708         /* Sanity check */
 709         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
 710
 711         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 712                                              vmstate_ics_base_irq,
 713                                              ICSIRQState),
 714         VMSTATE_END_OF_LIST()
 715     },
 716 };
 717
 718 static Property ics_base_properties[] = {
 719     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
 720     DEFINE_PROP_END_OF_LIST(),
 721 };
 722
 723 static void ics_base_class_init(ObjectClass *klass, void *data)
 724 {
 725     DeviceClass *dc = DEVICE_CLASS(klass);
 726
 727     dc->realize = ics_base_realize;
 728     dc->props = ics_base_properties;
 729     dc->reset = ics_base_reset;
 730     dc->vmsd = &vmstate_ics_base;
 731 }
 732
 733 static const TypeInfo ics_base_info = {
 734     .name = TYPE_ICS_BASE,
 735     .parent = TYPE_DEVICE,
 736     .abstract = true,
 737     .instance_size = sizeof(ICSState),
 738     .instance_init = ics_base_instance_init,
 739     .class_init = ics_base_class_init,
 740     .class_size = sizeof(ICSStateClass),
 741 };
 742
 743 static const TypeInfo xics_fabric_info = {
 744     .name = TYPE_XICS_FABRIC,
 745     .parent = TYPE_INTERFACE,
 746     .class_size = sizeof(XICSFabricClass),
 747 };
 748
 749 /*
 750  * Exported functions
 751  */
 752 ICPState *xics_icp_get(XICSFabric *xi, int server)
 753 {
 754     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 755
 756     return xic->icp_get(xi, server);
 757 }
 758
 759 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
 760 {
 761     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
 762
 763     ics->irqs[srcno].flags |=
 764         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
 765
 766     if (kvm_irqchip_in_kernel()) {
 767         Error *local_err = NULL;
 768
 769         ics_reset_irq(ics->irqs + srcno);
 770         ics_set_kvm_state_one(ics, srcno, &local_err);
 771         if (local_err) {
 772             error_report_err(local_err);
 773         }
 774     }
 775 }
 776
 777 static void xics_register_types(void)
 778 {
 779     type_register_static(&ics_simple_info);
 780     type_register_static(&ics_base_info);
 781     type_register_static(&icp_info);
 782     type_register_static(&xics_fabric_info);
 783 }
 784
 785 type_init(xics_register_types)