2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
25 #include "hw/sysbus.h"
26 #include "exec/address-spaces.h"
27 #include "intel_iommu_internal.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/pci_bus.h"
30 #include "hw/i386/pc.h"
31 #include "hw/i386/apic-msidef.h"
32 #include "hw/boards.h"
33 #include "hw/i386/x86-iommu.h"
34 #include "hw/pci-host/q35.h"
35 #include "sysemu/kvm.h"
36 #include "hw/i386/apic_internal.h"
40 /* context entry operations */
41 #define VTD_CE_GET_RID2PASID(ce) \
42 ((ce)->val[1] & VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK)
43 #define VTD_CE_GET_PASID_DIR_TABLE(ce) \
44 ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)
47 #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT)
48 #define VTD_PE_GET_LEVEL(pe) (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW))
49 #define VTD_PE_GET_FPD_ERR(ret_fr, is_fpd_set, s, source_id, addr, is_write) {\
52 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) { \
53 trace_vtd_fault_disabled(); \
55 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write); \
61 static void vtd_address_space_refresh_all(IntelIOMMUState
*s
);
62 static void vtd_address_space_unmap(VTDAddressSpace
*as
, IOMMUNotifier
*n
);
64 static void vtd_define_quad(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
,
65 uint64_t wmask
, uint64_t w1cmask
)
67 stq_le_p(&s
->csr
[addr
], val
);
68 stq_le_p(&s
->wmask
[addr
], wmask
);
69 stq_le_p(&s
->w1cmask
[addr
], w1cmask
);
72 static void vtd_define_quad_wo(IntelIOMMUState
*s
, hwaddr addr
, uint64_t mask
)
74 stq_le_p(&s
->womask
[addr
], mask
);
77 static void vtd_define_long(IntelIOMMUState
*s
, hwaddr addr
, uint32_t val
,
78 uint32_t wmask
, uint32_t w1cmask
)
80 stl_le_p(&s
->csr
[addr
], val
);
81 stl_le_p(&s
->wmask
[addr
], wmask
);
82 stl_le_p(&s
->w1cmask
[addr
], w1cmask
);
85 static void vtd_define_long_wo(IntelIOMMUState
*s
, hwaddr addr
, uint32_t mask
)
87 stl_le_p(&s
->womask
[addr
], mask
);
90 /* "External" get/set operations */
91 static void vtd_set_quad(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
)
93 uint64_t oldval
= ldq_le_p(&s
->csr
[addr
]);
94 uint64_t wmask
= ldq_le_p(&s
->wmask
[addr
]);
95 uint64_t w1cmask
= ldq_le_p(&s
->w1cmask
[addr
]);
96 stq_le_p(&s
->csr
[addr
],
97 ((oldval
& ~wmask
) | (val
& wmask
)) & ~(w1cmask
& val
));
100 static void vtd_set_long(IntelIOMMUState
*s
, hwaddr addr
, uint32_t val
)
102 uint32_t oldval
= ldl_le_p(&s
->csr
[addr
]);
103 uint32_t wmask
= ldl_le_p(&s
->wmask
[addr
]);
104 uint32_t w1cmask
= ldl_le_p(&s
->w1cmask
[addr
]);
105 stl_le_p(&s
->csr
[addr
],
106 ((oldval
& ~wmask
) | (val
& wmask
)) & ~(w1cmask
& val
));
109 static uint64_t vtd_get_quad(IntelIOMMUState
*s
, hwaddr addr
)
111 uint64_t val
= ldq_le_p(&s
->csr
[addr
]);
112 uint64_t womask
= ldq_le_p(&s
->womask
[addr
]);
113 return val
& ~womask
;
116 static uint32_t vtd_get_long(IntelIOMMUState
*s
, hwaddr addr
)
118 uint32_t val
= ldl_le_p(&s
->csr
[addr
]);
119 uint32_t womask
= ldl_le_p(&s
->womask
[addr
]);
120 return val
& ~womask
;
123 /* "Internal" get/set operations */
124 static uint64_t vtd_get_quad_raw(IntelIOMMUState
*s
, hwaddr addr
)
126 return ldq_le_p(&s
->csr
[addr
]);
129 static uint32_t vtd_get_long_raw(IntelIOMMUState
*s
, hwaddr addr
)
131 return ldl_le_p(&s
->csr
[addr
]);
134 static void vtd_set_quad_raw(IntelIOMMUState
*s
, hwaddr addr
, uint64_t val
)
136 stq_le_p(&s
->csr
[addr
], val
);
139 static uint32_t vtd_set_clear_mask_long(IntelIOMMUState
*s
, hwaddr addr
,
140 uint32_t clear
, uint32_t mask
)
142 uint32_t new_val
= (ldl_le_p(&s
->csr
[addr
]) & ~clear
) | mask
;
143 stl_le_p(&s
->csr
[addr
], new_val
);
147 static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState
*s
, hwaddr addr
,
148 uint64_t clear
, uint64_t mask
)
150 uint64_t new_val
= (ldq_le_p(&s
->csr
[addr
]) & ~clear
) | mask
;
151 stq_le_p(&s
->csr
[addr
], new_val
);
155 static inline void vtd_iommu_lock(IntelIOMMUState
*s
)
157 qemu_mutex_lock(&s
->iommu_lock
);
160 static inline void vtd_iommu_unlock(IntelIOMMUState
*s
)
162 qemu_mutex_unlock(&s
->iommu_lock
);
165 static void vtd_update_scalable_state(IntelIOMMUState
*s
)
167 uint64_t val
= vtd_get_quad_raw(s
, DMAR_RTADDR_REG
);
169 if (s
->scalable_mode
) {
170 s
->root_scalable
= val
& VTD_RTADDR_SMT
;
174 /* Whether the address space needs to notify new mappings */
175 static inline gboolean
vtd_as_has_map_notifier(VTDAddressSpace
*as
)
177 return as
->notifier_flags
& IOMMU_NOTIFIER_MAP
;
180 /* GHashTable functions */
181 static gboolean
vtd_uint64_equal(gconstpointer v1
, gconstpointer v2
)
183 return *((const uint64_t *)v1
) == *((const uint64_t *)v2
);
186 static guint
vtd_uint64_hash(gconstpointer v
)
188 return (guint
)*(const uint64_t *)v
;
191 static gboolean
vtd_hash_remove_by_domain(gpointer key
, gpointer value
,
194 VTDIOTLBEntry
*entry
= (VTDIOTLBEntry
*)value
;
195 uint16_t domain_id
= *(uint16_t *)user_data
;
196 return entry
->domain_id
== domain_id
;
199 /* The shift of an addr for a certain level of paging structure */
200 static inline uint32_t vtd_slpt_level_shift(uint32_t level
)
203 return VTD_PAGE_SHIFT_4K
+ (level
- 1) * VTD_SL_LEVEL_BITS
;
206 static inline uint64_t vtd_slpt_level_page_mask(uint32_t level
)
208 return ~((1ULL << vtd_slpt_level_shift(level
)) - 1);
211 static gboolean
vtd_hash_remove_by_page(gpointer key
, gpointer value
,
214 VTDIOTLBEntry
*entry
= (VTDIOTLBEntry
*)value
;
215 VTDIOTLBPageInvInfo
*info
= (VTDIOTLBPageInvInfo
*)user_data
;
216 uint64_t gfn
= (info
->addr
>> VTD_PAGE_SHIFT_4K
) & info
->mask
;
217 uint64_t gfn_tlb
= (info
->addr
& entry
->mask
) >> VTD_PAGE_SHIFT_4K
;
218 return (entry
->domain_id
== info
->domain_id
) &&
219 (((entry
->gfn
& info
->mask
) == gfn
) ||
220 (entry
->gfn
== gfn_tlb
));
223 /* Reset all the gen of VTDAddressSpace to zero and set the gen of
224 * IntelIOMMUState to 1. Must be called with IOMMU lock held.
226 static void vtd_reset_context_cache_locked(IntelIOMMUState
*s
)
228 VTDAddressSpace
*vtd_as
;
230 GHashTableIter bus_it
;
233 trace_vtd_context_cache_reset();
235 g_hash_table_iter_init(&bus_it
, s
->vtd_as_by_busptr
);
237 while (g_hash_table_iter_next (&bus_it
, NULL
, (void**)&vtd_bus
)) {
238 for (devfn_it
= 0; devfn_it
< PCI_DEVFN_MAX
; ++devfn_it
) {
239 vtd_as
= vtd_bus
->dev_as
[devfn_it
];
243 vtd_as
->context_cache_entry
.context_cache_gen
= 0;
246 s
->context_cache_gen
= 1;
249 /* Must be called with IOMMU lock held. */
250 static void vtd_reset_iotlb_locked(IntelIOMMUState
*s
)
253 g_hash_table_remove_all(s
->iotlb
);
256 static void vtd_reset_iotlb(IntelIOMMUState
*s
)
259 vtd_reset_iotlb_locked(s
);
263 static void vtd_reset_caches(IntelIOMMUState
*s
)
266 vtd_reset_iotlb_locked(s
);
267 vtd_reset_context_cache_locked(s
);
271 static uint64_t vtd_get_iotlb_key(uint64_t gfn
, uint16_t source_id
,
274 return gfn
| ((uint64_t)(source_id
) << VTD_IOTLB_SID_SHIFT
) |
275 ((uint64_t)(level
) << VTD_IOTLB_LVL_SHIFT
);
278 static uint64_t vtd_get_iotlb_gfn(hwaddr addr
, uint32_t level
)
280 return (addr
& vtd_slpt_level_page_mask(level
)) >> VTD_PAGE_SHIFT_4K
;
283 /* Must be called with IOMMU lock held */
284 static VTDIOTLBEntry
*vtd_lookup_iotlb(IntelIOMMUState
*s
, uint16_t source_id
,
287 VTDIOTLBEntry
*entry
;
291 for (level
= VTD_SL_PT_LEVEL
; level
< VTD_SL_PML4_LEVEL
; level
++) {
292 key
= vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr
, level
),
294 entry
= g_hash_table_lookup(s
->iotlb
, &key
);
304 /* Must be with IOMMU lock held */
305 static void vtd_update_iotlb(IntelIOMMUState
*s
, uint16_t source_id
,
306 uint16_t domain_id
, hwaddr addr
, uint64_t slpte
,
307 uint8_t access_flags
, uint32_t level
)
309 VTDIOTLBEntry
*entry
= g_malloc(sizeof(*entry
));
310 uint64_t *key
= g_malloc(sizeof(*key
));
311 uint64_t gfn
= vtd_get_iotlb_gfn(addr
, level
);
313 trace_vtd_iotlb_page_update(source_id
, addr
, slpte
, domain_id
);
314 if (g_hash_table_size(s
->iotlb
) >= VTD_IOTLB_MAX_SIZE
) {
315 trace_vtd_iotlb_reset("iotlb exceeds size limit");
316 vtd_reset_iotlb_locked(s
);
320 entry
->domain_id
= domain_id
;
321 entry
->slpte
= slpte
;
322 entry
->access_flags
= access_flags
;
323 entry
->mask
= vtd_slpt_level_page_mask(level
);
324 *key
= vtd_get_iotlb_key(gfn
, source_id
, level
);
325 g_hash_table_replace(s
->iotlb
, key
, entry
);
328 /* Given the reg addr of both the message data and address, generate an
331 static void vtd_generate_interrupt(IntelIOMMUState
*s
, hwaddr mesg_addr_reg
,
332 hwaddr mesg_data_reg
)
336 assert(mesg_data_reg
< DMAR_REG_SIZE
);
337 assert(mesg_addr_reg
< DMAR_REG_SIZE
);
339 msi
.address
= vtd_get_long_raw(s
, mesg_addr_reg
);
340 msi
.data
= vtd_get_long_raw(s
, mesg_data_reg
);
342 trace_vtd_irq_generate(msi
.address
, msi
.data
);
344 apic_get_class()->send_msi(&msi
);
347 /* Generate a fault event to software via MSI if conditions are met.
348 * Notice that the value of FSTS_REG being passed to it should be the one
351 static void vtd_generate_fault_event(IntelIOMMUState
*s
, uint32_t pre_fsts
)
353 if (pre_fsts
& VTD_FSTS_PPF
|| pre_fsts
& VTD_FSTS_PFO
||
354 pre_fsts
& VTD_FSTS_IQE
) {
355 error_report_once("There are previous interrupt conditions "
356 "to be serviced by software, fault event "
360 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, 0, VTD_FECTL_IP
);
361 if (vtd_get_long_raw(s
, DMAR_FECTL_REG
) & VTD_FECTL_IM
) {
362 error_report_once("Interrupt Mask set, irq is not generated");
364 vtd_generate_interrupt(s
, DMAR_FEADDR_REG
, DMAR_FEDATA_REG
);
365 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
369 /* Check if the Fault (F) field of the Fault Recording Register referenced by
372 static bool vtd_is_frcd_set(IntelIOMMUState
*s
, uint16_t index
)
374 /* Each reg is 128-bit */
375 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
376 addr
+= 8; /* Access the high 64-bit half */
378 assert(index
< DMAR_FRCD_REG_NR
);
380 return vtd_get_quad_raw(s
, addr
) & VTD_FRCD_F
;
383 /* Update the PPF field of Fault Status Register.
384 * Should be called whenever change the F field of any fault recording
387 static void vtd_update_fsts_ppf(IntelIOMMUState
*s
)
390 uint32_t ppf_mask
= 0;
392 for (i
= 0; i
< DMAR_FRCD_REG_NR
; i
++) {
393 if (vtd_is_frcd_set(s
, i
)) {
394 ppf_mask
= VTD_FSTS_PPF
;
398 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, VTD_FSTS_PPF
, ppf_mask
);
399 trace_vtd_fsts_ppf(!!ppf_mask
);
402 static void vtd_set_frcd_and_update_ppf(IntelIOMMUState
*s
, uint16_t index
)
404 /* Each reg is 128-bit */
405 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
406 addr
+= 8; /* Access the high 64-bit half */
408 assert(index
< DMAR_FRCD_REG_NR
);
410 vtd_set_clear_mask_quad(s
, addr
, 0, VTD_FRCD_F
);
411 vtd_update_fsts_ppf(s
);
414 /* Must not update F field now, should be done later */
415 static void vtd_record_frcd(IntelIOMMUState
*s
, uint16_t index
,
416 uint16_t source_id
, hwaddr addr
,
417 VTDFaultReason fault
, bool is_write
)
420 hwaddr frcd_reg_addr
= DMAR_FRCD_REG_OFFSET
+ (((uint64_t)index
) << 4);
422 assert(index
< DMAR_FRCD_REG_NR
);
424 lo
= VTD_FRCD_FI(addr
);
425 hi
= VTD_FRCD_SID(source_id
) | VTD_FRCD_FR(fault
);
429 vtd_set_quad_raw(s
, frcd_reg_addr
, lo
);
430 vtd_set_quad_raw(s
, frcd_reg_addr
+ 8, hi
);
432 trace_vtd_frr_new(index
, hi
, lo
);
435 /* Try to collapse multiple pending faults from the same requester */
436 static bool vtd_try_collapse_fault(IntelIOMMUState
*s
, uint16_t source_id
)
440 hwaddr addr
= DMAR_FRCD_REG_OFFSET
+ 8; /* The high 64-bit half */
442 for (i
= 0; i
< DMAR_FRCD_REG_NR
; i
++) {
443 frcd_reg
= vtd_get_quad_raw(s
, addr
);
444 if ((frcd_reg
& VTD_FRCD_F
) &&
445 ((frcd_reg
& VTD_FRCD_SID_MASK
) == source_id
)) {
448 addr
+= 16; /* 128-bit for each */
453 /* Log and report an DMAR (address translation) fault to software */
454 static void vtd_report_dmar_fault(IntelIOMMUState
*s
, uint16_t source_id
,
455 hwaddr addr
, VTDFaultReason fault
,
458 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
460 assert(fault
< VTD_FR_MAX
);
462 if (fault
== VTD_FR_RESERVED_ERR
) {
463 /* This is not a normal fault reason case. Drop it. */
467 trace_vtd_dmar_fault(source_id
, fault
, addr
, is_write
);
469 if (fsts_reg
& VTD_FSTS_PFO
) {
470 error_report_once("New fault is not recorded due to "
471 "Primary Fault Overflow");
475 if (vtd_try_collapse_fault(s
, source_id
)) {
476 error_report_once("New fault is not recorded due to "
477 "compression of faults");
481 if (vtd_is_frcd_set(s
, s
->next_frcd_reg
)) {
482 error_report_once("Next Fault Recording Reg is used, "
483 "new fault is not recorded, set PFO field");
484 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, 0, VTD_FSTS_PFO
);
488 vtd_record_frcd(s
, s
->next_frcd_reg
, source_id
, addr
, fault
, is_write
);
490 if (fsts_reg
& VTD_FSTS_PPF
) {
491 error_report_once("There are pending faults already, "
492 "fault event is not generated");
493 vtd_set_frcd_and_update_ppf(s
, s
->next_frcd_reg
);
495 if (s
->next_frcd_reg
== DMAR_FRCD_REG_NR
) {
496 s
->next_frcd_reg
= 0;
499 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, VTD_FSTS_FRI_MASK
,
500 VTD_FSTS_FRI(s
->next_frcd_reg
));
501 vtd_set_frcd_and_update_ppf(s
, s
->next_frcd_reg
); /* Will set PPF */
503 if (s
->next_frcd_reg
== DMAR_FRCD_REG_NR
) {
504 s
->next_frcd_reg
= 0;
506 /* This case actually cause the PPF to be Set.
507 * So generate fault event (interrupt).
509 vtd_generate_fault_event(s
, fsts_reg
);
513 /* Handle Invalidation Queue Errors of queued invalidation interface error
516 static void vtd_handle_inv_queue_error(IntelIOMMUState
*s
)
518 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
520 vtd_set_clear_mask_long(s
, DMAR_FSTS_REG
, 0, VTD_FSTS_IQE
);
521 vtd_generate_fault_event(s
, fsts_reg
);
524 /* Set the IWC field and try to generate an invalidation completion interrupt */
525 static void vtd_generate_completion_event(IntelIOMMUState
*s
)
527 if (vtd_get_long_raw(s
, DMAR_ICS_REG
) & VTD_ICS_IWC
) {
528 trace_vtd_inv_desc_wait_irq("One pending, skip current");
531 vtd_set_clear_mask_long(s
, DMAR_ICS_REG
, 0, VTD_ICS_IWC
);
532 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, 0, VTD_IECTL_IP
);
533 if (vtd_get_long_raw(s
, DMAR_IECTL_REG
) & VTD_IECTL_IM
) {
534 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, "
535 "new event not generated");
538 /* Generate the interrupt event */
539 trace_vtd_inv_desc_wait_irq("Generating complete event");
540 vtd_generate_interrupt(s
, DMAR_IEADDR_REG
, DMAR_IEDATA_REG
);
541 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
545 static inline bool vtd_root_entry_present(IntelIOMMUState
*s
,
549 if (s
->root_scalable
&& devfn
> UINT8_MAX
/ 2) {
550 return re
->hi
& VTD_ROOT_ENTRY_P
;
553 return re
->lo
& VTD_ROOT_ENTRY_P
;
556 static int vtd_get_root_entry(IntelIOMMUState
*s
, uint8_t index
,
561 addr
= s
->root
+ index
* sizeof(*re
);
562 if (dma_memory_read(&address_space_memory
, addr
, re
, sizeof(*re
))) {
564 return -VTD_FR_ROOT_TABLE_INV
;
566 re
->lo
= le64_to_cpu(re
->lo
);
567 re
->hi
= le64_to_cpu(re
->hi
);
571 static inline bool vtd_ce_present(VTDContextEntry
*context
)
573 return context
->lo
& VTD_CONTEXT_ENTRY_P
;
576 static int vtd_get_context_entry_from_root(IntelIOMMUState
*s
,
581 dma_addr_t addr
, ce_size
;
583 /* we have checked that root entry is present */
584 ce_size
= s
->root_scalable
? VTD_CTX_ENTRY_SCALABLE_SIZE
:
585 VTD_CTX_ENTRY_LEGACY_SIZE
;
587 if (s
->root_scalable
&& index
> UINT8_MAX
/ 2) {
588 index
= index
& (~VTD_DEVFN_CHECK_MASK
);
589 addr
= re
->hi
& VTD_ROOT_ENTRY_CTP
;
591 addr
= re
->lo
& VTD_ROOT_ENTRY_CTP
;
594 addr
= addr
+ index
* ce_size
;
595 if (dma_memory_read(&address_space_memory
, addr
, ce
, ce_size
)) {
596 return -VTD_FR_CONTEXT_TABLE_INV
;
599 ce
->lo
= le64_to_cpu(ce
->lo
);
600 ce
->hi
= le64_to_cpu(ce
->hi
);
601 if (ce_size
== VTD_CTX_ENTRY_SCALABLE_SIZE
) {
602 ce
->val
[2] = le64_to_cpu(ce
->val
[2]);
603 ce
->val
[3] = le64_to_cpu(ce
->val
[3]);
608 static inline dma_addr_t
vtd_ce_get_slpt_base(VTDContextEntry
*ce
)
610 return ce
->lo
& VTD_CONTEXT_ENTRY_SLPTPTR
;
613 static inline uint64_t vtd_get_slpte_addr(uint64_t slpte
, uint8_t aw
)
615 return slpte
& VTD_SL_PT_BASE_ADDR_MASK(aw
);
618 /* Whether the pte indicates the address of the page frame */
619 static inline bool vtd_is_last_slpte(uint64_t slpte
, uint32_t level
)
621 return level
== VTD_SL_PT_LEVEL
|| (slpte
& VTD_SL_PT_PAGE_SIZE_MASK
);
624 /* Get the content of a spte located in @base_addr[@index] */
625 static uint64_t vtd_get_slpte(dma_addr_t base_addr
, uint32_t index
)
629 assert(index
< VTD_SL_PT_ENTRY_NR
);
631 if (dma_memory_read(&address_space_memory
,
632 base_addr
+ index
* sizeof(slpte
), &slpte
,
634 slpte
= (uint64_t)-1;
637 slpte
= le64_to_cpu(slpte
);
641 /* Given an iova and the level of paging structure, return the offset
644 static inline uint32_t vtd_iova_level_offset(uint64_t iova
, uint32_t level
)
646 return (iova
>> vtd_slpt_level_shift(level
)) &
647 ((1ULL << VTD_SL_LEVEL_BITS
) - 1);
650 /* Check Capability Register to see if the @level of page-table is supported */
651 static inline bool vtd_is_level_supported(IntelIOMMUState
*s
, uint32_t level
)
653 return VTD_CAP_SAGAW_MASK
& s
->cap
&
654 (1ULL << (level
- 2 + VTD_CAP_SAGAW_SHIFT
));
657 /* Return true if check passed, otherwise false */
658 static inline bool vtd_pe_type_check(X86IOMMUState
*x86_iommu
,
661 switch (VTD_PE_GET_TYPE(pe
)) {
662 case VTD_SM_PASID_ENTRY_FLT
:
663 case VTD_SM_PASID_ENTRY_SLT
:
664 case VTD_SM_PASID_ENTRY_NESTED
:
666 case VTD_SM_PASID_ENTRY_PT
:
667 if (!x86_iommu
->pt_supported
) {
678 static int vtd_get_pasid_dire(dma_addr_t pasid_dir_base
,
680 VTDPASIDDirEntry
*pdire
)
683 dma_addr_t addr
, entry_size
;
685 index
= VTD_PASID_DIR_INDEX(pasid
);
686 entry_size
= VTD_PASID_DIR_ENTRY_SIZE
;
687 addr
= pasid_dir_base
+ index
* entry_size
;
688 if (dma_memory_read(&address_space_memory
, addr
, pdire
, entry_size
)) {
689 return -VTD_FR_PASID_TABLE_INV
;
695 static int vtd_get_pasid_entry(IntelIOMMUState
*s
,
697 VTDPASIDDirEntry
*pdire
,
701 dma_addr_t addr
, entry_size
;
702 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
704 index
= VTD_PASID_TABLE_INDEX(pasid
);
705 entry_size
= VTD_PASID_ENTRY_SIZE
;
706 addr
= pdire
->val
& VTD_PASID_TABLE_BASE_ADDR_MASK
;
707 addr
= addr
+ index
* entry_size
;
708 if (dma_memory_read(&address_space_memory
, addr
, pe
, entry_size
)) {
709 return -VTD_FR_PASID_TABLE_INV
;
712 /* Do translation type check */
713 if (!vtd_pe_type_check(x86_iommu
, pe
)) {
714 return -VTD_FR_PASID_TABLE_INV
;
717 if (!vtd_is_level_supported(s
, VTD_PE_GET_LEVEL(pe
))) {
718 return -VTD_FR_PASID_TABLE_INV
;
724 static int vtd_get_pasid_entry_from_pasid(IntelIOMMUState
*s
,
725 dma_addr_t pasid_dir_base
,
730 VTDPASIDDirEntry pdire
;
732 ret
= vtd_get_pasid_dire(pasid_dir_base
, pasid
, &pdire
);
737 ret
= vtd_get_pasid_entry(s
, pasid
, &pdire
, pe
);
745 static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState
*s
,
750 dma_addr_t pasid_dir_base
;
753 pasid
= VTD_CE_GET_RID2PASID(ce
);
754 pasid_dir_base
= VTD_CE_GET_PASID_DIR_TABLE(ce
);
755 ret
= vtd_get_pasid_entry_from_pasid(s
, pasid_dir_base
, pasid
, pe
);
760 static int vtd_ce_get_pasid_fpd(IntelIOMMUState
*s
,
766 dma_addr_t pasid_dir_base
;
767 VTDPASIDDirEntry pdire
;
770 pasid
= VTD_CE_GET_RID2PASID(ce
);
771 pasid_dir_base
= VTD_CE_GET_PASID_DIR_TABLE(ce
);
773 ret
= vtd_get_pasid_dire(pasid_dir_base
, pasid
, &pdire
);
778 if (pdire
.val
& VTD_PASID_DIR_FPD
) {
783 ret
= vtd_get_pasid_entry(s
, pasid
, &pdire
, &pe
);
788 if (pe
.val
[0] & VTD_PASID_ENTRY_FPD
) {
795 /* Get the page-table level that hardware should use for the second-level
796 * page-table walk from the Address Width field of context-entry.
798 static inline uint32_t vtd_ce_get_level(VTDContextEntry
*ce
)
800 return 2 + (ce
->hi
& VTD_CONTEXT_ENTRY_AW
);
803 static uint32_t vtd_get_iova_level(IntelIOMMUState
*s
,
808 if (s
->root_scalable
) {
809 vtd_ce_get_rid2pasid_entry(s
, ce
, &pe
);
810 return VTD_PE_GET_LEVEL(&pe
);
813 return vtd_ce_get_level(ce
);
816 static inline uint32_t vtd_ce_get_agaw(VTDContextEntry
*ce
)
818 return 30 + (ce
->hi
& VTD_CONTEXT_ENTRY_AW
) * 9;
821 static uint32_t vtd_get_iova_agaw(IntelIOMMUState
*s
,
826 if (s
->root_scalable
) {
827 vtd_ce_get_rid2pasid_entry(s
, ce
, &pe
);
828 return 30 + ((pe
.val
[0] >> 2) & VTD_SM_PASID_ENTRY_AW
) * 9;
831 return vtd_ce_get_agaw(ce
);
834 static inline uint32_t vtd_ce_get_type(VTDContextEntry
*ce
)
836 return ce
->lo
& VTD_CONTEXT_ENTRY_TT
;
839 /* Only for Legacy Mode. Return true if check passed, otherwise false */
840 static inline bool vtd_ce_type_check(X86IOMMUState
*x86_iommu
,
843 switch (vtd_ce_get_type(ce
)) {
844 case VTD_CONTEXT_TT_MULTI_LEVEL
:
845 /* Always supported */
847 case VTD_CONTEXT_TT_DEV_IOTLB
:
848 if (!x86_iommu
->dt_supported
) {
849 error_report_once("%s: DT specified but not supported", __func__
);
853 case VTD_CONTEXT_TT_PASS_THROUGH
:
854 if (!x86_iommu
->pt_supported
) {
855 error_report_once("%s: PT specified but not supported", __func__
);
861 error_report_once("%s: unknown ce type: %"PRIu32
, __func__
,
862 vtd_ce_get_type(ce
));
868 static inline uint64_t vtd_iova_limit(IntelIOMMUState
*s
,
869 VTDContextEntry
*ce
, uint8_t aw
)
871 uint32_t ce_agaw
= vtd_get_iova_agaw(s
, ce
);
872 return 1ULL << MIN(ce_agaw
, aw
);
875 /* Return true if IOVA passes range check, otherwise false. */
876 static inline bool vtd_iova_range_check(IntelIOMMUState
*s
,
877 uint64_t iova
, VTDContextEntry
*ce
,
881 * Check if @iova is above 2^X-1, where X is the minimum of MGAW
882 * in CAP_REG and AW in context-entry.
884 return !(iova
& ~(vtd_iova_limit(s
, ce
, aw
) - 1));
887 static dma_addr_t
vtd_get_iova_pgtbl_base(IntelIOMMUState
*s
,
892 if (s
->root_scalable
) {
893 vtd_ce_get_rid2pasid_entry(s
, ce
, &pe
);
894 return pe
.val
[0] & VTD_SM_PASID_ENTRY_SLPTPTR
;
897 return vtd_ce_get_slpt_base(ce
);
901 * Rsvd field masks for spte:
902 * Index [1] to [4] 4k pages
903 * Index [5] to [8] large pages
905 static uint64_t vtd_paging_entry_rsvd_field
[9];
907 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte
, uint32_t level
)
909 if (slpte
& VTD_SL_PT_PAGE_SIZE_MASK
) {
910 /* Maybe large page */
911 return slpte
& vtd_paging_entry_rsvd_field
[level
+ 4];
913 return slpte
& vtd_paging_entry_rsvd_field
[level
];
917 /* Find the VTD address space associated with a given bus number */
918 static VTDBus
*vtd_find_as_from_bus_num(IntelIOMMUState
*s
, uint8_t bus_num
)
920 VTDBus
*vtd_bus
= s
->vtd_as_by_bus_num
[bus_num
];
923 * Iterate over the registered buses to find the one which
924 * currently hold this bus number, and update the bus_num
929 g_hash_table_iter_init(&iter
, s
->vtd_as_by_busptr
);
930 while (g_hash_table_iter_next(&iter
, NULL
, (void **)&vtd_bus
)) {
931 if (pci_bus_num(vtd_bus
->bus
) == bus_num
) {
932 s
->vtd_as_by_bus_num
[bus_num
] = vtd_bus
;
940 /* Given the @iova, get relevant @slptep. @slpte_level will be the last level
941 * of the translation, can be used for deciding the size of large page.
943 static int vtd_iova_to_slpte(IntelIOMMUState
*s
, VTDContextEntry
*ce
,
944 uint64_t iova
, bool is_write
,
945 uint64_t *slptep
, uint32_t *slpte_level
,
946 bool *reads
, bool *writes
, uint8_t aw_bits
)
948 dma_addr_t addr
= vtd_get_iova_pgtbl_base(s
, ce
);
949 uint32_t level
= vtd_get_iova_level(s
, ce
);
952 uint64_t access_right_check
;
954 if (!vtd_iova_range_check(s
, iova
, ce
, aw_bits
)) {
955 error_report_once("%s: detected IOVA overflow (iova=0x%" PRIx64
")",
957 return -VTD_FR_ADDR_BEYOND_MGAW
;
960 /* FIXME: what is the Atomics request here? */
961 access_right_check
= is_write
? VTD_SL_W
: VTD_SL_R
;
964 offset
= vtd_iova_level_offset(iova
, level
);
965 slpte
= vtd_get_slpte(addr
, offset
);
967 if (slpte
== (uint64_t)-1) {
968 error_report_once("%s: detected read error on DMAR slpte "
969 "(iova=0x%" PRIx64
")", __func__
, iova
);
970 if (level
== vtd_get_iova_level(s
, ce
)) {
971 /* Invalid programming of context-entry */
972 return -VTD_FR_CONTEXT_ENTRY_INV
;
974 return -VTD_FR_PAGING_ENTRY_INV
;
977 *reads
= (*reads
) && (slpte
& VTD_SL_R
);
978 *writes
= (*writes
) && (slpte
& VTD_SL_W
);
979 if (!(slpte
& access_right_check
)) {
980 error_report_once("%s: detected slpte permission error "
981 "(iova=0x%" PRIx64
", level=0x%" PRIx32
", "
982 "slpte=0x%" PRIx64
", write=%d)", __func__
,
983 iova
, level
, slpte
, is_write
);
984 return is_write
? -VTD_FR_WRITE
: -VTD_FR_READ
;
986 if (vtd_slpte_nonzero_rsvd(slpte
, level
)) {
987 error_report_once("%s: detected splte reserve non-zero "
988 "iova=0x%" PRIx64
", level=0x%" PRIx32
989 "slpte=0x%" PRIx64
")", __func__
, iova
,
991 return -VTD_FR_PAGING_ENTRY_RSVD
;
994 if (vtd_is_last_slpte(slpte
, level
)) {
996 *slpte_level
= level
;
999 addr
= vtd_get_slpte_addr(slpte
, aw_bits
);
1004 typedef int (*vtd_page_walk_hook
)(IOMMUTLBEntry
*entry
, void *private);
1007 * Constant information used during page walking
1009 * @hook_fn: hook func to be called when detected page
1010 * @private: private data to be passed into hook func
1011 * @notify_unmap: whether we should notify invalid entries
1012 * @as: VT-d address space of the device
1013 * @aw: maximum address width
1014 * @domain: domain ID of the page walk
1017 VTDAddressSpace
*as
;
1018 vtd_page_walk_hook hook_fn
;
1023 } vtd_page_walk_info
;
1025 static int vtd_page_walk_one(IOMMUTLBEntry
*entry
, vtd_page_walk_info
*info
)
1027 VTDAddressSpace
*as
= info
->as
;
1028 vtd_page_walk_hook hook_fn
= info
->hook_fn
;
1029 void *private = info
->private;
1031 .iova
= entry
->iova
,
1032 .size
= entry
->addr_mask
,
1033 .translated_addr
= entry
->translated_addr
,
1034 .perm
= entry
->perm
,
1036 DMAMap
*mapped
= iova_tree_find(as
->iova_tree
, &target
);
1038 if (entry
->perm
== IOMMU_NONE
&& !info
->notify_unmap
) {
1039 trace_vtd_page_walk_one_skip_unmap(entry
->iova
, entry
->addr_mask
);
1045 /* Update local IOVA mapped ranges */
1048 /* If it's exactly the same translation, skip */
1049 if (!memcmp(mapped
, &target
, sizeof(target
))) {
1050 trace_vtd_page_walk_one_skip_map(entry
->iova
, entry
->addr_mask
,
1051 entry
->translated_addr
);
1055 * Translation changed. Normally this should not
1056 * happen, but it can happen when with buggy guest
1057 * OSes. Note that there will be a small window that
1058 * we don't have map at all. But that's the best
1059 * effort we can do. The ideal way to emulate this is
1060 * atomically modify the PTE to follow what has
1061 * changed, but we can't. One example is that vfio
1062 * driver only has VFIO_IOMMU_[UN]MAP_DMA but no
1063 * interface to modify a mapping (meanwhile it seems
1064 * meaningless to even provide one). Anyway, let's
1065 * mark this as a TODO in case one day we'll have
1066 * a better solution.
1068 IOMMUAccessFlags cache_perm
= entry
->perm
;
1071 /* Emulate an UNMAP */
1072 entry
->perm
= IOMMU_NONE
;
1073 trace_vtd_page_walk_one(info
->domain_id
,
1075 entry
->translated_addr
,
1078 ret
= hook_fn(entry
, private);
1082 /* Drop any existing mapping */
1083 iova_tree_remove(as
->iova_tree
, &target
);
1084 /* Recover the correct permission */
1085 entry
->perm
= cache_perm
;
1088 iova_tree_insert(as
->iova_tree
, &target
);
1091 /* Skip since we didn't map this range at all */
1092 trace_vtd_page_walk_one_skip_unmap(entry
->iova
, entry
->addr_mask
);
1095 iova_tree_remove(as
->iova_tree
, &target
);
1098 trace_vtd_page_walk_one(info
->domain_id
, entry
->iova
,
1099 entry
->translated_addr
, entry
->addr_mask
,
1101 return hook_fn(entry
, private);
1105 * vtd_page_walk_level - walk over specific level for IOVA range
1107 * @addr: base GPA addr to start the walk
1108 * @start: IOVA range start address
1109 * @end: IOVA range end address (start <= addr < end)
1110 * @read: whether parent level has read permission
1111 * @write: whether parent level has write permission
1112 * @info: constant information for the page walk
1114 static int vtd_page_walk_level(dma_addr_t addr
, uint64_t start
,
1115 uint64_t end
, uint32_t level
, bool read
,
1116 bool write
, vtd_page_walk_info
*info
)
1118 bool read_cur
, write_cur
, entry_valid
;
1121 uint64_t subpage_size
, subpage_mask
;
1122 IOMMUTLBEntry entry
;
1123 uint64_t iova
= start
;
1127 trace_vtd_page_walk_level(addr
, level
, start
, end
);
1129 subpage_size
= 1ULL << vtd_slpt_level_shift(level
);
1130 subpage_mask
= vtd_slpt_level_page_mask(level
);
1132 while (iova
< end
) {
1133 iova_next
= (iova
& subpage_mask
) + subpage_size
;
1135 offset
= vtd_iova_level_offset(iova
, level
);
1136 slpte
= vtd_get_slpte(addr
, offset
);
1138 if (slpte
== (uint64_t)-1) {
1139 trace_vtd_page_walk_skip_read(iova
, iova_next
);
1143 if (vtd_slpte_nonzero_rsvd(slpte
, level
)) {
1144 trace_vtd_page_walk_skip_reserve(iova
, iova_next
);
1148 /* Permissions are stacked with parents' */
1149 read_cur
= read
&& (slpte
& VTD_SL_R
);
1150 write_cur
= write
&& (slpte
& VTD_SL_W
);
1153 * As long as we have either read/write permission, this is a
1154 * valid entry. The rule works for both page entries and page
1157 entry_valid
= read_cur
| write_cur
;
1159 if (!vtd_is_last_slpte(slpte
, level
) && entry_valid
) {
1161 * This is a valid PDE (or even bigger than PDE). We need
1162 * to walk one further level.
1164 ret
= vtd_page_walk_level(vtd_get_slpte_addr(slpte
, info
->aw
),
1165 iova
, MIN(iova_next
, end
), level
- 1,
1166 read_cur
, write_cur
, info
);
1169 * This means we are either:
1171 * (1) the real page entry (either 4K page, or huge page)
1172 * (2) the whole range is invalid
1174 * In either case, we send an IOTLB notification down.
1176 entry
.target_as
= &address_space_memory
;
1177 entry
.iova
= iova
& subpage_mask
;
1178 entry
.perm
= IOMMU_ACCESS_FLAG(read_cur
, write_cur
);
1179 entry
.addr_mask
= ~subpage_mask
;
1180 /* NOTE: this is only meaningful if entry_valid == true */
1181 entry
.translated_addr
= vtd_get_slpte_addr(slpte
, info
->aw
);
1182 ret
= vtd_page_walk_one(&entry
, info
);
1197 * vtd_page_walk - walk specific IOVA range, and call the hook
1199 * @s: intel iommu state
1200 * @ce: context entry to walk upon
1201 * @start: IOVA address to start the walk
1202 * @end: IOVA range end address (start <= addr < end)
1203 * @info: page walking information struct
1205 static int vtd_page_walk(IntelIOMMUState
*s
, VTDContextEntry
*ce
,
1206 uint64_t start
, uint64_t end
,
1207 vtd_page_walk_info
*info
)
1209 dma_addr_t addr
= vtd_get_iova_pgtbl_base(s
, ce
);
1210 uint32_t level
= vtd_get_iova_level(s
, ce
);
1212 if (!vtd_iova_range_check(s
, start
, ce
, info
->aw
)) {
1213 return -VTD_FR_ADDR_BEYOND_MGAW
;
1216 if (!vtd_iova_range_check(s
, end
, ce
, info
->aw
)) {
1217 /* Fix end so that it reaches the maximum */
1218 end
= vtd_iova_limit(s
, ce
, info
->aw
);
1221 return vtd_page_walk_level(addr
, start
, end
, level
, true, true, info
);
1224 static int vtd_root_entry_rsvd_bits_check(IntelIOMMUState
*s
,
1227 /* Legacy Mode reserved bits check */
1228 if (!s
->root_scalable
&&
1229 (re
->hi
|| (re
->lo
& VTD_ROOT_ENTRY_RSVD(s
->aw_bits
))))
1232 /* Scalable Mode reserved bits check */
1233 if (s
->root_scalable
&&
1234 ((re
->lo
& VTD_ROOT_ENTRY_RSVD(s
->aw_bits
)) ||
1235 (re
->hi
& VTD_ROOT_ENTRY_RSVD(s
->aw_bits
))))
1241 error_report_once("%s: invalid root entry: hi=0x%"PRIx64
1243 __func__
, re
->hi
, re
->lo
);
1244 return -VTD_FR_ROOT_ENTRY_RSVD
;
1247 static inline int vtd_context_entry_rsvd_bits_check(IntelIOMMUState
*s
,
1248 VTDContextEntry
*ce
)
1250 if (!s
->root_scalable
&&
1251 (ce
->hi
& VTD_CONTEXT_ENTRY_RSVD_HI
||
1252 ce
->lo
& VTD_CONTEXT_ENTRY_RSVD_LO(s
->aw_bits
))) {
1253 error_report_once("%s: invalid context entry: hi=%"PRIx64
1254 ", lo=%"PRIx64
" (reserved nonzero)",
1255 __func__
, ce
->hi
, ce
->lo
);
1256 return -VTD_FR_CONTEXT_ENTRY_RSVD
;
1259 if (s
->root_scalable
&&
1260 (ce
->val
[0] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(s
->aw_bits
) ||
1261 ce
->val
[1] & VTD_SM_CONTEXT_ENTRY_RSVD_VAL1
||
1264 error_report_once("%s: invalid context entry: val[3]=%"PRIx64
1267 ", val[0]=%"PRIx64
" (reserved nonzero)",
1268 __func__
, ce
->val
[3], ce
->val
[2],
1269 ce
->val
[1], ce
->val
[0]);
1270 return -VTD_FR_CONTEXT_ENTRY_RSVD
;
1276 static int vtd_ce_rid2pasid_check(IntelIOMMUState
*s
,
1277 VTDContextEntry
*ce
)
1282 * Make sure in Scalable Mode, a present context entry
1283 * has valid rid2pasid setting, which includes valid
1284 * rid2pasid field and corresponding pasid entry setting
1286 return vtd_ce_get_rid2pasid_entry(s
, ce
, &pe
);
1289 /* Map a device to its corresponding domain (context-entry) */
1290 static int vtd_dev_to_context_entry(IntelIOMMUState
*s
, uint8_t bus_num
,
1291 uint8_t devfn
, VTDContextEntry
*ce
)
1295 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
1297 ret_fr
= vtd_get_root_entry(s
, bus_num
, &re
);
1302 if (!vtd_root_entry_present(s
, &re
, devfn
)) {
1303 /* Not error - it's okay we don't have root entry. */
1304 trace_vtd_re_not_present(bus_num
);
1305 return -VTD_FR_ROOT_ENTRY_P
;
1308 ret_fr
= vtd_root_entry_rsvd_bits_check(s
, &re
);
1313 ret_fr
= vtd_get_context_entry_from_root(s
, &re
, devfn
, ce
);
1318 if (!vtd_ce_present(ce
)) {
1319 /* Not error - it's okay we don't have context entry. */
1320 trace_vtd_ce_not_present(bus_num
, devfn
);
1321 return -VTD_FR_CONTEXT_ENTRY_P
;
1324 ret_fr
= vtd_context_entry_rsvd_bits_check(s
, ce
);
1329 /* Check if the programming of context-entry is valid */
1330 if (!s
->root_scalable
&&
1331 !vtd_is_level_supported(s
, vtd_ce_get_level(ce
))) {
1332 error_report_once("%s: invalid context entry: hi=%"PRIx64
1333 ", lo=%"PRIx64
" (level %d not supported)",
1334 __func__
, ce
->hi
, ce
->lo
,
1335 vtd_ce_get_level(ce
));
1336 return -VTD_FR_CONTEXT_ENTRY_INV
;
1339 if (!s
->root_scalable
) {
1340 /* Do translation type check */
1341 if (!vtd_ce_type_check(x86_iommu
, ce
)) {
1342 /* Errors dumped in vtd_ce_type_check() */
1343 return -VTD_FR_CONTEXT_ENTRY_INV
;
1347 * Check if the programming of context-entry.rid2pasid
1348 * and corresponding pasid setting is valid, and thus
1349 * avoids to check pasid entry fetching result in future
1350 * helper function calling.
1352 ret_fr
= vtd_ce_rid2pasid_check(s
, ce
);
1361 static int vtd_sync_shadow_page_hook(IOMMUTLBEntry
*entry
,
1364 memory_region_notify_iommu((IOMMUMemoryRegion
*)private, 0, *entry
);
1368 static uint16_t vtd_get_domain_id(IntelIOMMUState
*s
,
1369 VTDContextEntry
*ce
)
1373 if (s
->root_scalable
) {
1374 vtd_ce_get_rid2pasid_entry(s
, ce
, &pe
);
1375 return VTD_SM_PASID_ENTRY_DID(pe
.val
[1]);
1378 return VTD_CONTEXT_ENTRY_DID(ce
->hi
);
1381 static int vtd_sync_shadow_page_table_range(VTDAddressSpace
*vtd_as
,
1382 VTDContextEntry
*ce
,
1383 hwaddr addr
, hwaddr size
)
1385 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
1386 vtd_page_walk_info info
= {
1387 .hook_fn
= vtd_sync_shadow_page_hook
,
1388 .private = (void *)&vtd_as
->iommu
,
1389 .notify_unmap
= true,
1392 .domain_id
= vtd_get_domain_id(s
, ce
),
1395 return vtd_page_walk(s
, ce
, addr
, addr
+ size
, &info
);
1398 static int vtd_sync_shadow_page_table(VTDAddressSpace
*vtd_as
)
1404 ret
= vtd_dev_to_context_entry(vtd_as
->iommu_state
,
1405 pci_bus_num(vtd_as
->bus
),
1406 vtd_as
->devfn
, &ce
);
1408 if (ret
== -VTD_FR_CONTEXT_ENTRY_P
) {
1410 * It's a valid scenario to have a context entry that is
1411 * not present. For example, when a device is removed
1412 * from an existing domain then the context entry will be
1413 * zeroed by the guest before it was put into another
1414 * domain. When this happens, instead of synchronizing
1415 * the shadow pages we should invalidate all existing
1416 * mappings and notify the backends.
1418 IOMMU_NOTIFIER_FOREACH(n
, &vtd_as
->iommu
) {
1419 vtd_address_space_unmap(vtd_as
, n
);
1426 return vtd_sync_shadow_page_table_range(vtd_as
, &ce
, 0, UINT64_MAX
);
1430 * Check if specific device is configed to bypass address
1431 * translation for DMA requests. In Scalable Mode, bypass
1432 * 1st-level translation or 2nd-level translation, it depends
1435 static bool vtd_dev_pt_enabled(VTDAddressSpace
*as
)
1444 s
= as
->iommu_state
;
1445 ret
= vtd_dev_to_context_entry(s
, pci_bus_num(as
->bus
),
1449 * Possibly failed to parse the context entry for some reason
1450 * (e.g., during init, or any guest configuration errors on
1451 * context entries). We should assume PT not enabled for
1457 if (s
->root_scalable
) {
1458 ret
= vtd_ce_get_rid2pasid_entry(s
, &ce
, &pe
);
1460 error_report_once("%s: vtd_ce_get_rid2pasid_entry error: %"PRId32
,
1464 return (VTD_PE_GET_TYPE(&pe
) == VTD_SM_PASID_ENTRY_PT
);
1467 return (vtd_ce_get_type(&ce
) == VTD_CONTEXT_TT_PASS_THROUGH
);
1470 /* Return whether the device is using IOMMU translation. */
1471 static bool vtd_switch_address_space(VTDAddressSpace
*as
)
1474 /* Whether we need to take the BQL on our own */
1475 bool take_bql
= !qemu_mutex_iothread_locked();
1479 use_iommu
= as
->iommu_state
->dmar_enabled
&& !vtd_dev_pt_enabled(as
);
1481 trace_vtd_switch_address_space(pci_bus_num(as
->bus
),
1482 VTD_PCI_SLOT(as
->devfn
),
1483 VTD_PCI_FUNC(as
->devfn
),
1487 * It's possible that we reach here without BQL, e.g., when called
1488 * from vtd_pt_enable_fast_path(). However the memory APIs need
1489 * it. We'd better make sure we have had it already, or, take it.
1492 qemu_mutex_lock_iothread();
1495 /* Turn off first then on the other */
1497 memory_region_set_enabled(&as
->nodmar
, false);
1498 memory_region_set_enabled(MEMORY_REGION(&as
->iommu
), true);
1500 memory_region_set_enabled(MEMORY_REGION(&as
->iommu
), false);
1501 memory_region_set_enabled(&as
->nodmar
, true);
1505 qemu_mutex_unlock_iothread();
1511 static void vtd_switch_address_space_all(IntelIOMMUState
*s
)
1513 GHashTableIter iter
;
1517 g_hash_table_iter_init(&iter
, s
->vtd_as_by_busptr
);
1518 while (g_hash_table_iter_next(&iter
, NULL
, (void **)&vtd_bus
)) {
1519 for (i
= 0; i
< PCI_DEVFN_MAX
; i
++) {
1520 if (!vtd_bus
->dev_as
[i
]) {
1523 vtd_switch_address_space(vtd_bus
->dev_as
[i
]);
1528 static inline uint16_t vtd_make_source_id(uint8_t bus_num
, uint8_t devfn
)
1530 return ((bus_num
& 0xffUL
) << 8) | (devfn
& 0xffUL
);
1533 static const bool vtd_qualified_faults
[] = {
1534 [VTD_FR_RESERVED
] = false,
1535 [VTD_FR_ROOT_ENTRY_P
] = false,
1536 [VTD_FR_CONTEXT_ENTRY_P
] = true,
1537 [VTD_FR_CONTEXT_ENTRY_INV
] = true,
1538 [VTD_FR_ADDR_BEYOND_MGAW
] = true,
1539 [VTD_FR_WRITE
] = true,
1540 [VTD_FR_READ
] = true,
1541 [VTD_FR_PAGING_ENTRY_INV
] = true,
1542 [VTD_FR_ROOT_TABLE_INV
] = false,
1543 [VTD_FR_CONTEXT_TABLE_INV
] = false,
1544 [VTD_FR_ROOT_ENTRY_RSVD
] = false,
1545 [VTD_FR_PAGING_ENTRY_RSVD
] = true,
1546 [VTD_FR_CONTEXT_ENTRY_TT
] = true,
1547 [VTD_FR_PASID_TABLE_INV
] = false,
1548 [VTD_FR_RESERVED_ERR
] = false,
1549 [VTD_FR_MAX
] = false,
1552 /* To see if a fault condition is "qualified", which is reported to software
1553 * only if the FPD field in the context-entry used to process the faulting
1556 static inline bool vtd_is_qualified_fault(VTDFaultReason fault
)
1558 return vtd_qualified_faults
[fault
];
1561 static inline bool vtd_is_interrupt_addr(hwaddr addr
)
1563 return VTD_INTERRUPT_ADDR_FIRST
<= addr
&& addr
<= VTD_INTERRUPT_ADDR_LAST
;
1566 static void vtd_pt_enable_fast_path(IntelIOMMUState
*s
, uint16_t source_id
)
1569 VTDAddressSpace
*vtd_as
;
1570 bool success
= false;
1572 vtd_bus
= vtd_find_as_from_bus_num(s
, VTD_SID_TO_BUS(source_id
));
1577 vtd_as
= vtd_bus
->dev_as
[VTD_SID_TO_DEVFN(source_id
)];
1582 if (vtd_switch_address_space(vtd_as
) == false) {
1583 /* We switched off IOMMU region successfully. */
1588 trace_vtd_pt_enable_fast_path(source_id
, success
);
1591 /* Map dev to context-entry then do a paging-structures walk to do a iommu
1594 * Called from RCU critical section.
1596 * @bus_num: The bus number
1597 * @devfn: The devfn, which is the combined of device and function number
1598 * @is_write: The access is a write operation
1599 * @entry: IOMMUTLBEntry that contain the addr to be translated and result
1601 * Returns true if translation is successful, otherwise false.
1603 static bool vtd_do_iommu_translate(VTDAddressSpace
*vtd_as
, PCIBus
*bus
,
1604 uint8_t devfn
, hwaddr addr
, bool is_write
,
1605 IOMMUTLBEntry
*entry
)
1607 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
1609 uint8_t bus_num
= pci_bus_num(bus
);
1610 VTDContextCacheEntry
*cc_entry
;
1611 uint64_t slpte
, page_mask
;
1613 uint16_t source_id
= vtd_make_source_id(bus_num
, devfn
);
1615 bool is_fpd_set
= false;
1618 uint8_t access_flags
;
1619 VTDIOTLBEntry
*iotlb_entry
;
1622 * We have standalone memory region for interrupt addresses, we
1623 * should never receive translation requests in this region.
1625 assert(!vtd_is_interrupt_addr(addr
));
1629 cc_entry
= &vtd_as
->context_cache_entry
;
1631 /* Try to fetch slpte form IOTLB */
1632 iotlb_entry
= vtd_lookup_iotlb(s
, source_id
, addr
);
1634 trace_vtd_iotlb_page_hit(source_id
, addr
, iotlb_entry
->slpte
,
1635 iotlb_entry
->domain_id
);
1636 slpte
= iotlb_entry
->slpte
;
1637 access_flags
= iotlb_entry
->access_flags
;
1638 page_mask
= iotlb_entry
->mask
;
1642 /* Try to fetch context-entry from cache first */
1643 if (cc_entry
->context_cache_gen
== s
->context_cache_gen
) {
1644 trace_vtd_iotlb_cc_hit(bus_num
, devfn
, cc_entry
->context_entry
.hi
,
1645 cc_entry
->context_entry
.lo
,
1646 cc_entry
->context_cache_gen
);
1647 ce
= cc_entry
->context_entry
;
1648 is_fpd_set
= ce
.lo
& VTD_CONTEXT_ENTRY_FPD
;
1649 if (!is_fpd_set
&& s
->root_scalable
) {
1650 ret_fr
= vtd_ce_get_pasid_fpd(s
, &ce
, &is_fpd_set
);
1651 VTD_PE_GET_FPD_ERR(ret_fr
, is_fpd_set
, s
, source_id
, addr
, is_write
);
1654 ret_fr
= vtd_dev_to_context_entry(s
, bus_num
, devfn
, &ce
);
1655 is_fpd_set
= ce
.lo
& VTD_CONTEXT_ENTRY_FPD
;
1656 if (!ret_fr
&& !is_fpd_set
&& s
->root_scalable
) {
1657 ret_fr
= vtd_ce_get_pasid_fpd(s
, &ce
, &is_fpd_set
);
1659 VTD_PE_GET_FPD_ERR(ret_fr
, is_fpd_set
, s
, source_id
, addr
, is_write
);
1660 /* Update context-cache */
1661 trace_vtd_iotlb_cc_update(bus_num
, devfn
, ce
.hi
, ce
.lo
,
1662 cc_entry
->context_cache_gen
,
1663 s
->context_cache_gen
);
1664 cc_entry
->context_entry
= ce
;
1665 cc_entry
->context_cache_gen
= s
->context_cache_gen
;
1669 * We don't need to translate for pass-through context entries.
1670 * Also, let's ignore IOTLB caching as well for PT devices.
1672 if (vtd_ce_get_type(&ce
) == VTD_CONTEXT_TT_PASS_THROUGH
) {
1673 entry
->iova
= addr
& VTD_PAGE_MASK_4K
;
1674 entry
->translated_addr
= entry
->iova
;
1675 entry
->addr_mask
= ~VTD_PAGE_MASK_4K
;
1676 entry
->perm
= IOMMU_RW
;
1677 trace_vtd_translate_pt(source_id
, entry
->iova
);
1680 * When this happens, it means firstly caching-mode is not
1681 * enabled, and this is the first passthrough translation for
1682 * the device. Let's enable the fast path for passthrough.
1684 * When passthrough is disabled again for the device, we can
1685 * capture it via the context entry invalidation, then the
1686 * IOMMU region can be swapped back.
1688 vtd_pt_enable_fast_path(s
, source_id
);
1689 vtd_iommu_unlock(s
);
1693 ret_fr
= vtd_iova_to_slpte(s
, &ce
, addr
, is_write
, &slpte
, &level
,
1694 &reads
, &writes
, s
->aw_bits
);
1695 VTD_PE_GET_FPD_ERR(ret_fr
, is_fpd_set
, s
, source_id
, addr
, is_write
);
1697 page_mask
= vtd_slpt_level_page_mask(level
);
1698 access_flags
= IOMMU_ACCESS_FLAG(reads
, writes
);
1699 vtd_update_iotlb(s
, source_id
, vtd_get_domain_id(s
, &ce
), addr
, slpte
,
1700 access_flags
, level
);
1702 vtd_iommu_unlock(s
);
1703 entry
->iova
= addr
& page_mask
;
1704 entry
->translated_addr
= vtd_get_slpte_addr(slpte
, s
->aw_bits
) & page_mask
;
1705 entry
->addr_mask
= ~page_mask
;
1706 entry
->perm
= access_flags
;
1710 vtd_iommu_unlock(s
);
1712 entry
->translated_addr
= 0;
1713 entry
->addr_mask
= 0;
1714 entry
->perm
= IOMMU_NONE
;
1718 static void vtd_root_table_setup(IntelIOMMUState
*s
)
1720 s
->root
= vtd_get_quad_raw(s
, DMAR_RTADDR_REG
);
1721 s
->root_extended
= s
->root
& VTD_RTADDR_RTT
;
1722 s
->root
&= VTD_RTADDR_ADDR_MASK(s
->aw_bits
);
1724 vtd_update_scalable_state(s
);
1726 trace_vtd_reg_dmar_root(s
->root
, s
->root_extended
);
1729 static void vtd_iec_notify_all(IntelIOMMUState
*s
, bool global
,
1730 uint32_t index
, uint32_t mask
)
1732 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s
), global
, index
, mask
);
1735 static void vtd_interrupt_remap_table_setup(IntelIOMMUState
*s
)
1738 value
= vtd_get_quad_raw(s
, DMAR_IRTA_REG
);
1739 s
->intr_size
= 1UL << ((value
& VTD_IRTA_SIZE_MASK
) + 1);
1740 s
->intr_root
= value
& VTD_IRTA_ADDR_MASK(s
->aw_bits
);
1741 s
->intr_eime
= value
& VTD_IRTA_EIME
;
1743 /* Notify global invalidation */
1744 vtd_iec_notify_all(s
, true, 0, 0);
1746 trace_vtd_reg_ir_root(s
->intr_root
, s
->intr_size
);
1749 static void vtd_iommu_replay_all(IntelIOMMUState
*s
)
1751 VTDAddressSpace
*vtd_as
;
1753 QLIST_FOREACH(vtd_as
, &s
->vtd_as_with_notifiers
, next
) {
1754 vtd_sync_shadow_page_table(vtd_as
);
1758 static void vtd_context_global_invalidate(IntelIOMMUState
*s
)
1760 trace_vtd_inv_desc_cc_global();
1761 /* Protects context cache */
1763 s
->context_cache_gen
++;
1764 if (s
->context_cache_gen
== VTD_CONTEXT_CACHE_GEN_MAX
) {
1765 vtd_reset_context_cache_locked(s
);
1767 vtd_iommu_unlock(s
);
1768 vtd_address_space_refresh_all(s
);
1770 * From VT-d spec 6.5.2.1, a global context entry invalidation
1771 * should be followed by a IOTLB global invalidation, so we should
1772 * be safe even without this. Hoewever, let's replay the region as
1773 * well to be safer, and go back here when we need finer tunes for
1774 * VT-d emulation codes.
1776 vtd_iommu_replay_all(s
);
1779 /* Do a context-cache device-selective invalidation.
1780 * @func_mask: FM field after shifting
1782 static void vtd_context_device_invalidate(IntelIOMMUState
*s
,
1788 VTDAddressSpace
*vtd_as
;
1789 uint8_t bus_n
, devfn
;
1792 trace_vtd_inv_desc_cc_devices(source_id
, func_mask
);
1794 switch (func_mask
& 3) {
1796 mask
= 0; /* No bits in the SID field masked */
1799 mask
= 4; /* Mask bit 2 in the SID field */
1802 mask
= 6; /* Mask bit 2:1 in the SID field */
1805 mask
= 7; /* Mask bit 2:0 in the SID field */
1810 bus_n
= VTD_SID_TO_BUS(source_id
);
1811 vtd_bus
= vtd_find_as_from_bus_num(s
, bus_n
);
1813 devfn
= VTD_SID_TO_DEVFN(source_id
);
1814 for (devfn_it
= 0; devfn_it
< PCI_DEVFN_MAX
; ++devfn_it
) {
1815 vtd_as
= vtd_bus
->dev_as
[devfn_it
];
1816 if (vtd_as
&& ((devfn_it
& mask
) == (devfn
& mask
))) {
1817 trace_vtd_inv_desc_cc_device(bus_n
, VTD_PCI_SLOT(devfn_it
),
1818 VTD_PCI_FUNC(devfn_it
));
1820 vtd_as
->context_cache_entry
.context_cache_gen
= 0;
1821 vtd_iommu_unlock(s
);
1823 * Do switch address space when needed, in case if the
1824 * device passthrough bit is switched.
1826 vtd_switch_address_space(vtd_as
);
1828 * So a device is moving out of (or moving into) a
1829 * domain, resync the shadow page table.
1830 * This won't bring bad even if we have no such
1831 * notifier registered - the IOMMU notification
1832 * framework will skip MAP notifications if that
1835 vtd_sync_shadow_page_table(vtd_as
);
1841 /* Context-cache invalidation
1842 * Returns the Context Actual Invalidation Granularity.
1843 * @val: the content of the CCMD_REG
1845 static uint64_t vtd_context_cache_invalidate(IntelIOMMUState
*s
, uint64_t val
)
1848 uint64_t type
= val
& VTD_CCMD_CIRG_MASK
;
1851 case VTD_CCMD_DOMAIN_INVL
:
1853 case VTD_CCMD_GLOBAL_INVL
:
1854 caig
= VTD_CCMD_GLOBAL_INVL_A
;
1855 vtd_context_global_invalidate(s
);
1858 case VTD_CCMD_DEVICE_INVL
:
1859 caig
= VTD_CCMD_DEVICE_INVL_A
;
1860 vtd_context_device_invalidate(s
, VTD_CCMD_SID(val
), VTD_CCMD_FM(val
));
1864 error_report_once("%s: invalid context: 0x%" PRIx64
,
1871 static void vtd_iotlb_global_invalidate(IntelIOMMUState
*s
)
1873 trace_vtd_inv_desc_iotlb_global();
1875 vtd_iommu_replay_all(s
);
1878 static void vtd_iotlb_domain_invalidate(IntelIOMMUState
*s
, uint16_t domain_id
)
1881 VTDAddressSpace
*vtd_as
;
1883 trace_vtd_inv_desc_iotlb_domain(domain_id
);
1886 g_hash_table_foreach_remove(s
->iotlb
, vtd_hash_remove_by_domain
,
1888 vtd_iommu_unlock(s
);
1890 QLIST_FOREACH(vtd_as
, &s
->vtd_as_with_notifiers
, next
) {
1891 if (!vtd_dev_to_context_entry(s
, pci_bus_num(vtd_as
->bus
),
1892 vtd_as
->devfn
, &ce
) &&
1893 domain_id
== vtd_get_domain_id(s
, &ce
)) {
1894 vtd_sync_shadow_page_table(vtd_as
);
1899 static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState
*s
,
1900 uint16_t domain_id
, hwaddr addr
,
1903 VTDAddressSpace
*vtd_as
;
1906 hwaddr size
= (1 << am
) * VTD_PAGE_SIZE
;
1908 QLIST_FOREACH(vtd_as
, &(s
->vtd_as_with_notifiers
), next
) {
1909 ret
= vtd_dev_to_context_entry(s
, pci_bus_num(vtd_as
->bus
),
1910 vtd_as
->devfn
, &ce
);
1911 if (!ret
&& domain_id
== vtd_get_domain_id(s
, &ce
)) {
1912 if (vtd_as_has_map_notifier(vtd_as
)) {
1914 * As long as we have MAP notifications registered in
1915 * any of our IOMMU notifiers, we need to sync the
1916 * shadow page table.
1918 vtd_sync_shadow_page_table_range(vtd_as
, &ce
, addr
, size
);
1921 * For UNMAP-only notifiers, we don't need to walk the
1922 * page tables. We just deliver the PSI down to
1923 * invalidate caches.
1925 IOMMUTLBEntry entry
= {
1926 .target_as
= &address_space_memory
,
1928 .translated_addr
= 0,
1929 .addr_mask
= size
- 1,
1932 memory_region_notify_iommu(&vtd_as
->iommu
, 0, entry
);
1938 static void vtd_iotlb_page_invalidate(IntelIOMMUState
*s
, uint16_t domain_id
,
1939 hwaddr addr
, uint8_t am
)
1941 VTDIOTLBPageInvInfo info
;
1943 trace_vtd_inv_desc_iotlb_pages(domain_id
, addr
, am
);
1945 assert(am
<= VTD_MAMV
);
1946 info
.domain_id
= domain_id
;
1948 info
.mask
= ~((1 << am
) - 1);
1950 g_hash_table_foreach_remove(s
->iotlb
, vtd_hash_remove_by_page
, &info
);
1951 vtd_iommu_unlock(s
);
1952 vtd_iotlb_page_invalidate_notify(s
, domain_id
, addr
, am
);
1956 * Returns the IOTLB Actual Invalidation Granularity.
1957 * @val: the content of the IOTLB_REG
1959 static uint64_t vtd_iotlb_flush(IntelIOMMUState
*s
, uint64_t val
)
1962 uint64_t type
= val
& VTD_TLB_FLUSH_GRANU_MASK
;
1968 case VTD_TLB_GLOBAL_FLUSH
:
1969 iaig
= VTD_TLB_GLOBAL_FLUSH_A
;
1970 vtd_iotlb_global_invalidate(s
);
1973 case VTD_TLB_DSI_FLUSH
:
1974 domain_id
= VTD_TLB_DID(val
);
1975 iaig
= VTD_TLB_DSI_FLUSH_A
;
1976 vtd_iotlb_domain_invalidate(s
, domain_id
);
1979 case VTD_TLB_PSI_FLUSH
:
1980 domain_id
= VTD_TLB_DID(val
);
1981 addr
= vtd_get_quad_raw(s
, DMAR_IVA_REG
);
1982 am
= VTD_IVA_AM(addr
);
1983 addr
= VTD_IVA_ADDR(addr
);
1984 if (am
> VTD_MAMV
) {
1985 error_report_once("%s: address mask overflow: 0x%" PRIx64
,
1986 __func__
, vtd_get_quad_raw(s
, DMAR_IVA_REG
));
1990 iaig
= VTD_TLB_PSI_FLUSH_A
;
1991 vtd_iotlb_page_invalidate(s
, domain_id
, addr
, am
);
1995 error_report_once("%s: invalid granularity: 0x%" PRIx64
,
2002 static void vtd_fetch_inv_desc(IntelIOMMUState
*s
);
2004 static inline bool vtd_queued_inv_disable_check(IntelIOMMUState
*s
)
2006 return s
->qi_enabled
&& (s
->iq_tail
== s
->iq_head
) &&
2007 (s
->iq_last_desc_type
== VTD_INV_DESC_WAIT
);
2010 static void vtd_handle_gcmd_qie(IntelIOMMUState
*s
, bool en
)
2012 uint64_t iqa_val
= vtd_get_quad_raw(s
, DMAR_IQA_REG
);
2014 trace_vtd_inv_qi_enable(en
);
2017 s
->iq
= iqa_val
& VTD_IQA_IQA_MASK(s
->aw_bits
);
2018 /* 2^(x+8) entries */
2019 s
->iq_size
= 1UL << ((iqa_val
& VTD_IQA_QS
) + 8 - (s
->iq_dw
? 1 : 0));
2020 s
->qi_enabled
= true;
2021 trace_vtd_inv_qi_setup(s
->iq
, s
->iq_size
);
2022 /* Ok - report back to driver */
2023 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_QIES
);
2025 if (s
->iq_tail
!= 0) {
2027 * This is a spec violation but Windows guests are known to set up
2028 * Queued Invalidation this way so we allow the write and process
2029 * Invalidation Descriptors right away.
2031 trace_vtd_warn_invalid_qi_tail(s
->iq_tail
);
2032 if (!(vtd_get_long_raw(s
, DMAR_FSTS_REG
) & VTD_FSTS_IQE
)) {
2033 vtd_fetch_inv_desc(s
);
2037 if (vtd_queued_inv_disable_check(s
)) {
2038 /* disable Queued Invalidation */
2039 vtd_set_quad_raw(s
, DMAR_IQH_REG
, 0);
2041 s
->qi_enabled
= false;
2042 /* Ok - report back to driver */
2043 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_QIES
, 0);
2045 error_report_once("%s: detected improper state when disable QI "
2046 "(head=0x%x, tail=0x%x, last_type=%d)",
2048 s
->iq_head
, s
->iq_tail
, s
->iq_last_desc_type
);
2053 /* Set Root Table Pointer */
2054 static void vtd_handle_gcmd_srtp(IntelIOMMUState
*s
)
2056 vtd_root_table_setup(s
);
2057 /* Ok - report back to driver */
2058 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_RTPS
);
2059 vtd_reset_caches(s
);
2060 vtd_address_space_refresh_all(s
);
2063 /* Set Interrupt Remap Table Pointer */
2064 static void vtd_handle_gcmd_sirtp(IntelIOMMUState
*s
)
2066 vtd_interrupt_remap_table_setup(s
);
2067 /* Ok - report back to driver */
2068 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_IRTPS
);
2071 /* Handle Translation Enable/Disable */
2072 static void vtd_handle_gcmd_te(IntelIOMMUState
*s
, bool en
)
2074 if (s
->dmar_enabled
== en
) {
2078 trace_vtd_dmar_enable(en
);
2081 s
->dmar_enabled
= true;
2082 /* Ok - report back to driver */
2083 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_TES
);
2085 s
->dmar_enabled
= false;
2087 /* Clear the index of Fault Recording Register */
2088 s
->next_frcd_reg
= 0;
2089 /* Ok - report back to driver */
2090 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_TES
, 0);
2093 vtd_reset_caches(s
);
2094 vtd_address_space_refresh_all(s
);
2097 /* Handle Interrupt Remap Enable/Disable */
2098 static void vtd_handle_gcmd_ire(IntelIOMMUState
*s
, bool en
)
2100 trace_vtd_ir_enable(en
);
2103 s
->intr_enabled
= true;
2104 /* Ok - report back to driver */
2105 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, 0, VTD_GSTS_IRES
);
2107 s
->intr_enabled
= false;
2108 /* Ok - report back to driver */
2109 vtd_set_clear_mask_long(s
, DMAR_GSTS_REG
, VTD_GSTS_IRES
, 0);
2113 /* Handle write to Global Command Register */
2114 static void vtd_handle_gcmd_write(IntelIOMMUState
*s
)
2116 uint32_t status
= vtd_get_long_raw(s
, DMAR_GSTS_REG
);
2117 uint32_t val
= vtd_get_long_raw(s
, DMAR_GCMD_REG
);
2118 uint32_t changed
= status
^ val
;
2120 trace_vtd_reg_write_gcmd(status
, val
);
2121 if (changed
& VTD_GCMD_TE
) {
2122 /* Translation enable/disable */
2123 vtd_handle_gcmd_te(s
, val
& VTD_GCMD_TE
);
2125 if (val
& VTD_GCMD_SRTP
) {
2126 /* Set/update the root-table pointer */
2127 vtd_handle_gcmd_srtp(s
);
2129 if (changed
& VTD_GCMD_QIE
) {
2130 /* Queued Invalidation Enable */
2131 vtd_handle_gcmd_qie(s
, val
& VTD_GCMD_QIE
);
2133 if (val
& VTD_GCMD_SIRTP
) {
2134 /* Set/update the interrupt remapping root-table pointer */
2135 vtd_handle_gcmd_sirtp(s
);
2137 if (changed
& VTD_GCMD_IRE
) {
2138 /* Interrupt remap enable/disable */
2139 vtd_handle_gcmd_ire(s
, val
& VTD_GCMD_IRE
);
2143 /* Handle write to Context Command Register */
2144 static void vtd_handle_ccmd_write(IntelIOMMUState
*s
)
2147 uint64_t val
= vtd_get_quad_raw(s
, DMAR_CCMD_REG
);
2149 /* Context-cache invalidation request */
2150 if (val
& VTD_CCMD_ICC
) {
2151 if (s
->qi_enabled
) {
2152 error_report_once("Queued Invalidation enabled, "
2153 "should not use register-based invalidation");
2156 ret
= vtd_context_cache_invalidate(s
, val
);
2157 /* Invalidation completed. Change something to show */
2158 vtd_set_clear_mask_quad(s
, DMAR_CCMD_REG
, VTD_CCMD_ICC
, 0ULL);
2159 ret
= vtd_set_clear_mask_quad(s
, DMAR_CCMD_REG
, VTD_CCMD_CAIG_MASK
,
2164 /* Handle write to IOTLB Invalidation Register */
2165 static void vtd_handle_iotlb_write(IntelIOMMUState
*s
)
2168 uint64_t val
= vtd_get_quad_raw(s
, DMAR_IOTLB_REG
);
2170 /* IOTLB invalidation request */
2171 if (val
& VTD_TLB_IVT
) {
2172 if (s
->qi_enabled
) {
2173 error_report_once("Queued Invalidation enabled, "
2174 "should not use register-based invalidation");
2177 ret
= vtd_iotlb_flush(s
, val
);
2178 /* Invalidation completed. Change something to show */
2179 vtd_set_clear_mask_quad(s
, DMAR_IOTLB_REG
, VTD_TLB_IVT
, 0ULL);
2180 ret
= vtd_set_clear_mask_quad(s
, DMAR_IOTLB_REG
,
2181 VTD_TLB_FLUSH_GRANU_MASK_A
, ret
);
2185 /* Fetch an Invalidation Descriptor from the Invalidation Queue */
2186 static bool vtd_get_inv_desc(IntelIOMMUState
*s
,
2187 VTDInvDesc
*inv_desc
)
2189 dma_addr_t base_addr
= s
->iq
;
2190 uint32_t offset
= s
->iq_head
;
2191 uint32_t dw
= s
->iq_dw
? 32 : 16;
2192 dma_addr_t addr
= base_addr
+ offset
* dw
;
2194 if (dma_memory_read(&address_space_memory
, addr
, inv_desc
, dw
)) {
2195 error_report_once("Read INV DESC failed.");
2198 inv_desc
->lo
= le64_to_cpu(inv_desc
->lo
);
2199 inv_desc
->hi
= le64_to_cpu(inv_desc
->hi
);
2201 inv_desc
->val
[2] = le64_to_cpu(inv_desc
->val
[2]);
2202 inv_desc
->val
[3] = le64_to_cpu(inv_desc
->val
[3]);
2207 static bool vtd_process_wait_desc(IntelIOMMUState
*s
, VTDInvDesc
*inv_desc
)
2209 if ((inv_desc
->hi
& VTD_INV_DESC_WAIT_RSVD_HI
) ||
2210 (inv_desc
->lo
& VTD_INV_DESC_WAIT_RSVD_LO
)) {
2211 error_report_once("%s: invalid wait desc: hi=%"PRIx64
", lo=%"PRIx64
2212 " (reserved nonzero)", __func__
, inv_desc
->hi
,
2216 if (inv_desc
->lo
& VTD_INV_DESC_WAIT_SW
) {
2218 uint32_t status_data
= (uint32_t)(inv_desc
->lo
>>
2219 VTD_INV_DESC_WAIT_DATA_SHIFT
);
2221 assert(!(inv_desc
->lo
& VTD_INV_DESC_WAIT_IF
));
2223 /* FIXME: need to be masked with HAW? */
2224 dma_addr_t status_addr
= inv_desc
->hi
;
2225 trace_vtd_inv_desc_wait_sw(status_addr
, status_data
);
2226 status_data
= cpu_to_le32(status_data
);
2227 if (dma_memory_write(&address_space_memory
, status_addr
, &status_data
,
2228 sizeof(status_data
))) {
2229 trace_vtd_inv_desc_wait_write_fail(inv_desc
->hi
, inv_desc
->lo
);
2232 } else if (inv_desc
->lo
& VTD_INV_DESC_WAIT_IF
) {
2233 /* Interrupt flag */
2234 vtd_generate_completion_event(s
);
2236 error_report_once("%s: invalid wait desc: hi=%"PRIx64
", lo=%"PRIx64
2237 " (unknown type)", __func__
, inv_desc
->hi
,
2244 static bool vtd_process_context_cache_desc(IntelIOMMUState
*s
,
2245 VTDInvDesc
*inv_desc
)
2247 uint16_t sid
, fmask
;
2249 if ((inv_desc
->lo
& VTD_INV_DESC_CC_RSVD
) || inv_desc
->hi
) {
2250 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64
", lo=%"PRIx64
2251 " (reserved nonzero)", __func__
, inv_desc
->hi
,
2255 switch (inv_desc
->lo
& VTD_INV_DESC_CC_G
) {
2256 case VTD_INV_DESC_CC_DOMAIN
:
2257 trace_vtd_inv_desc_cc_domain(
2258 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc
->lo
));
2260 case VTD_INV_DESC_CC_GLOBAL
:
2261 vtd_context_global_invalidate(s
);
2264 case VTD_INV_DESC_CC_DEVICE
:
2265 sid
= VTD_INV_DESC_CC_SID(inv_desc
->lo
);
2266 fmask
= VTD_INV_DESC_CC_FM(inv_desc
->lo
);
2267 vtd_context_device_invalidate(s
, sid
, fmask
);
2271 error_report_once("%s: invalid cc inv desc: hi=%"PRIx64
", lo=%"PRIx64
2272 " (invalid type)", __func__
, inv_desc
->hi
,
2279 static bool vtd_process_iotlb_desc(IntelIOMMUState
*s
, VTDInvDesc
*inv_desc
)
2285 if ((inv_desc
->lo
& VTD_INV_DESC_IOTLB_RSVD_LO
) ||
2286 (inv_desc
->hi
& VTD_INV_DESC_IOTLB_RSVD_HI
)) {
2287 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64
2288 ", lo=0x%"PRIx64
" (reserved bits unzero)\n",
2289 __func__
, inv_desc
->hi
, inv_desc
->lo
);
2293 switch (inv_desc
->lo
& VTD_INV_DESC_IOTLB_G
) {
2294 case VTD_INV_DESC_IOTLB_GLOBAL
:
2295 vtd_iotlb_global_invalidate(s
);
2298 case VTD_INV_DESC_IOTLB_DOMAIN
:
2299 domain_id
= VTD_INV_DESC_IOTLB_DID(inv_desc
->lo
);
2300 vtd_iotlb_domain_invalidate(s
, domain_id
);
2303 case VTD_INV_DESC_IOTLB_PAGE
:
2304 domain_id
= VTD_INV_DESC_IOTLB_DID(inv_desc
->lo
);
2305 addr
= VTD_INV_DESC_IOTLB_ADDR(inv_desc
->hi
);
2306 am
= VTD_INV_DESC_IOTLB_AM(inv_desc
->hi
);
2307 if (am
> VTD_MAMV
) {
2308 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64
2309 ", lo=0x%"PRIx64
" (am=%u > VTD_MAMV=%u)\n",
2310 __func__
, inv_desc
->hi
, inv_desc
->lo
,
2311 am
, (unsigned)VTD_MAMV
);
2314 vtd_iotlb_page_invalidate(s
, domain_id
, addr
, am
);
2318 error_report_once("%s: invalid iotlb inv desc: hi=0x%"PRIx64
2319 ", lo=0x%"PRIx64
" (type mismatch: 0x%llx)\n",
2320 __func__
, inv_desc
->hi
, inv_desc
->lo
,
2321 inv_desc
->lo
& VTD_INV_DESC_IOTLB_G
);
2327 static bool vtd_process_inv_iec_desc(IntelIOMMUState
*s
,
2328 VTDInvDesc
*inv_desc
)
2330 trace_vtd_inv_desc_iec(inv_desc
->iec
.granularity
,
2331 inv_desc
->iec
.index
,
2332 inv_desc
->iec
.index_mask
);
2334 vtd_iec_notify_all(s
, !inv_desc
->iec
.granularity
,
2335 inv_desc
->iec
.index
,
2336 inv_desc
->iec
.index_mask
);
2340 static bool vtd_process_device_iotlb_desc(IntelIOMMUState
*s
,
2341 VTDInvDesc
*inv_desc
)
2343 VTDAddressSpace
*vtd_dev_as
;
2344 IOMMUTLBEntry entry
;
2345 struct VTDBus
*vtd_bus
;
2353 addr
= VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc
->hi
);
2354 sid
= VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc
->lo
);
2357 size
= VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc
->hi
);
2359 if ((inv_desc
->lo
& VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO
) ||
2360 (inv_desc
->hi
& VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI
)) {
2361 error_report_once("%s: invalid dev-iotlb inv desc: hi=%"PRIx64
2362 ", lo=%"PRIx64
" (reserved nonzero)", __func__
,
2363 inv_desc
->hi
, inv_desc
->lo
);
2367 vtd_bus
= vtd_find_as_from_bus_num(s
, bus_num
);
2372 vtd_dev_as
= vtd_bus
->dev_as
[devfn
];
2377 /* According to ATS spec table 2.4:
2378 * S = 0, bits 15:12 = xxxx range size: 4K
2379 * S = 1, bits 15:12 = xxx0 range size: 8K
2380 * S = 1, bits 15:12 = xx01 range size: 16K
2381 * S = 1, bits 15:12 = x011 range size: 32K
2382 * S = 1, bits 15:12 = 0111 range size: 64K
2386 sz
= (VTD_PAGE_SIZE
* 2) << cto64(addr
>> VTD_PAGE_SHIFT
);
2392 entry
.target_as
= &vtd_dev_as
->as
;
2393 entry
.addr_mask
= sz
- 1;
2395 entry
.perm
= IOMMU_NONE
;
2396 entry
.translated_addr
= 0;
2397 memory_region_notify_iommu(&vtd_dev_as
->iommu
, 0, entry
);
2403 static bool vtd_process_inv_desc(IntelIOMMUState
*s
)
2405 VTDInvDesc inv_desc
;
2408 trace_vtd_inv_qi_head(s
->iq_head
);
2409 if (!vtd_get_inv_desc(s
, &inv_desc
)) {
2410 s
->iq_last_desc_type
= VTD_INV_DESC_NONE
;
2414 desc_type
= inv_desc
.lo
& VTD_INV_DESC_TYPE
;
2415 /* FIXME: should update at first or at last? */
2416 s
->iq_last_desc_type
= desc_type
;
2418 switch (desc_type
) {
2419 case VTD_INV_DESC_CC
:
2420 trace_vtd_inv_desc("context-cache", inv_desc
.hi
, inv_desc
.lo
);
2421 if (!vtd_process_context_cache_desc(s
, &inv_desc
)) {
2426 case VTD_INV_DESC_IOTLB
:
2427 trace_vtd_inv_desc("iotlb", inv_desc
.hi
, inv_desc
.lo
);
2428 if (!vtd_process_iotlb_desc(s
, &inv_desc
)) {
2434 * TODO: the entity of below two cases will be implemented in future series.
2435 * To make guest (which integrates scalable mode support patch set in
2436 * iommu driver) work, just return true is enough so far.
2438 case VTD_INV_DESC_PC
:
2441 case VTD_INV_DESC_PIOTLB
:
2444 case VTD_INV_DESC_WAIT
:
2445 trace_vtd_inv_desc("wait", inv_desc
.hi
, inv_desc
.lo
);
2446 if (!vtd_process_wait_desc(s
, &inv_desc
)) {
2451 case VTD_INV_DESC_IEC
:
2452 trace_vtd_inv_desc("iec", inv_desc
.hi
, inv_desc
.lo
);
2453 if (!vtd_process_inv_iec_desc(s
, &inv_desc
)) {
2458 case VTD_INV_DESC_DEVICE
:
2459 trace_vtd_inv_desc("device", inv_desc
.hi
, inv_desc
.lo
);
2460 if (!vtd_process_device_iotlb_desc(s
, &inv_desc
)) {
2466 error_report_once("%s: invalid inv desc: hi=%"PRIx64
", lo=%"PRIx64
2467 " (unknown type)", __func__
, inv_desc
.hi
,
2472 if (s
->iq_head
== s
->iq_size
) {
2478 /* Try to fetch and process more Invalidation Descriptors */
2479 static void vtd_fetch_inv_desc(IntelIOMMUState
*s
)
2481 trace_vtd_inv_qi_fetch();
2483 if (s
->iq_tail
>= s
->iq_size
) {
2484 /* Detects an invalid Tail pointer */
2485 error_report_once("%s: detected invalid QI tail "
2486 "(tail=0x%x, size=0x%x)",
2487 __func__
, s
->iq_tail
, s
->iq_size
);
2488 vtd_handle_inv_queue_error(s
);
2491 while (s
->iq_head
!= s
->iq_tail
) {
2492 if (!vtd_process_inv_desc(s
)) {
2493 /* Invalidation Queue Errors */
2494 vtd_handle_inv_queue_error(s
);
2497 /* Must update the IQH_REG in time */
2498 vtd_set_quad_raw(s
, DMAR_IQH_REG
,
2499 (((uint64_t)(s
->iq_head
)) << VTD_IQH_QH_SHIFT
) &
2504 /* Handle write to Invalidation Queue Tail Register */
2505 static void vtd_handle_iqt_write(IntelIOMMUState
*s
)
2507 uint64_t val
= vtd_get_quad_raw(s
, DMAR_IQT_REG
);
2509 if (s
->iq_dw
&& (val
& VTD_IQT_QT_256_RSV_BIT
)) {
2510 error_report_once("%s: RSV bit is set: val=0x%"PRIx64
,
2514 s
->iq_tail
= VTD_IQT_QT(s
->iq_dw
, val
);
2515 trace_vtd_inv_qi_tail(s
->iq_tail
);
2517 if (s
->qi_enabled
&& !(vtd_get_long_raw(s
, DMAR_FSTS_REG
) & VTD_FSTS_IQE
)) {
2518 /* Process Invalidation Queue here */
2519 vtd_fetch_inv_desc(s
);
2523 static void vtd_handle_fsts_write(IntelIOMMUState
*s
)
2525 uint32_t fsts_reg
= vtd_get_long_raw(s
, DMAR_FSTS_REG
);
2526 uint32_t fectl_reg
= vtd_get_long_raw(s
, DMAR_FECTL_REG
);
2527 uint32_t status_fields
= VTD_FSTS_PFO
| VTD_FSTS_PPF
| VTD_FSTS_IQE
;
2529 if ((fectl_reg
& VTD_FECTL_IP
) && !(fsts_reg
& status_fields
)) {
2530 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
2531 trace_vtd_fsts_clear_ip();
2533 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
2534 * Descriptors if there are any when Queued Invalidation is enabled?
2538 static void vtd_handle_fectl_write(IntelIOMMUState
*s
)
2541 /* FIXME: when software clears the IM field, check the IP field. But do we
2542 * need to compare the old value and the new value to conclude that
2543 * software clears the IM field? Or just check if the IM field is zero?
2545 fectl_reg
= vtd_get_long_raw(s
, DMAR_FECTL_REG
);
2547 trace_vtd_reg_write_fectl(fectl_reg
);
2549 if ((fectl_reg
& VTD_FECTL_IP
) && !(fectl_reg
& VTD_FECTL_IM
)) {
2550 vtd_generate_interrupt(s
, DMAR_FEADDR_REG
, DMAR_FEDATA_REG
);
2551 vtd_set_clear_mask_long(s
, DMAR_FECTL_REG
, VTD_FECTL_IP
, 0);
2555 static void vtd_handle_ics_write(IntelIOMMUState
*s
)
2557 uint32_t ics_reg
= vtd_get_long_raw(s
, DMAR_ICS_REG
);
2558 uint32_t iectl_reg
= vtd_get_long_raw(s
, DMAR_IECTL_REG
);
2560 if ((iectl_reg
& VTD_IECTL_IP
) && !(ics_reg
& VTD_ICS_IWC
)) {
2561 trace_vtd_reg_ics_clear_ip();
2562 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
2566 static void vtd_handle_iectl_write(IntelIOMMUState
*s
)
2569 /* FIXME: when software clears the IM field, check the IP field. But do we
2570 * need to compare the old value and the new value to conclude that
2571 * software clears the IM field? Or just check if the IM field is zero?
2573 iectl_reg
= vtd_get_long_raw(s
, DMAR_IECTL_REG
);
2575 trace_vtd_reg_write_iectl(iectl_reg
);
2577 if ((iectl_reg
& VTD_IECTL_IP
) && !(iectl_reg
& VTD_IECTL_IM
)) {
2578 vtd_generate_interrupt(s
, DMAR_IEADDR_REG
, DMAR_IEDATA_REG
);
2579 vtd_set_clear_mask_long(s
, DMAR_IECTL_REG
, VTD_IECTL_IP
, 0);
2583 static uint64_t vtd_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
2585 IntelIOMMUState
*s
= opaque
;
2588 trace_vtd_reg_read(addr
, size
);
2590 if (addr
+ size
> DMAR_REG_SIZE
) {
2591 error_report_once("%s: MMIO over range: addr=0x%" PRIx64
2592 " size=0x%u", __func__
, addr
, size
);
2593 return (uint64_t)-1;
2597 /* Root Table Address Register, 64-bit */
2598 case DMAR_RTADDR_REG
:
2600 val
= s
->root
& ((1ULL << 32) - 1);
2606 case DMAR_RTADDR_REG_HI
:
2608 val
= s
->root
>> 32;
2611 /* Invalidation Queue Address Register, 64-bit */
2613 val
= s
->iq
| (vtd_get_quad(s
, DMAR_IQA_REG
) & VTD_IQA_QS
);
2615 val
= val
& ((1ULL << 32) - 1);
2619 case DMAR_IQA_REG_HI
:
2626 val
= vtd_get_long(s
, addr
);
2628 val
= vtd_get_quad(s
, addr
);
2635 static void vtd_mem_write(void *opaque
, hwaddr addr
,
2636 uint64_t val
, unsigned size
)
2638 IntelIOMMUState
*s
= opaque
;
2640 trace_vtd_reg_write(addr
, size
, val
);
2642 if (addr
+ size
> DMAR_REG_SIZE
) {
2643 error_report_once("%s: MMIO over range: addr=0x%" PRIx64
2644 " size=0x%u", __func__
, addr
, size
);
2649 /* Global Command Register, 32-bit */
2651 vtd_set_long(s
, addr
, val
);
2652 vtd_handle_gcmd_write(s
);
2655 /* Context Command Register, 64-bit */
2658 vtd_set_long(s
, addr
, val
);
2660 vtd_set_quad(s
, addr
, val
);
2661 vtd_handle_ccmd_write(s
);
2665 case DMAR_CCMD_REG_HI
:
2667 vtd_set_long(s
, addr
, val
);
2668 vtd_handle_ccmd_write(s
);
2671 /* IOTLB Invalidation Register, 64-bit */
2672 case DMAR_IOTLB_REG
:
2674 vtd_set_long(s
, addr
, val
);
2676 vtd_set_quad(s
, addr
, val
);
2677 vtd_handle_iotlb_write(s
);
2681 case DMAR_IOTLB_REG_HI
:
2683 vtd_set_long(s
, addr
, val
);
2684 vtd_handle_iotlb_write(s
);
2687 /* Invalidate Address Register, 64-bit */
2690 vtd_set_long(s
, addr
, val
);
2692 vtd_set_quad(s
, addr
, val
);
2696 case DMAR_IVA_REG_HI
:
2698 vtd_set_long(s
, addr
, val
);
2701 /* Fault Status Register, 32-bit */
2704 vtd_set_long(s
, addr
, val
);
2705 vtd_handle_fsts_write(s
);
2708 /* Fault Event Control Register, 32-bit */
2709 case DMAR_FECTL_REG
:
2711 vtd_set_long(s
, addr
, val
);
2712 vtd_handle_fectl_write(s
);
2715 /* Fault Event Data Register, 32-bit */
2716 case DMAR_FEDATA_REG
:
2718 vtd_set_long(s
, addr
, val
);
2721 /* Fault Event Address Register, 32-bit */
2722 case DMAR_FEADDR_REG
:
2724 vtd_set_long(s
, addr
, val
);
2727 * While the register is 32-bit only, some guests (Xen...) write to
2730 vtd_set_quad(s
, addr
, val
);
2734 /* Fault Event Upper Address Register, 32-bit */
2735 case DMAR_FEUADDR_REG
:
2737 vtd_set_long(s
, addr
, val
);
2740 /* Protected Memory Enable Register, 32-bit */
2743 vtd_set_long(s
, addr
, val
);
2746 /* Root Table Address Register, 64-bit */
2747 case DMAR_RTADDR_REG
:
2749 vtd_set_long(s
, addr
, val
);
2751 vtd_set_quad(s
, addr
, val
);
2755 case DMAR_RTADDR_REG_HI
:
2757 vtd_set_long(s
, addr
, val
);
2760 /* Invalidation Queue Tail Register, 64-bit */
2763 vtd_set_long(s
, addr
, val
);
2765 vtd_set_quad(s
, addr
, val
);
2767 vtd_handle_iqt_write(s
);
2770 case DMAR_IQT_REG_HI
:
2772 vtd_set_long(s
, addr
, val
);
2773 /* 19:63 of IQT_REG is RsvdZ, do nothing here */
2776 /* Invalidation Queue Address Register, 64-bit */
2779 vtd_set_long(s
, addr
, val
);
2781 vtd_set_quad(s
, addr
, val
);
2783 if (s
->ecap
& VTD_ECAP_SMTS
&&
2784 val
& VTD_IQA_DW_MASK
) {
2791 case DMAR_IQA_REG_HI
:
2793 vtd_set_long(s
, addr
, val
);
2796 /* Invalidation Completion Status Register, 32-bit */
2799 vtd_set_long(s
, addr
, val
);
2800 vtd_handle_ics_write(s
);
2803 /* Invalidation Event Control Register, 32-bit */
2804 case DMAR_IECTL_REG
:
2806 vtd_set_long(s
, addr
, val
);
2807 vtd_handle_iectl_write(s
);
2810 /* Invalidation Event Data Register, 32-bit */
2811 case DMAR_IEDATA_REG
:
2813 vtd_set_long(s
, addr
, val
);
2816 /* Invalidation Event Address Register, 32-bit */
2817 case DMAR_IEADDR_REG
:
2819 vtd_set_long(s
, addr
, val
);
2822 /* Invalidation Event Upper Address Register, 32-bit */
2823 case DMAR_IEUADDR_REG
:
2825 vtd_set_long(s
, addr
, val
);
2828 /* Fault Recording Registers, 128-bit */
2829 case DMAR_FRCD_REG_0_0
:
2831 vtd_set_long(s
, addr
, val
);
2833 vtd_set_quad(s
, addr
, val
);
2837 case DMAR_FRCD_REG_0_1
:
2839 vtd_set_long(s
, addr
, val
);
2842 case DMAR_FRCD_REG_0_2
:
2844 vtd_set_long(s
, addr
, val
);
2846 vtd_set_quad(s
, addr
, val
);
2847 /* May clear bit 127 (Fault), update PPF */
2848 vtd_update_fsts_ppf(s
);
2852 case DMAR_FRCD_REG_0_3
:
2854 vtd_set_long(s
, addr
, val
);
2855 /* May clear bit 127 (Fault), update PPF */
2856 vtd_update_fsts_ppf(s
);
2861 vtd_set_long(s
, addr
, val
);
2863 vtd_set_quad(s
, addr
, val
);
2867 case DMAR_IRTA_REG_HI
:
2869 vtd_set_long(s
, addr
, val
);
2874 vtd_set_long(s
, addr
, val
);
2876 vtd_set_quad(s
, addr
, val
);
2881 static IOMMUTLBEntry
vtd_iommu_translate(IOMMUMemoryRegion
*iommu
, hwaddr addr
,
2882 IOMMUAccessFlags flag
, int iommu_idx
)
2884 VTDAddressSpace
*vtd_as
= container_of(iommu
, VTDAddressSpace
, iommu
);
2885 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
2886 IOMMUTLBEntry iotlb
= {
2887 /* We'll fill in the rest later. */
2888 .target_as
= &address_space_memory
,
2892 if (likely(s
->dmar_enabled
)) {
2893 success
= vtd_do_iommu_translate(vtd_as
, vtd_as
->bus
, vtd_as
->devfn
,
2894 addr
, flag
& IOMMU_WO
, &iotlb
);
2896 /* DMAR disabled, passthrough, use 4k-page*/
2897 iotlb
.iova
= addr
& VTD_PAGE_MASK_4K
;
2898 iotlb
.translated_addr
= addr
& VTD_PAGE_MASK_4K
;
2899 iotlb
.addr_mask
= ~VTD_PAGE_MASK_4K
;
2900 iotlb
.perm
= IOMMU_RW
;
2904 if (likely(success
)) {
2905 trace_vtd_dmar_translate(pci_bus_num(vtd_as
->bus
),
2906 VTD_PCI_SLOT(vtd_as
->devfn
),
2907 VTD_PCI_FUNC(vtd_as
->devfn
),
2908 iotlb
.iova
, iotlb
.translated_addr
,
2911 error_report_once("%s: detected translation failure "
2912 "(dev=%02x:%02x:%02x, iova=0x%" PRIx64
")",
2913 __func__
, pci_bus_num(vtd_as
->bus
),
2914 VTD_PCI_SLOT(vtd_as
->devfn
),
2915 VTD_PCI_FUNC(vtd_as
->devfn
),
2922 static void vtd_iommu_notify_flag_changed(IOMMUMemoryRegion
*iommu
,
2923 IOMMUNotifierFlag old
,
2924 IOMMUNotifierFlag
new)
2926 VTDAddressSpace
*vtd_as
= container_of(iommu
, VTDAddressSpace
, iommu
);
2927 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
2929 if (!s
->caching_mode
&& new & IOMMU_NOTIFIER_MAP
) {
2930 error_report("We need to set caching-mode=on for intel-iommu to enable "
2931 "device assignment with IOMMU protection.");
2935 /* Update per-address-space notifier flags */
2936 vtd_as
->notifier_flags
= new;
2938 if (old
== IOMMU_NOTIFIER_NONE
) {
2939 QLIST_INSERT_HEAD(&s
->vtd_as_with_notifiers
, vtd_as
, next
);
2940 } else if (new == IOMMU_NOTIFIER_NONE
) {
2941 QLIST_REMOVE(vtd_as
, next
);
2945 static int vtd_post_load(void *opaque
, int version_id
)
2947 IntelIOMMUState
*iommu
= opaque
;
2950 * Memory regions are dynamically turned on/off depending on
2951 * context entry configurations from the guest. After migration,
2952 * we need to make sure the memory regions are still correct.
2954 vtd_switch_address_space_all(iommu
);
2957 * We don't need to migrate the root_scalable because we can
2958 * simply do the calculation after the loading is complete. We
2959 * can actually do similar things with root, dmar_enabled, etc.
2960 * however since we've had them already so we'd better keep them
2961 * for compatibility of migration.
2963 vtd_update_scalable_state(iommu
);
2968 static const VMStateDescription vtd_vmstate
= {
2969 .name
= "iommu-intel",
2971 .minimum_version_id
= 1,
2972 .priority
= MIG_PRI_IOMMU
,
2973 .post_load
= vtd_post_load
,
2974 .fields
= (VMStateField
[]) {
2975 VMSTATE_UINT64(root
, IntelIOMMUState
),
2976 VMSTATE_UINT64(intr_root
, IntelIOMMUState
),
2977 VMSTATE_UINT64(iq
, IntelIOMMUState
),
2978 VMSTATE_UINT32(intr_size
, IntelIOMMUState
),
2979 VMSTATE_UINT16(iq_head
, IntelIOMMUState
),
2980 VMSTATE_UINT16(iq_tail
, IntelIOMMUState
),
2981 VMSTATE_UINT16(iq_size
, IntelIOMMUState
),
2982 VMSTATE_UINT16(next_frcd_reg
, IntelIOMMUState
),
2983 VMSTATE_UINT8_ARRAY(csr
, IntelIOMMUState
, DMAR_REG_SIZE
),
2984 VMSTATE_UINT8(iq_last_desc_type
, IntelIOMMUState
),
2985 VMSTATE_BOOL(root_extended
, IntelIOMMUState
),
2986 VMSTATE_BOOL(dmar_enabled
, IntelIOMMUState
),
2987 VMSTATE_BOOL(qi_enabled
, IntelIOMMUState
),
2988 VMSTATE_BOOL(intr_enabled
, IntelIOMMUState
),
2989 VMSTATE_BOOL(intr_eime
, IntelIOMMUState
),
2990 VMSTATE_END_OF_LIST()
2994 static const MemoryRegionOps vtd_mem_ops
= {
2995 .read
= vtd_mem_read
,
2996 .write
= vtd_mem_write
,
2997 .endianness
= DEVICE_LITTLE_ENDIAN
,
2999 .min_access_size
= 4,
3000 .max_access_size
= 8,
3003 .min_access_size
= 4,
3004 .max_access_size
= 8,
3008 static Property vtd_properties
[] = {
3009 DEFINE_PROP_UINT32("version", IntelIOMMUState
, version
, 0),
3010 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState
, intr_eim
,
3012 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState
, buggy_eim
, false),
3013 DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState
, aw_bits
,
3014 VTD_HOST_ADDRESS_WIDTH
),
3015 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState
, caching_mode
, FALSE
),
3016 DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState
, scalable_mode
, FALSE
),
3017 DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState
, dma_drain
, true),
3018 DEFINE_PROP_END_OF_LIST(),
3021 /* Read IRTE entry with specific index */
3022 static int vtd_irte_get(IntelIOMMUState
*iommu
, uint16_t index
,
3023 VTD_IR_TableEntry
*entry
, uint16_t sid
)
3025 static const uint16_t vtd_svt_mask
[VTD_SQ_MAX
] = \
3026 {0xffff, 0xfffb, 0xfff9, 0xfff8};
3027 dma_addr_t addr
= 0x00;
3028 uint16_t mask
, source_id
;
3029 uint8_t bus
, bus_max
, bus_min
;
3031 addr
= iommu
->intr_root
+ index
* sizeof(*entry
);
3032 if (dma_memory_read(&address_space_memory
, addr
, entry
,
3034 error_report_once("%s: read failed: ind=0x%x addr=0x%" PRIx64
,
3035 __func__
, index
, addr
);
3036 return -VTD_FR_IR_ROOT_INVAL
;
3039 trace_vtd_ir_irte_get(index
, le64_to_cpu(entry
->data
[1]),
3040 le64_to_cpu(entry
->data
[0]));
3042 if (!entry
->irte
.present
) {
3043 error_report_once("%s: detected non-present IRTE "
3044 "(index=%u, high=0x%" PRIx64
", low=0x%" PRIx64
")",
3045 __func__
, index
, le64_to_cpu(entry
->data
[1]),
3046 le64_to_cpu(entry
->data
[0]));
3047 return -VTD_FR_IR_ENTRY_P
;
3050 if (entry
->irte
.__reserved_0
|| entry
->irte
.__reserved_1
||
3051 entry
->irte
.__reserved_2
) {
3052 error_report_once("%s: detected non-zero reserved IRTE "
3053 "(index=%u, high=0x%" PRIx64
", low=0x%" PRIx64
")",
3054 __func__
, index
, le64_to_cpu(entry
->data
[1]),
3055 le64_to_cpu(entry
->data
[0]));
3056 return -VTD_FR_IR_IRTE_RSVD
;
3059 if (sid
!= X86_IOMMU_SID_INVALID
) {
3060 /* Validate IRTE SID */
3061 source_id
= le32_to_cpu(entry
->irte
.source_id
);
3062 switch (entry
->irte
.sid_vtype
) {
3067 mask
= vtd_svt_mask
[entry
->irte
.sid_q
];
3068 if ((source_id
& mask
) != (sid
& mask
)) {
3069 error_report_once("%s: invalid IRTE SID "
3070 "(index=%u, sid=%u, source_id=%u)",
3071 __func__
, index
, sid
, source_id
);
3072 return -VTD_FR_IR_SID_ERR
;
3077 bus_max
= source_id
>> 8;
3078 bus_min
= source_id
& 0xff;
3080 if (bus
> bus_max
|| bus
< bus_min
) {
3081 error_report_once("%s: invalid SVT_BUS "
3082 "(index=%u, bus=%u, min=%u, max=%u)",
3083 __func__
, index
, bus
, bus_min
, bus_max
);
3084 return -VTD_FR_IR_SID_ERR
;
3089 error_report_once("%s: detected invalid IRTE SVT "
3090 "(index=%u, type=%d)", __func__
,
3091 index
, entry
->irte
.sid_vtype
);
3092 /* Take this as verification failure. */
3093 return -VTD_FR_IR_SID_ERR
;
3101 /* Fetch IRQ information of specific IR index */
3102 static int vtd_remap_irq_get(IntelIOMMUState
*iommu
, uint16_t index
,
3103 X86IOMMUIrq
*irq
, uint16_t sid
)
3105 VTD_IR_TableEntry irte
= {};
3108 ret
= vtd_irte_get(iommu
, index
, &irte
, sid
);
3113 irq
->trigger_mode
= irte
.irte
.trigger_mode
;
3114 irq
->vector
= irte
.irte
.vector
;
3115 irq
->delivery_mode
= irte
.irte
.delivery_mode
;
3116 irq
->dest
= le32_to_cpu(irte
.irte
.dest_id
);
3117 if (!iommu
->intr_eime
) {
3118 #define VTD_IR_APIC_DEST_MASK (0xff00ULL)
3119 #define VTD_IR_APIC_DEST_SHIFT (8)
3120 irq
->dest
= (irq
->dest
& VTD_IR_APIC_DEST_MASK
) >>
3121 VTD_IR_APIC_DEST_SHIFT
;
3123 irq
->dest_mode
= irte
.irte
.dest_mode
;
3124 irq
->redir_hint
= irte
.irte
.redir_hint
;
3126 trace_vtd_ir_remap(index
, irq
->trigger_mode
, irq
->vector
,
3127 irq
->delivery_mode
, irq
->dest
, irq
->dest_mode
);
3132 /* Interrupt remapping for MSI/MSI-X entry */
3133 static int vtd_interrupt_remap_msi(IntelIOMMUState
*iommu
,
3135 MSIMessage
*translated
,
3139 VTD_IR_MSIAddress addr
;
3141 X86IOMMUIrq irq
= {};
3143 assert(origin
&& translated
);
3145 trace_vtd_ir_remap_msi_req(origin
->address
, origin
->data
);
3147 if (!iommu
|| !iommu
->intr_enabled
) {
3148 memcpy(translated
, origin
, sizeof(*origin
));
3152 if (origin
->address
& VTD_MSI_ADDR_HI_MASK
) {
3153 error_report_once("%s: MSI address high 32 bits non-zero detected: "
3154 "address=0x%" PRIx64
, __func__
, origin
->address
);
3155 return -VTD_FR_IR_REQ_RSVD
;
3158 addr
.data
= origin
->address
& VTD_MSI_ADDR_LO_MASK
;
3159 if (addr
.addr
.__head
!= 0xfee) {
3160 error_report_once("%s: MSI address low 32 bit invalid: 0x%" PRIx32
,
3161 __func__
, addr
.data
);
3162 return -VTD_FR_IR_REQ_RSVD
;
3165 /* This is compatible mode. */
3166 if (addr
.addr
.int_mode
!= VTD_IR_INT_FORMAT_REMAP
) {
3167 memcpy(translated
, origin
, sizeof(*origin
));
3171 index
= addr
.addr
.index_h
<< 15 | le16_to_cpu(addr
.addr
.index_l
);
3173 #define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
3174 #define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
3176 if (addr
.addr
.sub_valid
) {
3177 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
3178 index
+= origin
->data
& VTD_IR_MSI_DATA_SUBHANDLE
;
3181 ret
= vtd_remap_irq_get(iommu
, index
, &irq
, sid
);
3186 if (addr
.addr
.sub_valid
) {
3187 trace_vtd_ir_remap_type("MSI");
3188 if (origin
->data
& VTD_IR_MSI_DATA_RESERVED
) {
3189 error_report_once("%s: invalid IR MSI "
3190 "(sid=%u, address=0x%" PRIx64
3191 ", data=0x%" PRIx32
")",
3192 __func__
, sid
, origin
->address
, origin
->data
);
3193 return -VTD_FR_IR_REQ_RSVD
;
3196 uint8_t vector
= origin
->data
& 0xff;
3197 uint8_t trigger_mode
= (origin
->data
>> MSI_DATA_TRIGGER_SHIFT
) & 0x1;
3199 trace_vtd_ir_remap_type("IOAPIC");
3200 /* IOAPIC entry vector should be aligned with IRTE vector
3201 * (see vt-d spec 5.1.5.1). */
3202 if (vector
!= irq
.vector
) {
3203 trace_vtd_warn_ir_vector(sid
, index
, vector
, irq
.vector
);
3206 /* The Trigger Mode field must match the Trigger Mode in the IRTE.
3207 * (see vt-d spec 5.1.5.1). */
3208 if (trigger_mode
!= irq
.trigger_mode
) {
3209 trace_vtd_warn_ir_trigger(sid
, index
, trigger_mode
,
3215 * We'd better keep the last two bits, assuming that guest OS
3216 * might modify it. Keep it does not hurt after all.
3218 irq
.msi_addr_last_bits
= addr
.addr
.__not_care
;
3220 /* Translate X86IOMMUIrq to MSI message */
3221 x86_iommu_irq_to_msi_message(&irq
, translated
);
3224 trace_vtd_ir_remap_msi(origin
->address
, origin
->data
,
3225 translated
->address
, translated
->data
);
3229 static int vtd_int_remap(X86IOMMUState
*iommu
, MSIMessage
*src
,
3230 MSIMessage
*dst
, uint16_t sid
)
3232 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu
),
3236 static MemTxResult
vtd_mem_ir_read(void *opaque
, hwaddr addr
,
3237 uint64_t *data
, unsigned size
,
3243 static MemTxResult
vtd_mem_ir_write(void *opaque
, hwaddr addr
,
3244 uint64_t value
, unsigned size
,
3248 MSIMessage from
= {}, to
= {};
3249 uint16_t sid
= X86_IOMMU_SID_INVALID
;
3251 from
.address
= (uint64_t) addr
+ VTD_INTERRUPT_ADDR_FIRST
;
3252 from
.data
= (uint32_t) value
;
3254 if (!attrs
.unspecified
) {
3255 /* We have explicit Source ID */
3256 sid
= attrs
.requester_id
;
3259 ret
= vtd_interrupt_remap_msi(opaque
, &from
, &to
, sid
);
3261 /* TODO: report error */
3262 /* Drop this interrupt */
3266 apic_get_class()->send_msi(&to
);
3271 static const MemoryRegionOps vtd_mem_ir_ops
= {
3272 .read_with_attrs
= vtd_mem_ir_read
,
3273 .write_with_attrs
= vtd_mem_ir_write
,
3274 .endianness
= DEVICE_LITTLE_ENDIAN
,
3276 .min_access_size
= 4,
3277 .max_access_size
= 4,
3280 .min_access_size
= 4,
3281 .max_access_size
= 4,
3285 VTDAddressSpace
*vtd_find_add_as(IntelIOMMUState
*s
, PCIBus
*bus
, int devfn
)
3287 uintptr_t key
= (uintptr_t)bus
;
3288 VTDBus
*vtd_bus
= g_hash_table_lookup(s
->vtd_as_by_busptr
, &key
);
3289 VTDAddressSpace
*vtd_dev_as
;
3293 uintptr_t *new_key
= g_malloc(sizeof(*new_key
));
3294 *new_key
= (uintptr_t)bus
;
3295 /* No corresponding free() */
3296 vtd_bus
= g_malloc0(sizeof(VTDBus
) + sizeof(VTDAddressSpace
*) * \
3299 g_hash_table_insert(s
->vtd_as_by_busptr
, new_key
, vtd_bus
);
3302 vtd_dev_as
= vtd_bus
->dev_as
[devfn
];
3305 snprintf(name
, sizeof(name
), "vtd-%02x.%x", PCI_SLOT(devfn
),
3307 vtd_bus
->dev_as
[devfn
] = vtd_dev_as
= g_malloc0(sizeof(VTDAddressSpace
));
3309 vtd_dev_as
->bus
= bus
;
3310 vtd_dev_as
->devfn
= (uint8_t)devfn
;
3311 vtd_dev_as
->iommu_state
= s
;
3312 vtd_dev_as
->context_cache_entry
.context_cache_gen
= 0;
3313 vtd_dev_as
->iova_tree
= iova_tree_new();
3315 memory_region_init(&vtd_dev_as
->root
, OBJECT(s
), name
, UINT64_MAX
);
3316 address_space_init(&vtd_dev_as
->as
, &vtd_dev_as
->root
, "vtd-root");
3319 * Build the DMAR-disabled container with aliases to the
3320 * shared MRs. Note that aliasing to a shared memory region
3321 * could help the memory API to detect same FlatViews so we
3322 * can have devices to share the same FlatView when DMAR is
3323 * disabled (either by not providing "intel_iommu=on" or with
3324 * "iommu=pt"). It will greatly reduce the total number of
3325 * FlatViews of the system hence VM runs faster.
3327 memory_region_init_alias(&vtd_dev_as
->nodmar
, OBJECT(s
),
3328 "vtd-nodmar", &s
->mr_nodmar
, 0,
3329 memory_region_size(&s
->mr_nodmar
));
3332 * Build the per-device DMAR-enabled container.
3334 * TODO: currently we have per-device IOMMU memory region only
3335 * because we have per-device IOMMU notifiers for devices. If
3336 * one day we can abstract the IOMMU notifiers out of the
3337 * memory regions then we can also share the same memory
3338 * region here just like what we've done above with the nodmar
3341 strcat(name
, "-dmar");
3342 memory_region_init_iommu(&vtd_dev_as
->iommu
, sizeof(vtd_dev_as
->iommu
),
3343 TYPE_INTEL_IOMMU_MEMORY_REGION
, OBJECT(s
),
3345 memory_region_init_alias(&vtd_dev_as
->iommu_ir
, OBJECT(s
), "vtd-ir",
3346 &s
->mr_ir
, 0, memory_region_size(&s
->mr_ir
));
3347 memory_region_add_subregion_overlap(MEMORY_REGION(&vtd_dev_as
->iommu
),
3348 VTD_INTERRUPT_ADDR_FIRST
,
3349 &vtd_dev_as
->iommu_ir
, 1);
3352 * Hook both the containers under the root container, we
3353 * switch between DMAR & noDMAR by enable/disable
3354 * corresponding sub-containers
3356 memory_region_add_subregion_overlap(&vtd_dev_as
->root
, 0,
3357 MEMORY_REGION(&vtd_dev_as
->iommu
),
3359 memory_region_add_subregion_overlap(&vtd_dev_as
->root
, 0,
3360 &vtd_dev_as
->nodmar
, 0);
3362 vtd_switch_address_space(vtd_dev_as
);
3367 /* Unmap the whole range in the notifier's scope. */
3368 static void vtd_address_space_unmap(VTDAddressSpace
*as
, IOMMUNotifier
*n
)
3370 IOMMUTLBEntry entry
;
3372 hwaddr start
= n
->start
;
3373 hwaddr end
= n
->end
;
3374 IntelIOMMUState
*s
= as
->iommu_state
;
3378 * Note: all the codes in this function has a assumption that IOVA
3379 * bits are no more than VTD_MGAW bits (which is restricted by
3380 * VT-d spec), otherwise we need to consider overflow of 64 bits.
3383 if (end
> VTD_ADDRESS_SIZE(s
->aw_bits
)) {
3385 * Don't need to unmap regions that is bigger than the whole
3386 * VT-d supported address space size
3388 end
= VTD_ADDRESS_SIZE(s
->aw_bits
);
3391 assert(start
<= end
);
3394 if (ctpop64(size
) != 1) {
3396 * This size cannot format a correct mask. Let's enlarge it to
3397 * suite the minimum available mask.
3399 int n
= 64 - clz64(size
);
3400 if (n
> s
->aw_bits
) {
3401 /* should not happen, but in case it happens, limit it */
3407 entry
.target_as
= &address_space_memory
;
3408 /* Adjust iova for the size */
3409 entry
.iova
= n
->start
& ~(size
- 1);
3410 /* This field is meaningless for unmap */
3411 entry
.translated_addr
= 0;
3412 entry
.perm
= IOMMU_NONE
;
3413 entry
.addr_mask
= size
- 1;
3415 trace_vtd_as_unmap_whole(pci_bus_num(as
->bus
),
3416 VTD_PCI_SLOT(as
->devfn
),
3417 VTD_PCI_FUNC(as
->devfn
),
3420 map
.iova
= entry
.iova
;
3421 map
.size
= entry
.addr_mask
;
3422 iova_tree_remove(as
->iova_tree
, &map
);
3424 memory_region_notify_one(n
, &entry
);
3427 static void vtd_address_space_unmap_all(IntelIOMMUState
*s
)
3429 VTDAddressSpace
*vtd_as
;
3432 QLIST_FOREACH(vtd_as
, &s
->vtd_as_with_notifiers
, next
) {
3433 IOMMU_NOTIFIER_FOREACH(n
, &vtd_as
->iommu
) {
3434 vtd_address_space_unmap(vtd_as
, n
);
3439 static void vtd_address_space_refresh_all(IntelIOMMUState
*s
)
3441 vtd_address_space_unmap_all(s
);
3442 vtd_switch_address_space_all(s
);
3445 static int vtd_replay_hook(IOMMUTLBEntry
*entry
, void *private)
3447 memory_region_notify_one((IOMMUNotifier
*)private, entry
);
3451 static void vtd_iommu_replay(IOMMUMemoryRegion
*iommu_mr
, IOMMUNotifier
*n
)
3453 VTDAddressSpace
*vtd_as
= container_of(iommu_mr
, VTDAddressSpace
, iommu
);
3454 IntelIOMMUState
*s
= vtd_as
->iommu_state
;
3455 uint8_t bus_n
= pci_bus_num(vtd_as
->bus
);
3459 * The replay can be triggered by either a invalidation or a newly
3460 * created entry. No matter what, we release existing mappings
3461 * (it means flushing caches for UNMAP-only registers).
3463 vtd_address_space_unmap(vtd_as
, n
);
3465 if (vtd_dev_to_context_entry(s
, bus_n
, vtd_as
->devfn
, &ce
) == 0) {
3466 trace_vtd_replay_ce_valid(s
->root_scalable
? "scalable mode" :
3468 bus_n
, PCI_SLOT(vtd_as
->devfn
),
3469 PCI_FUNC(vtd_as
->devfn
),
3470 vtd_get_domain_id(s
, &ce
),
3472 if (vtd_as_has_map_notifier(vtd_as
)) {
3473 /* This is required only for MAP typed notifiers */
3474 vtd_page_walk_info info
= {
3475 .hook_fn
= vtd_replay_hook
,
3476 .private = (void *)n
,
3477 .notify_unmap
= false,
3480 .domain_id
= vtd_get_domain_id(s
, &ce
),
3483 vtd_page_walk(s
, &ce
, 0, ~0ULL, &info
);
3486 trace_vtd_replay_ce_invalid(bus_n
, PCI_SLOT(vtd_as
->devfn
),
3487 PCI_FUNC(vtd_as
->devfn
));
3493 /* Do the initialization. It will also be called when reset, so pay
3494 * attention when adding new initialization stuff.
3496 static void vtd_init(IntelIOMMUState
*s
)
3498 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
3500 memset(s
->csr
, 0, DMAR_REG_SIZE
);
3501 memset(s
->wmask
, 0, DMAR_REG_SIZE
);
3502 memset(s
->w1cmask
, 0, DMAR_REG_SIZE
);
3503 memset(s
->womask
, 0, DMAR_REG_SIZE
);
3506 s
->root_extended
= false;
3507 s
->root_scalable
= false;
3508 s
->dmar_enabled
= false;
3509 s
->intr_enabled
= false;
3514 s
->qi_enabled
= false;
3515 s
->iq_last_desc_type
= VTD_INV_DESC_NONE
;
3517 s
->next_frcd_reg
= 0;
3518 s
->cap
= VTD_CAP_FRO
| VTD_CAP_NFR
| VTD_CAP_ND
|
3519 VTD_CAP_MAMV
| VTD_CAP_PSI
| VTD_CAP_SLLPS
|
3520 VTD_CAP_SAGAW_39bit
| VTD_CAP_MGAW(s
->aw_bits
);
3522 s
->cap
|= VTD_CAP_DRAIN
;
3524 if (s
->aw_bits
== VTD_HOST_AW_48BIT
) {
3525 s
->cap
|= VTD_CAP_SAGAW_48bit
;
3527 s
->ecap
= VTD_ECAP_QI
| VTD_ECAP_IRO
;
3530 * Rsvd field masks for spte
3532 vtd_paging_entry_rsvd_field
[0] = ~0ULL;
3533 vtd_paging_entry_rsvd_field
[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s
->aw_bits
);
3534 vtd_paging_entry_rsvd_field
[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s
->aw_bits
);
3535 vtd_paging_entry_rsvd_field
[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s
->aw_bits
);
3536 vtd_paging_entry_rsvd_field
[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s
->aw_bits
);
3537 vtd_paging_entry_rsvd_field
[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s
->aw_bits
);
3538 vtd_paging_entry_rsvd_field
[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s
->aw_bits
);
3539 vtd_paging_entry_rsvd_field
[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s
->aw_bits
);
3540 vtd_paging_entry_rsvd_field
[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s
->aw_bits
);
3542 if (x86_iommu_ir_supported(x86_iommu
)) {
3543 s
->ecap
|= VTD_ECAP_IR
| VTD_ECAP_MHMV
;
3544 if (s
->intr_eim
== ON_OFF_AUTO_ON
) {
3545 s
->ecap
|= VTD_ECAP_EIM
;
3547 assert(s
->intr_eim
!= ON_OFF_AUTO_AUTO
);
3550 if (x86_iommu
->dt_supported
) {
3551 s
->ecap
|= VTD_ECAP_DT
;
3554 if (x86_iommu
->pt_supported
) {
3555 s
->ecap
|= VTD_ECAP_PT
;
3558 if (s
->caching_mode
) {
3559 s
->cap
|= VTD_CAP_CM
;
3562 /* TODO: read cap/ecap from host to decide which cap to be exposed. */
3563 if (s
->scalable_mode
) {
3564 s
->ecap
|= VTD_ECAP_SMTS
| VTD_ECAP_SRS
| VTD_ECAP_SLTS
;
3567 vtd_reset_caches(s
);
3569 /* Define registers with default values and bit semantics */
3570 vtd_define_long(s
, DMAR_VER_REG
, 0x10UL
, 0, 0);
3571 vtd_define_quad(s
, DMAR_CAP_REG
, s
->cap
, 0, 0);
3572 vtd_define_quad(s
, DMAR_ECAP_REG
, s
->ecap
, 0, 0);
3573 vtd_define_long(s
, DMAR_GCMD_REG
, 0, 0xff800000UL
, 0);
3574 vtd_define_long_wo(s
, DMAR_GCMD_REG
, 0xff800000UL
);
3575 vtd_define_long(s
, DMAR_GSTS_REG
, 0, 0, 0);
3576 vtd_define_quad(s
, DMAR_RTADDR_REG
, 0, 0xfffffffffffffc00ULL
, 0);
3577 vtd_define_quad(s
, DMAR_CCMD_REG
, 0, 0xe0000003ffffffffULL
, 0);
3578 vtd_define_quad_wo(s
, DMAR_CCMD_REG
, 0x3ffff0000ULL
);
3580 /* Advanced Fault Logging not supported */
3581 vtd_define_long(s
, DMAR_FSTS_REG
, 0, 0, 0x11UL
);
3582 vtd_define_long(s
, DMAR_FECTL_REG
, 0x80000000UL
, 0x80000000UL
, 0);
3583 vtd_define_long(s
, DMAR_FEDATA_REG
, 0, 0x0000ffffUL
, 0);
3584 vtd_define_long(s
, DMAR_FEADDR_REG
, 0, 0xfffffffcUL
, 0);
3586 /* Treated as RsvdZ when EIM in ECAP_REG is not supported
3587 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0);
3589 vtd_define_long(s
, DMAR_FEUADDR_REG
, 0, 0, 0);
3591 /* Treated as RO for implementations that PLMR and PHMR fields reported
3592 * as Clear in the CAP_REG.
3593 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0);
3595 vtd_define_long(s
, DMAR_PMEN_REG
, 0, 0, 0);
3597 vtd_define_quad(s
, DMAR_IQH_REG
, 0, 0, 0);
3598 vtd_define_quad(s
, DMAR_IQT_REG
, 0, 0x7fff0ULL
, 0);
3599 vtd_define_quad(s
, DMAR_IQA_REG
, 0, 0xfffffffffffff807ULL
, 0);
3600 vtd_define_long(s
, DMAR_ICS_REG
, 0, 0, 0x1UL
);
3601 vtd_define_long(s
, DMAR_IECTL_REG
, 0x80000000UL
, 0x80000000UL
, 0);
3602 vtd_define_long(s
, DMAR_IEDATA_REG
, 0, 0xffffffffUL
, 0);
3603 vtd_define_long(s
, DMAR_IEADDR_REG
, 0, 0xfffffffcUL
, 0);
3604 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */
3605 vtd_define_long(s
, DMAR_IEUADDR_REG
, 0, 0, 0);
3607 /* IOTLB registers */
3608 vtd_define_quad(s
, DMAR_IOTLB_REG
, 0, 0Xb003ffff00000000ULL
, 0);
3609 vtd_define_quad(s
, DMAR_IVA_REG
, 0, 0xfffffffffffff07fULL
, 0);
3610 vtd_define_quad_wo(s
, DMAR_IVA_REG
, 0xfffffffffffff07fULL
);
3612 /* Fault Recording Registers, 128-bit */
3613 vtd_define_quad(s
, DMAR_FRCD_REG_0_0
, 0, 0, 0);
3614 vtd_define_quad(s
, DMAR_FRCD_REG_0_2
, 0, 0, 0x8000000000000000ULL
);
3617 * Interrupt remapping registers.
3619 vtd_define_quad(s
, DMAR_IRTA_REG
, 0, 0xfffffffffffff80fULL
, 0);
3622 /* Should not reset address_spaces when reset because devices will still use
3623 * the address space they got at first (won't ask the bus again).
3625 static void vtd_reset(DeviceState
*dev
)
3627 IntelIOMMUState
*s
= INTEL_IOMMU_DEVICE(dev
);
3630 vtd_address_space_refresh_all(s
);
3633 static AddressSpace
*vtd_host_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
3635 IntelIOMMUState
*s
= opaque
;
3636 VTDAddressSpace
*vtd_as
;
3638 assert(0 <= devfn
&& devfn
< PCI_DEVFN_MAX
);
3640 vtd_as
= vtd_find_add_as(s
, bus
, devfn
);
3644 static bool vtd_decide_config(IntelIOMMUState
*s
, Error
**errp
)
3646 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(s
);
3648 if (s
->intr_eim
== ON_OFF_AUTO_ON
&& !x86_iommu_ir_supported(x86_iommu
)) {
3649 error_setg(errp
, "eim=on cannot be selected without intremap=on");
3653 if (s
->intr_eim
== ON_OFF_AUTO_AUTO
) {
3654 s
->intr_eim
= (kvm_irqchip_in_kernel() || s
->buggy_eim
)
3655 && x86_iommu_ir_supported(x86_iommu
) ?
3656 ON_OFF_AUTO_ON
: ON_OFF_AUTO_OFF
;
3658 if (s
->intr_eim
== ON_OFF_AUTO_ON
&& !s
->buggy_eim
) {
3659 if (!kvm_irqchip_in_kernel()) {
3660 error_setg(errp
, "eim=on requires accel=kvm,kernel-irqchip=split");
3663 if (!kvm_enable_x2apic()) {
3664 error_setg(errp
, "eim=on requires support on the KVM side"
3665 "(X2APIC_API, first shipped in v4.7)");
3670 /* Currently only address widths supported are 39 and 48 bits */
3671 if ((s
->aw_bits
!= VTD_HOST_AW_39BIT
) &&
3672 (s
->aw_bits
!= VTD_HOST_AW_48BIT
)) {
3673 error_setg(errp
, "Supported values for x-aw-bits are: %d, %d",
3674 VTD_HOST_AW_39BIT
, VTD_HOST_AW_48BIT
);
3678 if (s
->scalable_mode
&& !s
->dma_drain
) {
3679 error_setg(errp
, "Need to set dma_drain for scalable mode");
3686 static void vtd_realize(DeviceState
*dev
, Error
**errp
)
3688 MachineState
*ms
= MACHINE(qdev_get_machine());
3689 PCMachineState
*pcms
= PC_MACHINE(ms
);
3690 PCIBus
*bus
= pcms
->bus
;
3691 IntelIOMMUState
*s
= INTEL_IOMMU_DEVICE(dev
);
3692 X86IOMMUState
*x86_iommu
= X86_IOMMU_DEVICE(dev
);
3694 x86_iommu
->type
= TYPE_INTEL
;
3696 if (!vtd_decide_config(s
, errp
)) {
3700 QLIST_INIT(&s
->vtd_as_with_notifiers
);
3701 qemu_mutex_init(&s
->iommu_lock
);
3702 memset(s
->vtd_as_by_bus_num
, 0, sizeof(s
->vtd_as_by_bus_num
));
3703 memory_region_init_io(&s
->csrmem
, OBJECT(s
), &vtd_mem_ops
, s
,
3704 "intel_iommu", DMAR_REG_SIZE
);
3706 /* Create the shared memory regions by all devices */
3707 memory_region_init(&s
->mr_nodmar
, OBJECT(s
), "vtd-nodmar",
3709 memory_region_init_io(&s
->mr_ir
, OBJECT(s
), &vtd_mem_ir_ops
,
3710 s
, "vtd-ir", VTD_INTERRUPT_ADDR_SIZE
);
3711 memory_region_init_alias(&s
->mr_sys_alias
, OBJECT(s
),
3712 "vtd-sys-alias", get_system_memory(), 0,
3713 memory_region_size(get_system_memory()));
3714 memory_region_add_subregion_overlap(&s
->mr_nodmar
, 0,
3715 &s
->mr_sys_alias
, 0);
3716 memory_region_add_subregion_overlap(&s
->mr_nodmar
,
3717 VTD_INTERRUPT_ADDR_FIRST
,
3720 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->csrmem
);
3721 /* No corresponding destroy */
3722 s
->iotlb
= g_hash_table_new_full(vtd_uint64_hash
, vtd_uint64_equal
,
3724 s
->vtd_as_by_busptr
= g_hash_table_new_full(vtd_uint64_hash
, vtd_uint64_equal
,
3727 sysbus_mmio_map(SYS_BUS_DEVICE(s
), 0, Q35_HOST_BRIDGE_IOMMU_ADDR
);
3728 pci_setup_iommu(bus
, vtd_host_dma_iommu
, dev
);
3729 /* Pseudo address space under root PCI bus. */
3730 pcms
->ioapic_as
= vtd_host_dma_iommu(bus
, s
, Q35_PSEUDO_DEVFN_IOAPIC
);
3733 static void vtd_class_init(ObjectClass
*klass
, void *data
)
3735 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3736 X86IOMMUClass
*x86_class
= X86_IOMMU_CLASS(klass
);
3738 dc
->reset
= vtd_reset
;
3739 dc
->vmsd
= &vtd_vmstate
;
3740 dc
->props
= vtd_properties
;
3741 dc
->hotpluggable
= false;
3742 x86_class
->realize
= vtd_realize
;
3743 x86_class
->int_remap
= vtd_int_remap
;
3744 /* Supported by the pc-q35-* machine types */
3745 dc
->user_creatable
= true;
3748 static const TypeInfo vtd_info
= {
3749 .name
= TYPE_INTEL_IOMMU_DEVICE
,
3750 .parent
= TYPE_X86_IOMMU_DEVICE
,
3751 .instance_size
= sizeof(IntelIOMMUState
),
3752 .class_init
= vtd_class_init
,
3755 static void vtd_iommu_memory_region_class_init(ObjectClass
*klass
,
3758 IOMMUMemoryRegionClass
*imrc
= IOMMU_MEMORY_REGION_CLASS(klass
);
3760 imrc
->translate
= vtd_iommu_translate
;
3761 imrc
->notify_flag_changed
= vtd_iommu_notify_flag_changed
;
3762 imrc
->replay
= vtd_iommu_replay
;
3765 static const TypeInfo vtd_iommu_memory_region_info
= {
3766 .parent
= TYPE_IOMMU_MEMORY_REGION
,
3767 .name
= TYPE_INTEL_IOMMU_MEMORY_REGION
,
3768 .class_init
= vtd_iommu_memory_region_class_init
,
3771 static void vtd_register_types(void)
3773 type_register_static(&vtd_info
);
3774 type_register_static(&vtd_iommu_memory_region_info
);
3777 type_init(vtd_register_types
)