2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "hw/sysbus.h"
34 #include "hw/arm/arm.h"
35 #include "hw/arm/primecell.h"
36 #include "hw/arm/virt.h"
37 #include "hw/devices.h"
39 #include "sysemu/block-backend.h"
40 #include "sysemu/device_tree.h"
41 #include "sysemu/numa.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/kvm.h"
44 #include "hw/boards.h"
45 #include "hw/compat.h"
46 #include "hw/loader.h"
47 #include "exec/address-spaces.h"
48 #include "qemu/bitops.h"
49 #include "qemu/error-report.h"
50 #include "hw/pci-host/gpex.h"
51 #include "hw/arm/virt-acpi-build.h"
52 #include "hw/arm/sysbus-fdt.h"
53 #include "hw/platform-bus.h"
54 #include "hw/arm/fdt.h"
55 #include "hw/intc/arm_gic.h"
56 #include "hw/intc/arm_gicv3_common.h"
58 #include "hw/smbios/smbios.h"
59 #include "qapi/visitor.h"
60 #include "standard-headers/linux/input.h"
62 /* Number of external interrupt lines to configure the GIC with */
65 #define PLATFORM_BUS_NUM_IRQS 64
67 static ARMPlatformBusSystemParams platform_bus_params
;
69 typedef struct VirtBoardInfo
{
70 struct arm_boot_info bootinfo
;
71 const char *cpu_model
;
72 const MemMapEntry
*memmap
;
77 uint32_t clock_phandle
;
85 VirtBoardInfo
*daughterboard
;
86 bool disallow_affinity_adjustment
;
98 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
99 #define VIRT_MACHINE(obj) \
100 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
101 #define VIRT_MACHINE_GET_CLASS(obj) \
102 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
103 #define VIRT_MACHINE_CLASS(klass) \
104 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
107 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
108 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
111 MachineClass *mc = MACHINE_CLASS(oc); \
112 virt_machine_##major##_##minor##_options(mc); \
113 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
115 mc->alias = "virt"; \
118 static const TypeInfo machvirt_##major##_##minor##_info = { \
119 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
120 .parent = TYPE_VIRT_MACHINE, \
121 .instance_init = virt_##major##_##minor##_instance_init, \
122 .class_init = virt_##major##_##minor##_class_init, \
124 static void machvirt_machine_##major##_##minor##_init(void) \
126 type_register_static(&machvirt_##major##_##minor##_info); \
128 type_init(machvirt_machine_##major##_##minor##_init);
130 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
131 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
132 #define DEFINE_VIRT_MACHINE(major, minor) \
133 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
136 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
137 * RAM can go up to the 256GB mark, leaving 256GB of the physical
138 * address space unallocated and free for future use between 256G and 512G.
139 * If we need to provide more RAM to VMs in the future then we need to:
140 * * allocate a second bank of RAM starting at 2TB and working up
141 * * fix the DT and ACPI table generation code in QEMU to correctly
142 * report two split lumps of RAM to the guest
143 * * fix KVM in the host kernel to allow guests with >40 bit address spaces
144 * (We don't want to fill all the way up to 512GB with RAM because
145 * we might want it for non-RAM purposes later. Conversely it seems
146 * reasonable to assume that anybody configuring a VM with a quarter
147 * of a terabyte of RAM will be doing it on a host with more than a
148 * terabyte of physical address space.)
150 #define RAMLIMIT_GB 255
151 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
153 /* Addresses and sizes of our components.
154 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
155 * 128MB..256MB is used for miscellaneous device I/O.
156 * 256MB..1GB is reserved for possible future PCI support (ie where the
157 * PCI memory window will go if we add a PCI host controller).
158 * 1GB and up is RAM (which may happily spill over into the
159 * high memory region beyond 4GB).
160 * This represents a compromise between how much RAM can be given to
161 * a 32 bit VM and leaving space for expansion and in particular for PCI.
162 * Note that devices should generally be placed at multiples of 0x10000,
163 * to accommodate guests using 64K pages.
165 static const MemMapEntry a15memmap
[] = {
166 /* Space up to 0x8000000 is reserved for a boot ROM */
167 [VIRT_FLASH
] = { 0, 0x08000000 },
168 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
169 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
170 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
171 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
172 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
173 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
174 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
175 /* This redistributor space allows up to 2*64kB*123 CPUs */
176 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
177 [VIRT_UART
] = { 0x09000000, 0x00001000 },
178 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
179 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
180 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
181 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
182 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
183 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
184 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
185 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
186 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
187 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
188 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
189 [VIRT_MEM
] = { 0x40000000, RAMLIMIT_BYTES
},
190 /* Second PCIe window, 512GB wide at the 512GB boundary */
191 [VIRT_PCIE_MMIO_HIGH
] = { 0x8000000000ULL
, 0x8000000000ULL
},
194 static const int a15irqmap
[] = {
197 [VIRT_PCIE
] = 3, /* ... to 6 */
199 [VIRT_SECURE_UART
] = 8,
200 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
201 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
202 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
205 static VirtBoardInfo machines
[] = {
207 .cpu_model
= "cortex-a15",
212 .cpu_model
= "cortex-a53",
217 .cpu_model
= "cortex-a57",
228 static VirtBoardInfo
*find_machine_info(const char *cpu
)
232 for (i
= 0; i
< ARRAY_SIZE(machines
); i
++) {
233 if (strcmp(cpu
, machines
[i
].cpu_model
) == 0) {
240 static void create_fdt(VirtBoardInfo
*vbi
)
242 void *fdt
= create_device_tree(&vbi
->fdt_size
);
245 error_report("create_device_tree() failed");
252 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
253 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
254 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
257 * /chosen and /memory nodes must exist for load_dtb
258 * to fill in necessary properties later
260 qemu_fdt_add_subnode(fdt
, "/chosen");
261 qemu_fdt_add_subnode(fdt
, "/memory");
262 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
264 /* Clock node, for the benefit of the UART. The kernel device tree
265 * binding documentation claims the PL011 node clock properties are
266 * optional but in practice if you omit them the kernel refuses to
267 * probe for the device.
269 vbi
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
270 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
271 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
272 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
273 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
274 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
276 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vbi
->clock_phandle
);
280 static void fdt_add_psci_node(const VirtBoardInfo
*vbi
)
282 uint32_t cpu_suspend_fn
;
286 void *fdt
= vbi
->fdt
;
287 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
289 if (!vbi
->using_psci
) {
293 qemu_fdt_add_subnode(fdt
, "/psci");
294 if (armcpu
->psci_version
== 2) {
295 const char comp
[] = "arm,psci-0.2\0arm,psci";
296 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
298 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
299 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
300 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
301 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
302 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
304 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
305 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
306 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
309 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
311 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
312 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
313 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
314 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
317 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
318 * to the instruction that should be used to invoke PSCI functions.
319 * However, the device tree binding uses 'method' instead, so that is
320 * what we should use here.
322 qemu_fdt_setprop_string(fdt
, "/psci", "method", "hvc");
324 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
325 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
326 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
327 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
330 static void fdt_add_timer_nodes(const VirtBoardInfo
*vbi
, int gictype
)
332 /* Note that on A15 h/w these interrupts are level-triggered,
333 * but for the GIC implementation provided by both QEMU and KVM
334 * they are edge-triggered.
337 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
340 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
341 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
342 (1 << vbi
->smp_cpus
) - 1);
345 qemu_fdt_add_subnode(vbi
->fdt
, "/timer");
347 armcpu
= ARM_CPU(qemu_get_cpu(0));
348 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
349 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
350 qemu_fdt_setprop(vbi
->fdt
, "/timer", "compatible",
351 compat
, sizeof(compat
));
353 qemu_fdt_setprop_string(vbi
->fdt
, "/timer", "compatible",
356 qemu_fdt_setprop(vbi
->fdt
, "/timer", "always-on", NULL
, 0);
357 qemu_fdt_setprop_cells(vbi
->fdt
, "/timer", "interrupts",
358 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
359 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
360 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
361 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
364 static void fdt_add_cpu_nodes(const VirtBoardInfo
*vbi
)
371 * From Documentation/devicetree/bindings/arm/cpus.txt
372 * On ARM v8 64-bit systems value should be set to 2,
373 * that corresponds to the MPIDR_EL1 register size.
374 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
375 * in the system, #address-cells can be set to 1, since
376 * MPIDR_EL1[63:32] bits are not used for CPUs
379 * Here we actually don't know whether our system is 32- or 64-bit one.
380 * The simplest way to go is to examine affinity IDs of all our CPUs. If
381 * at least one of them has Aff3 populated, we set #address-cells to 2.
383 for (cpu
= 0; cpu
< vbi
->smp_cpus
; cpu
++) {
384 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
386 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
392 qemu_fdt_add_subnode(vbi
->fdt
, "/cpus");
393 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#address-cells", addr_cells
);
394 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#size-cells", 0x0);
396 for (cpu
= vbi
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
397 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
398 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
400 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
401 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "cpu");
402 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible",
403 armcpu
->dtb_compatible
);
405 if (vbi
->using_psci
&& vbi
->smp_cpus
> 1) {
406 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
407 "enable-method", "psci");
410 if (addr_cells
== 2) {
411 qemu_fdt_setprop_u64(vbi
->fdt
, nodename
, "reg",
412 armcpu
->mp_affinity
);
414 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "reg",
415 armcpu
->mp_affinity
);
418 i
= numa_get_node_for_cpu(cpu
);
419 if (i
< nb_numa_nodes
) {
420 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "numa-node-id", i
);
427 static void fdt_add_its_gic_node(VirtBoardInfo
*vbi
)
429 vbi
->msi_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
430 qemu_fdt_add_subnode(vbi
->fdt
, "/intc/its");
431 qemu_fdt_setprop_string(vbi
->fdt
, "/intc/its", "compatible",
433 qemu_fdt_setprop(vbi
->fdt
, "/intc/its", "msi-controller", NULL
, 0);
434 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc/its", "reg",
435 2, vbi
->memmap
[VIRT_GIC_ITS
].base
,
436 2, vbi
->memmap
[VIRT_GIC_ITS
].size
);
437 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc/its", "phandle", vbi
->msi_phandle
);
440 static void fdt_add_v2m_gic_node(VirtBoardInfo
*vbi
)
442 vbi
->msi_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
443 qemu_fdt_add_subnode(vbi
->fdt
, "/intc/v2m");
444 qemu_fdt_setprop_string(vbi
->fdt
, "/intc/v2m", "compatible",
445 "arm,gic-v2m-frame");
446 qemu_fdt_setprop(vbi
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
447 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc/v2m", "reg",
448 2, vbi
->memmap
[VIRT_GIC_V2M
].base
,
449 2, vbi
->memmap
[VIRT_GIC_V2M
].size
);
450 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc/v2m", "phandle", vbi
->msi_phandle
);
453 static void fdt_add_gic_node(VirtBoardInfo
*vbi
, int type
)
455 vbi
->gic_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
456 qemu_fdt_setprop_cell(vbi
->fdt
, "/", "interrupt-parent", vbi
->gic_phandle
);
458 qemu_fdt_add_subnode(vbi
->fdt
, "/intc");
459 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#interrupt-cells", 3);
460 qemu_fdt_setprop(vbi
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
461 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#address-cells", 0x2);
462 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#size-cells", 0x2);
463 qemu_fdt_setprop(vbi
->fdt
, "/intc", "ranges", NULL
, 0);
465 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
467 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
468 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
469 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
470 2, vbi
->memmap
[VIRT_GIC_REDIST
].base
,
471 2, vbi
->memmap
[VIRT_GIC_REDIST
].size
);
473 /* 'cortex-a15-gic' means 'GIC v2' */
474 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
475 "arm,cortex-a15-gic");
476 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
477 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
478 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
479 2, vbi
->memmap
[VIRT_GIC_CPU
].base
,
480 2, vbi
->memmap
[VIRT_GIC_CPU
].size
);
483 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "phandle", vbi
->gic_phandle
);
486 static void fdt_add_pmu_nodes(const VirtBoardInfo
*vbi
, int gictype
)
490 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
493 armcpu
= ARM_CPU(cpu
);
494 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
) ||
495 !kvm_arm_pmu_create(cpu
, PPI(VIRTUAL_PMU_IRQ
))) {
501 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
502 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
503 (1 << vbi
->smp_cpus
) - 1);
506 armcpu
= ARM_CPU(qemu_get_cpu(0));
507 qemu_fdt_add_subnode(vbi
->fdt
, "/pmu");
508 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
509 const char compat
[] = "arm,armv8-pmuv3";
510 qemu_fdt_setprop(vbi
->fdt
, "/pmu", "compatible",
511 compat
, sizeof(compat
));
512 qemu_fdt_setprop_cells(vbi
->fdt
, "/pmu", "interrupts",
513 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
517 static void create_its(VirtBoardInfo
*vbi
, DeviceState
*gicdev
)
519 const char *itsclass
= its_class_name();
523 /* Do nothing if not supported */
527 dev
= qdev_create(NULL
, itsclass
);
529 object_property_set_link(OBJECT(dev
), OBJECT(gicdev
), "parent-gicv3",
531 qdev_init_nofail(dev
);
532 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vbi
->memmap
[VIRT_GIC_ITS
].base
);
534 fdt_add_its_gic_node(vbi
);
537 static void create_v2m(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
540 int irq
= vbi
->irqmap
[VIRT_GIC_V2M
];
543 dev
= qdev_create(NULL
, "arm-gicv2m");
544 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vbi
->memmap
[VIRT_GIC_V2M
].base
);
545 qdev_prop_set_uint32(dev
, "base-spi", irq
);
546 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
547 qdev_init_nofail(dev
);
549 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
550 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
553 fdt_add_v2m_gic_node(vbi
);
556 static void create_gic(VirtBoardInfo
*vbi
, qemu_irq
*pic
, int type
,
557 bool secure
, bool no_its
)
559 /* We create a standalone GIC */
561 SysBusDevice
*gicbusdev
;
565 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
567 gicdev
= qdev_create(NULL
, gictype
);
568 qdev_prop_set_uint32(gicdev
, "revision", type
);
569 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
570 /* Note that the num-irq property counts both internal and external
571 * interrupts; there are always 32 of the former (mandated by GIC spec).
573 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
574 if (!kvm_irqchip_in_kernel()) {
575 qdev_prop_set_bit(gicdev
, "has-security-extensions", secure
);
577 qdev_init_nofail(gicdev
);
578 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
579 sysbus_mmio_map(gicbusdev
, 0, vbi
->memmap
[VIRT_GIC_DIST
].base
);
581 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_REDIST
].base
);
583 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_CPU
].base
);
586 /* Wire the outputs from each CPU's generic timer to the
587 * appropriate GIC PPI inputs, and the GIC's IRQ output to
588 * the CPU's IRQ input.
590 for (i
= 0; i
< smp_cpus
; i
++) {
591 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
592 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
594 /* Mapping from the output timer irq lines from the CPU to the
595 * GIC PPI inputs we use for the virt board.
597 const int timer_irq
[] = {
598 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
599 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
600 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
601 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
604 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
605 qdev_connect_gpio_out(cpudev
, irq
,
606 qdev_get_gpio_in(gicdev
,
607 ppibase
+ timer_irq
[irq
]));
610 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
611 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
612 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
615 for (i
= 0; i
< NUM_IRQS
; i
++) {
616 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
619 fdt_add_gic_node(vbi
, type
);
621 if (type
== 3 && !no_its
) {
622 create_its(vbi
, gicdev
);
623 } else if (type
== 2) {
624 create_v2m(vbi
, pic
);
628 static void create_uart(const VirtBoardInfo
*vbi
, qemu_irq
*pic
, int uart
,
629 MemoryRegion
*mem
, CharDriverState
*chr
)
632 hwaddr base
= vbi
->memmap
[uart
].base
;
633 hwaddr size
= vbi
->memmap
[uart
].size
;
634 int irq
= vbi
->irqmap
[uart
];
635 const char compat
[] = "arm,pl011\0arm,primecell";
636 const char clocknames
[] = "uartclk\0apb_pclk";
637 DeviceState
*dev
= qdev_create(NULL
, "pl011");
638 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
640 qdev_prop_set_chr(dev
, "chardev", chr
);
641 qdev_init_nofail(dev
);
642 memory_region_add_subregion(mem
, base
,
643 sysbus_mmio_get_region(s
, 0));
644 sysbus_connect_irq(s
, 0, pic
[irq
]);
646 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
647 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
648 /* Note that we can't use setprop_string because of the embedded NUL */
649 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible",
650 compat
, sizeof(compat
));
651 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
653 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
654 GIC_FDT_IRQ_TYPE_SPI
, irq
,
655 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
656 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "clocks",
657 vbi
->clock_phandle
, vbi
->clock_phandle
);
658 qemu_fdt_setprop(vbi
->fdt
, nodename
, "clock-names",
659 clocknames
, sizeof(clocknames
));
661 if (uart
== VIRT_UART
) {
662 qemu_fdt_setprop_string(vbi
->fdt
, "/chosen", "stdout-path", nodename
);
664 /* Mark as not usable by the normal world */
665 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "status", "disabled");
666 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "secure-status", "okay");
672 static void create_rtc(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
675 hwaddr base
= vbi
->memmap
[VIRT_RTC
].base
;
676 hwaddr size
= vbi
->memmap
[VIRT_RTC
].size
;
677 int irq
= vbi
->irqmap
[VIRT_RTC
];
678 const char compat
[] = "arm,pl031\0arm,primecell";
680 sysbus_create_simple("pl031", base
, pic
[irq
]);
682 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
683 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
684 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
685 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
687 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
688 GIC_FDT_IRQ_TYPE_SPI
, irq
,
689 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
690 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
691 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
695 static DeviceState
*gpio_key_dev
;
696 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
698 /* use gpio Pin 3 for power button event */
699 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
702 static Notifier virt_system_powerdown_notifier
= {
703 .notify
= virt_powerdown_req
706 static void create_gpio(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
709 DeviceState
*pl061_dev
;
710 hwaddr base
= vbi
->memmap
[VIRT_GPIO
].base
;
711 hwaddr size
= vbi
->memmap
[VIRT_GPIO
].size
;
712 int irq
= vbi
->irqmap
[VIRT_GPIO
];
713 const char compat
[] = "arm,pl061\0arm,primecell";
715 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
717 uint32_t phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
718 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
719 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
720 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
722 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
723 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#gpio-cells", 2);
724 qemu_fdt_setprop(vbi
->fdt
, nodename
, "gpio-controller", NULL
, 0);
725 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
726 GIC_FDT_IRQ_TYPE_SPI
, irq
,
727 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
728 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
729 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
730 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "phandle", phandle
);
732 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
733 qdev_get_gpio_in(pl061_dev
, 3));
734 qemu_fdt_add_subnode(vbi
->fdt
, "/gpio-keys");
735 qemu_fdt_setprop_string(vbi
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
736 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys", "#size-cells", 0);
737 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys", "#address-cells", 1);
739 qemu_fdt_add_subnode(vbi
->fdt
, "/gpio-keys/poweroff");
740 qemu_fdt_setprop_string(vbi
->fdt
, "/gpio-keys/poweroff",
741 "label", "GPIO Key Poweroff");
742 qemu_fdt_setprop_cell(vbi
->fdt
, "/gpio-keys/poweroff", "linux,code",
744 qemu_fdt_setprop_cells(vbi
->fdt
, "/gpio-keys/poweroff",
745 "gpios", phandle
, 3, 0);
747 /* connect powerdown request */
748 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
753 static void create_virtio_devices(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
756 hwaddr size
= vbi
->memmap
[VIRT_MMIO
].size
;
758 /* We create the transports in forwards order. Since qbus_realize()
759 * prepends (not appends) new child buses, the incrementing loop below will
760 * create a list of virtio-mmio buses with decreasing base addresses.
762 * When a -device option is processed from the command line,
763 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
764 * order. The upshot is that -device options in increasing command line
765 * order are mapped to virtio-mmio buses with decreasing base addresses.
767 * When this code was originally written, that arrangement ensured that the
768 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
769 * the first -device on the command line. (The end-to-end order is a
770 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
771 * guest kernel's name-to-address assignment strategy.)
773 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
774 * the message, if not necessarily the code, of commit 70161ff336.
775 * Therefore the loop now establishes the inverse of the original intent.
777 * Unfortunately, we can't counteract the kernel change by reversing the
778 * loop; it would break existing command lines.
780 * In any case, the kernel makes no guarantee about the stability of
781 * enumeration order of virtio devices (as demonstrated by it changing
782 * between kernel versions). For reliable and stable identification
783 * of disks users must use UUIDs or similar mechanisms.
785 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
786 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
787 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
789 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
792 /* We add dtb nodes in reverse order so that they appear in the finished
793 * device tree lowest address first.
795 * Note that this mapping is independent of the loop above. The previous
796 * loop influences virtio device to virtio transport assignment, whereas
797 * this loop controls how virtio transports are laid out in the dtb.
799 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
801 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
802 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
804 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
805 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
806 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
807 "compatible", "virtio,mmio");
808 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
810 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
811 GIC_FDT_IRQ_TYPE_SPI
, irq
,
812 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
817 static void create_one_flash(const char *name
, hwaddr flashbase
,
818 hwaddr flashsize
, const char *file
,
819 MemoryRegion
*sysmem
)
821 /* Create and map a single flash device. We use the same
822 * parameters as the flash devices on the Versatile Express board.
824 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
825 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
826 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
827 const uint64_t sectorlength
= 256 * 1024;
830 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
834 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
835 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
836 qdev_prop_set_uint8(dev
, "width", 4);
837 qdev_prop_set_uint8(dev
, "device-width", 2);
838 qdev_prop_set_bit(dev
, "big-endian", false);
839 qdev_prop_set_uint16(dev
, "id0", 0x89);
840 qdev_prop_set_uint16(dev
, "id1", 0x18);
841 qdev_prop_set_uint16(dev
, "id2", 0x00);
842 qdev_prop_set_uint16(dev
, "id3", 0x00);
843 qdev_prop_set_string(dev
, "name", name
);
844 qdev_init_nofail(dev
);
846 memory_region_add_subregion(sysmem
, flashbase
,
847 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0));
853 if (drive_get(IF_PFLASH
, 0, 0)) {
854 error_report("The contents of the first flash device may be "
855 "specified with -bios or with -drive if=pflash... "
856 "but you cannot use both options at once");
859 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, file
);
861 error_report("Could not find ROM image '%s'", file
);
864 image_size
= load_image_mr(fn
, sysbus_mmio_get_region(sbd
, 0));
866 if (image_size
< 0) {
867 error_report("Could not load ROM image '%s'", file
);
873 static void create_flash(const VirtBoardInfo
*vbi
,
874 MemoryRegion
*sysmem
,
875 MemoryRegion
*secure_sysmem
)
877 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
878 * Any file passed via -bios goes in the first of these.
879 * sysmem is the system memory space. secure_sysmem is the secure view
880 * of the system, and the first flash device should be made visible only
881 * there. The second flash device is visible to both secure and nonsecure.
882 * If sysmem == secure_sysmem this means there is no separate Secure
883 * address space and both flash devices are generally visible.
885 hwaddr flashsize
= vbi
->memmap
[VIRT_FLASH
].size
/ 2;
886 hwaddr flashbase
= vbi
->memmap
[VIRT_FLASH
].base
;
889 create_one_flash("virt.flash0", flashbase
, flashsize
,
890 bios_name
, secure_sysmem
);
891 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
,
894 if (sysmem
== secure_sysmem
) {
895 /* Report both flash devices as a single node in the DT */
896 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
897 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
898 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
899 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
900 2, flashbase
, 2, flashsize
,
901 2, flashbase
+ flashsize
, 2, flashsize
);
902 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
905 /* Report the devices as separate nodes so we can mark one as
906 * only visible to the secure world.
908 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
909 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
910 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
911 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
912 2, flashbase
, 2, flashsize
);
913 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
914 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "status", "disabled");
915 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "secure-status", "okay");
918 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
919 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
920 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
921 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
922 2, flashbase
+ flashsize
, 2, flashsize
);
923 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
928 static void create_fw_cfg(const VirtBoardInfo
*vbi
, AddressSpace
*as
)
930 hwaddr base
= vbi
->memmap
[VIRT_FW_CFG
].base
;
931 hwaddr size
= vbi
->memmap
[VIRT_FW_CFG
].size
;
934 fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
936 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
937 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
938 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
939 "compatible", "qemu,fw-cfg-mmio");
940 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
945 static void create_pcie_irq_map(const VirtBoardInfo
*vbi
, uint32_t gic_phandle
,
946 int first_irq
, const char *nodename
)
949 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
950 uint32_t *irq_map
= full_irq_map
;
952 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
953 for (pin
= 0; pin
< 4; pin
++) {
954 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
955 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
956 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
960 devfn
<< 8, 0, 0, /* devfn */
961 pin
+ 1, /* PCI pin */
962 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
964 /* Convert map to big endian */
965 for (i
= 0; i
< 10; i
++) {
966 irq_map
[i
] = cpu_to_be32(map
[i
]);
972 qemu_fdt_setprop(vbi
->fdt
, nodename
, "interrupt-map",
973 full_irq_map
, sizeof(full_irq_map
));
975 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupt-map-mask",
976 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
980 static void create_pcie(const VirtBoardInfo
*vbi
, qemu_irq
*pic
,
983 hwaddr base_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].base
;
984 hwaddr size_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].size
;
985 hwaddr base_mmio_high
= vbi
->memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
986 hwaddr size_mmio_high
= vbi
->memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
987 hwaddr base_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].base
;
988 hwaddr size_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].size
;
989 hwaddr base_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].base
;
990 hwaddr size_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].size
;
991 hwaddr base
= base_mmio
;
992 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
993 int irq
= vbi
->irqmap
[VIRT_PCIE
];
994 MemoryRegion
*mmio_alias
;
995 MemoryRegion
*mmio_reg
;
996 MemoryRegion
*ecam_alias
;
997 MemoryRegion
*ecam_reg
;
1003 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
1004 qdev_init_nofail(dev
);
1006 /* Map only the first size_ecam bytes of ECAM space */
1007 ecam_alias
= g_new0(MemoryRegion
, 1);
1008 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1009 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1010 ecam_reg
, 0, size_ecam
);
1011 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1013 /* Map the MMIO window into system address space so as to expose
1014 * the section of PCI MMIO space which starts at the same base address
1015 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1018 mmio_alias
= g_new0(MemoryRegion
, 1);
1019 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1020 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1021 mmio_reg
, base_mmio
, size_mmio
);
1022 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1025 /* Map high MMIO space */
1026 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1028 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1029 mmio_reg
, base_mmio_high
, size_mmio_high
);
1030 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1034 /* Map IO port space */
1035 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1037 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1038 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
1041 pci
= PCI_HOST_BRIDGE(dev
);
1043 for (i
= 0; i
< nb_nics
; i
++) {
1044 NICInfo
*nd
= &nd_table
[i
];
1047 nd
->model
= g_strdup("virtio");
1050 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1054 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1055 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
1056 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
1057 "compatible", "pci-host-ecam-generic");
1058 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "pci");
1059 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#address-cells", 3);
1060 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#size-cells", 2);
1061 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "bus-range", 0,
1063 qemu_fdt_setprop(vbi
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1065 if (vbi
->msi_phandle
) {
1066 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "msi-parent",
1070 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
1071 2, base_ecam
, 2, size_ecam
);
1074 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
1075 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1076 2, base_pio
, 2, size_pio
,
1077 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1078 2, base_mmio
, 2, size_mmio
,
1079 1, FDT_PCI_RANGE_MMIO_64BIT
,
1081 2, base_mmio_high
, 2, size_mmio_high
);
1083 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
1084 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1085 2, base_pio
, 2, size_pio
,
1086 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1087 2, base_mmio
, 2, size_mmio
);
1090 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#interrupt-cells", 1);
1091 create_pcie_irq_map(vbi
, vbi
->gic_phandle
, irq
, nodename
);
1096 static void create_platform_bus(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
1101 ARMPlatformBusFDTParams
*fdt_params
= g_new(ARMPlatformBusFDTParams
, 1);
1102 MemoryRegion
*sysmem
= get_system_memory();
1104 platform_bus_params
.platform_bus_base
= vbi
->memmap
[VIRT_PLATFORM_BUS
].base
;
1105 platform_bus_params
.platform_bus_size
= vbi
->memmap
[VIRT_PLATFORM_BUS
].size
;
1106 platform_bus_params
.platform_bus_first_irq
= vbi
->irqmap
[VIRT_PLATFORM_BUS
];
1107 platform_bus_params
.platform_bus_num_irqs
= PLATFORM_BUS_NUM_IRQS
;
1109 fdt_params
->system_params
= &platform_bus_params
;
1110 fdt_params
->binfo
= &vbi
->bootinfo
;
1111 fdt_params
->intc
= "/intc";
1113 * register a machine init done notifier that creates the device tree
1114 * nodes of the platform bus and its children dynamic sysbus devices
1116 arm_register_platform_bus_fdt_creator(fdt_params
);
1118 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1119 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1120 qdev_prop_set_uint32(dev
, "num_irqs",
1121 platform_bus_params
.platform_bus_num_irqs
);
1122 qdev_prop_set_uint32(dev
, "mmio_size",
1123 platform_bus_params
.platform_bus_size
);
1124 qdev_init_nofail(dev
);
1125 s
= SYS_BUS_DEVICE(dev
);
1127 for (i
= 0; i
< platform_bus_params
.platform_bus_num_irqs
; i
++) {
1128 int irqn
= platform_bus_params
.platform_bus_first_irq
+ i
;
1129 sysbus_connect_irq(s
, i
, pic
[irqn
]);
1132 memory_region_add_subregion(sysmem
,
1133 platform_bus_params
.platform_bus_base
,
1134 sysbus_mmio_get_region(s
, 0));
1137 static void create_secure_ram(VirtBoardInfo
*vbi
, MemoryRegion
*secure_sysmem
)
1139 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1141 hwaddr base
= vbi
->memmap
[VIRT_SECURE_MEM
].base
;
1142 hwaddr size
= vbi
->memmap
[VIRT_SECURE_MEM
].size
;
1144 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
, &error_fatal
);
1145 vmstate_register_ram_global(secram
);
1146 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1148 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1149 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
1150 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "memory");
1151 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1152 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "status", "disabled");
1153 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "secure-status", "okay");
1158 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1160 const VirtBoardInfo
*board
= (const VirtBoardInfo
*)binfo
;
1162 *fdt_size
= board
->fdt_size
;
1166 static void virt_build_smbios(VirtGuestInfo
*guest_info
)
1168 FWCfgState
*fw_cfg
= guest_info
->fw_cfg
;
1169 uint8_t *smbios_tables
, *smbios_anchor
;
1170 size_t smbios_tables_len
, smbios_anchor_len
;
1171 const char *product
= "QEMU Virtual Machine";
1177 if (kvm_enabled()) {
1178 product
= "KVM Virtual Machine";
1181 smbios_set_defaults("QEMU", product
,
1182 "1.0", false, true, SMBIOS_ENTRY_POINT_30
);
1184 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1185 &smbios_anchor
, &smbios_anchor_len
);
1187 if (smbios_anchor
) {
1188 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-tables",
1189 smbios_tables
, smbios_tables_len
);
1190 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-anchor",
1191 smbios_anchor
, smbios_anchor_len
);
1196 void virt_guest_info_machine_done(Notifier
*notifier
, void *data
)
1198 VirtGuestInfoState
*guest_info_state
= container_of(notifier
,
1199 VirtGuestInfoState
, machine_done
);
1200 virt_acpi_setup(&guest_info_state
->info
);
1201 virt_build_smbios(&guest_info_state
->info
);
1204 static void machvirt_init(MachineState
*machine
)
1206 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1207 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1208 qemu_irq pic
[NUM_IRQS
];
1209 MemoryRegion
*sysmem
= get_system_memory();
1210 MemoryRegion
*secure_sysmem
= NULL
;
1211 int gic_version
= vms
->gic_version
;
1212 int n
, virt_max_cpus
;
1213 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1214 const char *cpu_model
= machine
->cpu_model
;
1216 VirtGuestInfoState
*guest_info_state
= g_malloc0(sizeof *guest_info_state
);
1217 VirtGuestInfo
*guest_info
= &guest_info_state
->info
;
1220 const char *typename
;
1223 bool firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1227 cpu_model
= "cortex-a15";
1230 /* We can probe only here because during property set
1231 * KVM is not available yet
1234 if (!kvm_enabled()) {
1235 error_report("gic-version=host requires KVM");
1239 gic_version
= kvm_arm_vgic_probe();
1241 error_report("Unable to determine GIC version supported by host");
1246 /* Separate the actual CPU model name from any appended features */
1247 cpustr
= g_strsplit(cpu_model
, ",", 2);
1249 vbi
= find_machine_info(cpustr
[0]);
1252 error_report("mach-virt: CPU %s not supported", cpustr
[0]);
1256 /* If we have an EL3 boot ROM then the assumption is that it will
1257 * implement PSCI itself, so disable QEMU's internal implementation
1258 * so it doesn't get in the way. Instead of starting secondary
1259 * CPUs in PSCI powerdown state we will start them all running and
1260 * let the boot ROM sort them out.
1261 * The usual case is that we do use QEMU's PSCI implementation.
1263 vbi
->using_psci
= !(vms
->secure
&& firmware_loaded
);
1265 /* The maximum number of CPUs depends on the GIC version, or on how
1266 * many redistributors we can fit into the memory map.
1268 if (gic_version
== 3) {
1269 virt_max_cpus
= vbi
->memmap
[VIRT_GIC_REDIST
].size
/ 0x20000;
1270 clustersz
= GICV3_TARGETLIST_BITS
;
1272 virt_max_cpus
= GIC_NCPU
;
1273 clustersz
= GIC_TARGETLIST_BITS
;
1276 if (max_cpus
> virt_max_cpus
) {
1277 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1278 "supported by machine 'mach-virt' (%d)",
1279 max_cpus
, virt_max_cpus
);
1283 vbi
->smp_cpus
= smp_cpus
;
1285 if (machine
->ram_size
> vbi
->memmap
[VIRT_MEM
].size
) {
1286 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB
);
1291 if (kvm_enabled()) {
1292 error_report("mach-virt: KVM does not support Security extensions");
1296 /* The Secure view of the world is the same as the NonSecure,
1297 * but with a few extra devices. Create it as a container region
1298 * containing the system memory at low priority; any secure-only
1299 * devices go in at higher priority and take precedence.
1301 secure_sysmem
= g_new(MemoryRegion
, 1);
1302 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1304 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1309 oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpustr
[0]);
1311 error_report("Unable to find CPU definition");
1314 typename
= object_class_get_name(oc
);
1316 /* convert -smp CPU options specified by the user into global props */
1318 cc
->parse_features(typename
, cpustr
[1], &err
);
1321 error_report_err(err
);
1325 for (n
= 0; n
< smp_cpus
; n
++) {
1326 Object
*cpuobj
= object_new(typename
);
1327 if (!vmc
->disallow_affinity_adjustment
) {
1328 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1329 * GIC's target-list limitations. 32-bit KVM hosts currently
1330 * always create clusters of 4 CPUs, but that is expected to
1331 * change when they gain support for gicv3. When KVM is enabled
1332 * it will override the changes we make here, therefore our
1333 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1334 * and to improve SGI efficiency.
1336 uint8_t aff1
= n
/ clustersz
;
1337 uint8_t aff0
= n
% clustersz
;
1338 object_property_set_int(cpuobj
, (aff1
<< ARM_AFF1_SHIFT
) | aff0
,
1339 "mp-affinity", NULL
);
1343 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1346 if (vbi
->using_psci
) {
1347 object_property_set_int(cpuobj
, QEMU_PSCI_CONDUIT_HVC
,
1348 "psci-conduit", NULL
);
1350 /* Secondary CPUs start in PSCI powered-down state */
1352 object_property_set_bool(cpuobj
, true,
1353 "start-powered-off", NULL
);
1357 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu", NULL
)) {
1358 object_property_set_bool(cpuobj
, false, "pmu", NULL
);
1361 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1362 object_property_set_int(cpuobj
, vbi
->memmap
[VIRT_CPUPERIPHS
].base
,
1363 "reset-cbar", &error_abort
);
1366 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1369 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1370 "secure-memory", &error_abort
);
1373 object_property_set_bool(cpuobj
, true, "realized", NULL
);
1375 fdt_add_timer_nodes(vbi
, gic_version
);
1376 fdt_add_cpu_nodes(vbi
);
1377 fdt_add_psci_node(vbi
);
1379 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1381 memory_region_add_subregion(sysmem
, vbi
->memmap
[VIRT_MEM
].base
, ram
);
1383 create_flash(vbi
, sysmem
, secure_sysmem
? secure_sysmem
: sysmem
);
1385 create_gic(vbi
, pic
, gic_version
, vms
->secure
, vmc
->no_its
);
1387 fdt_add_pmu_nodes(vbi
, gic_version
);
1389 create_uart(vbi
, pic
, VIRT_UART
, sysmem
, serial_hds
[0]);
1392 create_secure_ram(vbi
, secure_sysmem
);
1393 create_uart(vbi
, pic
, VIRT_SECURE_UART
, secure_sysmem
, serial_hds
[1]);
1396 create_rtc(vbi
, pic
);
1398 create_pcie(vbi
, pic
, vms
->highmem
);
1400 create_gpio(vbi
, pic
);
1402 /* Create mmio transports, so the user can create virtio backends
1403 * (which will be automatically plugged in to the transports). If
1404 * no backend is created the transport will just sit harmlessly idle.
1406 create_virtio_devices(vbi
, pic
);
1408 create_fw_cfg(vbi
, &address_space_memory
);
1409 rom_set_fw(fw_cfg_find());
1411 guest_info
->smp_cpus
= smp_cpus
;
1412 guest_info
->fw_cfg
= fw_cfg_find();
1413 guest_info
->memmap
= vbi
->memmap
;
1414 guest_info
->irqmap
= vbi
->irqmap
;
1415 guest_info
->use_highmem
= vms
->highmem
;
1416 guest_info
->gic_version
= gic_version
;
1417 guest_info
->no_its
= vmc
->no_its
;
1418 guest_info_state
->machine_done
.notify
= virt_guest_info_machine_done
;
1419 qemu_add_machine_init_done_notifier(&guest_info_state
->machine_done
);
1421 vbi
->bootinfo
.ram_size
= machine
->ram_size
;
1422 vbi
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1423 vbi
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1424 vbi
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1425 vbi
->bootinfo
.nb_cpus
= smp_cpus
;
1426 vbi
->bootinfo
.board_id
= -1;
1427 vbi
->bootinfo
.loader_start
= vbi
->memmap
[VIRT_MEM
].base
;
1428 vbi
->bootinfo
.get_dtb
= machvirt_dtb
;
1429 vbi
->bootinfo
.firmware_loaded
= firmware_loaded
;
1430 arm_load_kernel(ARM_CPU(first_cpu
), &vbi
->bootinfo
);
1433 * arm_load_kernel machine init done notifier registration must
1434 * happen before the platform_bus_create call. In this latter,
1435 * another notifier is registered which adds platform bus nodes.
1436 * Notifiers are executed in registration reverse order.
1438 create_platform_bus(vbi
, pic
);
1441 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1443 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1448 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1450 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1452 vms
->secure
= value
;
1455 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1457 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1459 return vms
->highmem
;
1462 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1464 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1466 vms
->highmem
= value
;
1469 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1471 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1472 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1474 return g_strdup(val
);
1477 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1479 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1481 if (!strcmp(value
, "3")) {
1482 vms
->gic_version
= 3;
1483 } else if (!strcmp(value
, "2")) {
1484 vms
->gic_version
= 2;
1485 } else if (!strcmp(value
, "host")) {
1486 vms
->gic_version
= 0; /* Will probe later */
1488 error_setg(errp
, "Invalid gic-version value");
1489 error_append_hint(errp
, "Valid values are 3, 2, host.\n");
1493 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1495 MachineClass
*mc
= MACHINE_CLASS(oc
);
1497 mc
->init
= machvirt_init
;
1498 /* Start max_cpus at the maximum QEMU supports. We'll further restrict
1499 * it later in machvirt_init, where we have more information about the
1500 * configuration of the particular instance.
1503 mc
->has_dynamic_sysbus
= true;
1504 mc
->block_default_type
= IF_VIRTIO
;
1506 mc
->pci_allow_0_address
= true;
1507 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1508 mc
->minimum_page_bits
= 12;
1511 static const TypeInfo virt_machine_info
= {
1512 .name
= TYPE_VIRT_MACHINE
,
1513 .parent
= TYPE_MACHINE
,
1515 .instance_size
= sizeof(VirtMachineState
),
1516 .class_size
= sizeof(VirtMachineClass
),
1517 .class_init
= virt_machine_class_init
,
1520 static void machvirt_machine_init(void)
1522 type_register_static(&virt_machine_info
);
1524 type_init(machvirt_machine_init
);
1526 static void virt_2_8_instance_init(Object
*obj
)
1528 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1530 /* EL3 is disabled by default on virt: this makes us consistent
1531 * between KVM and TCG for this board, and it also allows us to
1532 * boot UEFI blobs which assume no TrustZone support.
1534 vms
->secure
= false;
1535 object_property_add_bool(obj
, "secure", virt_get_secure
,
1536 virt_set_secure
, NULL
);
1537 object_property_set_description(obj
, "secure",
1538 "Set on/off to enable/disable the ARM "
1539 "Security Extensions (TrustZone)",
1542 /* High memory is enabled by default */
1543 vms
->highmem
= true;
1544 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1545 virt_set_highmem
, NULL
);
1546 object_property_set_description(obj
, "highmem",
1547 "Set on/off to enable/disable using "
1548 "physical address space above 32 bits",
1550 /* Default GIC type is v2 */
1551 vms
->gic_version
= 2;
1552 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1553 virt_set_gic_version
, NULL
);
1554 object_property_set_description(obj
, "gic-version",
1556 "Valid values are 2, 3 and host", NULL
);
1559 static void virt_machine_2_8_options(MachineClass
*mc
)
1562 DEFINE_VIRT_MACHINE_AS_LATEST(2, 8)
1564 #define VIRT_COMPAT_2_7 \
1567 static void virt_2_7_instance_init(Object
*obj
)
1569 virt_2_8_instance_init(obj
);
1572 static void virt_machine_2_7_options(MachineClass
*mc
)
1574 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1576 virt_machine_2_8_options(mc
);
1577 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_7
);
1578 /* ITS was introduced with 2.8 */
1580 /* Stick with 1K pages for migration compatibility */
1581 mc
->minimum_page_bits
= 0;
1583 DEFINE_VIRT_MACHINE(2, 7)
1585 #define VIRT_COMPAT_2_6 \
1588 static void virt_2_6_instance_init(Object
*obj
)
1590 virt_2_7_instance_init(obj
);
1593 static void virt_machine_2_6_options(MachineClass
*mc
)
1595 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1597 virt_machine_2_7_options(mc
);
1598 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_6
);
1599 vmc
->disallow_affinity_adjustment
= true;
1600 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
1603 DEFINE_VIRT_MACHINE(2, 6)