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hw/arm: xlnx-zynqmp: Clean up coding convention issues
[qemu/ar7.git] / hw / arm / xlnx-zynqmp.c
blobe2056a764e207b312d9aa8098dae1f15edf6ae9c
1 /*
2 * Xilinx Zynq MPSoC emulation
3 *
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu/module.h"
21 #include "cpu.h"
22 #include "hw/arm/xlnx-zynqmp.h"
23 #include "hw/intc/arm_gic_common.h"
24 #include "hw/boards.h"
25 #include "exec/address-spaces.h"
26 #include "sysemu/kvm.h"
27 #include "sysemu/sysemu.h"
28 #include "kvm_arm.h"
29
30 #define GIC_NUM_SPI_INTR 160
31
32 #define ARM_PHYS_TIMER_PPI 30
33 #define ARM_VIRT_TIMER_PPI 27
34 #define ARM_HYP_TIMER_PPI 26
35 #define ARM_SEC_TIMER_PPI 29
36 #define GIC_MAINTENANCE_PPI 25
37
38 #define GEM_REVISION 0x40070106
39
40 #define GIC_BASE_ADDR 0xf9000000
41 #define GIC_DIST_ADDR 0xf9010000
42 #define GIC_CPU_ADDR 0xf9020000
43 #define GIC_VIFACE_ADDR 0xf9040000
44 #define GIC_VCPU_ADDR 0xf9060000
45
46 #define SATA_INTR 133
47 #define SATA_ADDR 0xFD0C0000
48 #define SATA_NUM_PORTS 2
49
50 #define QSPI_ADDR 0xff0f0000
51 #define LQSPI_ADDR 0xc0000000
52 #define QSPI_IRQ 15
53
54 #define DP_ADDR 0xfd4a0000
55 #define DP_IRQ 113
56
57 #define DPDMA_ADDR 0xfd4c0000
58 #define DPDMA_IRQ 116
59
60 #define IPI_ADDR 0xFF300000
61 #define IPI_IRQ 64
62
63 #define RTC_ADDR 0xffa60000
64 #define RTC_IRQ 26
65
66 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
67
68 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
69 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
70 };
71
72 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
73 57, 59, 61, 63,
74 };
75
76 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
77 0xFF000000, 0xFF010000,
78 };
79
80 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
81 21, 22,
82 };
83
84 static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = {
85 0xFF060000, 0xFF070000,
86 };
87
88 static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = {
89 23, 24,
90 };
91
92 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
93 0xFF160000, 0xFF170000,
94 };
95
96 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
97 48, 49,
98 };
99
100 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
101 0xFF040000, 0xFF050000,
102 };
103
104 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
105 19, 20,
106 };
107
108 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
109 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
110 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
111 };
112
113 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
114 124, 125, 126, 127, 128, 129, 130, 131
115 };
116
117 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
118 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
119 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
120 };
121
122 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
123 77, 78, 79, 80, 81, 82, 83, 84
124 };
125
126 typedef struct XlnxZynqMPGICRegion {
127 int region_index;
128 uint32_t address;
129 uint32_t offset;
130 bool virt;
131 } XlnxZynqMPGICRegion;
132
133 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
134 /* Distributor */
135 {
136 .region_index = 0,
137 .address = GIC_DIST_ADDR,
138 .offset = 0,
139 .virt = false
140 },
141
142 /* CPU interface */
143 {
144 .region_index = 1,
145 .address = GIC_CPU_ADDR,
146 .offset = 0,
147 .virt = false
148 },
149 {
150 .region_index = 1,
151 .address = GIC_CPU_ADDR + 0x10000,
152 .offset = 0x1000,
153 .virt = false
154 },
155
156 /* Virtual interface */
157 {
158 .region_index = 2,
159 .address = GIC_VIFACE_ADDR,
160 .offset = 0,
161 .virt = true
162 },
163
164 /* Virtual CPU interface */
165 {
166 .region_index = 3,
167 .address = GIC_VCPU_ADDR,
168 .offset = 0,
169 .virt = true
170 },
171 {
172 .region_index = 3,
173 .address = GIC_VCPU_ADDR + 0x10000,
174 .offset = 0x1000,
175 .virt = true
176 },
177 };
178
179 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
180 {
181 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
182 }
183
184 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
185 const char *boot_cpu, Error **errp)
186 {
187 int i;
188 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS,
189 XLNX_ZYNQMP_NUM_RPU_CPUS);
190
191 if (num_rpus <= 0) {
192 /* Don't create rpu-cluster object if there's nothing to put in it */
193 return;
194 }
195
196 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster,
197 TYPE_CPU_CLUSTER);
198 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1);
199
200 for (i = 0; i < num_rpus; i++) {
201 const char *name;
202
203 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
204 &s->rpu_cpu[i],
205 ARM_CPU_TYPE_NAME("cortex-r5f"));
206
207 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
208 if (strcmp(name, boot_cpu)) {
209 /* Secondary CPUs start in PSCI powered-down state */
210 object_property_set_bool(OBJECT(&s->rpu_cpu[i]),
211 "start-powered-off", true, &error_abort);
212 } else {
213 s->boot_cpu_ptr = &s->rpu_cpu[i];
214 }
215
216 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true,
217 &error_abort);
218 if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) {
219 return;
220 }
221 }
222
223 qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
224 }
225
226 static void xlnx_zynqmp_init(Object *obj)
227 {
228 MachineState *ms = MACHINE(qdev_get_machine());
229 XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
230 int i;
231 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
232
233 object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
234 TYPE_CPU_CLUSTER);
235 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0);
236
237 for (i = 0; i < num_apus; i++) {
238 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
239 &s->apu_cpu[i],
240 ARM_CPU_TYPE_NAME("cortex-a53"));
241 }
242
243 object_initialize_child(obj, "gic", &s->gic, gic_class_name());
244
245 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
246 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM);
247 }
248
249 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
250 object_initialize_child(obj, "uart[*]", &s->uart[i],
251 TYPE_CADENCE_UART);
252 }
253
254 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
255 object_initialize_child(obj, "can[*]", &s->can[i],
256 TYPE_XLNX_ZYNQMP_CAN);
257 }
258
259 object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
260
261 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
262 object_initialize_child(obj, "sdhci[*]", &s->sdhci[i],
263 TYPE_SYSBUS_SDHCI);
264 }
265
266 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
267 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS);
268 }
269
270 object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS);
271
272 object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP);
273
274 object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA);
275
276 object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI);
277
278 object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC);
279
280 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
281 object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA);
282 }
283
284 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
285 object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA);
286 }
287 }
288
289 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
290 {
291 MachineState *ms = MACHINE(qdev_get_machine());
292 XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
293 MemoryRegion *system_memory = get_system_memory();
294 uint8_t i;
295 uint64_t ram_size;
296 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
297 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
298 ram_addr_t ddr_low_size, ddr_high_size;
299 qemu_irq gic_spi[GIC_NUM_SPI_INTR];
300 Error *err = NULL;
301
302 ram_size = memory_region_size(s->ddr_ram);
303
304 /*
305 * Create the DDR Memory Regions. User friendly checks should happen at
306 * the board level
307 */
308 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
309 /*
310 * The RAM size is above the maximum available for the low DDR.
311 * Create the high DDR memory region as well.
312 */
313 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
314 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
315 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
316
317 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev),
318 "ddr-ram-high", s->ddr_ram, ddr_low_size,
319 ddr_high_size);
320 memory_region_add_subregion(get_system_memory(),
321 XLNX_ZYNQMP_HIGH_RAM_START,
322 &s->ddr_ram_high);
323 } else {
324 /* RAM must be non-zero */
325 assert(ram_size);
326 ddr_low_size = ram_size;
327 }
328
329 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low",
330 s->ddr_ram, 0, ddr_low_size);
331 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
332
333 /* Create the four OCM banks */
334 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
335 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
336
337 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
338 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
339 memory_region_add_subregion(get_system_memory(),
340 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
341 i * XLNX_ZYNQMP_OCM_RAM_SIZE,
342 &s->ocm_ram[i]);
343
344 g_free(ocm_name);
345 }
346
347 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
348 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
349 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
350 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
351 qdev_prop_set_bit(DEVICE(&s->gic),
352 "has-virtualization-extensions", s->virt);
353
354 qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
355
356 /* Realize APUs before realizing the GIC. KVM requires this. */
357 for (i = 0; i < num_apus; i++) {
358 const char *name;
359
360 object_property_set_int(OBJECT(&s->apu_cpu[i]), "psci-conduit",
361 QEMU_PSCI_CONDUIT_SMC, &error_abort);
362
363 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
364 if (strcmp(name, boot_cpu)) {
365 /* Secondary CPUs start in PSCI powered-down state */
366 object_property_set_bool(OBJECT(&s->apu_cpu[i]),
367 "start-powered-off", true, &error_abort);
368 } else {
369 s->boot_cpu_ptr = &s->apu_cpu[i];
370 }
371
372 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure,
373 NULL);
374 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt,
375 NULL);
376 object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar",
377 GIC_BASE_ADDR, &error_abort);
378 object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count",
379 num_apus, &error_abort);
380 if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) {
381 return;
382 }
383 }
384
385 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
386 return;
387 }
388
389 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
390 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
391 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
392 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
393 MemoryRegion *mr;
394 uint32_t addr = r->address;
395 int j;
396
397 if (r->virt && !s->virt) {
398 continue;
399 }
400
401 mr = sysbus_mmio_get_region(gic, r->region_index);
402 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
403 MemoryRegion *alias = &s->gic_mr[i][j];
404
405 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
406 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
407 memory_region_add_subregion(system_memory, addr, alias);
408
409 addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
410 }
411 }
412
413 for (i = 0; i < num_apus; i++) {
414 qemu_irq irq;
415
416 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
417 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
418 ARM_CPU_IRQ));
419 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
420 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
421 ARM_CPU_FIQ));
422 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
423 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
424 ARM_CPU_VIRQ));
425 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
426 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
427 ARM_CPU_VFIQ));
428 irq = qdev_get_gpio_in(DEVICE(&s->gic),
429 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
430 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
431 irq = qdev_get_gpio_in(DEVICE(&s->gic),
432 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
433 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
434 irq = qdev_get_gpio_in(DEVICE(&s->gic),
435 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
436 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
437 irq = qdev_get_gpio_in(DEVICE(&s->gic),
438 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
439 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
440
441 if (s->virt) {
442 irq = qdev_get_gpio_in(DEVICE(&s->gic),
443 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
444 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
445 }
446 }
447
448 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err);
449 if (err) {
450 error_propagate(errp, err);
451 return;
452 }
453
454 if (!s->boot_cpu_ptr) {
455 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
456 return;
457 }
458
459 for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
460 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
461 }
462
463 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
464 NICInfo *nd = &nd_table[i];
465
466 /* FIXME use qdev NIC properties instead of nd_table[] */
467 if (nd->used) {
468 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
469 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
470 }
471 object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
472 &error_abort);
473 object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
474 &error_abort);
475 object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
476 &error_abort);
477 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
478 return;
479 }
480 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
481 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
482 gic_spi[gem_intr[i]]);
483 }
484
485 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
486 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
487 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
488 return;
489 }
490 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
491 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
492 gic_spi[uart_intr[i]]);
493 }
494
495 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
496 object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq",
497 XLNX_ZYNQMP_CAN_REF_CLK, &error_abort);
498
499 object_property_set_link(OBJECT(&s->can[i]), "canbus",
500 OBJECT(s->canbus[i]), &error_fatal);
501
502 sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err);
503 if (err) {
504 error_propagate(errp, err);
505 return;
506 }
507 sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]);
508 sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0,
509 gic_spi[can_intr[i]]);
510 }
511
512 object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
513 &error_abort);
514 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
515 return;
516 }
517
518 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
519 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
520
521 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
522 char *bus_name;
523 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
524 Object *sdhci = OBJECT(&s->sdhci[i]);
525
526 /*
527 * Compatible with:
528 * - SD Host Controller Specification Version 3.00
529 * - SDIO Specification Version 3.0
530 * - eMMC Specification Version 4.51
531 */
532 if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) {
533 return;
534 }
535 if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES,
536 errp)) {
537 return;
538 }
539 if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) {
540 return;
541 }
542 if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) {
543 return;
544 }
545 sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
546 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
547
548 /* Alias controller SD bus to the SoC itself */
549 bus_name = g_strdup_printf("sd-bus%d", i);
550 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus");
551 g_free(bus_name);
552 }
553
554 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
555 gchar *bus_name;
556
557 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
558 return;
559 }
560
561 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
562 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
563 gic_spi[spi_intr[i]]);
564
565 /* Alias controller SPI bus to the SoC itself */
566 bus_name = g_strdup_printf("spi%d", i);
567 object_property_add_alias(OBJECT(s), bus_name,
568 OBJECT(&s->spi[i]), "spi0");
569 g_free(bus_name);
570 }
571
572 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) {
573 return;
574 }
575 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
576 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
577 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
578
579 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
580 gchar *bus_name;
581 gchar *target_bus;
582
583 /* Alias controller SPI bus to the SoC itself */
584 bus_name = g_strdup_printf("qspi%d", i);
585 target_bus = g_strdup_printf("spi%d", i);
586 object_property_add_alias(OBJECT(s), bus_name,
587 OBJECT(&s->qspi), target_bus);
588 g_free(bus_name);
589 g_free(target_bus);
590 }
591
592 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) {
593 return;
594 }
595 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
596 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
597
598 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) {
599 return;
600 }
601 object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma),
602 &error_abort);
603 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
604 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
605
606 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) {
607 return;
608 }
609 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
610 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
611
612 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
613 return;
614 }
615 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
616 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
617
618 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
619 if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
620 errp)) {
621 return;
622 }
623 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) {
624 return;
625 }
626
627 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
628 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
629 gic_spi[gdma_ch_intr[i]]);
630 }
631
632 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
633 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) {
634 return;
635 }
636
637 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
638 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
639 gic_spi[adma_ch_intr[i]]);
640 }
641 }
642
643 static Property xlnx_zynqmp_props[] = {
644 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
645 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
646 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
647 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
648 MemoryRegion *),
649 DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS,
650 CanBusState *),
651 DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS,
652 CanBusState *),
653 DEFINE_PROP_END_OF_LIST()
654 };
655
656 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
657 {
658 DeviceClass *dc = DEVICE_CLASS(oc);
659
660 device_class_set_props(dc, xlnx_zynqmp_props);
661 dc->realize = xlnx_zynqmp_realize;
662 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
663 dc->user_creatable = false;
664 }
665
666 static const TypeInfo xlnx_zynqmp_type_info = {
667 .name = TYPE_XLNX_ZYNQMP,
668 .parent = TYPE_DEVICE,
669 .instance_size = sizeof(XlnxZynqMPState),
670 .instance_init = xlnx_zynqmp_init,
671 .class_init = xlnx_zynqmp_class_init,
672 };
673
674 static void xlnx_zynqmp_register_types(void)
675 {
676 type_register_static(&xlnx_zynqmp_type_info);
677 }
678
679 type_init(xlnx_zynqmp_register_types)
AR7 emulation for QEMU