2 * TriCore emulation for qemu: main CPU struct.
4 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
25 #include "exec/cpu-defs.h"
26 #include "tricore-defs.h"
28 struct tricore_boot_info
;
30 typedef struct tricore_def_t tricore_def_t
;
32 typedef struct CPUTriCoreState CPUTriCoreState
;
33 struct CPUTriCoreState
{
39 /* Frequently accessed PSW_USB bits are stored separately for efficiency.
40 This contains all the other bits. Use psw_{read,write} to access
44 /* PSW flag cache for faster execution
47 uint32_t PSW_USB_V
; /* Only if bit 31 set, then flag is set */
48 uint32_t PSW_USB_SV
; /* Only if bit 31 set, then flag is set */
49 uint32_t PSW_USB_AV
; /* Only if bit 31 set, then flag is set. */
50 uint32_t PSW_USB_SAV
; /* Only if bit 31 set, then flag is set. */
64 /* Mem Protection Register */
147 /* Memory Management Registers */
165 /* Debug Registers */
181 /* Floating Point Registers */
182 float_status fp_status
;
185 uint32_t hflags
; /* CPU State */
189 /* Internal CPU feature flags. */
192 const tricore_def_t
*cpu_model
;
194 struct QEMUTimer
*timer
; /* Internal timer */
199 * @env: #CPUTriCoreState
211 static inline TriCoreCPU
*tricore_env_get_cpu(CPUTriCoreState
*env
)
213 return TRICORE_CPU(container_of(env
, TriCoreCPU
, env
));
216 #define ENV_GET_CPU(e) CPU(tricore_env_get_cpu(e))
218 #define ENV_OFFSET offsetof(TriCoreCPU, env)
220 hwaddr
tricore_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
221 void tricore_cpu_dump_state(CPUState
*cpu
, FILE *f
, int flags
);
224 #define MASK_PCXI_PCPN 0xff000000
225 #define MASK_PCXI_PIE_1_3 0x00800000
226 #define MASK_PCXI_PIE_1_6 0x00200000
227 #define MASK_PCXI_UL 0x00400000
228 #define MASK_PCXI_PCXS 0x000f0000
229 #define MASK_PCXI_PCXO 0x0000ffff
231 #define MASK_PSW_USB 0xff000000
232 #define MASK_USB_C 0x80000000
233 #define MASK_USB_V 0x40000000
234 #define MASK_USB_SV 0x20000000
235 #define MASK_USB_AV 0x10000000
236 #define MASK_USB_SAV 0x08000000
237 #define MASK_PSW_PRS 0x00003000
238 #define MASK_PSW_IO 0x00000c00
239 #define MASK_PSW_IS 0x00000200
240 #define MASK_PSW_GW 0x00000100
241 #define MASK_PSW_CDE 0x00000080
242 #define MASK_PSW_CDC 0x0000007f
243 #define MASK_PSW_FPU_RM 0x3000000
245 #define MASK_SYSCON_PRO_TEN 0x2
246 #define MASK_SYSCON_FCD_SF 0x1
248 #define MASK_CPUID_MOD 0xffff0000
249 #define MASK_CPUID_MOD_32B 0x0000ff00
250 #define MASK_CPUID_REV 0x000000ff
252 #define MASK_ICR_PIPN 0x00ff0000
253 #define MASK_ICR_IE_1_3 0x00000100
254 #define MASK_ICR_IE_1_6 0x00008000
255 #define MASK_ICR_CCPN 0x000000ff
257 #define MASK_FCX_FCXS 0x000f0000
258 #define MASK_FCX_FCXO 0x0000ffff
260 #define MASK_LCX_LCXS 0x000f0000
261 #define MASK_LCX_LCX0 0x0000ffff
263 #define MASK_DBGSR_DE 0x1
264 #define MASK_DBGSR_HALT 0x6
265 #define MASK_DBGSR_SUSP 0x10
266 #define MASK_DBGSR_PREVSUSP 0x20
267 #define MASK_DBGSR_PEVT 0x40
268 #define MASK_DBGSR_EVTSRC 0x1f00
270 #define TRICORE_HFLAG_KUU 0x3
271 #define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */
272 #define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */
273 #define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */
275 enum tricore_features
{
282 static inline int tricore_feature(CPUTriCoreState
*env
, int feature
)
284 return (env
->features
& (1ULL << feature
)) != 0;
287 /* TriCore Traps Classes*/
364 uint32_t psw_read(CPUTriCoreState
*env
);
365 void psw_write(CPUTriCoreState
*env
, uint32_t val
);
367 void fpu_set_state(CPUTriCoreState
*env
);
369 #define MMU_USER_IDX 2
371 void tricore_cpu_list(void);
373 #define cpu_signal_handler cpu_tricore_signal_handler
374 #define cpu_list tricore_cpu_list
376 static inline int cpu_mmu_index(CPUTriCoreState
*env
, bool ifetch
)
381 typedef CPUTriCoreState CPUArchState
;
382 typedef TriCoreCPU ArchCPU
;
384 #include "exec/cpu-all.h"
387 /* 1 bit to define user level / supervisor access */
390 /* 1 bit to indicate direction */
392 /* Type of instruction that generated the access */
393 ACCESS_CODE
= 0x10, /* Code fetch access */
394 ACCESS_INT
= 0x20, /* Integer load/store access */
395 ACCESS_FLOAT
= 0x30, /* floating point load/store access */
398 void cpu_state_reset(CPUTriCoreState
*s
);
399 void tricore_tcg_init(void);
400 int cpu_tricore_signal_handler(int host_signum
, void *pinfo
, void *puc
);
402 static inline void cpu_get_tb_cpu_state(CPUTriCoreState
*env
, target_ulong
*pc
,
403 target_ulong
*cs_base
, uint32_t *flags
)
410 #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
411 #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
412 #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
415 bool tricore_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
416 MMUAccessType access_type
, int mmu_idx
,
417 bool probe
, uintptr_t retaddr
);
419 #endif /* TRICORE_CPU_H */