2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 * controller, MPCore distributed interrupt controller and ARMv7-M
12 * Nested Vectored Interrupt Controller.
13 * It is compiled in two ways:
14 * (1) as a standalone file to produce a sysbus device which is a GIC
15 * that can be used on the realview board and as one of the builtin
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
17 * (2) by being directly #included into armv7m_nvic.c to produce the
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "gic_internal.h"
24 #include "qapi/error.h"
32 #define DPRINTF(fmt, ...) \
33 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0)
35 #define DPRINTF(fmt, ...) do {} while(0)
38 static const uint8_t gic_id_11mpcore
[] = {
39 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
42 static const uint8_t gic_id_gicv1
[] = {
43 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
46 static const uint8_t gic_id_gicv2
[] = {
47 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
50 static inline int gic_get_current_cpu(GICState
*s
)
53 return current_cpu
->cpu_index
;
58 /* Return true if this GIC config has interrupt groups, which is
59 * true if we're a GICv2, or a GICv1 with the security extensions.
61 static inline bool gic_has_groups(GICState
*s
)
63 return s
->revision
== 2 || s
->security_extn
;
66 /* TODO: Many places that call this routine could be optimized. */
67 /* Update interrupt status after enabled or pending bits have been changed. */
68 void gic_update(GICState
*s
)
73 int irq_level
, fiq_level
;
77 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
79 s
->current_pending
[cpu
] = 1023;
80 if (!(s
->ctlr
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
))
81 || !(s
->cpu_ctlr
[cpu
] & (GICC_CTLR_EN_GRP0
| GICC_CTLR_EN_GRP1
))) {
82 qemu_irq_lower(s
->parent_irq
[cpu
]);
83 qemu_irq_lower(s
->parent_fiq
[cpu
]);
88 for (irq
= 0; irq
< s
->num_irq
; irq
++) {
89 if (GIC_TEST_ENABLED(irq
, cm
) && gic_test_pending(s
, irq
, cm
) &&
90 (irq
< GIC_INTERNAL
|| GIC_TARGET(irq
) & cm
)) {
91 if (GIC_GET_PRIORITY(irq
, cpu
) < best_prio
) {
92 best_prio
= GIC_GET_PRIORITY(irq
, cpu
);
98 if (best_irq
!= 1023) {
99 trace_gic_update_bestirq(cpu
, best_irq
, best_prio
,
100 s
->priority_mask
[cpu
], s
->running_priority
[cpu
]);
103 irq_level
= fiq_level
= 0;
105 if (best_prio
< s
->priority_mask
[cpu
]) {
106 s
->current_pending
[cpu
] = best_irq
;
107 if (best_prio
< s
->running_priority
[cpu
]) {
108 int group
= GIC_TEST_GROUP(best_irq
, cm
);
110 if (extract32(s
->ctlr
, group
, 1) &&
111 extract32(s
->cpu_ctlr
[cpu
], group
, 1)) {
112 if (group
== 0 && s
->cpu_ctlr
[cpu
] & GICC_CTLR_FIQ_EN
) {
113 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
116 trace_gic_update_set_irq(cpu
, "fiq", fiq_level
);
118 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
121 trace_gic_update_set_irq(cpu
, "irq", irq_level
);
127 qemu_set_irq(s
->parent_irq
[cpu
], irq_level
);
128 qemu_set_irq(s
->parent_fiq
[cpu
], fiq_level
);
132 void gic_set_pending_private(GICState
*s
, int cpu
, int irq
)
136 if (gic_test_pending(s
, irq
, cm
)) {
140 DPRINTF("Set %d pending cpu %d\n", irq
, cpu
);
141 GIC_SET_PENDING(irq
, cm
);
145 static void gic_set_irq_11mpcore(GICState
*s
, int irq
, int level
,
149 GIC_SET_LEVEL(irq
, cm
);
150 if (GIC_TEST_EDGE_TRIGGER(irq
) || GIC_TEST_ENABLED(irq
, cm
)) {
151 DPRINTF("Set %d pending mask %x\n", irq
, target
);
152 GIC_SET_PENDING(irq
, target
);
155 GIC_CLEAR_LEVEL(irq
, cm
);
159 static void gic_set_irq_generic(GICState
*s
, int irq
, int level
,
163 GIC_SET_LEVEL(irq
, cm
);
164 DPRINTF("Set %d pending mask %x\n", irq
, target
);
165 if (GIC_TEST_EDGE_TRIGGER(irq
)) {
166 GIC_SET_PENDING(irq
, target
);
169 GIC_CLEAR_LEVEL(irq
, cm
);
173 /* Process a change in an external IRQ input. */
174 static void gic_set_irq(void *opaque
, int irq
, int level
)
176 /* Meaning of the 'irq' parameter:
177 * [0..N-1] : external interrupts
178 * [N..N+31] : PPI (internal) interrupts for CPU 0
179 * [N+32..N+63] : PPI (internal interrupts for CPU 1
182 GICState
*s
= (GICState
*)opaque
;
184 if (irq
< (s
->num_irq
- GIC_INTERNAL
)) {
185 /* The first external input line is internal interrupt 32. */
188 target
= GIC_TARGET(irq
);
191 irq
-= (s
->num_irq
- GIC_INTERNAL
);
192 cpu
= irq
/ GIC_INTERNAL
;
198 assert(irq
>= GIC_NR_SGIS
);
200 if (level
== GIC_TEST_LEVEL(irq
, cm
)) {
204 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
205 gic_set_irq_11mpcore(s
, irq
, level
, cm
, target
);
207 gic_set_irq_generic(s
, irq
, level
, cm
, target
);
209 trace_gic_set_irq(irq
, level
, cm
, target
);
214 static uint16_t gic_get_current_pending_irq(GICState
*s
, int cpu
,
217 uint16_t pending_irq
= s
->current_pending
[cpu
];
219 if (pending_irq
< GIC_MAXIRQ
&& gic_has_groups(s
)) {
220 int group
= GIC_TEST_GROUP(pending_irq
, (1 << cpu
));
221 /* On a GIC without the security extensions, reading this register
222 * behaves in the same way as a secure access to a GIC with them.
224 bool secure
= !s
->security_extn
|| attrs
.secure
;
226 if (group
== 0 && !secure
) {
227 /* Group0 interrupts hidden from Non-secure access */
230 if (group
== 1 && secure
&& !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_ACK_CTL
)) {
231 /* Group1 interrupts only seen by Secure access if
240 static int gic_get_group_priority(GICState
*s
, int cpu
, int irq
)
242 /* Return the group priority of the specified interrupt
243 * (which is the top bits of its priority, with the number
244 * of bits masked determined by the applicable binary point register).
249 if (gic_has_groups(s
) &&
250 !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) &&
251 GIC_TEST_GROUP(irq
, (1 << cpu
))) {
257 /* a BPR of 0 means the group priority bits are [7:1];
258 * a BPR of 1 means they are [7:2], and so on down to
259 * a BPR of 7 meaning no group priority bits at all.
261 mask
= ~0U << ((bpr
& 7) + 1);
263 return GIC_GET_PRIORITY(irq
, cpu
) & mask
;
266 static void gic_activate_irq(GICState
*s
, int cpu
, int irq
)
268 /* Set the appropriate Active Priority Register bit for this IRQ,
269 * and update the running priority.
271 int prio
= gic_get_group_priority(s
, cpu
, irq
);
272 int preemption_level
= prio
>> (GIC_MIN_BPR
+ 1);
273 int regno
= preemption_level
/ 32;
274 int bitno
= preemption_level
% 32;
276 if (gic_has_groups(s
) && GIC_TEST_GROUP(irq
, (1 << cpu
))) {
277 s
->nsapr
[regno
][cpu
] |= (1 << bitno
);
279 s
->apr
[regno
][cpu
] |= (1 << bitno
);
282 s
->running_priority
[cpu
] = prio
;
283 GIC_SET_ACTIVE(irq
, 1 << cpu
);
286 static int gic_get_prio_from_apr_bits(GICState
*s
, int cpu
)
288 /* Recalculate the current running priority for this CPU based
289 * on the set bits in the Active Priority Registers.
292 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
293 uint32_t apr
= s
->apr
[i
][cpu
] | s
->nsapr
[i
][cpu
];
297 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
302 static void gic_drop_prio(GICState
*s
, int cpu
, int group
)
304 /* Drop the priority of the currently active interrupt in the
307 * Note that we can guarantee (because of the requirement to nest
308 * GICC_IAR reads [which activate an interrupt and raise priority]
309 * with GICC_EOIR writes [which drop the priority for the interrupt])
310 * that the interrupt we're being called for is the highest priority
311 * active interrupt, meaning that it has the lowest set bit in the
314 * If the guest does not honour the ordering constraints then the
315 * behaviour of the GIC is UNPREDICTABLE, which for us means that
316 * the values of the APR registers might become incorrect and the
317 * running priority will be wrong, so interrupts that should preempt
318 * might not do so, and interrupts that should not preempt might do so.
322 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
323 uint32_t *papr
= group
? &s
->nsapr
[i
][cpu
] : &s
->apr
[i
][cpu
];
327 /* Clear lowest set bit */
332 s
->running_priority
[cpu
] = gic_get_prio_from_apr_bits(s
, cpu
);
335 uint32_t gic_acknowledge_irq(GICState
*s
, int cpu
, MemTxAttrs attrs
)
340 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
341 * for the case where this GIC supports grouping and the pending interrupt
342 * is in the wrong group.
344 irq
= gic_get_current_pending_irq(s
, cpu
, attrs
);
345 trace_gic_acknowledge_irq(cpu
, irq
);
347 if (irq
>= GIC_MAXIRQ
) {
348 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq
);
352 if (GIC_GET_PRIORITY(irq
, cpu
) >= s
->running_priority
[cpu
]) {
353 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq
);
357 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
358 /* Clear pending flags for both level and edge triggered interrupts.
359 * Level triggered IRQs will be reasserted once they become inactive.
361 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
364 if (irq
< GIC_NR_SGIS
) {
365 /* Lookup the source CPU for the SGI and clear this in the
366 * sgi_pending map. Return the src and clear the overall pending
367 * state on this CPU if the SGI is not pending from any CPUs.
369 assert(s
->sgi_pending
[irq
][cpu
] != 0);
370 src
= ctz32(s
->sgi_pending
[irq
][cpu
]);
371 s
->sgi_pending
[irq
][cpu
] &= ~(1 << src
);
372 if (s
->sgi_pending
[irq
][cpu
] == 0) {
373 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
375 ret
= irq
| ((src
& 0x7) << 10);
377 /* Clear pending state for both level and edge triggered
378 * interrupts. (level triggered interrupts with an active line
379 * remain pending, see gic_test_pending)
381 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
386 gic_activate_irq(s
, cpu
, irq
);
388 DPRINTF("ACK %d\n", irq
);
392 void gic_set_priority(GICState
*s
, int cpu
, int irq
, uint8_t val
,
395 if (s
->security_extn
&& !attrs
.secure
) {
396 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
397 return; /* Ignore Non-secure access of Group0 IRQ */
399 val
= 0x80 | (val
>> 1); /* Non-secure view */
402 if (irq
< GIC_INTERNAL
) {
403 s
->priority1
[irq
][cpu
] = val
;
405 s
->priority2
[(irq
) - GIC_INTERNAL
] = val
;
409 static uint32_t gic_get_priority(GICState
*s
, int cpu
, int irq
,
412 uint32_t prio
= GIC_GET_PRIORITY(irq
, cpu
);
414 if (s
->security_extn
&& !attrs
.secure
) {
415 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
416 return 0; /* Non-secure access cannot read priority of Group0 IRQ */
418 prio
= (prio
<< 1) & 0xff; /* Non-secure view */
423 static void gic_set_priority_mask(GICState
*s
, int cpu
, uint8_t pmask
,
426 if (s
->security_extn
&& !attrs
.secure
) {
427 if (s
->priority_mask
[cpu
] & 0x80) {
428 /* Priority Mask in upper half */
429 pmask
= 0x80 | (pmask
>> 1);
431 /* Non-secure write ignored if priority mask is in lower half */
435 s
->priority_mask
[cpu
] = pmask
;
438 static uint32_t gic_get_priority_mask(GICState
*s
, int cpu
, MemTxAttrs attrs
)
440 uint32_t pmask
= s
->priority_mask
[cpu
];
442 if (s
->security_extn
&& !attrs
.secure
) {
444 /* Priority Mask in upper half, return Non-secure view */
445 pmask
= (pmask
<< 1) & 0xff;
447 /* Priority Mask in lower half, RAZ */
454 static uint32_t gic_get_cpu_control(GICState
*s
, int cpu
, MemTxAttrs attrs
)
456 uint32_t ret
= s
->cpu_ctlr
[cpu
];
458 if (s
->security_extn
&& !attrs
.secure
) {
459 /* Construct the NS banked view of GICC_CTLR from the correct
460 * bits of the S banked view. We don't need to move the bypass
461 * control bits because we don't implement that (IMPDEF) part
462 * of the GIC architecture.
464 ret
= (ret
& (GICC_CTLR_EN_GRP1
| GICC_CTLR_EOIMODE_NS
)) >> 1;
469 static void gic_set_cpu_control(GICState
*s
, int cpu
, uint32_t value
,
474 if (s
->security_extn
&& !attrs
.secure
) {
475 /* The NS view can only write certain bits in the register;
476 * the rest are unchanged
478 mask
= GICC_CTLR_EN_GRP1
;
479 if (s
->revision
== 2) {
480 mask
|= GICC_CTLR_EOIMODE_NS
;
482 s
->cpu_ctlr
[cpu
] &= ~mask
;
483 s
->cpu_ctlr
[cpu
] |= (value
<< 1) & mask
;
485 if (s
->revision
== 2) {
486 mask
= s
->security_extn
? GICC_CTLR_V2_S_MASK
: GICC_CTLR_V2_MASK
;
488 mask
= s
->security_extn
? GICC_CTLR_V1_S_MASK
: GICC_CTLR_V1_MASK
;
490 s
->cpu_ctlr
[cpu
] = value
& mask
;
492 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
493 "Group1 Interrupts %sabled\n", cpu
,
494 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP0
) ? "En" : "Dis",
495 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP1
) ? "En" : "Dis");
498 static uint8_t gic_get_running_priority(GICState
*s
, int cpu
, MemTxAttrs attrs
)
500 if (s
->security_extn
&& !attrs
.secure
) {
501 if (s
->running_priority
[cpu
] & 0x80) {
502 /* Running priority in upper half of range: return the Non-secure
503 * view of the priority.
505 return s
->running_priority
[cpu
] << 1;
507 /* Running priority in lower half of range: RAZ */
511 return s
->running_priority
[cpu
];
515 /* Return true if we should split priority drop and interrupt deactivation,
516 * ie whether the relevant EOIMode bit is set.
518 static bool gic_eoi_split(GICState
*s
, int cpu
, MemTxAttrs attrs
)
520 if (s
->revision
!= 2) {
521 /* Before GICv2 prio-drop and deactivate are not separable */
524 if (s
->security_extn
&& !attrs
.secure
) {
525 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE_NS
;
527 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE
;
530 static void gic_deactivate_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
533 int group
= gic_has_groups(s
) && GIC_TEST_GROUP(irq
, cm
);
535 if (!gic_eoi_split(s
, cpu
, attrs
)) {
536 /* This is UNPREDICTABLE; we choose to ignore it */
537 qemu_log_mask(LOG_GUEST_ERROR
,
538 "gic_deactivate_irq: GICC_DIR write when EOIMode clear");
542 if (s
->security_extn
&& !attrs
.secure
&& !group
) {
543 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq
);
547 GIC_CLEAR_ACTIVE(irq
, cm
);
550 void gic_complete_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
555 DPRINTF("EOI %d\n", irq
);
556 if (irq
>= s
->num_irq
) {
557 /* This handles two cases:
558 * 1. If software writes the ID of a spurious interrupt [ie 1023]
559 * to the GICC_EOIR, the GIC ignores that write.
560 * 2. If software writes the number of a non-existent interrupt
561 * this must be a subcase of "value written does not match the last
562 * valid interrupt value read from the Interrupt Acknowledge
563 * register" and so this is UNPREDICTABLE. We choose to ignore it.
567 if (s
->running_priority
[cpu
] == 0x100) {
568 return; /* No active IRQ. */
571 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
572 /* Mark level triggered interrupts as pending if they are still
574 if (!GIC_TEST_EDGE_TRIGGER(irq
) && GIC_TEST_ENABLED(irq
, cm
)
575 && GIC_TEST_LEVEL(irq
, cm
) && (GIC_TARGET(irq
) & cm
) != 0) {
576 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
577 GIC_SET_PENDING(irq
, cm
);
581 group
= gic_has_groups(s
) && GIC_TEST_GROUP(irq
, cm
);
583 if (s
->security_extn
&& !attrs
.secure
&& !group
) {
584 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq
);
588 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1
589 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1,
590 * i.e. go ahead and complete the irq anyway.
593 gic_drop_prio(s
, cpu
, group
);
595 /* In GICv2 the guest can choose to split priority-drop and deactivate */
596 if (!gic_eoi_split(s
, cpu
, attrs
)) {
597 GIC_CLEAR_ACTIVE(irq
, cm
);
602 static uint32_t gic_dist_readb(void *opaque
, hwaddr offset
, MemTxAttrs attrs
)
604 GICState
*s
= (GICState
*)opaque
;
612 cpu
= gic_get_current_cpu(s
);
614 if (offset
< 0x100) {
615 if (offset
== 0) { /* GICD_CTLR */
616 if (s
->security_extn
&& !attrs
.secure
) {
617 /* The NS bank of this register is just an alias of the
618 * EnableGrp1 bit in the S bank version.
620 return extract32(s
->ctlr
, 1, 1);
626 /* Interrupt Controller Type Register */
627 return ((s
->num_irq
/ 32) - 1)
628 | ((s
->num_cpu
- 1) << 5)
629 | (s
->security_extn
<< 10);
632 if (offset
>= 0x80) {
633 /* Interrupt Group Registers: these RAZ/WI if this is an NS
634 * access to a GIC with the security extensions, or if the GIC
635 * doesn't have groups at all.
638 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
639 /* Every byte offset holds 8 group status bits */
640 irq
= (offset
- 0x080) * 8 + GIC_BASE_IRQ
;
641 if (irq
>= s
->num_irq
) {
644 for (i
= 0; i
< 8; i
++) {
645 if (GIC_TEST_GROUP(irq
+ i
, cm
)) {
653 } else if (offset
< 0x200) {
654 /* Interrupt Set/Clear Enable. */
656 irq
= (offset
- 0x100) * 8;
658 irq
= (offset
- 0x180) * 8;
660 if (irq
>= s
->num_irq
)
663 for (i
= 0; i
< 8; i
++) {
664 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
668 } else if (offset
< 0x300) {
669 /* Interrupt Set/Clear Pending. */
671 irq
= (offset
- 0x200) * 8;
673 irq
= (offset
- 0x280) * 8;
675 if (irq
>= s
->num_irq
)
678 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
679 for (i
= 0; i
< 8; i
++) {
680 if (gic_test_pending(s
, irq
+ i
, mask
)) {
684 } else if (offset
< 0x400) {
685 /* Interrupt Active. */
686 irq
= (offset
- 0x300) * 8 + GIC_BASE_IRQ
;
687 if (irq
>= s
->num_irq
)
690 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
691 for (i
= 0; i
< 8; i
++) {
692 if (GIC_TEST_ACTIVE(irq
+ i
, mask
)) {
696 } else if (offset
< 0x800) {
697 /* Interrupt Priority. */
698 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
699 if (irq
>= s
->num_irq
)
701 res
= gic_get_priority(s
, cpu
, irq
, attrs
);
702 } else if (offset
< 0xc00) {
703 /* Interrupt CPU Target. */
704 if (s
->num_cpu
== 1 && s
->revision
!= REV_11MPCORE
) {
705 /* For uniprocessor GICs these RAZ/WI */
708 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
709 if (irq
>= s
->num_irq
) {
712 if (irq
>= 29 && irq
<= 31) {
715 res
= GIC_TARGET(irq
);
718 } else if (offset
< 0xf00) {
719 /* Interrupt Configuration. */
720 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
721 if (irq
>= s
->num_irq
)
724 for (i
= 0; i
< 4; i
++) {
725 if (GIC_TEST_MODEL(irq
+ i
))
726 res
|= (1 << (i
* 2));
727 if (GIC_TEST_EDGE_TRIGGER(irq
+ i
))
728 res
|= (2 << (i
* 2));
730 } else if (offset
< 0xf10) {
732 } else if (offset
< 0xf30) {
733 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
737 if (offset
< 0xf20) {
738 /* GICD_CPENDSGIRn */
739 irq
= (offset
- 0xf10);
741 irq
= (offset
- 0xf20);
742 /* GICD_SPENDSGIRn */
745 res
= s
->sgi_pending
[irq
][cpu
];
746 } else if (offset
< 0xfd0) {
748 } else if (offset
< 0x1000) {
752 switch (s
->revision
) {
754 res
= gic_id_11mpcore
[(offset
- 0xfd0) >> 2];
757 res
= gic_id_gicv1
[(offset
- 0xfd0) >> 2];
760 res
= gic_id_gicv2
[(offset
- 0xfd0) >> 2];
763 /* Shouldn't be able to get here */
770 g_assert_not_reached();
774 qemu_log_mask(LOG_GUEST_ERROR
,
775 "gic_dist_readb: Bad offset %x\n", (int)offset
);
779 static MemTxResult
gic_dist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
780 unsigned size
, MemTxAttrs attrs
)
784 *data
= gic_dist_readb(opaque
, offset
, attrs
);
787 *data
= gic_dist_readb(opaque
, offset
, attrs
);
788 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
791 *data
= gic_dist_readb(opaque
, offset
, attrs
);
792 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
793 *data
|= gic_dist_readb(opaque
, offset
+ 2, attrs
) << 16;
794 *data
|= gic_dist_readb(opaque
, offset
+ 3, attrs
) << 24;
801 static void gic_dist_writeb(void *opaque
, hwaddr offset
,
802 uint32_t value
, MemTxAttrs attrs
)
804 GICState
*s
= (GICState
*)opaque
;
809 cpu
= gic_get_current_cpu(s
);
810 if (offset
< 0x100) {
812 if (s
->security_extn
&& !attrs
.secure
) {
813 /* NS version is just an alias of the S version's bit 1 */
814 s
->ctlr
= deposit32(s
->ctlr
, 1, 1, value
);
815 } else if (gic_has_groups(s
)) {
816 s
->ctlr
= value
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
);
818 s
->ctlr
= value
& GICD_CTLR_EN_GRP0
;
820 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
821 s
->ctlr
& GICD_CTLR_EN_GRP0
? "En" : "Dis",
822 s
->ctlr
& GICD_CTLR_EN_GRP1
? "En" : "Dis");
823 } else if (offset
< 4) {
825 } else if (offset
>= 0x80) {
826 /* Interrupt Group Registers: RAZ/WI for NS access to secure
827 * GIC, or for GICs without groups.
829 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
830 /* Every byte offset holds 8 group status bits */
831 irq
= (offset
- 0x80) * 8 + GIC_BASE_IRQ
;
832 if (irq
>= s
->num_irq
) {
835 for (i
= 0; i
< 8; i
++) {
836 /* Group bits are banked for private interrupts */
837 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
838 if (value
& (1 << i
)) {
839 /* Group1 (Non-secure) */
840 GIC_SET_GROUP(irq
+ i
, cm
);
842 /* Group0 (Secure) */
843 GIC_CLEAR_GROUP(irq
+ i
, cm
);
850 } else if (offset
< 0x180) {
851 /* Interrupt Set Enable. */
852 irq
= (offset
- 0x100) * 8 + GIC_BASE_IRQ
;
853 if (irq
>= s
->num_irq
)
855 if (irq
< GIC_NR_SGIS
) {
859 for (i
= 0; i
< 8; i
++) {
860 if (value
& (1 << i
)) {
862 (irq
< GIC_INTERNAL
) ? (1 << cpu
) : GIC_TARGET(irq
+ i
);
863 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
865 if (!GIC_TEST_ENABLED(irq
+ i
, cm
)) {
866 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
867 trace_gic_enable_irq(irq
+ i
);
869 GIC_SET_ENABLED(irq
+ i
, cm
);
870 /* If a raised level triggered IRQ enabled then mark
872 if (GIC_TEST_LEVEL(irq
+ i
, mask
)
873 && !GIC_TEST_EDGE_TRIGGER(irq
+ i
)) {
874 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
875 GIC_SET_PENDING(irq
+ i
, mask
);
879 } else if (offset
< 0x200) {
880 /* Interrupt Clear Enable. */
881 irq
= (offset
- 0x180) * 8 + GIC_BASE_IRQ
;
882 if (irq
>= s
->num_irq
)
884 if (irq
< GIC_NR_SGIS
) {
888 for (i
= 0; i
< 8; i
++) {
889 if (value
& (1 << i
)) {
890 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
892 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
893 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
894 trace_gic_disable_irq(irq
+ i
);
896 GIC_CLEAR_ENABLED(irq
+ i
, cm
);
899 } else if (offset
< 0x280) {
900 /* Interrupt Set Pending. */
901 irq
= (offset
- 0x200) * 8 + GIC_BASE_IRQ
;
902 if (irq
>= s
->num_irq
)
904 if (irq
< GIC_NR_SGIS
) {
908 for (i
= 0; i
< 8; i
++) {
909 if (value
& (1 << i
)) {
910 GIC_SET_PENDING(irq
+ i
, GIC_TARGET(irq
+ i
));
913 } else if (offset
< 0x300) {
914 /* Interrupt Clear Pending. */
915 irq
= (offset
- 0x280) * 8 + GIC_BASE_IRQ
;
916 if (irq
>= s
->num_irq
)
918 if (irq
< GIC_NR_SGIS
) {
922 for (i
= 0; i
< 8; i
++) {
923 /* ??? This currently clears the pending bit for all CPUs, even
924 for per-CPU interrupts. It's unclear whether this is the
926 if (value
& (1 << i
)) {
927 GIC_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
930 } else if (offset
< 0x400) {
931 /* Interrupt Active. */
933 } else if (offset
< 0x800) {
934 /* Interrupt Priority. */
935 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
936 if (irq
>= s
->num_irq
)
938 gic_set_priority(s
, cpu
, irq
, value
, attrs
);
939 } else if (offset
< 0xc00) {
940 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
941 * annoying exception of the 11MPCore's GIC.
943 if (s
->num_cpu
!= 1 || s
->revision
== REV_11MPCORE
) {
944 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
945 if (irq
>= s
->num_irq
) {
950 } else if (irq
< GIC_INTERNAL
) {
951 value
= ALL_CPU_MASK
;
953 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
955 } else if (offset
< 0xf00) {
956 /* Interrupt Configuration. */
957 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
958 if (irq
>= s
->num_irq
)
960 if (irq
< GIC_NR_SGIS
)
962 for (i
= 0; i
< 4; i
++) {
963 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
964 if (value
& (1 << (i
* 2))) {
965 GIC_SET_MODEL(irq
+ i
);
967 GIC_CLEAR_MODEL(irq
+ i
);
970 if (value
& (2 << (i
* 2))) {
971 GIC_SET_EDGE_TRIGGER(irq
+ i
);
973 GIC_CLEAR_EDGE_TRIGGER(irq
+ i
);
976 } else if (offset
< 0xf10) {
977 /* 0xf00 is only handled for 32-bit writes. */
979 } else if (offset
< 0xf20) {
980 /* GICD_CPENDSGIRn */
981 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
984 irq
= (offset
- 0xf10);
986 s
->sgi_pending
[irq
][cpu
] &= ~value
;
987 if (s
->sgi_pending
[irq
][cpu
] == 0) {
988 GIC_CLEAR_PENDING(irq
, 1 << cpu
);
990 } else if (offset
< 0xf30) {
991 /* GICD_SPENDSGIRn */
992 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
995 irq
= (offset
- 0xf20);
997 GIC_SET_PENDING(irq
, 1 << cpu
);
998 s
->sgi_pending
[irq
][cpu
] |= value
;
1005 qemu_log_mask(LOG_GUEST_ERROR
,
1006 "gic_dist_writeb: Bad offset %x\n", (int)offset
);
1009 static void gic_dist_writew(void *opaque
, hwaddr offset
,
1010 uint32_t value
, MemTxAttrs attrs
)
1012 gic_dist_writeb(opaque
, offset
, value
& 0xff, attrs
);
1013 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8, attrs
);
1016 static void gic_dist_writel(void *opaque
, hwaddr offset
,
1017 uint32_t value
, MemTxAttrs attrs
)
1019 GICState
*s
= (GICState
*)opaque
;
1020 if (offset
== 0xf00) {
1026 cpu
= gic_get_current_cpu(s
);
1027 irq
= value
& 0x3ff;
1028 switch ((value
>> 24) & 3) {
1030 mask
= (value
>> 16) & ALL_CPU_MASK
;
1033 mask
= ALL_CPU_MASK
^ (1 << cpu
);
1039 DPRINTF("Bad Soft Int target filter\n");
1040 mask
= ALL_CPU_MASK
;
1043 GIC_SET_PENDING(irq
, mask
);
1044 target_cpu
= ctz32(mask
);
1045 while (target_cpu
< GIC_NCPU
) {
1046 s
->sgi_pending
[irq
][target_cpu
] |= (1 << cpu
);
1047 mask
&= ~(1 << target_cpu
);
1048 target_cpu
= ctz32(mask
);
1053 gic_dist_writew(opaque
, offset
, value
& 0xffff, attrs
);
1054 gic_dist_writew(opaque
, offset
+ 2, value
>> 16, attrs
);
1057 static MemTxResult
gic_dist_write(void *opaque
, hwaddr offset
, uint64_t data
,
1058 unsigned size
, MemTxAttrs attrs
)
1062 gic_dist_writeb(opaque
, offset
, data
, attrs
);
1065 gic_dist_writew(opaque
, offset
, data
, attrs
);
1068 gic_dist_writel(opaque
, offset
, data
, attrs
);
1075 static inline uint32_t gic_apr_ns_view(GICState
*s
, int cpu
, int regno
)
1077 /* Return the Nonsecure view of GICC_APR<regno>. This is the
1078 * second half of GICC_NSAPR.
1080 switch (GIC_MIN_BPR
) {
1083 return s
->nsapr
[regno
+ 2][cpu
];
1088 return s
->nsapr
[regno
+ 1][cpu
];
1093 return extract32(s
->nsapr
[0][cpu
], 16, 16);
1098 return extract32(s
->nsapr
[0][cpu
], 8, 8);
1102 g_assert_not_reached();
1107 static inline void gic_apr_write_ns_view(GICState
*s
, int cpu
, int regno
,
1110 /* Write the Nonsecure view of GICC_APR<regno>. */
1111 switch (GIC_MIN_BPR
) {
1114 s
->nsapr
[regno
+ 2][cpu
] = value
;
1119 s
->nsapr
[regno
+ 1][cpu
] = value
;
1124 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 16, 16, value
);
1129 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 8, 8, value
);
1133 g_assert_not_reached();
1137 static MemTxResult
gic_cpu_read(GICState
*s
, int cpu
, int offset
,
1138 uint64_t *data
, MemTxAttrs attrs
)
1141 case 0x00: /* Control */
1142 *data
= gic_get_cpu_control(s
, cpu
, attrs
);
1144 case 0x04: /* Priority mask */
1145 *data
= gic_get_priority_mask(s
, cpu
, attrs
);
1147 case 0x08: /* Binary Point */
1148 if (s
->security_extn
&& !attrs
.secure
) {
1149 /* BPR is banked. Non-secure copy stored in ABPR. */
1150 *data
= s
->abpr
[cpu
];
1152 *data
= s
->bpr
[cpu
];
1155 case 0x0c: /* Acknowledge */
1156 *data
= gic_acknowledge_irq(s
, cpu
, attrs
);
1158 case 0x14: /* Running Priority */
1159 *data
= gic_get_running_priority(s
, cpu
, attrs
);
1161 case 0x18: /* Highest Pending Interrupt */
1162 *data
= gic_get_current_pending_irq(s
, cpu
, attrs
);
1164 case 0x1c: /* Aliased Binary Point */
1165 /* GIC v2, no security: ABPR
1166 * GIC v1, no security: not implemented (RAZ/WI)
1167 * With security extensions, secure access: ABPR (alias of NS BPR)
1168 * With security extensions, nonsecure access: RAZ/WI
1170 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1173 *data
= s
->abpr
[cpu
];
1176 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1178 int regno
= (offset
- 0xd0) / 4;
1180 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1182 } else if (s
->security_extn
&& !attrs
.secure
) {
1183 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1184 *data
= gic_apr_ns_view(s
, regno
, cpu
);
1186 *data
= s
->apr
[regno
][cpu
];
1190 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1192 int regno
= (offset
- 0xe0) / 4;
1194 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2 || !gic_has_groups(s
) ||
1195 (s
->security_extn
&& !attrs
.secure
)) {
1198 *data
= s
->nsapr
[regno
][cpu
];
1203 qemu_log_mask(LOG_GUEST_ERROR
,
1204 "gic_cpu_read: Bad offset %x\n", (int)offset
);
1210 static MemTxResult
gic_cpu_write(GICState
*s
, int cpu
, int offset
,
1211 uint32_t value
, MemTxAttrs attrs
)
1214 case 0x00: /* Control */
1215 gic_set_cpu_control(s
, cpu
, value
, attrs
);
1217 case 0x04: /* Priority mask */
1218 gic_set_priority_mask(s
, cpu
, value
, attrs
);
1220 case 0x08: /* Binary Point */
1221 if (s
->security_extn
&& !attrs
.secure
) {
1222 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1224 s
->bpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_BPR
);
1227 case 0x10: /* End Of Interrupt */
1228 gic_complete_irq(s
, cpu
, value
& 0x3ff, attrs
);
1230 case 0x1c: /* Aliased Binary Point */
1231 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1232 /* unimplemented, or NS access: RAZ/WI */
1235 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1238 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1240 int regno
= (offset
- 0xd0) / 4;
1242 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1245 if (s
->security_extn
&& !attrs
.secure
) {
1246 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1247 gic_apr_write_ns_view(s
, regno
, cpu
, value
);
1249 s
->apr
[regno
][cpu
] = value
;
1253 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1255 int regno
= (offset
- 0xe0) / 4;
1257 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1260 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1263 s
->nsapr
[regno
][cpu
] = value
;
1268 gic_deactivate_irq(s
, cpu
, value
& 0x3ff, attrs
);
1271 qemu_log_mask(LOG_GUEST_ERROR
,
1272 "gic_cpu_write: Bad offset %x\n", (int)offset
);
1279 /* Wrappers to read/write the GIC CPU interface for the current CPU */
1280 static MemTxResult
gic_thiscpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1281 unsigned size
, MemTxAttrs attrs
)
1283 GICState
*s
= (GICState
*)opaque
;
1284 return gic_cpu_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1287 static MemTxResult
gic_thiscpu_write(void *opaque
, hwaddr addr
,
1288 uint64_t value
, unsigned size
,
1291 GICState
*s
= (GICState
*)opaque
;
1292 return gic_cpu_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1295 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
1296 * These just decode the opaque pointer into GICState* + cpu id.
1298 static MemTxResult
gic_do_cpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1299 unsigned size
, MemTxAttrs attrs
)
1301 GICState
**backref
= (GICState
**)opaque
;
1302 GICState
*s
= *backref
;
1303 int id
= (backref
- s
->backref
);
1304 return gic_cpu_read(s
, id
, addr
, data
, attrs
);
1307 static MemTxResult
gic_do_cpu_write(void *opaque
, hwaddr addr
,
1308 uint64_t value
, unsigned size
,
1311 GICState
**backref
= (GICState
**)opaque
;
1312 GICState
*s
= *backref
;
1313 int id
= (backref
- s
->backref
);
1314 return gic_cpu_write(s
, id
, addr
, value
, attrs
);
1317 static const MemoryRegionOps gic_ops
[2] = {
1319 .read_with_attrs
= gic_dist_read
,
1320 .write_with_attrs
= gic_dist_write
,
1321 .endianness
= DEVICE_NATIVE_ENDIAN
,
1324 .read_with_attrs
= gic_thiscpu_read
,
1325 .write_with_attrs
= gic_thiscpu_write
,
1326 .endianness
= DEVICE_NATIVE_ENDIAN
,
1330 static const MemoryRegionOps gic_cpu_ops
= {
1331 .read_with_attrs
= gic_do_cpu_read
,
1332 .write_with_attrs
= gic_do_cpu_write
,
1333 .endianness
= DEVICE_NATIVE_ENDIAN
,
1336 /* This function is used by nvic model */
1337 void gic_init_irqs_and_distributor(GICState
*s
)
1339 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1342 static void arm_gic_realize(DeviceState
*dev
, Error
**errp
)
1344 /* Device instance realize function for the GIC sysbus device */
1346 GICState
*s
= ARM_GIC(dev
);
1347 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1348 ARMGICClass
*agc
= ARM_GIC_GET_CLASS(s
);
1349 Error
*local_err
= NULL
;
1351 agc
->parent_realize(dev
, &local_err
);
1353 error_propagate(errp
, local_err
);
1357 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */
1358 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1360 /* Extra core-specific regions for the CPU interfaces. This is
1361 * necessary for "franken-GIC" implementations, for example on
1363 * NB that the memory region size of 0x100 applies for the 11MPCore
1364 * and also cores following the GIC v1 spec (ie A9).
1365 * GIC v2 defines a larger memory region (0x1000) so this will need
1366 * to be extended when we implement A15.
1368 for (i
= 0; i
< s
->num_cpu
; i
++) {
1370 memory_region_init_io(&s
->cpuiomem
[i
+1], OBJECT(s
), &gic_cpu_ops
,
1371 &s
->backref
[i
], "gic_cpu", 0x100);
1372 sysbus_init_mmio(sbd
, &s
->cpuiomem
[i
+1]);
1376 static void arm_gic_class_init(ObjectClass
*klass
, void *data
)
1378 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1379 ARMGICClass
*agc
= ARM_GIC_CLASS(klass
);
1381 agc
->parent_realize
= dc
->realize
;
1382 dc
->realize
= arm_gic_realize
;
1385 static const TypeInfo arm_gic_info
= {
1386 .name
= TYPE_ARM_GIC
,
1387 .parent
= TYPE_ARM_GIC_COMMON
,
1388 .instance_size
= sizeof(GICState
),
1389 .class_init
= arm_gic_class_init
,
1390 .class_size
= sizeof(ARMGICClass
),
1393 static void arm_gic_register_types(void)
1395 type_register_static(&arm_gic_info
);
1398 type_init(arm_gic_register_types
)