2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "sysemu/block-backend.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/ssi/ssi.h"
29 #include "migration/vmstate.h"
30 #include "qemu/bitops.h"
32 #include "qemu/module.h"
33 #include "qemu/error-report.h"
34 #include "qapi/error.h"
36 #include "qom/object.h"
38 /* Fields for FlashPartInfo->flags */
40 /* erase capabilities */
43 /* set to allow the page program command to write 0s back to 1. Useful for
44 * modelling EEPROM with SPI flash command set
48 /* 16 MiB max in 3 byte address mode */
49 #define MAX_3BYTES_SIZE 0x1000000
51 #define SPI_NOR_MAX_ID_LEN 6
53 typedef struct FlashPartInfo
{
54 const char *part_name
;
56 * This array stores the ID bytes.
57 * The first three bytes are the JEDIC ID.
58 * JEDEC ID zero means "no ID" (mostly older chips).
60 uint8_t id
[SPI_NOR_MAX_ID_LEN
];
62 /* there is confusion between manufacturers as to what a sector is. In this
63 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
64 * command (opcode 0xd8).
71 * Big sized spi nor are often stacked devices, thus sometime
72 * replace chip erase with die erase.
73 * This field inform how many die is in the chip.
78 /* adapted from linux */
79 /* Used when the "_ext_id" is two bytes at most */
80 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
81 .part_name = _part_name,\
83 ((_jedec_id) >> 16) & 0xff,\
84 ((_jedec_id) >> 8) & 0xff,\
86 ((_ext_id) >> 8) & 0xff,\
89 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
90 .sector_size = (_sector_size),\
91 .n_sectors = (_n_sectors),\
96 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
97 .part_name = _part_name,\
99 ((_jedec_id) >> 16) & 0xff,\
100 ((_jedec_id) >> 8) & 0xff,\
102 ((_ext_id) >> 16) & 0xff,\
103 ((_ext_id) >> 8) & 0xff,\
107 .sector_size = (_sector_size),\
108 .n_sectors = (_n_sectors),\
113 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\
115 .part_name = _part_name,\
117 ((_jedec_id) >> 16) & 0xff,\
118 ((_jedec_id) >> 8) & 0xff,\
120 ((_ext_id) >> 8) & 0xff,\
123 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
124 .sector_size = (_sector_size),\
125 .n_sectors = (_n_sectors),\
130 #define JEDEC_NUMONYX 0x20
131 #define JEDEC_WINBOND 0xEF
132 #define JEDEC_SPANSION 0x01
134 /* Numonyx (Micron) Configuration register macros */
135 #define VCFG_DUMMY 0x1
136 #define VCFG_WRAP_SEQUENTIAL 0x2
137 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
138 #define NVCFG_XIP_MODE_MASK (7 << 9)
139 #define VCFG_XIP_MODE_ENABLED (1 << 3)
140 #define CFG_DUMMY_CLK_LEN 4
141 #define NVCFG_DUMMY_CLK_POS 12
142 #define VCFG_DUMMY_CLK_POS 4
143 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7
144 #define EVCFG_VPP_ACCELERATOR (1 << 3)
145 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
146 #define NVCFG_DUAL_IO_MASK (1 << 2)
147 #define EVCFG_DUAL_IO_ENABLED (1 << 6)
148 #define NVCFG_QUAD_IO_MASK (1 << 3)
149 #define EVCFG_QUAD_IO_ENABLED (1 << 7)
150 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
151 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
153 /* Numonyx (Micron) Flag Status Register macros */
154 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
155 #define FSR_FLASH_READY (1 << 7)
157 /* Spansion configuration registers macros. */
158 #define SPANSION_QUAD_CFG_POS 0
159 #define SPANSION_QUAD_CFG_LEN 1
160 #define SPANSION_DUMMY_CLK_POS 0
161 #define SPANSION_DUMMY_CLK_LEN 4
162 #define SPANSION_ADDR_LEN_POS 7
163 #define SPANSION_ADDR_LEN_LEN 1
166 * Spansion read mode command length in bytes,
167 * the mode is currently not supported.
170 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
171 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
173 static const FlashPartInfo known_devices
[] = {
174 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
175 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K
) },
176 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K
) },
178 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K
) },
179 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K
) },
180 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K
) },
182 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K
) },
183 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K
) },
184 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K
) },
185 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K
) },
187 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K
) },
189 /* Atmel EEPROMS - it is assumed, that don't care bit in command
190 * is set to 0. Block protection is not supported.
192 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM
) },
193 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM
) },
196 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K
) },
197 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
198 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
199 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
200 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K
) },
203 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K
) },
204 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K
) },
206 /* Intel/Numonyx -- xxxs33b */
207 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
208 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
209 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
210 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
213 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K
) },
214 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K
) },
215 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
216 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K
) },
217 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
218 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
219 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
220 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
221 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 0) },
222 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
223 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K
| ER_32K
) },
224 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K
| ER_32K
) },
225 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K
| ER_32K
) },
226 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K
| ER_32K
) },
229 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K
) },
230 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K
) },
231 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K
) },
232 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K
) },
233 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K
) },
234 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K
) },
235 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K
) },
236 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K
) },
237 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K
) },
238 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K
) },
239 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
240 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K
) },
241 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K
) },
242 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K
) },
243 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K
| ER_32K
) },
244 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K
, 4) },
245 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K
, 4) },
246 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K
, 2) },
247 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K
, 2) },
249 /* Spansion -- single (large) sector size only, at least
250 * for the chips listed here (without boot sectors).
252 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K
) },
253 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K
) },
254 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
255 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
256 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
257 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
258 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
259 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
260 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
261 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
262 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
263 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
264 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
265 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
266 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
267 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K
| ER_32K
) },
268 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K
| ER_32K
) },
270 /* Spansion -- boot sectors support */
271 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
272 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
274 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
275 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K
) },
276 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K
) },
277 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K
) },
278 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K
) },
279 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K
) },
280 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K
) },
281 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K
) },
282 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K
) },
283 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K
) },
285 /* ST Microelectronics -- newer production may have feature updates */
286 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
287 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
288 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
289 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
290 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
291 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
292 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
293 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
294 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
295 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
297 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
298 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
299 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
301 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
302 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
303 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K
) },
305 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K
) },
306 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K
) },
307 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K
) },
308 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
310 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
311 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K
) },
312 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K
) },
313 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K
) },
314 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K
) },
315 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K
) },
316 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K
) },
317 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K
) },
318 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K
) },
319 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K
) },
320 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K
) },
321 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K
) },
322 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K
) },
323 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K
) },
324 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K
) },
336 BULK_ERASE_60
= 0x60,
368 ERASE4_SECTOR
= 0xdc,
370 EN_4BYTE_ADDR
= 0xB7,
371 EX_4BYTE_ADDR
= 0xE9,
373 EXTEND_ADDR_READ
= 0xC8,
374 EXTEND_ADDR_WRITE
= 0xC5,
380 * Micron: 0x35 - enable QPI
381 * Spansion: 0x35 - read control register
402 STATE_COLLECTING_DATA
,
403 STATE_COLLECTING_VAR_LEN_DATA
,
416 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16
428 uint8_t data
[M25P80_INTERNAL_DATA_BUFFER_SZ
];
432 uint8_t needed_bytes
;
433 uint8_t cmd_in_progress
;
435 uint32_t nonvolatile_cfg
;
436 /* Configuration register for Macronix */
437 uint32_t volatile_cfg
;
438 uint32_t enh_volatile_cfg
;
439 /* Spansion cfg registers. */
440 uint8_t spansion_cr1nv
;
441 uint8_t spansion_cr2nv
;
442 uint8_t spansion_cr3nv
;
443 uint8_t spansion_cr4nv
;
444 uint8_t spansion_cr1v
;
445 uint8_t spansion_cr2v
;
446 uint8_t spansion_cr3v
;
447 uint8_t spansion_cr4v
;
449 bool four_bytes_address_mode
;
456 const FlashPartInfo
*pi
;
459 typedef struct Flash Flash
;
462 SSISlaveClass parent_class
;
465 typedef struct M25P80Class M25P80Class
;
467 #define TYPE_M25P80 "m25p80-generic"
468 DECLARE_OBJ_CHECKERS(Flash
, M25P80Class
,
471 static inline Manufacturer
get_man(Flash
*s
)
473 switch (s
->pi
->id
[0]) {
489 static void blk_sync_complete(void *opaque
, int ret
)
491 QEMUIOVector
*iov
= opaque
;
493 qemu_iovec_destroy(iov
);
496 /* do nothing. Masters do not directly interact with the backing store,
497 * only the working copy so no mutexing required.
501 static void flash_sync_page(Flash
*s
, int page
)
505 if (!s
->blk
|| blk_is_read_only(s
->blk
)) {
509 iov
= g_new(QEMUIOVector
, 1);
510 qemu_iovec_init(iov
, 1);
511 qemu_iovec_add(iov
, s
->storage
+ page
* s
->pi
->page_size
,
513 blk_aio_pwritev(s
->blk
, page
* s
->pi
->page_size
, iov
, 0,
514 blk_sync_complete
, iov
);
517 static inline void flash_sync_area(Flash
*s
, int64_t off
, int64_t len
)
521 if (!s
->blk
|| blk_is_read_only(s
->blk
)) {
525 assert(!(len
% BDRV_SECTOR_SIZE
));
526 iov
= g_new(QEMUIOVector
, 1);
527 qemu_iovec_init(iov
, 1);
528 qemu_iovec_add(iov
, s
->storage
+ off
, len
);
529 blk_aio_pwritev(s
->blk
, off
, iov
, 0, blk_sync_complete
, iov
);
532 static void flash_erase(Flash
*s
, int offset
, FlashCMD cmd
)
535 uint8_t capa_to_assert
= 0;
541 capa_to_assert
= ER_4K
;
546 capa_to_assert
= ER_32K
;
550 len
= s
->pi
->sector_size
;
556 if (s
->pi
->die_cnt
) {
557 len
= s
->size
/ s
->pi
->die_cnt
;
558 offset
= offset
& (~(len
- 1));
560 qemu_log_mask(LOG_GUEST_ERROR
, "M25P80: die erase is not supported"
569 trace_m25p80_flash_erase(s
, offset
, len
);
571 if ((s
->pi
->flags
& capa_to_assert
) != capa_to_assert
) {
572 qemu_log_mask(LOG_GUEST_ERROR
, "M25P80: %d erase size not supported by"
576 if (!s
->write_enable
) {
577 qemu_log_mask(LOG_GUEST_ERROR
, "M25P80: erase with write protect!\n");
580 memset(s
->storage
+ offset
, 0xff, len
);
581 flash_sync_area(s
, offset
, len
);
584 static inline void flash_sync_dirty(Flash
*s
, int64_t newpage
)
586 if (s
->dirty_page
>= 0 && s
->dirty_page
!= newpage
) {
587 flash_sync_page(s
, s
->dirty_page
);
588 s
->dirty_page
= newpage
;
593 void flash_write8(Flash
*s
, uint32_t addr
, uint8_t data
)
595 uint32_t page
= addr
/ s
->pi
->page_size
;
596 uint8_t prev
= s
->storage
[s
->cur_addr
];
598 if (!s
->write_enable
) {
599 qemu_log_mask(LOG_GUEST_ERROR
, "M25P80: write with write protect!\n");
602 if ((prev
^ data
) & data
) {
603 trace_m25p80_programming_zero_to_one(s
, addr
, prev
, data
);
606 if (s
->pi
->flags
& EEPROM
) {
607 s
->storage
[s
->cur_addr
] = data
;
609 s
->storage
[s
->cur_addr
] &= data
;
612 flash_sync_dirty(s
, page
);
613 s
->dirty_page
= page
;
616 static inline int get_addr_length(Flash
*s
)
618 /* check if eeprom is in use */
619 if (s
->pi
->flags
== EEPROM
) {
623 switch (s
->cmd_in_progress
) {
638 return s
->four_bytes_address_mode
? 4 : 3;
642 static void complete_collecting_data(Flash
*s
)
646 n
= get_addr_length(s
);
647 s
->cur_addr
= (n
== 3 ? s
->ear
: 0);
648 for (i
= 0; i
< n
; ++i
) {
650 s
->cur_addr
|= s
->data
[i
];
653 s
->cur_addr
&= s
->size
- 1;
655 s
->state
= STATE_IDLE
;
657 trace_m25p80_complete_collecting(s
, s
->cmd_in_progress
, n
, s
->ear
,
660 switch (s
->cmd_in_progress
) {
667 s
->state
= STATE_PAGE_PROGRAM
;
681 s
->state
= STATE_READ
;
690 flash_erase(s
, s
->cur_addr
, s
->cmd_in_progress
);
693 switch (get_man(s
)) {
695 s
->quad_enable
= !!(s
->data
[1] & 0x02);
698 s
->quad_enable
= extract32(s
->data
[0], 6, 1);
700 s
->volatile_cfg
= s
->data
[1];
701 s
->four_bytes_address_mode
= extract32(s
->data
[1], 5, 1);
707 if (s
->write_enable
) {
708 s
->write_enable
= false;
712 case EXTEND_ADDR_WRITE
:
716 s
->nonvolatile_cfg
= s
->data
[0] | (s
->data
[1] << 8);
719 s
->volatile_cfg
= s
->data
[0];
722 s
->enh_volatile_cfg
= s
->data
[0];
726 if (get_man(s
) == MAN_SST
) {
727 if (s
->cur_addr
<= 1) {
729 s
->data
[0] = s
->pi
->id
[2];
730 s
->data
[1] = s
->pi
->id
[0];
732 s
->data
[0] = s
->pi
->id
[0];
733 s
->data
[1] = s
->pi
->id
[2];
737 s
->data_read_loop
= true;
738 s
->state
= STATE_READING_DATA
;
740 qemu_log_mask(LOG_GUEST_ERROR
,
741 "M25P80: Invalid read id address\n");
744 qemu_log_mask(LOG_GUEST_ERROR
,
745 "M25P80: Read id (command 0x90/0xAB) is not supported"
754 static void reset_memory(Flash
*s
)
756 s
->cmd_in_progress
= NOP
;
759 s
->four_bytes_address_mode
= false;
763 s
->state
= STATE_IDLE
;
764 s
->write_enable
= false;
765 s
->reset_enable
= false;
766 s
->quad_enable
= false;
768 switch (get_man(s
)) {
771 s
->volatile_cfg
|= VCFG_DUMMY
;
772 s
->volatile_cfg
|= VCFG_WRAP_SEQUENTIAL
;
773 if ((s
->nonvolatile_cfg
& NVCFG_XIP_MODE_MASK
)
774 != NVCFG_XIP_MODE_DISABLED
) {
775 s
->volatile_cfg
|= VCFG_XIP_MODE_ENABLED
;
777 s
->volatile_cfg
|= deposit32(s
->volatile_cfg
,
780 extract32(s
->nonvolatile_cfg
,
785 s
->enh_volatile_cfg
= 0;
786 s
->enh_volatile_cfg
|= EVCFG_OUT_DRIVER_STRENGTH_DEF
;
787 s
->enh_volatile_cfg
|= EVCFG_VPP_ACCELERATOR
;
788 s
->enh_volatile_cfg
|= EVCFG_RESET_HOLD_ENABLED
;
789 if (s
->nonvolatile_cfg
& NVCFG_DUAL_IO_MASK
) {
790 s
->enh_volatile_cfg
|= EVCFG_DUAL_IO_ENABLED
;
792 if (s
->nonvolatile_cfg
& NVCFG_QUAD_IO_MASK
) {
793 s
->enh_volatile_cfg
|= EVCFG_QUAD_IO_ENABLED
;
795 if (!(s
->nonvolatile_cfg
& NVCFG_4BYTE_ADDR_MASK
)) {
796 s
->four_bytes_address_mode
= true;
798 if (!(s
->nonvolatile_cfg
& NVCFG_LOWER_SEGMENT_MASK
)) {
799 s
->ear
= s
->size
/ MAX_3BYTES_SIZE
- 1;
803 s
->volatile_cfg
= 0x7;
806 s
->spansion_cr1v
= s
->spansion_cr1nv
;
807 s
->spansion_cr2v
= s
->spansion_cr2nv
;
808 s
->spansion_cr3v
= s
->spansion_cr3nv
;
809 s
->spansion_cr4v
= s
->spansion_cr4nv
;
810 s
->quad_enable
= extract32(s
->spansion_cr1v
,
811 SPANSION_QUAD_CFG_POS
,
812 SPANSION_QUAD_CFG_LEN
814 s
->four_bytes_address_mode
= extract32(s
->spansion_cr2v
,
815 SPANSION_ADDR_LEN_POS
,
816 SPANSION_ADDR_LEN_LEN
823 trace_m25p80_reset_done(s
);
826 static void decode_fast_read_cmd(Flash
*s
)
828 s
->needed_bytes
= get_addr_length(s
);
829 switch (get_man(s
)) {
830 /* Dummy cycles - modeled with bytes writes instead of bits */
832 s
->needed_bytes
+= 8;
835 s
->needed_bytes
+= extract32(s
->volatile_cfg
, 4, 4);
838 if (extract32(s
->volatile_cfg
, 6, 2) == 1) {
839 s
->needed_bytes
+= 6;
841 s
->needed_bytes
+= 8;
845 s
->needed_bytes
+= extract32(s
->spansion_cr2v
,
846 SPANSION_DUMMY_CLK_POS
,
847 SPANSION_DUMMY_CLK_LEN
855 s
->state
= STATE_COLLECTING_DATA
;
858 static void decode_dio_read_cmd(Flash
*s
)
860 s
->needed_bytes
= get_addr_length(s
);
861 /* Dummy cycles modeled with bytes writes instead of bits */
862 switch (get_man(s
)) {
864 s
->needed_bytes
+= WINBOND_CONTINUOUS_READ_MODE_CMD_LEN
;
867 s
->needed_bytes
+= SPANSION_CONTINUOUS_READ_MODE_CMD_LEN
;
868 s
->needed_bytes
+= extract32(s
->spansion_cr2v
,
869 SPANSION_DUMMY_CLK_POS
,
870 SPANSION_DUMMY_CLK_LEN
874 s
->needed_bytes
+= extract32(s
->volatile_cfg
, 4, 4);
877 switch (extract32(s
->volatile_cfg
, 6, 2)) {
879 s
->needed_bytes
+= 6;
882 s
->needed_bytes
+= 8;
885 s
->needed_bytes
+= 4;
894 s
->state
= STATE_COLLECTING_DATA
;
897 static void decode_qio_read_cmd(Flash
*s
)
899 s
->needed_bytes
= get_addr_length(s
);
900 /* Dummy cycles modeled with bytes writes instead of bits */
901 switch (get_man(s
)) {
903 s
->needed_bytes
+= WINBOND_CONTINUOUS_READ_MODE_CMD_LEN
;
904 s
->needed_bytes
+= 4;
907 s
->needed_bytes
+= SPANSION_CONTINUOUS_READ_MODE_CMD_LEN
;
908 s
->needed_bytes
+= extract32(s
->spansion_cr2v
,
909 SPANSION_DUMMY_CLK_POS
,
910 SPANSION_DUMMY_CLK_LEN
914 s
->needed_bytes
+= extract32(s
->volatile_cfg
, 4, 4);
917 switch (extract32(s
->volatile_cfg
, 6, 2)) {
919 s
->needed_bytes
+= 4;
922 s
->needed_bytes
+= 8;
925 s
->needed_bytes
+= 6;
934 s
->state
= STATE_COLLECTING_DATA
;
937 static void decode_new_cmd(Flash
*s
, uint32_t value
)
941 s
->cmd_in_progress
= value
;
942 trace_m25p80_command_decoded(s
, value
);
944 if (value
!= RESET_MEMORY
) {
945 s
->reset_enable
= false;
967 s
->needed_bytes
= get_addr_length(s
);
970 s
->state
= STATE_COLLECTING_DATA
;
979 decode_fast_read_cmd(s
);
984 decode_dio_read_cmd(s
);
989 decode_qio_read_cmd(s
);
993 if (s
->write_enable
) {
994 switch (get_man(s
)) {
997 s
->state
= STATE_COLLECTING_DATA
;
1000 s
->needed_bytes
= 2;
1001 s
->state
= STATE_COLLECTING_VAR_LEN_DATA
;
1004 s
->needed_bytes
= 1;
1005 s
->state
= STATE_COLLECTING_DATA
;
1012 s
->write_enable
= false;
1015 s
->write_enable
= true;
1019 s
->data
[0] = (!!s
->write_enable
) << 1;
1020 if (get_man(s
) == MAN_MACRONIX
) {
1021 s
->data
[0] |= (!!s
->quad_enable
) << 6;
1025 s
->data_read_loop
= true;
1026 s
->state
= STATE_READING_DATA
;
1030 s
->data
[0] = FSR_FLASH_READY
;
1031 if (s
->four_bytes_address_mode
) {
1032 s
->data
[0] |= FSR_4BYTE_ADDR_MODE_ENABLED
;
1036 s
->data_read_loop
= true;
1037 s
->state
= STATE_READING_DATA
;
1041 trace_m25p80_populated_jedec(s
);
1042 for (i
= 0; i
< s
->pi
->id_len
; i
++) {
1043 s
->data
[i
] = s
->pi
->id
[i
];
1045 for (; i
< SPI_NOR_MAX_ID_LEN
; i
++) {
1049 s
->len
= SPI_NOR_MAX_ID_LEN
;
1051 s
->state
= STATE_READING_DATA
;
1055 s
->data
[0] = s
->volatile_cfg
& 0xFF;
1056 s
->data
[0] |= (!!s
->four_bytes_address_mode
) << 5;
1059 s
->state
= STATE_READING_DATA
;
1064 if (s
->write_enable
) {
1065 trace_m25p80_chip_erase(s
);
1066 flash_erase(s
, 0, BULK_ERASE
);
1068 qemu_log_mask(LOG_GUEST_ERROR
, "M25P80: chip erase with write "
1075 s
->four_bytes_address_mode
= true;
1078 s
->four_bytes_address_mode
= false;
1081 case EXTEND_ADDR_READ
:
1082 s
->data
[0] = s
->ear
;
1085 s
->state
= STATE_READING_DATA
;
1088 case EXTEND_ADDR_WRITE
:
1089 if (s
->write_enable
) {
1090 s
->needed_bytes
= 1;
1093 s
->state
= STATE_COLLECTING_DATA
;
1097 s
->data
[0] = s
->nonvolatile_cfg
& 0xFF;
1098 s
->data
[1] = (s
->nonvolatile_cfg
>> 8) & 0xFF;
1101 s
->state
= STATE_READING_DATA
;
1104 if (s
->write_enable
&& get_man(s
) == MAN_NUMONYX
) {
1105 s
->needed_bytes
= 2;
1108 s
->state
= STATE_COLLECTING_DATA
;
1112 s
->data
[0] = s
->volatile_cfg
& 0xFF;
1115 s
->state
= STATE_READING_DATA
;
1118 if (s
->write_enable
) {
1119 s
->needed_bytes
= 1;
1122 s
->state
= STATE_COLLECTING_DATA
;
1126 s
->data
[0] = s
->enh_volatile_cfg
& 0xFF;
1129 s
->state
= STATE_READING_DATA
;
1132 if (s
->write_enable
) {
1133 s
->needed_bytes
= 1;
1136 s
->state
= STATE_COLLECTING_DATA
;
1140 s
->reset_enable
= true;
1143 if (s
->reset_enable
) {
1148 switch (get_man(s
)) {
1150 s
->data
[0] = (!!s
->quad_enable
) << 1;
1153 s
->state
= STATE_READING_DATA
;
1156 s
->quad_enable
= true;
1163 s
->quad_enable
= false;
1168 s
->state
= STATE_READING_DATA
;
1169 s
->data_read_loop
= true;
1171 qemu_log_mask(LOG_GUEST_ERROR
, "M25P80: Unknown cmd %x\n", value
);
1176 static int m25p80_cs(SSISlave
*ss
, bool select
)
1178 Flash
*s
= M25P80(ss
);
1181 if (s
->state
== STATE_COLLECTING_VAR_LEN_DATA
) {
1182 complete_collecting_data(s
);
1186 s
->state
= STATE_IDLE
;
1187 flash_sync_dirty(s
, -1);
1188 s
->data_read_loop
= false;
1191 trace_m25p80_select(s
, select
? "de" : "");
1196 static uint32_t m25p80_transfer8(SSISlave
*ss
, uint32_t tx
)
1198 Flash
*s
= M25P80(ss
);
1201 trace_m25p80_transfer(s
, s
->state
, s
->len
, s
->needed_bytes
, s
->pos
,
1202 s
->cur_addr
, (uint8_t)tx
);
1206 case STATE_PAGE_PROGRAM
:
1207 trace_m25p80_page_program(s
, s
->cur_addr
, (uint8_t)tx
);
1208 flash_write8(s
, s
->cur_addr
, (uint8_t)tx
);
1209 s
->cur_addr
= (s
->cur_addr
+ 1) & (s
->size
- 1);
1213 r
= s
->storage
[s
->cur_addr
];
1214 trace_m25p80_read_byte(s
, s
->cur_addr
, (uint8_t)r
);
1215 s
->cur_addr
= (s
->cur_addr
+ 1) & (s
->size
- 1);
1218 case STATE_COLLECTING_DATA
:
1219 case STATE_COLLECTING_VAR_LEN_DATA
:
1221 if (s
->len
>= M25P80_INTERNAL_DATA_BUFFER_SZ
) {
1222 qemu_log_mask(LOG_GUEST_ERROR
,
1223 "M25P80: Write overrun internal data buffer. "
1224 "SPI controller (QEMU emulator or guest driver) "
1225 "is misbehaving\n");
1226 s
->len
= s
->pos
= 0;
1227 s
->state
= STATE_IDLE
;
1231 s
->data
[s
->len
] = (uint8_t)tx
;
1234 if (s
->len
== s
->needed_bytes
) {
1235 complete_collecting_data(s
);
1239 case STATE_READING_DATA
:
1241 if (s
->pos
>= M25P80_INTERNAL_DATA_BUFFER_SZ
) {
1242 qemu_log_mask(LOG_GUEST_ERROR
,
1243 "M25P80: Read overrun internal data buffer. "
1244 "SPI controller (QEMU emulator or guest driver) "
1245 "is misbehaving\n");
1246 s
->len
= s
->pos
= 0;
1247 s
->state
= STATE_IDLE
;
1251 r
= s
->data
[s
->pos
];
1252 trace_m25p80_read_data(s
, s
->pos
, (uint8_t)r
);
1254 if (s
->pos
== s
->len
) {
1256 if (!s
->data_read_loop
) {
1257 s
->state
= STATE_IDLE
;
1264 decode_new_cmd(s
, (uint8_t)tx
);
1271 static void m25p80_realize(SSISlave
*ss
, Error
**errp
)
1273 Flash
*s
= M25P80(ss
);
1274 M25P80Class
*mc
= M25P80_GET_CLASS(s
);
1279 s
->size
= s
->pi
->sector_size
* s
->pi
->n_sectors
;
1283 uint64_t perm
= BLK_PERM_CONSISTENT_READ
|
1284 (blk_is_read_only(s
->blk
) ? 0 : BLK_PERM_WRITE
);
1285 ret
= blk_set_perm(s
->blk
, perm
, BLK_PERM_ALL
, errp
);
1290 trace_m25p80_binding(s
);
1291 s
->storage
= blk_blockalign(s
->blk
, s
->size
);
1293 if (blk_pread(s
->blk
, 0, s
->storage
, s
->size
) != s
->size
) {
1294 error_setg(errp
, "failed to read the initial flash content");
1298 trace_m25p80_binding_no_bdrv(s
);
1299 s
->storage
= blk_blockalign(NULL
, s
->size
);
1300 memset(s
->storage
, 0xFF, s
->size
);
1304 static void m25p80_reset(DeviceState
*d
)
1306 Flash
*s
= M25P80(d
);
1311 static int m25p80_pre_save(void *opaque
)
1313 flash_sync_dirty((Flash
*)opaque
, -1);
1318 static Property m25p80_properties
[] = {
1319 /* This is default value for Micron flash */
1320 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash
, nonvolatile_cfg
, 0x8FFF),
1321 DEFINE_PROP_UINT8("spansion-cr1nv", Flash
, spansion_cr1nv
, 0x0),
1322 DEFINE_PROP_UINT8("spansion-cr2nv", Flash
, spansion_cr2nv
, 0x8),
1323 DEFINE_PROP_UINT8("spansion-cr3nv", Flash
, spansion_cr3nv
, 0x2),
1324 DEFINE_PROP_UINT8("spansion-cr4nv", Flash
, spansion_cr4nv
, 0x10),
1325 DEFINE_PROP_DRIVE("drive", Flash
, blk
),
1326 DEFINE_PROP_END_OF_LIST(),
1329 static int m25p80_pre_load(void *opaque
)
1331 Flash
*s
= (Flash
*)opaque
;
1333 s
->data_read_loop
= false;
1337 static bool m25p80_data_read_loop_needed(void *opaque
)
1339 Flash
*s
= (Flash
*)opaque
;
1341 return s
->data_read_loop
;
1344 static const VMStateDescription vmstate_m25p80_data_read_loop
= {
1345 .name
= "m25p80/data_read_loop",
1347 .minimum_version_id
= 1,
1348 .needed
= m25p80_data_read_loop_needed
,
1349 .fields
= (VMStateField
[]) {
1350 VMSTATE_BOOL(data_read_loop
, Flash
),
1351 VMSTATE_END_OF_LIST()
1355 static const VMStateDescription vmstate_m25p80
= {
1358 .minimum_version_id
= 0,
1359 .pre_save
= m25p80_pre_save
,
1360 .pre_load
= m25p80_pre_load
,
1361 .fields
= (VMStateField
[]) {
1362 VMSTATE_UINT8(state
, Flash
),
1363 VMSTATE_UINT8_ARRAY(data
, Flash
, M25P80_INTERNAL_DATA_BUFFER_SZ
),
1364 VMSTATE_UINT32(len
, Flash
),
1365 VMSTATE_UINT32(pos
, Flash
),
1366 VMSTATE_UINT8(needed_bytes
, Flash
),
1367 VMSTATE_UINT8(cmd_in_progress
, Flash
),
1368 VMSTATE_UINT32(cur_addr
, Flash
),
1369 VMSTATE_BOOL(write_enable
, Flash
),
1370 VMSTATE_BOOL(reset_enable
, Flash
),
1371 VMSTATE_UINT8(ear
, Flash
),
1372 VMSTATE_BOOL(four_bytes_address_mode
, Flash
),
1373 VMSTATE_UINT32(nonvolatile_cfg
, Flash
),
1374 VMSTATE_UINT32(volatile_cfg
, Flash
),
1375 VMSTATE_UINT32(enh_volatile_cfg
, Flash
),
1376 VMSTATE_BOOL(quad_enable
, Flash
),
1377 VMSTATE_UINT8(spansion_cr1nv
, Flash
),
1378 VMSTATE_UINT8(spansion_cr2nv
, Flash
),
1379 VMSTATE_UINT8(spansion_cr3nv
, Flash
),
1380 VMSTATE_UINT8(spansion_cr4nv
, Flash
),
1381 VMSTATE_END_OF_LIST()
1383 .subsections
= (const VMStateDescription
* []) {
1384 &vmstate_m25p80_data_read_loop
,
1389 static void m25p80_class_init(ObjectClass
*klass
, void *data
)
1391 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1392 SSISlaveClass
*k
= SSI_SLAVE_CLASS(klass
);
1393 M25P80Class
*mc
= M25P80_CLASS(klass
);
1395 k
->realize
= m25p80_realize
;
1396 k
->transfer
= m25p80_transfer8
;
1397 k
->set_cs
= m25p80_cs
;
1398 k
->cs_polarity
= SSI_CS_LOW
;
1399 dc
->vmsd
= &vmstate_m25p80
;
1400 device_class_set_props(dc
, m25p80_properties
);
1401 dc
->reset
= m25p80_reset
;
1405 static const TypeInfo m25p80_info
= {
1406 .name
= TYPE_M25P80
,
1407 .parent
= TYPE_SSI_SLAVE
,
1408 .instance_size
= sizeof(Flash
),
1409 .class_size
= sizeof(M25P80Class
),
1413 static void m25p80_register_types(void)
1417 type_register_static(&m25p80_info
);
1418 for (i
= 0; i
< ARRAY_SIZE(known_devices
); ++i
) {
1420 .name
= known_devices
[i
].part_name
,
1421 .parent
= TYPE_M25P80
,
1422 .class_init
= m25p80_class_init
,
1423 .class_data
= (void *)&known_devices
[i
],
1429 type_init(m25p80_register_types
)