2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 * controller, MPCore distributed interrupt controller and ARMv7-M
12 * Nested Vectored Interrupt Controller.
13 * It is compiled in two ways:
14 * (1) as a standalone file to produce a sysbus device which is a GIC
15 * that can be used on the realview board and as one of the builtin
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
17 * (2) by being directly #included into armv7m_nvic.c to produce the
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "gic_internal.h"
24 #include "qapi/error.h"
31 #define DPRINTF(fmt, ...) \
32 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0)
34 #define DPRINTF(fmt, ...) do {} while(0)
37 static const uint8_t gic_id_11mpcore
[] = {
38 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
41 static const uint8_t gic_id_gicv1
[] = {
42 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
45 static const uint8_t gic_id_gicv2
[] = {
46 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
49 static inline int gic_get_current_cpu(GICState
*s
)
52 return current_cpu
->cpu_index
;
57 /* Return true if this GIC config has interrupt groups, which is
58 * true if we're a GICv2, or a GICv1 with the security extensions.
60 static inline bool gic_has_groups(GICState
*s
)
62 return s
->revision
== 2 || s
->security_extn
;
65 /* TODO: Many places that call this routine could be optimized. */
66 /* Update interrupt status after enabled or pending bits have been changed. */
67 void gic_update(GICState
*s
)
72 int irq_level
, fiq_level
;
76 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
78 s
->current_pending
[cpu
] = 1023;
79 if (!(s
->ctlr
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
))
80 || !(s
->cpu_ctlr
[cpu
] & (GICC_CTLR_EN_GRP0
| GICC_CTLR_EN_GRP1
))) {
81 qemu_irq_lower(s
->parent_irq
[cpu
]);
82 qemu_irq_lower(s
->parent_fiq
[cpu
]);
87 for (irq
= 0; irq
< s
->num_irq
; irq
++) {
88 if (GIC_TEST_ENABLED(irq
, cm
) && gic_test_pending(s
, irq
, cm
) &&
89 (irq
< GIC_INTERNAL
|| GIC_TARGET(irq
) & cm
)) {
90 if (GIC_GET_PRIORITY(irq
, cpu
) < best_prio
) {
91 best_prio
= GIC_GET_PRIORITY(irq
, cpu
);
97 if (best_irq
!= 1023) {
98 trace_gic_update_bestirq(cpu
, best_irq
, best_prio
,
99 s
->priority_mask
[cpu
], s
->running_priority
[cpu
]);
102 irq_level
= fiq_level
= 0;
104 if (best_prio
< s
->priority_mask
[cpu
]) {
105 s
->current_pending
[cpu
] = best_irq
;
106 if (best_prio
< s
->running_priority
[cpu
]) {
107 int group
= GIC_TEST_GROUP(best_irq
, cm
);
109 if (extract32(s
->ctlr
, group
, 1) &&
110 extract32(s
->cpu_ctlr
[cpu
], group
, 1)) {
111 if (group
== 0 && s
->cpu_ctlr
[cpu
] & GICC_CTLR_FIQ_EN
) {
112 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
115 trace_gic_update_set_irq(cpu
, "fiq", fiq_level
);
117 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
120 trace_gic_update_set_irq(cpu
, "irq", irq_level
);
126 qemu_set_irq(s
->parent_irq
[cpu
], irq_level
);
127 qemu_set_irq(s
->parent_fiq
[cpu
], fiq_level
);
131 void gic_set_pending_private(GICState
*s
, int cpu
, int irq
)
135 if (gic_test_pending(s
, irq
, cm
)) {
139 DPRINTF("Set %d pending cpu %d\n", irq
, cpu
);
140 GIC_SET_PENDING(irq
, cm
);
144 static void gic_set_irq_11mpcore(GICState
*s
, int irq
, int level
,
148 GIC_SET_LEVEL(irq
, cm
);
149 if (GIC_TEST_EDGE_TRIGGER(irq
) || GIC_TEST_ENABLED(irq
, cm
)) {
150 DPRINTF("Set %d pending mask %x\n", irq
, target
);
151 GIC_SET_PENDING(irq
, target
);
154 GIC_CLEAR_LEVEL(irq
, cm
);
158 static void gic_set_irq_generic(GICState
*s
, int irq
, int level
,
162 GIC_SET_LEVEL(irq
, cm
);
163 DPRINTF("Set %d pending mask %x\n", irq
, target
);
164 if (GIC_TEST_EDGE_TRIGGER(irq
)) {
165 GIC_SET_PENDING(irq
, target
);
168 GIC_CLEAR_LEVEL(irq
, cm
);
172 /* Process a change in an external IRQ input. */
173 static void gic_set_irq(void *opaque
, int irq
, int level
)
175 /* Meaning of the 'irq' parameter:
176 * [0..N-1] : external interrupts
177 * [N..N+31] : PPI (internal) interrupts for CPU 0
178 * [N+32..N+63] : PPI (internal interrupts for CPU 1
181 GICState
*s
= (GICState
*)opaque
;
183 if (irq
< (s
->num_irq
- GIC_INTERNAL
)) {
184 /* The first external input line is internal interrupt 32. */
187 target
= GIC_TARGET(irq
);
190 irq
-= (s
->num_irq
- GIC_INTERNAL
);
191 cpu
= irq
/ GIC_INTERNAL
;
197 assert(irq
>= GIC_NR_SGIS
);
199 if (level
== GIC_TEST_LEVEL(irq
, cm
)) {
203 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
204 gic_set_irq_11mpcore(s
, irq
, level
, cm
, target
);
206 gic_set_irq_generic(s
, irq
, level
, cm
, target
);
208 trace_gic_set_irq(irq
, level
, cm
, target
);
213 static uint16_t gic_get_current_pending_irq(GICState
*s
, int cpu
,
216 uint16_t pending_irq
= s
->current_pending
[cpu
];
218 if (pending_irq
< GIC_MAXIRQ
&& gic_has_groups(s
)) {
219 int group
= GIC_TEST_GROUP(pending_irq
, (1 << cpu
));
220 /* On a GIC without the security extensions, reading this register
221 * behaves in the same way as a secure access to a GIC with them.
223 bool secure
= !s
->security_extn
|| attrs
.secure
;
225 if (group
== 0 && !secure
) {
226 /* Group0 interrupts hidden from Non-secure access */
229 if (group
== 1 && secure
&& !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_ACK_CTL
)) {
230 /* Group1 interrupts only seen by Secure access if
239 static int gic_get_group_priority(GICState
*s
, int cpu
, int irq
)
241 /* Return the group priority of the specified interrupt
242 * (which is the top bits of its priority, with the number
243 * of bits masked determined by the applicable binary point register).
248 if (gic_has_groups(s
) &&
249 !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) &&
250 GIC_TEST_GROUP(irq
, (1 << cpu
))) {
256 /* a BPR of 0 means the group priority bits are [7:1];
257 * a BPR of 1 means they are [7:2], and so on down to
258 * a BPR of 7 meaning no group priority bits at all.
260 mask
= ~0U << ((bpr
& 7) + 1);
262 return GIC_GET_PRIORITY(irq
, cpu
) & mask
;
265 static void gic_activate_irq(GICState
*s
, int cpu
, int irq
)
267 /* Set the appropriate Active Priority Register bit for this IRQ,
268 * and update the running priority.
270 int prio
= gic_get_group_priority(s
, cpu
, irq
);
271 int preemption_level
= prio
>> (GIC_MIN_BPR
+ 1);
272 int regno
= preemption_level
/ 32;
273 int bitno
= preemption_level
% 32;
275 if (gic_has_groups(s
) && GIC_TEST_GROUP(irq
, (1 << cpu
))) {
276 s
->nsapr
[regno
][cpu
] |= (1 << bitno
);
278 s
->apr
[regno
][cpu
] |= (1 << bitno
);
281 s
->running_priority
[cpu
] = prio
;
282 GIC_SET_ACTIVE(irq
, 1 << cpu
);
285 static int gic_get_prio_from_apr_bits(GICState
*s
, int cpu
)
287 /* Recalculate the current running priority for this CPU based
288 * on the set bits in the Active Priority Registers.
291 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
292 uint32_t apr
= s
->apr
[i
][cpu
] | s
->nsapr
[i
][cpu
];
296 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
301 static void gic_drop_prio(GICState
*s
, int cpu
, int group
)
303 /* Drop the priority of the currently active interrupt in the
306 * Note that we can guarantee (because of the requirement to nest
307 * GICC_IAR reads [which activate an interrupt and raise priority]
308 * with GICC_EOIR writes [which drop the priority for the interrupt])
309 * that the interrupt we're being called for is the highest priority
310 * active interrupt, meaning that it has the lowest set bit in the
313 * If the guest does not honour the ordering constraints then the
314 * behaviour of the GIC is UNPREDICTABLE, which for us means that
315 * the values of the APR registers might become incorrect and the
316 * running priority will be wrong, so interrupts that should preempt
317 * might not do so, and interrupts that should not preempt might do so.
321 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
322 uint32_t *papr
= group
? &s
->nsapr
[i
][cpu
] : &s
->apr
[i
][cpu
];
326 /* Clear lowest set bit */
331 s
->running_priority
[cpu
] = gic_get_prio_from_apr_bits(s
, cpu
);
334 uint32_t gic_acknowledge_irq(GICState
*s
, int cpu
, MemTxAttrs attrs
)
339 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
340 * for the case where this GIC supports grouping and the pending interrupt
341 * is in the wrong group.
343 irq
= gic_get_current_pending_irq(s
, cpu
, attrs
);
344 trace_gic_acknowledge_irq(cpu
, irq
);
346 if (irq
>= GIC_MAXIRQ
) {
347 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq
);
351 if (GIC_GET_PRIORITY(irq
, cpu
) >= s
->running_priority
[cpu
]) {
352 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq
);
356 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
357 /* Clear pending flags for both level and edge triggered interrupts.
358 * Level triggered IRQs will be reasserted once they become inactive.
360 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
363 if (irq
< GIC_NR_SGIS
) {
364 /* Lookup the source CPU for the SGI and clear this in the
365 * sgi_pending map. Return the src and clear the overall pending
366 * state on this CPU if the SGI is not pending from any CPUs.
368 assert(s
->sgi_pending
[irq
][cpu
] != 0);
369 src
= ctz32(s
->sgi_pending
[irq
][cpu
]);
370 s
->sgi_pending
[irq
][cpu
] &= ~(1 << src
);
371 if (s
->sgi_pending
[irq
][cpu
] == 0) {
372 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
374 ret
= irq
| ((src
& 0x7) << 10);
376 /* Clear pending state for both level and edge triggered
377 * interrupts. (level triggered interrupts with an active line
378 * remain pending, see gic_test_pending)
380 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
385 gic_activate_irq(s
, cpu
, irq
);
387 DPRINTF("ACK %d\n", irq
);
391 void gic_set_priority(GICState
*s
, int cpu
, int irq
, uint8_t val
,
394 if (s
->security_extn
&& !attrs
.secure
) {
395 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
396 return; /* Ignore Non-secure access of Group0 IRQ */
398 val
= 0x80 | (val
>> 1); /* Non-secure view */
401 if (irq
< GIC_INTERNAL
) {
402 s
->priority1
[irq
][cpu
] = val
;
404 s
->priority2
[(irq
) - GIC_INTERNAL
] = val
;
408 static uint32_t gic_get_priority(GICState
*s
, int cpu
, int irq
,
411 uint32_t prio
= GIC_GET_PRIORITY(irq
, cpu
);
413 if (s
->security_extn
&& !attrs
.secure
) {
414 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
415 return 0; /* Non-secure access cannot read priority of Group0 IRQ */
417 prio
= (prio
<< 1) & 0xff; /* Non-secure view */
422 static void gic_set_priority_mask(GICState
*s
, int cpu
, uint8_t pmask
,
425 if (s
->security_extn
&& !attrs
.secure
) {
426 if (s
->priority_mask
[cpu
] & 0x80) {
427 /* Priority Mask in upper half */
428 pmask
= 0x80 | (pmask
>> 1);
430 /* Non-secure write ignored if priority mask is in lower half */
434 s
->priority_mask
[cpu
] = pmask
;
437 static uint32_t gic_get_priority_mask(GICState
*s
, int cpu
, MemTxAttrs attrs
)
439 uint32_t pmask
= s
->priority_mask
[cpu
];
441 if (s
->security_extn
&& !attrs
.secure
) {
443 /* Priority Mask in upper half, return Non-secure view */
444 pmask
= (pmask
<< 1) & 0xff;
446 /* Priority Mask in lower half, RAZ */
453 static uint32_t gic_get_cpu_control(GICState
*s
, int cpu
, MemTxAttrs attrs
)
455 uint32_t ret
= s
->cpu_ctlr
[cpu
];
457 if (s
->security_extn
&& !attrs
.secure
) {
458 /* Construct the NS banked view of GICC_CTLR from the correct
459 * bits of the S banked view. We don't need to move the bypass
460 * control bits because we don't implement that (IMPDEF) part
461 * of the GIC architecture.
463 ret
= (ret
& (GICC_CTLR_EN_GRP1
| GICC_CTLR_EOIMODE_NS
)) >> 1;
468 static void gic_set_cpu_control(GICState
*s
, int cpu
, uint32_t value
,
473 if (s
->security_extn
&& !attrs
.secure
) {
474 /* The NS view can only write certain bits in the register;
475 * the rest are unchanged
477 mask
= GICC_CTLR_EN_GRP1
;
478 if (s
->revision
== 2) {
479 mask
|= GICC_CTLR_EOIMODE_NS
;
481 s
->cpu_ctlr
[cpu
] &= ~mask
;
482 s
->cpu_ctlr
[cpu
] |= (value
<< 1) & mask
;
484 if (s
->revision
== 2) {
485 mask
= s
->security_extn
? GICC_CTLR_V2_S_MASK
: GICC_CTLR_V2_MASK
;
487 mask
= s
->security_extn
? GICC_CTLR_V1_S_MASK
: GICC_CTLR_V1_MASK
;
489 s
->cpu_ctlr
[cpu
] = value
& mask
;
491 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
492 "Group1 Interrupts %sabled\n", cpu
,
493 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP0
) ? "En" : "Dis",
494 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP1
) ? "En" : "Dis");
497 static uint8_t gic_get_running_priority(GICState
*s
, int cpu
, MemTxAttrs attrs
)
499 if (s
->security_extn
&& !attrs
.secure
) {
500 if (s
->running_priority
[cpu
] & 0x80) {
501 /* Running priority in upper half of range: return the Non-secure
502 * view of the priority.
504 return s
->running_priority
[cpu
] << 1;
506 /* Running priority in lower half of range: RAZ */
510 return s
->running_priority
[cpu
];
514 /* Return true if we should split priority drop and interrupt deactivation,
515 * ie whether the relevant EOIMode bit is set.
517 static bool gic_eoi_split(GICState
*s
, int cpu
, MemTxAttrs attrs
)
519 if (s
->revision
!= 2) {
520 /* Before GICv2 prio-drop and deactivate are not separable */
523 if (s
->security_extn
&& !attrs
.secure
) {
524 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE_NS
;
526 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE
;
529 static void gic_deactivate_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
532 int group
= gic_has_groups(s
) && GIC_TEST_GROUP(irq
, cm
);
534 if (!gic_eoi_split(s
, cpu
, attrs
)) {
535 /* This is UNPREDICTABLE; we choose to ignore it */
536 qemu_log_mask(LOG_GUEST_ERROR
,
537 "gic_deactivate_irq: GICC_DIR write when EOIMode clear");
541 if (s
->security_extn
&& !attrs
.secure
&& !group
) {
542 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq
);
546 GIC_CLEAR_ACTIVE(irq
, cm
);
549 void gic_complete_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
554 DPRINTF("EOI %d\n", irq
);
555 if (irq
>= s
->num_irq
) {
556 /* This handles two cases:
557 * 1. If software writes the ID of a spurious interrupt [ie 1023]
558 * to the GICC_EOIR, the GIC ignores that write.
559 * 2. If software writes the number of a non-existent interrupt
560 * this must be a subcase of "value written does not match the last
561 * valid interrupt value read from the Interrupt Acknowledge
562 * register" and so this is UNPREDICTABLE. We choose to ignore it.
566 if (s
->running_priority
[cpu
] == 0x100) {
567 return; /* No active IRQ. */
570 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
571 /* Mark level triggered interrupts as pending if they are still
573 if (!GIC_TEST_EDGE_TRIGGER(irq
) && GIC_TEST_ENABLED(irq
, cm
)
574 && GIC_TEST_LEVEL(irq
, cm
) && (GIC_TARGET(irq
) & cm
) != 0) {
575 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
576 GIC_SET_PENDING(irq
, cm
);
580 group
= gic_has_groups(s
) && GIC_TEST_GROUP(irq
, cm
);
582 if (s
->security_extn
&& !attrs
.secure
&& !group
) {
583 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq
);
587 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1
588 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1,
589 * i.e. go ahead and complete the irq anyway.
592 gic_drop_prio(s
, cpu
, group
);
594 /* In GICv2 the guest can choose to split priority-drop and deactivate */
595 if (!gic_eoi_split(s
, cpu
, attrs
)) {
596 GIC_CLEAR_ACTIVE(irq
, cm
);
601 static uint32_t gic_dist_readb(void *opaque
, hwaddr offset
, MemTxAttrs attrs
)
603 GICState
*s
= (GICState
*)opaque
;
611 cpu
= gic_get_current_cpu(s
);
613 if (offset
< 0x100) {
614 if (offset
== 0) { /* GICD_CTLR */
615 if (s
->security_extn
&& !attrs
.secure
) {
616 /* The NS bank of this register is just an alias of the
617 * EnableGrp1 bit in the S bank version.
619 return extract32(s
->ctlr
, 1, 1);
625 /* Interrupt Controller Type Register */
626 return ((s
->num_irq
/ 32) - 1)
627 | ((s
->num_cpu
- 1) << 5)
628 | (s
->security_extn
<< 10);
631 if (offset
>= 0x80) {
632 /* Interrupt Group Registers: these RAZ/WI if this is an NS
633 * access to a GIC with the security extensions, or if the GIC
634 * doesn't have groups at all.
637 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
638 /* Every byte offset holds 8 group status bits */
639 irq
= (offset
- 0x080) * 8 + GIC_BASE_IRQ
;
640 if (irq
>= s
->num_irq
) {
643 for (i
= 0; i
< 8; i
++) {
644 if (GIC_TEST_GROUP(irq
+ i
, cm
)) {
652 } else if (offset
< 0x200) {
653 /* Interrupt Set/Clear Enable. */
655 irq
= (offset
- 0x100) * 8;
657 irq
= (offset
- 0x180) * 8;
659 if (irq
>= s
->num_irq
)
662 for (i
= 0; i
< 8; i
++) {
663 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
667 } else if (offset
< 0x300) {
668 /* Interrupt Set/Clear Pending. */
670 irq
= (offset
- 0x200) * 8;
672 irq
= (offset
- 0x280) * 8;
674 if (irq
>= s
->num_irq
)
677 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
678 for (i
= 0; i
< 8; i
++) {
679 if (gic_test_pending(s
, irq
+ i
, mask
)) {
683 } else if (offset
< 0x400) {
684 /* Interrupt Active. */
685 irq
= (offset
- 0x300) * 8 + GIC_BASE_IRQ
;
686 if (irq
>= s
->num_irq
)
689 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
690 for (i
= 0; i
< 8; i
++) {
691 if (GIC_TEST_ACTIVE(irq
+ i
, mask
)) {
695 } else if (offset
< 0x800) {
696 /* Interrupt Priority. */
697 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
698 if (irq
>= s
->num_irq
)
700 res
= gic_get_priority(s
, cpu
, irq
, attrs
);
701 } else if (offset
< 0xc00) {
702 /* Interrupt CPU Target. */
703 if (s
->num_cpu
== 1 && s
->revision
!= REV_11MPCORE
) {
704 /* For uniprocessor GICs these RAZ/WI */
707 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
708 if (irq
>= s
->num_irq
) {
711 if (irq
>= 29 && irq
<= 31) {
714 res
= GIC_TARGET(irq
);
717 } else if (offset
< 0xf00) {
718 /* Interrupt Configuration. */
719 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
720 if (irq
>= s
->num_irq
)
723 for (i
= 0; i
< 4; i
++) {
724 if (GIC_TEST_MODEL(irq
+ i
))
725 res
|= (1 << (i
* 2));
726 if (GIC_TEST_EDGE_TRIGGER(irq
+ i
))
727 res
|= (2 << (i
* 2));
729 } else if (offset
< 0xf10) {
731 } else if (offset
< 0xf30) {
732 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
736 if (offset
< 0xf20) {
737 /* GICD_CPENDSGIRn */
738 irq
= (offset
- 0xf10);
740 irq
= (offset
- 0xf20);
741 /* GICD_SPENDSGIRn */
744 res
= s
->sgi_pending
[irq
][cpu
];
745 } else if (offset
< 0xfd0) {
747 } else if (offset
< 0x1000) {
751 switch (s
->revision
) {
753 res
= gic_id_11mpcore
[(offset
- 0xfd0) >> 2];
756 res
= gic_id_gicv1
[(offset
- 0xfd0) >> 2];
759 res
= gic_id_gicv2
[(offset
- 0xfd0) >> 2];
762 /* Shouldn't be able to get here */
769 g_assert_not_reached();
773 qemu_log_mask(LOG_GUEST_ERROR
,
774 "gic_dist_readb: Bad offset %x\n", (int)offset
);
778 static MemTxResult
gic_dist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
779 unsigned size
, MemTxAttrs attrs
)
783 *data
= gic_dist_readb(opaque
, offset
, attrs
);
786 *data
= gic_dist_readb(opaque
, offset
, attrs
);
787 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
790 *data
= gic_dist_readb(opaque
, offset
, attrs
);
791 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
792 *data
|= gic_dist_readb(opaque
, offset
+ 2, attrs
) << 16;
793 *data
|= gic_dist_readb(opaque
, offset
+ 3, attrs
) << 24;
800 static void gic_dist_writeb(void *opaque
, hwaddr offset
,
801 uint32_t value
, MemTxAttrs attrs
)
803 GICState
*s
= (GICState
*)opaque
;
808 cpu
= gic_get_current_cpu(s
);
809 if (offset
< 0x100) {
811 if (s
->security_extn
&& !attrs
.secure
) {
812 /* NS version is just an alias of the S version's bit 1 */
813 s
->ctlr
= deposit32(s
->ctlr
, 1, 1, value
);
814 } else if (gic_has_groups(s
)) {
815 s
->ctlr
= value
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
);
817 s
->ctlr
= value
& GICD_CTLR_EN_GRP0
;
819 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
820 s
->ctlr
& GICD_CTLR_EN_GRP0
? "En" : "Dis",
821 s
->ctlr
& GICD_CTLR_EN_GRP1
? "En" : "Dis");
822 } else if (offset
< 4) {
824 } else if (offset
>= 0x80) {
825 /* Interrupt Group Registers: RAZ/WI for NS access to secure
826 * GIC, or for GICs without groups.
828 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
829 /* Every byte offset holds 8 group status bits */
830 irq
= (offset
- 0x80) * 8 + GIC_BASE_IRQ
;
831 if (irq
>= s
->num_irq
) {
834 for (i
= 0; i
< 8; i
++) {
835 /* Group bits are banked for private interrupts */
836 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
837 if (value
& (1 << i
)) {
838 /* Group1 (Non-secure) */
839 GIC_SET_GROUP(irq
+ i
, cm
);
841 /* Group0 (Secure) */
842 GIC_CLEAR_GROUP(irq
+ i
, cm
);
849 } else if (offset
< 0x180) {
850 /* Interrupt Set Enable. */
851 irq
= (offset
- 0x100) * 8 + GIC_BASE_IRQ
;
852 if (irq
>= s
->num_irq
)
854 if (irq
< GIC_NR_SGIS
) {
858 for (i
= 0; i
< 8; i
++) {
859 if (value
& (1 << i
)) {
861 (irq
< GIC_INTERNAL
) ? (1 << cpu
) : GIC_TARGET(irq
+ i
);
862 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
864 if (!GIC_TEST_ENABLED(irq
+ i
, cm
)) {
865 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
866 trace_gic_enable_irq(irq
+ i
);
868 GIC_SET_ENABLED(irq
+ i
, cm
);
869 /* If a raised level triggered IRQ enabled then mark
871 if (GIC_TEST_LEVEL(irq
+ i
, mask
)
872 && !GIC_TEST_EDGE_TRIGGER(irq
+ i
)) {
873 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
874 GIC_SET_PENDING(irq
+ i
, mask
);
878 } else if (offset
< 0x200) {
879 /* Interrupt Clear Enable. */
880 irq
= (offset
- 0x180) * 8 + GIC_BASE_IRQ
;
881 if (irq
>= s
->num_irq
)
883 if (irq
< GIC_NR_SGIS
) {
887 for (i
= 0; i
< 8; i
++) {
888 if (value
& (1 << i
)) {
889 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
891 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
892 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
893 trace_gic_disable_irq(irq
+ i
);
895 GIC_CLEAR_ENABLED(irq
+ i
, cm
);
898 } else if (offset
< 0x280) {
899 /* Interrupt Set Pending. */
900 irq
= (offset
- 0x200) * 8 + GIC_BASE_IRQ
;
901 if (irq
>= s
->num_irq
)
903 if (irq
< GIC_NR_SGIS
) {
907 for (i
= 0; i
< 8; i
++) {
908 if (value
& (1 << i
)) {
909 GIC_SET_PENDING(irq
+ i
, GIC_TARGET(irq
+ i
));
912 } else if (offset
< 0x300) {
913 /* Interrupt Clear Pending. */
914 irq
= (offset
- 0x280) * 8 + GIC_BASE_IRQ
;
915 if (irq
>= s
->num_irq
)
917 if (irq
< GIC_NR_SGIS
) {
921 for (i
= 0; i
< 8; i
++) {
922 /* ??? This currently clears the pending bit for all CPUs, even
923 for per-CPU interrupts. It's unclear whether this is the
925 if (value
& (1 << i
)) {
926 GIC_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
929 } else if (offset
< 0x400) {
930 /* Interrupt Active. */
932 } else if (offset
< 0x800) {
933 /* Interrupt Priority. */
934 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
935 if (irq
>= s
->num_irq
)
937 gic_set_priority(s
, cpu
, irq
, value
, attrs
);
938 } else if (offset
< 0xc00) {
939 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
940 * annoying exception of the 11MPCore's GIC.
942 if (s
->num_cpu
!= 1 || s
->revision
== REV_11MPCORE
) {
943 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
944 if (irq
>= s
->num_irq
) {
949 } else if (irq
< GIC_INTERNAL
) {
950 value
= ALL_CPU_MASK
;
952 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
954 } else if (offset
< 0xf00) {
955 /* Interrupt Configuration. */
956 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
957 if (irq
>= s
->num_irq
)
959 if (irq
< GIC_NR_SGIS
)
961 for (i
= 0; i
< 4; i
++) {
962 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
963 if (value
& (1 << (i
* 2))) {
964 GIC_SET_MODEL(irq
+ i
);
966 GIC_CLEAR_MODEL(irq
+ i
);
969 if (value
& (2 << (i
* 2))) {
970 GIC_SET_EDGE_TRIGGER(irq
+ i
);
972 GIC_CLEAR_EDGE_TRIGGER(irq
+ i
);
975 } else if (offset
< 0xf10) {
976 /* 0xf00 is only handled for 32-bit writes. */
978 } else if (offset
< 0xf20) {
979 /* GICD_CPENDSGIRn */
980 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
983 irq
= (offset
- 0xf10);
985 s
->sgi_pending
[irq
][cpu
] &= ~value
;
986 if (s
->sgi_pending
[irq
][cpu
] == 0) {
987 GIC_CLEAR_PENDING(irq
, 1 << cpu
);
989 } else if (offset
< 0xf30) {
990 /* GICD_SPENDSGIRn */
991 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
994 irq
= (offset
- 0xf20);
996 GIC_SET_PENDING(irq
, 1 << cpu
);
997 s
->sgi_pending
[irq
][cpu
] |= value
;
1004 qemu_log_mask(LOG_GUEST_ERROR
,
1005 "gic_dist_writeb: Bad offset %x\n", (int)offset
);
1008 static void gic_dist_writew(void *opaque
, hwaddr offset
,
1009 uint32_t value
, MemTxAttrs attrs
)
1011 gic_dist_writeb(opaque
, offset
, value
& 0xff, attrs
);
1012 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8, attrs
);
1015 static void gic_dist_writel(void *opaque
, hwaddr offset
,
1016 uint32_t value
, MemTxAttrs attrs
)
1018 GICState
*s
= (GICState
*)opaque
;
1019 if (offset
== 0xf00) {
1025 cpu
= gic_get_current_cpu(s
);
1026 irq
= value
& 0x3ff;
1027 switch ((value
>> 24) & 3) {
1029 mask
= (value
>> 16) & ALL_CPU_MASK
;
1032 mask
= ALL_CPU_MASK
^ (1 << cpu
);
1038 DPRINTF("Bad Soft Int target filter\n");
1039 mask
= ALL_CPU_MASK
;
1042 GIC_SET_PENDING(irq
, mask
);
1043 target_cpu
= ctz32(mask
);
1044 while (target_cpu
< GIC_NCPU
) {
1045 s
->sgi_pending
[irq
][target_cpu
] |= (1 << cpu
);
1046 mask
&= ~(1 << target_cpu
);
1047 target_cpu
= ctz32(mask
);
1052 gic_dist_writew(opaque
, offset
, value
& 0xffff, attrs
);
1053 gic_dist_writew(opaque
, offset
+ 2, value
>> 16, attrs
);
1056 static MemTxResult
gic_dist_write(void *opaque
, hwaddr offset
, uint64_t data
,
1057 unsigned size
, MemTxAttrs attrs
)
1061 gic_dist_writeb(opaque
, offset
, data
, attrs
);
1064 gic_dist_writew(opaque
, offset
, data
, attrs
);
1067 gic_dist_writel(opaque
, offset
, data
, attrs
);
1074 static inline uint32_t gic_apr_ns_view(GICState
*s
, int cpu
, int regno
)
1076 /* Return the Nonsecure view of GICC_APR<regno>. This is the
1077 * second half of GICC_NSAPR.
1079 switch (GIC_MIN_BPR
) {
1082 return s
->nsapr
[regno
+ 2][cpu
];
1087 return s
->nsapr
[regno
+ 1][cpu
];
1092 return extract32(s
->nsapr
[0][cpu
], 16, 16);
1097 return extract32(s
->nsapr
[0][cpu
], 8, 8);
1101 g_assert_not_reached();
1106 static inline void gic_apr_write_ns_view(GICState
*s
, int cpu
, int regno
,
1109 /* Write the Nonsecure view of GICC_APR<regno>. */
1110 switch (GIC_MIN_BPR
) {
1113 s
->nsapr
[regno
+ 2][cpu
] = value
;
1118 s
->nsapr
[regno
+ 1][cpu
] = value
;
1123 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 16, 16, value
);
1128 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 8, 8, value
);
1132 g_assert_not_reached();
1136 static MemTxResult
gic_cpu_read(GICState
*s
, int cpu
, int offset
,
1137 uint64_t *data
, MemTxAttrs attrs
)
1140 case 0x00: /* Control */
1141 *data
= gic_get_cpu_control(s
, cpu
, attrs
);
1143 case 0x04: /* Priority mask */
1144 *data
= gic_get_priority_mask(s
, cpu
, attrs
);
1146 case 0x08: /* Binary Point */
1147 if (s
->security_extn
&& !attrs
.secure
) {
1148 /* BPR is banked. Non-secure copy stored in ABPR. */
1149 *data
= s
->abpr
[cpu
];
1151 *data
= s
->bpr
[cpu
];
1154 case 0x0c: /* Acknowledge */
1155 *data
= gic_acknowledge_irq(s
, cpu
, attrs
);
1157 case 0x14: /* Running Priority */
1158 *data
= gic_get_running_priority(s
, cpu
, attrs
);
1160 case 0x18: /* Highest Pending Interrupt */
1161 *data
= gic_get_current_pending_irq(s
, cpu
, attrs
);
1163 case 0x1c: /* Aliased Binary Point */
1164 /* GIC v2, no security: ABPR
1165 * GIC v1, no security: not implemented (RAZ/WI)
1166 * With security extensions, secure access: ABPR (alias of NS BPR)
1167 * With security extensions, nonsecure access: RAZ/WI
1169 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1172 *data
= s
->abpr
[cpu
];
1175 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1177 int regno
= (offset
- 0xd0) / 4;
1179 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1181 } else if (s
->security_extn
&& !attrs
.secure
) {
1182 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1183 *data
= gic_apr_ns_view(s
, regno
, cpu
);
1185 *data
= s
->apr
[regno
][cpu
];
1189 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1191 int regno
= (offset
- 0xe0) / 4;
1193 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2 || !gic_has_groups(s
) ||
1194 (s
->security_extn
&& !attrs
.secure
)) {
1197 *data
= s
->nsapr
[regno
][cpu
];
1202 qemu_log_mask(LOG_GUEST_ERROR
,
1203 "gic_cpu_read: Bad offset %x\n", (int)offset
);
1209 static MemTxResult
gic_cpu_write(GICState
*s
, int cpu
, int offset
,
1210 uint32_t value
, MemTxAttrs attrs
)
1213 case 0x00: /* Control */
1214 gic_set_cpu_control(s
, cpu
, value
, attrs
);
1216 case 0x04: /* Priority mask */
1217 gic_set_priority_mask(s
, cpu
, value
, attrs
);
1219 case 0x08: /* Binary Point */
1220 if (s
->security_extn
&& !attrs
.secure
) {
1221 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1223 s
->bpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_BPR
);
1226 case 0x10: /* End Of Interrupt */
1227 gic_complete_irq(s
, cpu
, value
& 0x3ff, attrs
);
1229 case 0x1c: /* Aliased Binary Point */
1230 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1231 /* unimplemented, or NS access: RAZ/WI */
1234 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1237 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1239 int regno
= (offset
- 0xd0) / 4;
1241 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1244 if (s
->security_extn
&& !attrs
.secure
) {
1245 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1246 gic_apr_write_ns_view(s
, regno
, cpu
, value
);
1248 s
->apr
[regno
][cpu
] = value
;
1252 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1254 int regno
= (offset
- 0xe0) / 4;
1256 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1259 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1262 s
->nsapr
[regno
][cpu
] = value
;
1267 gic_deactivate_irq(s
, cpu
, value
& 0x3ff, attrs
);
1270 qemu_log_mask(LOG_GUEST_ERROR
,
1271 "gic_cpu_write: Bad offset %x\n", (int)offset
);
1278 /* Wrappers to read/write the GIC CPU interface for the current CPU */
1279 static MemTxResult
gic_thiscpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1280 unsigned size
, MemTxAttrs attrs
)
1282 GICState
*s
= (GICState
*)opaque
;
1283 return gic_cpu_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1286 static MemTxResult
gic_thiscpu_write(void *opaque
, hwaddr addr
,
1287 uint64_t value
, unsigned size
,
1290 GICState
*s
= (GICState
*)opaque
;
1291 return gic_cpu_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1294 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
1295 * These just decode the opaque pointer into GICState* + cpu id.
1297 static MemTxResult
gic_do_cpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1298 unsigned size
, MemTxAttrs attrs
)
1300 GICState
**backref
= (GICState
**)opaque
;
1301 GICState
*s
= *backref
;
1302 int id
= (backref
- s
->backref
);
1303 return gic_cpu_read(s
, id
, addr
, data
, attrs
);
1306 static MemTxResult
gic_do_cpu_write(void *opaque
, hwaddr addr
,
1307 uint64_t value
, unsigned size
,
1310 GICState
**backref
= (GICState
**)opaque
;
1311 GICState
*s
= *backref
;
1312 int id
= (backref
- s
->backref
);
1313 return gic_cpu_write(s
, id
, addr
, value
, attrs
);
1316 static const MemoryRegionOps gic_ops
[2] = {
1318 .read_with_attrs
= gic_dist_read
,
1319 .write_with_attrs
= gic_dist_write
,
1320 .endianness
= DEVICE_NATIVE_ENDIAN
,
1323 .read_with_attrs
= gic_thiscpu_read
,
1324 .write_with_attrs
= gic_thiscpu_write
,
1325 .endianness
= DEVICE_NATIVE_ENDIAN
,
1329 static const MemoryRegionOps gic_cpu_ops
= {
1330 .read_with_attrs
= gic_do_cpu_read
,
1331 .write_with_attrs
= gic_do_cpu_write
,
1332 .endianness
= DEVICE_NATIVE_ENDIAN
,
1335 /* This function is used by nvic model */
1336 void gic_init_irqs_and_distributor(GICState
*s
)
1338 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1341 static void arm_gic_realize(DeviceState
*dev
, Error
**errp
)
1343 /* Device instance realize function for the GIC sysbus device */
1345 GICState
*s
= ARM_GIC(dev
);
1346 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1347 ARMGICClass
*agc
= ARM_GIC_GET_CLASS(s
);
1348 Error
*local_err
= NULL
;
1350 agc
->parent_realize(dev
, &local_err
);
1352 error_propagate(errp
, local_err
);
1356 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */
1357 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1359 /* Extra core-specific regions for the CPU interfaces. This is
1360 * necessary for "franken-GIC" implementations, for example on
1362 * NB that the memory region size of 0x100 applies for the 11MPCore
1363 * and also cores following the GIC v1 spec (ie A9).
1364 * GIC v2 defines a larger memory region (0x1000) so this will need
1365 * to be extended when we implement A15.
1367 for (i
= 0; i
< s
->num_cpu
; i
++) {
1369 memory_region_init_io(&s
->cpuiomem
[i
+1], OBJECT(s
), &gic_cpu_ops
,
1370 &s
->backref
[i
], "gic_cpu", 0x100);
1371 sysbus_init_mmio(sbd
, &s
->cpuiomem
[i
+1]);
1375 static void arm_gic_class_init(ObjectClass
*klass
, void *data
)
1377 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1378 ARMGICClass
*agc
= ARM_GIC_CLASS(klass
);
1380 agc
->parent_realize
= dc
->realize
;
1381 dc
->realize
= arm_gic_realize
;
1384 static const TypeInfo arm_gic_info
= {
1385 .name
= TYPE_ARM_GIC
,
1386 .parent
= TYPE_ARM_GIC_COMMON
,
1387 .instance_size
= sizeof(GICState
),
1388 .class_init
= arm_gic_class_init
,
1389 .class_size
= sizeof(ARMGICClass
),
1392 static void arm_gic_register_types(void)
1394 type_register_static(&arm_gic_info
);
1397 type_init(arm_gic_register_types
)