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aspeed/smc: remove call to aspeed_smc_update_cs() in reset function
[qemu/ar7.git] / hw / block / m25p80.c
blobe90451496e2ecadfe80a62420b99f73784e16830
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "sysemu/block-backend.h"
27 #include "sysemu/blockdev.h"
28 #include "hw/ssi/ssi.h"
29 #include "qemu/bitops.h"
30 #include "qemu/log.h"
31 #include "qemu/error-report.h"
32 #include "qapi/error.h"
33
34 #ifndef M25P80_ERR_DEBUG
35 #define M25P80_ERR_DEBUG 0
36 #endif
37
38 #define DB_PRINT_L(level, ...) do { \
39 if (M25P80_ERR_DEBUG > (level)) { \
40 fprintf(stderr, ": %s: ", __func__); \
41 fprintf(stderr, ## __VA_ARGS__); \
42 } \
43 } while (0);
44
45 /* Fields for FlashPartInfo->flags */
46
47 /* erase capabilities */
48 #define ER_4K 1
49 #define ER_32K 2
50 /* set to allow the page program command to write 0s back to 1. Useful for
51 * modelling EEPROM with SPI flash command set
52 */
53 #define EEPROM 0x100
54
55 /* 16 MiB max in 3 byte address mode */
56 #define MAX_3BYTES_SIZE 0x1000000
57
58 #define SPI_NOR_MAX_ID_LEN 6
59
60 typedef struct FlashPartInfo {
61 const char *part_name;
62 /*
63 * This array stores the ID bytes.
64 * The first three bytes are the JEDIC ID.
65 * JEDEC ID zero means "no ID" (mostly older chips).
66 */
67 uint8_t id[SPI_NOR_MAX_ID_LEN];
68 uint8_t id_len;
69 /* there is confusion between manufacturers as to what a sector is. In this
70 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
71 * command (opcode 0xd8).
72 */
73 uint32_t sector_size;
74 uint32_t n_sectors;
75 uint32_t page_size;
76 uint16_t flags;
77 /*
78 * Big sized spi nor are often stacked devices, thus sometime
79 * replace chip erase with die erase.
80 * This field inform how many die is in the chip.
81 */
82 uint8_t die_cnt;
83 } FlashPartInfo;
84
85 /* adapted from linux */
86 /* Used when the "_ext_id" is two bytes at most */
87 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
88 .part_name = _part_name,\
89 .id = {\
90 ((_jedec_id) >> 16) & 0xff,\
91 ((_jedec_id) >> 8) & 0xff,\
92 (_jedec_id) & 0xff,\
93 ((_ext_id) >> 8) & 0xff,\
94 (_ext_id) & 0xff,\
95 },\
96 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
97 .sector_size = (_sector_size),\
98 .n_sectors = (_n_sectors),\
99 .page_size = 256,\
100 .flags = (_flags),\
101 .die_cnt = 0
102
103 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
104 .part_name = _part_name,\
105 .id = {\
106 ((_jedec_id) >> 16) & 0xff,\
107 ((_jedec_id) >> 8) & 0xff,\
108 (_jedec_id) & 0xff,\
109 ((_ext_id) >> 16) & 0xff,\
110 ((_ext_id) >> 8) & 0xff,\
111 (_ext_id) & 0xff,\
112 },\
113 .id_len = 6,\
114 .sector_size = (_sector_size),\
115 .n_sectors = (_n_sectors),\
116 .page_size = 256,\
117 .flags = (_flags),\
118 .die_cnt = 0
119
120 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\
121 _flags, _die_cnt)\
122 .part_name = _part_name,\
123 .id = {\
124 ((_jedec_id) >> 16) & 0xff,\
125 ((_jedec_id) >> 8) & 0xff,\
126 (_jedec_id) & 0xff,\
127 ((_ext_id) >> 8) & 0xff,\
128 (_ext_id) & 0xff,\
129 },\
130 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
131 .sector_size = (_sector_size),\
132 .n_sectors = (_n_sectors),\
133 .page_size = 256,\
134 .flags = (_flags),\
135 .die_cnt = _die_cnt
136
137 #define JEDEC_NUMONYX 0x20
138 #define JEDEC_WINBOND 0xEF
139 #define JEDEC_SPANSION 0x01
140
141 /* Numonyx (Micron) Configuration register macros */
142 #define VCFG_DUMMY 0x1
143 #define VCFG_WRAP_SEQUENTIAL 0x2
144 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
145 #define NVCFG_XIP_MODE_MASK (7 << 9)
146 #define VCFG_XIP_MODE_ENABLED (1 << 3)
147 #define CFG_DUMMY_CLK_LEN 4
148 #define NVCFG_DUMMY_CLK_POS 12
149 #define VCFG_DUMMY_CLK_POS 4
150 #define EVCFG_OUT_DRIVER_STRENGHT_DEF 7
151 #define EVCFG_VPP_ACCELERATOR (1 << 3)
152 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
153 #define NVCFG_DUAL_IO_MASK (1 << 2)
154 #define EVCFG_DUAL_IO_ENABLED (1 << 6)
155 #define NVCFG_QUAD_IO_MASK (1 << 3)
156 #define EVCFG_QUAD_IO_ENABLED (1 << 7)
157 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
158 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
159
160 /* Numonyx (Micron) Flag Status Register macros */
161 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
162 #define FSR_FLASH_READY (1 << 7)
163
164 /* Spansion configuration registers macros. */
165 #define SPANSION_QUAD_CFG_POS 0
166 #define SPANSION_QUAD_CFG_LEN 1
167 #define SPANSION_DUMMY_CLK_POS 0
168 #define SPANSION_DUMMY_CLK_LEN 4
169 #define SPANSION_ADDR_LEN_POS 7
170 #define SPANSION_ADDR_LEN_LEN 1
171
172 /*
173 * Spansion read mode command length in bytes,
174 * the mode is currently not supported.
175 */
176
177 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
178 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
179
180 static const FlashPartInfo known_devices[] = {
181 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
182 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
183 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
184
185 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
186 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
187 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
188
189 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
190 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
191 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
192 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
193
194 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
195
196 /* Atmel EEPROMS - it is assumed, that don't care bit in command
197 * is set to 0. Block protection is not supported.
198 */
199 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
200 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
201
202 /* EON -- en25xxx */
203 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
204 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
205 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
206 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
207 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
208
209 /* GigaDevice */
210 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
211 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
212
213 /* Intel/Numonyx -- xxxs33b */
214 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
215 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
216 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
217 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
218
219 /* Macronix */
220 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
221 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
222 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
223 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
224 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
225 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
226 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
227 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
228 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
229 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
230 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
231 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
232 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
233
234 /* Micron */
235 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
236 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
237 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
238 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
239 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
240 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
241 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
242 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
243 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
244 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
245 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
246 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
247 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
248 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
249 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
250
251 /* Spansion -- single (large) sector size only, at least
252 * for the chips listed here (without boot sectors).
253 */
254 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
255 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
256 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
257 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
258 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
259 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
260 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
261 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
262 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
263 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
264 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
265 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
266 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
267 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
268 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
269 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
270 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
271
272 /* Spansion -- boot sectors support */
273 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
274 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
275
276 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
277 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
278 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
279 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
280 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
281 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
282 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
283 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
284 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
285 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
286
287 /* ST Microelectronics -- newer production may have feature updates */
288 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
289 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
290 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
291 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
292 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
293 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
294 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
295 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
296 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
297 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
298
299 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
300 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
301 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
302
303 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
304 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
305 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
306
307 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
308 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
309 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
310 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
311
312 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
313 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
314 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
315 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
316 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
317 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
318 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
319 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
320 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
321 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
322 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
323 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
324 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
325 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
326 };
327
328 typedef enum {
329 NOP = 0,
330 WRSR = 0x1,
331 WRDI = 0x4,
332 RDSR = 0x5,
333 WREN = 0x6,
334 JEDEC_READ = 0x9f,
335 BULK_ERASE = 0xc7,
336 READ_FSR = 0x70,
337 RDCR = 0x15,
338
339 READ = 0x03,
340 READ4 = 0x13,
341 FAST_READ = 0x0b,
342 FAST_READ4 = 0x0c,
343 DOR = 0x3b,
344 DOR4 = 0x3c,
345 QOR = 0x6b,
346 QOR4 = 0x6c,
347 DIOR = 0xbb,
348 DIOR4 = 0xbc,
349 QIOR = 0xeb,
350 QIOR4 = 0xec,
351
352 PP = 0x02,
353 PP4 = 0x12,
354 PP4_4 = 0x3e,
355 DPP = 0xa2,
356 QPP = 0x32,
357 QPP_4 = 0x34,
358
359 ERASE_4K = 0x20,
360 ERASE4_4K = 0x21,
361 ERASE_32K = 0x52,
362 ERASE4_32K = 0x5c,
363 ERASE_SECTOR = 0xd8,
364 ERASE4_SECTOR = 0xdc,
365
366 EN_4BYTE_ADDR = 0xB7,
367 EX_4BYTE_ADDR = 0xE9,
368
369 EXTEND_ADDR_READ = 0xC8,
370 EXTEND_ADDR_WRITE = 0xC5,
371
372 RESET_ENABLE = 0x66,
373 RESET_MEMORY = 0x99,
374
375 /*
376 * Micron: 0x35 - enable QPI
377 * Spansion: 0x35 - read control register
378 */
379 RDCR_EQIO = 0x35,
380 RSTQIO = 0xf5,
381
382 RNVCR = 0xB5,
383 WNVCR = 0xB1,
384
385 RVCR = 0x85,
386 WVCR = 0x81,
387
388 REVCR = 0x65,
389 WEVCR = 0x61,
390
391 DIE_ERASE = 0xC4,
392 } FlashCMD;
393
394 typedef enum {
395 STATE_IDLE,
396 STATE_PAGE_PROGRAM,
397 STATE_READ,
398 STATE_COLLECTING_DATA,
399 STATE_COLLECTING_VAR_LEN_DATA,
400 STATE_READING_DATA,
401 } CMDState;
402
403 typedef enum {
404 MAN_SPANSION,
405 MAN_MACRONIX,
406 MAN_NUMONYX,
407 MAN_WINBOND,
408 MAN_GENERIC,
409 } Manufacturer;
410
411 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16
412
413 typedef struct Flash {
414 SSISlave parent_obj;
415
416 BlockBackend *blk;
417
418 uint8_t *storage;
419 uint32_t size;
420 int page_size;
421
422 uint8_t state;
423 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ];
424 uint32_t len;
425 uint32_t pos;
426 uint8_t needed_bytes;
427 uint8_t cmd_in_progress;
428 uint32_t cur_addr;
429 uint32_t nonvolatile_cfg;
430 /* Configuration register for Macronix */
431 uint32_t volatile_cfg;
432 uint32_t enh_volatile_cfg;
433 /* Spansion cfg registers. */
434 uint8_t spansion_cr1nv;
435 uint8_t spansion_cr2nv;
436 uint8_t spansion_cr3nv;
437 uint8_t spansion_cr4nv;
438 uint8_t spansion_cr1v;
439 uint8_t spansion_cr2v;
440 uint8_t spansion_cr3v;
441 uint8_t spansion_cr4v;
442 bool write_enable;
443 bool four_bytes_address_mode;
444 bool reset_enable;
445 bool quad_enable;
446 uint8_t ear;
447
448 int64_t dirty_page;
449
450 const FlashPartInfo *pi;
451
452 } Flash;
453
454 typedef struct M25P80Class {
455 SSISlaveClass parent_class;
456 FlashPartInfo *pi;
457 } M25P80Class;
458
459 #define TYPE_M25P80 "m25p80-generic"
460 #define M25P80(obj) \
461 OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
462 #define M25P80_CLASS(klass) \
463 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
464 #define M25P80_GET_CLASS(obj) \
465 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
466
467 static inline Manufacturer get_man(Flash *s)
468 {
469 switch (s->pi->id[0]) {
470 case 0x20:
471 return MAN_NUMONYX;
472 case 0xEF:
473 return MAN_WINBOND;
474 case 0x01:
475 return MAN_SPANSION;
476 case 0xC2:
477 return MAN_MACRONIX;
478 default:
479 return MAN_GENERIC;
480 }
481 }
482
483 static void blk_sync_complete(void *opaque, int ret)
484 {
485 QEMUIOVector *iov = opaque;
486
487 qemu_iovec_destroy(iov);
488 g_free(iov);
489
490 /* do nothing. Masters do not directly interact with the backing store,
491 * only the working copy so no mutexing required.
492 */
493 }
494
495 static void flash_sync_page(Flash *s, int page)
496 {
497 QEMUIOVector *iov;
498
499 if (!s->blk || blk_is_read_only(s->blk)) {
500 return;
501 }
502
503 iov = g_new(QEMUIOVector, 1);
504 qemu_iovec_init(iov, 1);
505 qemu_iovec_add(iov, s->storage + page * s->pi->page_size,
506 s->pi->page_size);
507 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0,
508 blk_sync_complete, iov);
509 }
510
511 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
512 {
513 QEMUIOVector *iov;
514
515 if (!s->blk || blk_is_read_only(s->blk)) {
516 return;
517 }
518
519 assert(!(len % BDRV_SECTOR_SIZE));
520 iov = g_new(QEMUIOVector, 1);
521 qemu_iovec_init(iov, 1);
522 qemu_iovec_add(iov, s->storage + off, len);
523 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov);
524 }
525
526 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
527 {
528 uint32_t len;
529 uint8_t capa_to_assert = 0;
530
531 switch (cmd) {
532 case ERASE_4K:
533 case ERASE4_4K:
534 len = 4 << 10;
535 capa_to_assert = ER_4K;
536 break;
537 case ERASE_32K:
538 case ERASE4_32K:
539 len = 32 << 10;
540 capa_to_assert = ER_32K;
541 break;
542 case ERASE_SECTOR:
543 case ERASE4_SECTOR:
544 len = s->pi->sector_size;
545 break;
546 case BULK_ERASE:
547 len = s->size;
548 break;
549 case DIE_ERASE:
550 if (s->pi->die_cnt) {
551 len = s->size / s->pi->die_cnt;
552 offset = offset & (~(len - 1));
553 } else {
554 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported"
555 " by device\n");
556 return;
557 }
558 break;
559 default:
560 abort();
561 }
562
563 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
564 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
565 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
566 " device\n", len);
567 }
568
569 if (!s->write_enable) {
570 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
571 return;
572 }
573 memset(s->storage + offset, 0xff, len);
574 flash_sync_area(s, offset, len);
575 }
576
577 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
578 {
579 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
580 flash_sync_page(s, s->dirty_page);
581 s->dirty_page = newpage;
582 }
583 }
584
585 static inline
586 void flash_write8(Flash *s, uint32_t addr, uint8_t data)
587 {
588 uint32_t page = addr / s->pi->page_size;
589 uint8_t prev = s->storage[s->cur_addr];
590
591 if (!s->write_enable) {
592 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
593 }
594
595 if ((prev ^ data) & data) {
596 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 " %" PRIx8
597 " -> %" PRIx8 "\n", addr, prev, data);
598 }
599
600 if (s->pi->flags & EEPROM) {
601 s->storage[s->cur_addr] = data;
602 } else {
603 s->storage[s->cur_addr] &= data;
604 }
605
606 flash_sync_dirty(s, page);
607 s->dirty_page = page;
608 }
609
610 static inline int get_addr_length(Flash *s)
611 {
612 /* check if eeprom is in use */
613 if (s->pi->flags == EEPROM) {
614 return 2;
615 }
616
617 switch (s->cmd_in_progress) {
618 case PP4:
619 case PP4_4:
620 case QPP_4:
621 case READ4:
622 case QIOR4:
623 case ERASE4_4K:
624 case ERASE4_32K:
625 case ERASE4_SECTOR:
626 case FAST_READ4:
627 case DOR4:
628 case QOR4:
629 case DIOR4:
630 return 4;
631 default:
632 return s->four_bytes_address_mode ? 4 : 3;
633 }
634 }
635
636 static void complete_collecting_data(Flash *s)
637 {
638 int i, n;
639
640 n = get_addr_length(s);
641 s->cur_addr = (n == 3 ? s->ear : 0);
642 for (i = 0; i < n; ++i) {
643 s->cur_addr <<= 8;
644 s->cur_addr |= s->data[i];
645 }
646
647 s->cur_addr &= s->size - 1;
648
649 s->state = STATE_IDLE;
650
651 switch (s->cmd_in_progress) {
652 case DPP:
653 case QPP:
654 case QPP_4:
655 case PP:
656 case PP4:
657 case PP4_4:
658 s->state = STATE_PAGE_PROGRAM;
659 break;
660 case READ:
661 case READ4:
662 case FAST_READ:
663 case FAST_READ4:
664 case DOR:
665 case DOR4:
666 case QOR:
667 case QOR4:
668 case DIOR:
669 case DIOR4:
670 case QIOR:
671 case QIOR4:
672 s->state = STATE_READ;
673 break;
674 case ERASE_4K:
675 case ERASE4_4K:
676 case ERASE_32K:
677 case ERASE4_32K:
678 case ERASE_SECTOR:
679 case ERASE4_SECTOR:
680 case DIE_ERASE:
681 flash_erase(s, s->cur_addr, s->cmd_in_progress);
682 break;
683 case WRSR:
684 switch (get_man(s)) {
685 case MAN_SPANSION:
686 s->quad_enable = !!(s->data[1] & 0x02);
687 break;
688 case MAN_MACRONIX:
689 s->quad_enable = extract32(s->data[0], 6, 1);
690 if (s->len > 1) {
691 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
692 }
693 break;
694 default:
695 break;
696 }
697 if (s->write_enable) {
698 s->write_enable = false;
699 }
700 break;
701 case EXTEND_ADDR_WRITE:
702 s->ear = s->data[0];
703 break;
704 case WNVCR:
705 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
706 break;
707 case WVCR:
708 s->volatile_cfg = s->data[0];
709 break;
710 case WEVCR:
711 s->enh_volatile_cfg = s->data[0];
712 break;
713 default:
714 break;
715 }
716 }
717
718 static void reset_memory(Flash *s)
719 {
720 s->cmd_in_progress = NOP;
721 s->cur_addr = 0;
722 s->ear = 0;
723 s->four_bytes_address_mode = false;
724 s->len = 0;
725 s->needed_bytes = 0;
726 s->pos = 0;
727 s->state = STATE_IDLE;
728 s->write_enable = false;
729 s->reset_enable = false;
730 s->quad_enable = false;
731
732 switch (get_man(s)) {
733 case MAN_NUMONYX:
734 s->volatile_cfg = 0;
735 s->volatile_cfg |= VCFG_DUMMY;
736 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
737 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
738 != NVCFG_XIP_MODE_DISABLED) {
739 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED;
740 }
741 s->volatile_cfg |= deposit32(s->volatile_cfg,
742 VCFG_DUMMY_CLK_POS,
743 CFG_DUMMY_CLK_LEN,
744 extract32(s->nonvolatile_cfg,
745 NVCFG_DUMMY_CLK_POS,
746 CFG_DUMMY_CLK_LEN)
747 );
748
749 s->enh_volatile_cfg = 0;
750 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGHT_DEF;
751 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
752 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
753 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
754 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
755 }
756 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
757 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
758 }
759 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
760 s->four_bytes_address_mode = true;
761 }
762 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
763 s->ear = s->size / MAX_3BYTES_SIZE - 1;
764 }
765 break;
766 case MAN_MACRONIX:
767 s->volatile_cfg = 0x7;
768 break;
769 case MAN_SPANSION:
770 s->spansion_cr1v = s->spansion_cr1nv;
771 s->spansion_cr2v = s->spansion_cr2nv;
772 s->spansion_cr3v = s->spansion_cr3nv;
773 s->spansion_cr4v = s->spansion_cr4nv;
774 s->quad_enable = extract32(s->spansion_cr1v,
775 SPANSION_QUAD_CFG_POS,
776 SPANSION_QUAD_CFG_LEN
777 );
778 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
779 SPANSION_ADDR_LEN_POS,
780 SPANSION_ADDR_LEN_LEN
781 );
782 break;
783 default:
784 break;
785 }
786
787 DB_PRINT_L(0, "Reset done.\n");
788 }
789
790 static void decode_fast_read_cmd(Flash *s)
791 {
792 s->needed_bytes = get_addr_length(s);
793 switch (get_man(s)) {
794 /* Dummy cycles - modeled with bytes writes instead of bits */
795 case MAN_WINBOND:
796 s->needed_bytes += 8;
797 break;
798 case MAN_NUMONYX:
799 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
800 break;
801 case MAN_MACRONIX:
802 if (extract32(s->volatile_cfg, 6, 2) == 1) {
803 s->needed_bytes += 6;
804 } else {
805 s->needed_bytes += 8;
806 }
807 break;
808 case MAN_SPANSION:
809 s->needed_bytes += extract32(s->spansion_cr2v,
810 SPANSION_DUMMY_CLK_POS,
811 SPANSION_DUMMY_CLK_LEN
812 );
813 break;
814 default:
815 break;
816 }
817 s->pos = 0;
818 s->len = 0;
819 s->state = STATE_COLLECTING_DATA;
820 }
821
822 static void decode_dio_read_cmd(Flash *s)
823 {
824 s->needed_bytes = get_addr_length(s);
825 /* Dummy cycles modeled with bytes writes instead of bits */
826 switch (get_man(s)) {
827 case MAN_WINBOND:
828 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
829 break;
830 case MAN_SPANSION:
831 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
832 s->needed_bytes += extract32(s->spansion_cr2v,
833 SPANSION_DUMMY_CLK_POS,
834 SPANSION_DUMMY_CLK_LEN
835 );
836 break;
837 case MAN_NUMONYX:
838 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
839 break;
840 case MAN_MACRONIX:
841 switch (extract32(s->volatile_cfg, 6, 2)) {
842 case 1:
843 s->needed_bytes += 6;
844 break;
845 case 2:
846 s->needed_bytes += 8;
847 break;
848 default:
849 s->needed_bytes += 4;
850 break;
851 }
852 break;
853 default:
854 break;
855 }
856 s->pos = 0;
857 s->len = 0;
858 s->state = STATE_COLLECTING_DATA;
859 }
860
861 static void decode_qio_read_cmd(Flash *s)
862 {
863 s->needed_bytes = get_addr_length(s);
864 /* Dummy cycles modeled with bytes writes instead of bits */
865 switch (get_man(s)) {
866 case MAN_WINBOND:
867 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
868 s->needed_bytes += 4;
869 break;
870 case MAN_SPANSION:
871 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
872 s->needed_bytes += extract32(s->spansion_cr2v,
873 SPANSION_DUMMY_CLK_POS,
874 SPANSION_DUMMY_CLK_LEN
875 );
876 break;
877 case MAN_NUMONYX:
878 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
879 break;
880 case MAN_MACRONIX:
881 switch (extract32(s->volatile_cfg, 6, 2)) {
882 case 1:
883 s->needed_bytes += 4;
884 break;
885 case 2:
886 s->needed_bytes += 8;
887 break;
888 default:
889 s->needed_bytes += 6;
890 break;
891 }
892 break;
893 default:
894 break;
895 }
896 s->pos = 0;
897 s->len = 0;
898 s->state = STATE_COLLECTING_DATA;
899 }
900
901 static void decode_new_cmd(Flash *s, uint32_t value)
902 {
903 s->cmd_in_progress = value;
904 int i;
905 DB_PRINT_L(0, "decoded new command:%x\n", value);
906
907 if (value != RESET_MEMORY) {
908 s->reset_enable = false;
909 }
910
911 switch (value) {
912
913 case ERASE_4K:
914 case ERASE4_4K:
915 case ERASE_32K:
916 case ERASE4_32K:
917 case ERASE_SECTOR:
918 case ERASE4_SECTOR:
919 case READ:
920 case READ4:
921 case DPP:
922 case QPP:
923 case QPP_4:
924 case PP:
925 case PP4:
926 case PP4_4:
927 case DIE_ERASE:
928 s->needed_bytes = get_addr_length(s);
929 s->pos = 0;
930 s->len = 0;
931 s->state = STATE_COLLECTING_DATA;
932 break;
933
934 case FAST_READ:
935 case FAST_READ4:
936 case DOR:
937 case DOR4:
938 case QOR:
939 case QOR4:
940 decode_fast_read_cmd(s);
941 break;
942
943 case DIOR:
944 case DIOR4:
945 decode_dio_read_cmd(s);
946 break;
947
948 case QIOR:
949 case QIOR4:
950 decode_qio_read_cmd(s);
951 break;
952
953 case WRSR:
954 if (s->write_enable) {
955 switch (get_man(s)) {
956 case MAN_SPANSION:
957 s->needed_bytes = 2;
958 s->state = STATE_COLLECTING_DATA;
959 break;
960 case MAN_MACRONIX:
961 s->needed_bytes = 2;
962 s->state = STATE_COLLECTING_VAR_LEN_DATA;
963 break;
964 default:
965 s->needed_bytes = 1;
966 s->state = STATE_COLLECTING_DATA;
967 }
968 s->pos = 0;
969 }
970 break;
971
972 case WRDI:
973 s->write_enable = false;
974 break;
975 case WREN:
976 s->write_enable = true;
977 break;
978
979 case RDSR:
980 s->data[0] = (!!s->write_enable) << 1;
981 if (get_man(s) == MAN_MACRONIX) {
982 s->data[0] |= (!!s->quad_enable) << 6;
983 }
984 s->pos = 0;
985 s->len = 1;
986 s->state = STATE_READING_DATA;
987 break;
988
989 case READ_FSR:
990 s->data[0] = FSR_FLASH_READY;
991 if (s->four_bytes_address_mode) {
992 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
993 }
994 s->pos = 0;
995 s->len = 1;
996 s->state = STATE_READING_DATA;
997 break;
998
999 case JEDEC_READ:
1000 DB_PRINT_L(0, "populated jedec code\n");
1001 for (i = 0; i < s->pi->id_len; i++) {
1002 s->data[i] = s->pi->id[i];
1003 }
1004
1005 s->len = s->pi->id_len;
1006 s->pos = 0;
1007 s->state = STATE_READING_DATA;
1008 break;
1009
1010 case RDCR:
1011 s->data[0] = s->volatile_cfg & 0xFF;
1012 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
1013 s->pos = 0;
1014 s->len = 1;
1015 s->state = STATE_READING_DATA;
1016 break;
1017
1018 case BULK_ERASE:
1019 if (s->write_enable) {
1020 DB_PRINT_L(0, "chip erase\n");
1021 flash_erase(s, 0, BULK_ERASE);
1022 } else {
1023 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
1024 "protect!\n");
1025 }
1026 break;
1027 case NOP:
1028 break;
1029 case EN_4BYTE_ADDR:
1030 s->four_bytes_address_mode = true;
1031 break;
1032 case EX_4BYTE_ADDR:
1033 s->four_bytes_address_mode = false;
1034 break;
1035 case EXTEND_ADDR_READ:
1036 s->data[0] = s->ear;
1037 s->pos = 0;
1038 s->len = 1;
1039 s->state = STATE_READING_DATA;
1040 break;
1041 case EXTEND_ADDR_WRITE:
1042 if (s->write_enable) {
1043 s->needed_bytes = 1;
1044 s->pos = 0;
1045 s->len = 0;
1046 s->state = STATE_COLLECTING_DATA;
1047 }
1048 break;
1049 case RNVCR:
1050 s->data[0] = s->nonvolatile_cfg & 0xFF;
1051 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
1052 s->pos = 0;
1053 s->len = 2;
1054 s->state = STATE_READING_DATA;
1055 break;
1056 case WNVCR:
1057 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1058 s->needed_bytes = 2;
1059 s->pos = 0;
1060 s->len = 0;
1061 s->state = STATE_COLLECTING_DATA;
1062 }
1063 break;
1064 case RVCR:
1065 s->data[0] = s->volatile_cfg & 0xFF;
1066 s->pos = 0;
1067 s->len = 1;
1068 s->state = STATE_READING_DATA;
1069 break;
1070 case WVCR:
1071 if (s->write_enable) {
1072 s->needed_bytes = 1;
1073 s->pos = 0;
1074 s->len = 0;
1075 s->state = STATE_COLLECTING_DATA;
1076 }
1077 break;
1078 case REVCR:
1079 s->data[0] = s->enh_volatile_cfg & 0xFF;
1080 s->pos = 0;
1081 s->len = 1;
1082 s->state = STATE_READING_DATA;
1083 break;
1084 case WEVCR:
1085 if (s->write_enable) {
1086 s->needed_bytes = 1;
1087 s->pos = 0;
1088 s->len = 0;
1089 s->state = STATE_COLLECTING_DATA;
1090 }
1091 break;
1092 case RESET_ENABLE:
1093 s->reset_enable = true;
1094 break;
1095 case RESET_MEMORY:
1096 if (s->reset_enable) {
1097 reset_memory(s);
1098 }
1099 break;
1100 case RDCR_EQIO:
1101 switch (get_man(s)) {
1102 case MAN_SPANSION:
1103 s->data[0] = (!!s->quad_enable) << 1;
1104 s->pos = 0;
1105 s->len = 1;
1106 s->state = STATE_READING_DATA;
1107 break;
1108 case MAN_MACRONIX:
1109 s->quad_enable = true;
1110 break;
1111 default:
1112 break;
1113 }
1114 break;
1115 case RSTQIO:
1116 s->quad_enable = false;
1117 break;
1118 default:
1119 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1120 break;
1121 }
1122 }
1123
1124 static int m25p80_cs(SSISlave *ss, bool select)
1125 {
1126 Flash *s = M25P80(ss);
1127
1128 if (select) {
1129 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1130 complete_collecting_data(s);
1131 }
1132 s->len = 0;
1133 s->pos = 0;
1134 s->state = STATE_IDLE;
1135 flash_sync_dirty(s, -1);
1136 }
1137
1138 DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
1139
1140 return 0;
1141 }
1142
1143 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
1144 {
1145 Flash *s = M25P80(ss);
1146 uint32_t r = 0;
1147
1148 switch (s->state) {
1149
1150 case STATE_PAGE_PROGRAM:
1151 DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n",
1152 s->cur_addr, (uint8_t)tx);
1153 flash_write8(s, s->cur_addr, (uint8_t)tx);
1154 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1155 break;
1156
1157 case STATE_READ:
1158 r = s->storage[s->cur_addr];
1159 DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr,
1160 (uint8_t)r);
1161 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1162 break;
1163
1164 case STATE_COLLECTING_DATA:
1165 case STATE_COLLECTING_VAR_LEN_DATA:
1166
1167 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1168 qemu_log_mask(LOG_GUEST_ERROR,
1169 "M25P80: Write overrun internal data buffer. "
1170 "SPI controller (QEMU emulator or guest driver) "
1171 "is misbehaving\n");
1172 s->len = s->pos = 0;
1173 s->state = STATE_IDLE;
1174 break;
1175 }
1176
1177 s->data[s->len] = (uint8_t)tx;
1178 s->len++;
1179
1180 if (s->len == s->needed_bytes) {
1181 complete_collecting_data(s);
1182 }
1183 break;
1184
1185 case STATE_READING_DATA:
1186
1187 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1188 qemu_log_mask(LOG_GUEST_ERROR,
1189 "M25P80: Read overrun internal data buffer. "
1190 "SPI controller (QEMU emulator or guest driver) "
1191 "is misbehaving\n");
1192 s->len = s->pos = 0;
1193 s->state = STATE_IDLE;
1194 break;
1195 }
1196
1197 r = s->data[s->pos];
1198 s->pos++;
1199 if (s->pos == s->len) {
1200 s->pos = 0;
1201 s->state = STATE_IDLE;
1202 }
1203 break;
1204
1205 default:
1206 case STATE_IDLE:
1207 decode_new_cmd(s, (uint8_t)tx);
1208 break;
1209 }
1210
1211 return r;
1212 }
1213
1214 static void m25p80_realize(SSISlave *ss, Error **errp)
1215 {
1216 Flash *s = M25P80(ss);
1217 M25P80Class *mc = M25P80_GET_CLASS(s);
1218
1219 s->pi = mc->pi;
1220
1221 s->size = s->pi->sector_size * s->pi->n_sectors;
1222 s->dirty_page = -1;
1223
1224 if (s->blk) {
1225 DB_PRINT_L(0, "Binding to IF_MTD drive\n");
1226 s->storage = blk_blockalign(s->blk, s->size);
1227
1228 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
1229 error_setg(errp, "failed to read the initial flash content");
1230 return;
1231 }
1232 } else {
1233 DB_PRINT_L(0, "No BDRV - binding to RAM\n");
1234 s->storage = blk_blockalign(NULL, s->size);
1235 memset(s->storage, 0xFF, s->size);
1236 }
1237 }
1238
1239 static void m25p80_reset(DeviceState *d)
1240 {
1241 Flash *s = M25P80(d);
1242
1243 reset_memory(s);
1244 }
1245
1246 static void m25p80_pre_save(void *opaque)
1247 {
1248 flash_sync_dirty((Flash *)opaque, -1);
1249 }
1250
1251 static Property m25p80_properties[] = {
1252 /* This is default value for Micron flash */
1253 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1254 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1255 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1256 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1257 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1258 DEFINE_PROP_DRIVE("drive", Flash, blk),
1259 DEFINE_PROP_END_OF_LIST(),
1260 };
1261
1262 static const VMStateDescription vmstate_m25p80 = {
1263 .name = "m25p80",
1264 .version_id = 0,
1265 .minimum_version_id = 0,
1266 .pre_save = m25p80_pre_save,
1267 .fields = (VMStateField[]) {
1268 VMSTATE_UINT8(state, Flash),
1269 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ),
1270 VMSTATE_UINT32(len, Flash),
1271 VMSTATE_UINT32(pos, Flash),
1272 VMSTATE_UINT8(needed_bytes, Flash),
1273 VMSTATE_UINT8(cmd_in_progress, Flash),
1274 VMSTATE_UINT32(cur_addr, Flash),
1275 VMSTATE_BOOL(write_enable, Flash),
1276 VMSTATE_BOOL(reset_enable, Flash),
1277 VMSTATE_UINT8(ear, Flash),
1278 VMSTATE_BOOL(four_bytes_address_mode, Flash),
1279 VMSTATE_UINT32(nonvolatile_cfg, Flash),
1280 VMSTATE_UINT32(volatile_cfg, Flash),
1281 VMSTATE_UINT32(enh_volatile_cfg, Flash),
1282 VMSTATE_BOOL(quad_enable, Flash),
1283 VMSTATE_UINT8(spansion_cr1nv, Flash),
1284 VMSTATE_UINT8(spansion_cr2nv, Flash),
1285 VMSTATE_UINT8(spansion_cr3nv, Flash),
1286 VMSTATE_UINT8(spansion_cr4nv, Flash),
1287 VMSTATE_END_OF_LIST()
1288 }
1289 };
1290
1291 static void m25p80_class_init(ObjectClass *klass, void *data)
1292 {
1293 DeviceClass *dc = DEVICE_CLASS(klass);
1294 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
1295 M25P80Class *mc = M25P80_CLASS(klass);
1296
1297 k->realize = m25p80_realize;
1298 k->transfer = m25p80_transfer8;
1299 k->set_cs = m25p80_cs;
1300 k->cs_polarity = SSI_CS_LOW;
1301 dc->vmsd = &vmstate_m25p80;
1302 dc->props = m25p80_properties;
1303 dc->reset = m25p80_reset;
1304 mc->pi = data;
1305 }
1306
1307 static const TypeInfo m25p80_info = {
1308 .name = TYPE_M25P80,
1309 .parent = TYPE_SSI_SLAVE,
1310 .instance_size = sizeof(Flash),
1311 .class_size = sizeof(M25P80Class),
1312 .abstract = true,
1313 };
1314
1315 static void m25p80_register_types(void)
1316 {
1317 int i;
1318
1319 type_register_static(&m25p80_info);
1320 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1321 TypeInfo ti = {
1322 .name = known_devices[i].part_name,
1323 .parent = TYPE_M25P80,
1324 .class_init = m25p80_class_init,
1325 .class_data = (void *)&known_devices[i],
1326 };
1327 type_register(&ti);
1328 }
1329 }
1330
1331 type_init(m25p80_register_types)
AR7 emulation for QEMU