2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu/units.h"
33 #include "qapi/error.h"
34 #include "hw/sysbus.h"
35 #include "hw/arm/arm.h"
36 #include "hw/arm/primecell.h"
37 #include "hw/arm/virt.h"
38 #include "hw/block/flash.h"
39 #include "hw/vfio/vfio-calxeda-xgmac.h"
40 #include "hw/vfio/vfio-amd-xgbe.h"
41 #include "hw/display/ramfb.h"
43 #include "sysemu/device_tree.h"
44 #include "sysemu/numa.h"
45 #include "sysemu/sysemu.h"
46 #include "sysemu/kvm.h"
47 #include "hw/loader.h"
48 #include "exec/address-spaces.h"
49 #include "qemu/bitops.h"
50 #include "qemu/error-report.h"
51 #include "hw/pci-host/gpex.h"
52 #include "hw/arm/sysbus-fdt.h"
53 #include "hw/platform-bus.h"
54 #include "hw/arm/fdt.h"
55 #include "hw/intc/arm_gic.h"
56 #include "hw/intc/arm_gicv3_common.h"
58 #include "hw/firmware/smbios.h"
59 #include "qapi/visitor.h"
60 #include "standard-headers/linux/input.h"
61 #include "hw/arm/smmuv3.h"
62 #include "hw/acpi/acpi.h"
63 #include "target/arm/internals.h"
65 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
66 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
69 MachineClass *mc = MACHINE_CLASS(oc); \
70 virt_machine_##major##_##minor##_options(mc); \
71 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
76 static const TypeInfo machvirt_##major##_##minor##_info = { \
77 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
78 .parent = TYPE_VIRT_MACHINE, \
79 .class_init = virt_##major##_##minor##_class_init, \
81 static void machvirt_machine_##major##_##minor##_init(void) \
83 type_register_static(&machvirt_##major##_##minor##_info); \
85 type_init(machvirt_machine_##major##_##minor##_init);
87 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
88 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
89 #define DEFINE_VIRT_MACHINE(major, minor) \
90 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
93 /* Number of external interrupt lines to configure the GIC with */
96 #define PLATFORM_BUS_NUM_IRQS 64
98 /* Legacy RAM limit in GB (< version 4.0) */
99 #define LEGACY_RAMLIMIT_GB 255
100 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
102 /* Addresses and sizes of our components.
103 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
104 * 128MB..256MB is used for miscellaneous device I/O.
105 * 256MB..1GB is reserved for possible future PCI support (ie where the
106 * PCI memory window will go if we add a PCI host controller).
107 * 1GB and up is RAM (which may happily spill over into the
108 * high memory region beyond 4GB).
109 * This represents a compromise between how much RAM can be given to
110 * a 32 bit VM and leaving space for expansion and in particular for PCI.
111 * Note that devices should generally be placed at multiples of 0x10000,
112 * to accommodate guests using 64K pages.
114 static const MemMapEntry base_memmap
[] = {
115 /* Space up to 0x8000000 is reserved for a boot ROM */
116 [VIRT_FLASH
] = { 0, 0x08000000 },
117 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
118 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
119 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
120 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
121 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
122 [VIRT_GIC_HYP
] = { 0x08030000, 0x00010000 },
123 [VIRT_GIC_VCPU
] = { 0x08040000, 0x00010000 },
124 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
125 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
126 /* This redistributor space allows up to 2*64kB*123 CPUs */
127 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
128 [VIRT_UART
] = { 0x09000000, 0x00001000 },
129 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
130 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
131 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
132 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
133 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
134 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
135 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
136 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
137 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
138 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
139 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
140 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
141 /* Actual RAM size depends on initial RAM and device memory settings */
142 [VIRT_MEM
] = { GiB
, LEGACY_RAMLIMIT_BYTES
},
146 * Highmem IO Regions: This memory map is floating, located after the RAM.
147 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
148 * top of the RAM, so that its base get the same alignment as the size,
149 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
150 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
151 * Note the extended_memmap is sized so that it eventually also includes the
152 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
153 * index of base_memmap).
155 static MemMapEntry extended_memmap
[] = {
156 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
157 [VIRT_HIGH_GIC_REDIST2
] = { 0x0, 64 * MiB
},
158 [VIRT_HIGH_PCIE_ECAM
] = { 0x0, 256 * MiB
},
159 /* Second PCIe window */
160 [VIRT_HIGH_PCIE_MMIO
] = { 0x0, 512 * GiB
},
163 static const int a15irqmap
[] = {
166 [VIRT_PCIE
] = 3, /* ... to 6 */
168 [VIRT_SECURE_UART
] = 8,
169 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
170 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
171 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
172 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
175 static const char *valid_cpus
[] = {
176 ARM_CPU_TYPE_NAME("cortex-a15"),
177 ARM_CPU_TYPE_NAME("cortex-a53"),
178 ARM_CPU_TYPE_NAME("cortex-a57"),
179 ARM_CPU_TYPE_NAME("cortex-a72"),
180 ARM_CPU_TYPE_NAME("host"),
181 ARM_CPU_TYPE_NAME("max"),
184 static bool cpu_type_valid(const char *cpu
)
188 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
189 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
196 static void create_fdt(VirtMachineState
*vms
)
198 void *fdt
= create_device_tree(&vms
->fdt_size
);
201 error_report("create_device_tree() failed");
208 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
209 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
210 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
212 /* /chosen must exist for load_dtb to fill in necessary properties later */
213 qemu_fdt_add_subnode(fdt
, "/chosen");
215 /* Clock node, for the benefit of the UART. The kernel device tree
216 * binding documentation claims the PL011 node clock properties are
217 * optional but in practice if you omit them the kernel refuses to
218 * probe for the device.
220 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
221 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
222 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
223 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
224 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
225 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
227 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
229 if (have_numa_distance
) {
230 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
231 uint32_t *matrix
= g_malloc0(size
);
234 for (i
= 0; i
< nb_numa_nodes
; i
++) {
235 for (j
= 0; j
< nb_numa_nodes
; j
++) {
236 idx
= (i
* nb_numa_nodes
+ j
) * 3;
237 matrix
[idx
+ 0] = cpu_to_be32(i
);
238 matrix
[idx
+ 1] = cpu_to_be32(j
);
239 matrix
[idx
+ 2] = cpu_to_be32(numa_info
[i
].distance
[j
]);
243 qemu_fdt_add_subnode(fdt
, "/distance-map");
244 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
245 "numa-distance-map-v1");
246 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
252 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
254 /* On real hardware these interrupts are level-triggered.
255 * On KVM they were edge-triggered before host kernel version 4.4,
256 * and level-triggered afterwards.
257 * On emulated QEMU they are level-triggered.
259 * Getting the DTB info about them wrong is awkward for some
261 * pre-4.8 ignore the DT and leave the interrupt configured
262 * with whatever the GIC reset value (or the bootloader) left it at
263 * 4.8 before rc6 honour the incorrect data by programming it back
264 * into the GIC, causing problems
265 * 4.8rc6 and later ignore the DT and always write "level triggered"
268 * For backwards-compatibility, virt-2.8 and earlier will continue
269 * to say these are edge-triggered, but later machines will report
270 * the correct information.
273 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
274 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
276 if (vmc
->claim_edge_triggered_timers
) {
277 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
280 if (vms
->gic_version
== 2) {
281 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
282 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
283 (1 << vms
->smp_cpus
) - 1);
286 qemu_fdt_add_subnode(vms
->fdt
, "/timer");
288 armcpu
= ARM_CPU(qemu_get_cpu(0));
289 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
290 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
291 qemu_fdt_setprop(vms
->fdt
, "/timer", "compatible",
292 compat
, sizeof(compat
));
294 qemu_fdt_setprop_string(vms
->fdt
, "/timer", "compatible",
297 qemu_fdt_setprop(vms
->fdt
, "/timer", "always-on", NULL
, 0);
298 qemu_fdt_setprop_cells(vms
->fdt
, "/timer", "interrupts",
299 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
300 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
301 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
302 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
305 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
309 const MachineState
*ms
= MACHINE(vms
);
312 * From Documentation/devicetree/bindings/arm/cpus.txt
313 * On ARM v8 64-bit systems value should be set to 2,
314 * that corresponds to the MPIDR_EL1 register size.
315 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
316 * in the system, #address-cells can be set to 1, since
317 * MPIDR_EL1[63:32] bits are not used for CPUs
320 * Here we actually don't know whether our system is 32- or 64-bit one.
321 * The simplest way to go is to examine affinity IDs of all our CPUs. If
322 * at least one of them has Aff3 populated, we set #address-cells to 2.
324 for (cpu
= 0; cpu
< vms
->smp_cpus
; cpu
++) {
325 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
327 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
333 qemu_fdt_add_subnode(vms
->fdt
, "/cpus");
334 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#address-cells", addr_cells
);
335 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#size-cells", 0x0);
337 for (cpu
= vms
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
338 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
339 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
340 CPUState
*cs
= CPU(armcpu
);
342 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
343 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "cpu");
344 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
345 armcpu
->dtb_compatible
);
347 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
348 && vms
->smp_cpus
> 1) {
349 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
350 "enable-method", "psci");
353 if (addr_cells
== 2) {
354 qemu_fdt_setprop_u64(vms
->fdt
, nodename
, "reg",
355 armcpu
->mp_affinity
);
357 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "reg",
358 armcpu
->mp_affinity
);
361 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
362 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "numa-node-id",
363 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
370 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
374 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
375 nodename
= g_strdup_printf("/intc/its@%" PRIx64
,
376 vms
->memmap
[VIRT_GIC_ITS
].base
);
377 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
378 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
380 qemu_fdt_setprop(vms
->fdt
, nodename
, "msi-controller", NULL
, 0);
381 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
382 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
383 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
384 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
388 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
392 nodename
= g_strdup_printf("/intc/v2m@%" PRIx64
,
393 vms
->memmap
[VIRT_GIC_V2M
].base
);
394 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
395 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
396 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
397 "arm,gic-v2m-frame");
398 qemu_fdt_setprop(vms
->fdt
, nodename
, "msi-controller", NULL
, 0);
399 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
400 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
401 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
402 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", vms
->msi_phandle
);
406 static void fdt_add_gic_node(VirtMachineState
*vms
)
410 vms
->gic_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
411 qemu_fdt_setprop_cell(vms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
413 nodename
= g_strdup_printf("/intc@%" PRIx64
,
414 vms
->memmap
[VIRT_GIC_DIST
].base
);
415 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
416 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 3);
417 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
418 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 0x2);
419 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 0x2);
420 qemu_fdt_setprop(vms
->fdt
, nodename
, "ranges", NULL
, 0);
421 if (vms
->gic_version
== 3) {
422 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
424 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
427 qemu_fdt_setprop_cell(vms
->fdt
, nodename
,
428 "#redistributor-regions", nb_redist_regions
);
430 if (nb_redist_regions
== 1) {
431 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
432 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
433 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
434 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
435 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
437 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
438 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
439 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
440 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
441 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
442 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
,
443 2, vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
);
447 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
448 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
449 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
452 /* 'cortex-a15-gic' means 'GIC v2' */
453 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
454 "arm,cortex-a15-gic");
456 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
457 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
458 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
459 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
460 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
462 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
463 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
464 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
465 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
466 2, vms
->memmap
[VIRT_GIC_CPU
].size
,
467 2, vms
->memmap
[VIRT_GIC_HYP
].base
,
468 2, vms
->memmap
[VIRT_GIC_HYP
].size
,
469 2, vms
->memmap
[VIRT_GIC_VCPU
].base
,
470 2, vms
->memmap
[VIRT_GIC_VCPU
].size
);
471 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
472 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GIC_MAINT_IRQ
,
473 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
477 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", vms
->gic_phandle
);
481 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
485 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
488 armcpu
= ARM_CPU(cpu
);
489 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
493 if (kvm_irqchip_in_kernel()) {
494 kvm_arm_pmu_set_irq(cpu
, PPI(VIRTUAL_PMU_IRQ
));
496 kvm_arm_pmu_init(cpu
);
500 if (vms
->gic_version
== 2) {
501 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
502 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
503 (1 << vms
->smp_cpus
) - 1);
506 armcpu
= ARM_CPU(qemu_get_cpu(0));
507 qemu_fdt_add_subnode(vms
->fdt
, "/pmu");
508 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
509 const char compat
[] = "arm,armv8-pmuv3";
510 qemu_fdt_setprop(vms
->fdt
, "/pmu", "compatible",
511 compat
, sizeof(compat
));
512 qemu_fdt_setprop_cells(vms
->fdt
, "/pmu", "interrupts",
513 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
517 static void create_its(VirtMachineState
*vms
, DeviceState
*gicdev
)
519 const char *itsclass
= its_class_name();
523 /* Do nothing if not supported */
527 dev
= qdev_create(NULL
, itsclass
);
529 object_property_set_link(OBJECT(dev
), OBJECT(gicdev
), "parent-gicv3",
531 qdev_init_nofail(dev
);
532 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
534 fdt_add_its_gic_node(vms
);
537 static void create_v2m(VirtMachineState
*vms
, qemu_irq
*pic
)
540 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
543 dev
= qdev_create(NULL
, "arm-gicv2m");
544 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
545 qdev_prop_set_uint32(dev
, "base-spi", irq
);
546 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
547 qdev_init_nofail(dev
);
549 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
550 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
553 fdt_add_v2m_gic_node(vms
);
556 static void create_gic(VirtMachineState
*vms
, qemu_irq
*pic
)
558 /* We create a standalone GIC */
560 SysBusDevice
*gicbusdev
;
562 int type
= vms
->gic_version
, i
;
563 uint32_t nb_redist_regions
= 0;
565 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
567 gicdev
= qdev_create(NULL
, gictype
);
568 qdev_prop_set_uint32(gicdev
, "revision", type
);
569 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
570 /* Note that the num-irq property counts both internal and external
571 * interrupts; there are always 32 of the former (mandated by GIC spec).
573 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
574 if (!kvm_irqchip_in_kernel()) {
575 qdev_prop_set_bit(gicdev
, "has-security-extensions", vms
->secure
);
579 uint32_t redist0_capacity
=
580 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
581 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
583 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
585 qdev_prop_set_uint32(gicdev
, "len-redist-region-count",
587 qdev_prop_set_uint32(gicdev
, "redist-region-count[0]", redist0_count
);
589 if (nb_redist_regions
== 2) {
590 uint32_t redist1_capacity
=
591 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
593 qdev_prop_set_uint32(gicdev
, "redist-region-count[1]",
594 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
597 if (!kvm_irqchip_in_kernel()) {
598 qdev_prop_set_bit(gicdev
, "has-virtualization-extensions",
602 qdev_init_nofail(gicdev
);
603 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
604 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
606 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
607 if (nb_redist_regions
== 2) {
608 sysbus_mmio_map(gicbusdev
, 2,
609 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].base
);
612 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
614 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_HYP
].base
);
615 sysbus_mmio_map(gicbusdev
, 3, vms
->memmap
[VIRT_GIC_VCPU
].base
);
619 /* Wire the outputs from each CPU's generic timer and the GICv3
620 * maintenance interrupt signal to the appropriate GIC PPI inputs,
621 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
623 for (i
= 0; i
< smp_cpus
; i
++) {
624 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
625 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
627 /* Mapping from the output timer irq lines from the CPU to the
628 * GIC PPI inputs we use for the virt board.
630 const int timer_irq
[] = {
631 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
632 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
633 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
634 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
637 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
638 qdev_connect_gpio_out(cpudev
, irq
,
639 qdev_get_gpio_in(gicdev
,
640 ppibase
+ timer_irq
[irq
]));
644 qemu_irq irq
= qdev_get_gpio_in(gicdev
,
645 ppibase
+ ARCH_GIC_MAINT_IRQ
);
646 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt",
648 } else if (vms
->virt
) {
649 qemu_irq irq
= qdev_get_gpio_in(gicdev
,
650 ppibase
+ ARCH_GIC_MAINT_IRQ
);
651 sysbus_connect_irq(gicbusdev
, i
+ 4 * smp_cpus
, irq
);
654 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
655 qdev_get_gpio_in(gicdev
, ppibase
658 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
659 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
660 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
661 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
662 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
663 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
664 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
667 for (i
= 0; i
< NUM_IRQS
; i
++) {
668 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
671 fdt_add_gic_node(vms
);
673 if (type
== 3 && vms
->its
) {
674 create_its(vms
, gicdev
);
675 } else if (type
== 2) {
676 create_v2m(vms
, pic
);
680 static void create_uart(const VirtMachineState
*vms
, qemu_irq
*pic
, int uart
,
681 MemoryRegion
*mem
, Chardev
*chr
)
684 hwaddr base
= vms
->memmap
[uart
].base
;
685 hwaddr size
= vms
->memmap
[uart
].size
;
686 int irq
= vms
->irqmap
[uart
];
687 const char compat
[] = "arm,pl011\0arm,primecell";
688 const char clocknames
[] = "uartclk\0apb_pclk";
689 DeviceState
*dev
= qdev_create(NULL
, "pl011");
690 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
692 qdev_prop_set_chr(dev
, "chardev", chr
);
693 qdev_init_nofail(dev
);
694 memory_region_add_subregion(mem
, base
,
695 sysbus_mmio_get_region(s
, 0));
696 sysbus_connect_irq(s
, 0, pic
[irq
]);
698 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
699 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
700 /* Note that we can't use setprop_string because of the embedded NUL */
701 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible",
702 compat
, sizeof(compat
));
703 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
705 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
706 GIC_FDT_IRQ_TYPE_SPI
, irq
,
707 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
708 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "clocks",
709 vms
->clock_phandle
, vms
->clock_phandle
);
710 qemu_fdt_setprop(vms
->fdt
, nodename
, "clock-names",
711 clocknames
, sizeof(clocknames
));
713 if (uart
== VIRT_UART
) {
714 qemu_fdt_setprop_string(vms
->fdt
, "/chosen", "stdout-path", nodename
);
716 /* Mark as not usable by the normal world */
717 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
718 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
720 qemu_fdt_add_subnode(vms
->fdt
, "/secure-chosen");
721 qemu_fdt_setprop_string(vms
->fdt
, "/secure-chosen", "stdout-path",
728 static void create_rtc(const VirtMachineState
*vms
, qemu_irq
*pic
)
731 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
732 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
733 int irq
= vms
->irqmap
[VIRT_RTC
];
734 const char compat
[] = "arm,pl031\0arm,primecell";
736 sysbus_create_simple("pl031", base
, pic
[irq
]);
738 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
739 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
740 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
741 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
743 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
744 GIC_FDT_IRQ_TYPE_SPI
, irq
,
745 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
746 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
747 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
751 static DeviceState
*gpio_key_dev
;
752 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
754 /* use gpio Pin 3 for power button event */
755 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
758 static Notifier virt_system_powerdown_notifier
= {
759 .notify
= virt_powerdown_req
762 static void create_gpio(const VirtMachineState
*vms
, qemu_irq
*pic
)
765 DeviceState
*pl061_dev
;
766 hwaddr base
= vms
->memmap
[VIRT_GPIO
].base
;
767 hwaddr size
= vms
->memmap
[VIRT_GPIO
].size
;
768 int irq
= vms
->irqmap
[VIRT_GPIO
];
769 const char compat
[] = "arm,pl061\0arm,primecell";
771 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
773 uint32_t phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
774 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
775 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
776 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
778 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
779 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#gpio-cells", 2);
780 qemu_fdt_setprop(vms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
781 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
782 GIC_FDT_IRQ_TYPE_SPI
, irq
,
783 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
784 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
785 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
786 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", phandle
);
788 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
789 qdev_get_gpio_in(pl061_dev
, 3));
790 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys");
791 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
792 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#size-cells", 0);
793 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#address-cells", 1);
795 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys/poweroff");
796 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys/poweroff",
797 "label", "GPIO Key Poweroff");
798 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys/poweroff", "linux,code",
800 qemu_fdt_setprop_cells(vms
->fdt
, "/gpio-keys/poweroff",
801 "gpios", phandle
, 3, 0);
803 /* connect powerdown request */
804 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
809 static void create_virtio_devices(const VirtMachineState
*vms
, qemu_irq
*pic
)
812 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
814 /* We create the transports in forwards order. Since qbus_realize()
815 * prepends (not appends) new child buses, the incrementing loop below will
816 * create a list of virtio-mmio buses with decreasing base addresses.
818 * When a -device option is processed from the command line,
819 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
820 * order. The upshot is that -device options in increasing command line
821 * order are mapped to virtio-mmio buses with decreasing base addresses.
823 * When this code was originally written, that arrangement ensured that the
824 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
825 * the first -device on the command line. (The end-to-end order is a
826 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
827 * guest kernel's name-to-address assignment strategy.)
829 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
830 * the message, if not necessarily the code, of commit 70161ff336.
831 * Therefore the loop now establishes the inverse of the original intent.
833 * Unfortunately, we can't counteract the kernel change by reversing the
834 * loop; it would break existing command lines.
836 * In any case, the kernel makes no guarantee about the stability of
837 * enumeration order of virtio devices (as demonstrated by it changing
838 * between kernel versions). For reliable and stable identification
839 * of disks users must use UUIDs or similar mechanisms.
841 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
842 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
843 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
845 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
848 /* We add dtb nodes in reverse order so that they appear in the finished
849 * device tree lowest address first.
851 * Note that this mapping is independent of the loop above. The previous
852 * loop influences virtio device to virtio transport assignment, whereas
853 * this loop controls how virtio transports are laid out in the dtb.
855 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
857 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
858 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
860 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
861 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
862 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
863 "compatible", "virtio,mmio");
864 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
866 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
867 GIC_FDT_IRQ_TYPE_SPI
, irq
,
868 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
869 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
874 static void create_one_flash(const char *name
, hwaddr flashbase
,
875 hwaddr flashsize
, const char *file
,
876 MemoryRegion
*sysmem
)
878 /* Create and map a single flash device. We use the same
879 * parameters as the flash devices on the Versatile Express board.
881 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
882 DeviceState
*dev
= qdev_create(NULL
, TYPE_PFLASH_CFI01
);
883 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
884 const uint64_t sectorlength
= 256 * 1024;
887 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
891 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
892 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
893 qdev_prop_set_uint8(dev
, "width", 4);
894 qdev_prop_set_uint8(dev
, "device-width", 2);
895 qdev_prop_set_bit(dev
, "big-endian", false);
896 qdev_prop_set_uint16(dev
, "id0", 0x89);
897 qdev_prop_set_uint16(dev
, "id1", 0x18);
898 qdev_prop_set_uint16(dev
, "id2", 0x00);
899 qdev_prop_set_uint16(dev
, "id3", 0x00);
900 qdev_prop_set_string(dev
, "name", name
);
901 qdev_init_nofail(dev
);
903 memory_region_add_subregion(sysmem
, flashbase
,
904 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0));
910 if (drive_get(IF_PFLASH
, 0, 0)) {
911 error_report("The contents of the first flash device may be "
912 "specified with -bios or with -drive if=pflash... "
913 "but you cannot use both options at once");
916 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, file
);
918 error_report("Could not find ROM image '%s'", file
);
921 image_size
= load_image_mr(fn
, sysbus_mmio_get_region(sbd
, 0));
923 if (image_size
< 0) {
924 error_report("Could not load ROM image '%s'", file
);
930 static void create_flash(const VirtMachineState
*vms
,
931 MemoryRegion
*sysmem
,
932 MemoryRegion
*secure_sysmem
)
934 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
935 * Any file passed via -bios goes in the first of these.
936 * sysmem is the system memory space. secure_sysmem is the secure view
937 * of the system, and the first flash device should be made visible only
938 * there. The second flash device is visible to both secure and nonsecure.
939 * If sysmem == secure_sysmem this means there is no separate Secure
940 * address space and both flash devices are generally visible.
942 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
943 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
946 create_one_flash("virt.flash0", flashbase
, flashsize
,
947 bios_name
, secure_sysmem
);
948 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
,
951 if (sysmem
== secure_sysmem
) {
952 /* Report both flash devices as a single node in the DT */
953 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
954 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
955 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
956 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
957 2, flashbase
, 2, flashsize
,
958 2, flashbase
+ flashsize
, 2, flashsize
);
959 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
962 /* Report the devices as separate nodes so we can mark one as
963 * only visible to the secure world.
965 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
966 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
967 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
968 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
969 2, flashbase
, 2, flashsize
);
970 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
971 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
972 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
975 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
976 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
977 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
978 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
979 2, flashbase
+ flashsize
, 2, flashsize
);
980 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
985 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
987 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
988 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
992 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
993 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)smp_cpus
);
995 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
996 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
997 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
998 "compatible", "qemu,fw-cfg-mmio");
999 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1001 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1006 static void create_pcie_irq_map(const VirtMachineState
*vms
,
1007 uint32_t gic_phandle
,
1008 int first_irq
, const char *nodename
)
1011 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
1012 uint32_t *irq_map
= full_irq_map
;
1014 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
1015 for (pin
= 0; pin
< 4; pin
++) {
1016 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
1017 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
1018 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
1022 devfn
<< 8, 0, 0, /* devfn */
1023 pin
+ 1, /* PCI pin */
1024 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
1026 /* Convert map to big endian */
1027 for (i
= 0; i
< 10; i
++) {
1028 irq_map
[i
] = cpu_to_be32(map
[i
]);
1034 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-map",
1035 full_irq_map
, sizeof(full_irq_map
));
1037 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupt-map-mask",
1038 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
1042 static void create_smmu(const VirtMachineState
*vms
, qemu_irq
*pic
,
1046 const char compat
[] = "arm,smmu-v3";
1047 int irq
= vms
->irqmap
[VIRT_SMMU
];
1049 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
1050 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
1051 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1054 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1058 dev
= qdev_create(NULL
, "arm-smmuv3");
1060 object_property_set_link(OBJECT(dev
), OBJECT(bus
), "primary-bus",
1062 qdev_init_nofail(dev
);
1063 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1064 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1065 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
1068 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1069 qemu_fdt_add_subnode(vms
->fdt
, node
);
1070 qemu_fdt_setprop(vms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1071 qemu_fdt_setprop_sized_cells(vms
->fdt
, node
, "reg", 2, base
, 2, size
);
1073 qemu_fdt_setprop_cells(vms
->fdt
, node
, "interrupts",
1074 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1075 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1076 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1077 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1079 qemu_fdt_setprop(vms
->fdt
, node
, "interrupt-names", irq_names
,
1082 qemu_fdt_setprop_cell(vms
->fdt
, node
, "clocks", vms
->clock_phandle
);
1083 qemu_fdt_setprop_string(vms
->fdt
, node
, "clock-names", "apb_pclk");
1084 qemu_fdt_setprop(vms
->fdt
, node
, "dma-coherent", NULL
, 0);
1086 qemu_fdt_setprop_cell(vms
->fdt
, node
, "#iommu-cells", 1);
1088 qemu_fdt_setprop_cell(vms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1092 static void create_pcie(VirtMachineState
*vms
, qemu_irq
*pic
)
1094 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1095 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1096 hwaddr base_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].base
;
1097 hwaddr size_mmio_high
= vms
->memmap
[VIRT_HIGH_PCIE_MMIO
].size
;
1098 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1099 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1100 hwaddr base_ecam
, size_ecam
;
1101 hwaddr base
= base_mmio
;
1103 int irq
= vms
->irqmap
[VIRT_PCIE
];
1104 MemoryRegion
*mmio_alias
;
1105 MemoryRegion
*mmio_reg
;
1106 MemoryRegion
*ecam_alias
;
1107 MemoryRegion
*ecam_reg
;
1113 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
1114 qdev_init_nofail(dev
);
1116 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1117 base_ecam
= vms
->memmap
[ecam_id
].base
;
1118 size_ecam
= vms
->memmap
[ecam_id
].size
;
1119 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1120 /* Map only the first size_ecam bytes of ECAM space */
1121 ecam_alias
= g_new0(MemoryRegion
, 1);
1122 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1123 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1124 ecam_reg
, 0, size_ecam
);
1125 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1127 /* Map the MMIO window into system address space so as to expose
1128 * the section of PCI MMIO space which starts at the same base address
1129 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1132 mmio_alias
= g_new0(MemoryRegion
, 1);
1133 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1134 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1135 mmio_reg
, base_mmio
, size_mmio
);
1136 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1139 /* Map high MMIO space */
1140 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1142 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1143 mmio_reg
, base_mmio_high
, size_mmio_high
);
1144 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1148 /* Map IO port space */
1149 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1151 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1152 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
1153 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1156 pci
= PCI_HOST_BRIDGE(dev
);
1158 for (i
= 0; i
< nb_nics
; i
++) {
1159 NICInfo
*nd
= &nd_table
[i
];
1162 nd
->model
= g_strdup("virtio");
1165 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1169 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1170 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1171 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1172 "compatible", "pci-host-ecam-generic");
1173 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "pci");
1174 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 3);
1175 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 2);
1176 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "linux,pci-domain", 0);
1177 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "bus-range", 0,
1179 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1181 if (vms
->msi_phandle
) {
1182 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "msi-parent",
1186 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1187 2, base_ecam
, 2, size_ecam
);
1190 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1191 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1192 2, base_pio
, 2, size_pio
,
1193 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1194 2, base_mmio
, 2, size_mmio
,
1195 1, FDT_PCI_RANGE_MMIO_64BIT
,
1197 2, base_mmio_high
, 2, size_mmio_high
);
1199 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1200 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1201 2, base_pio
, 2, size_pio
,
1202 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1203 2, base_mmio
, 2, size_mmio
);
1206 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 1);
1207 create_pcie_irq_map(vms
, vms
->gic_phandle
, irq
, nodename
);
1210 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
1212 create_smmu(vms
, pic
, pci
->bus
);
1214 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "iommu-map",
1215 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1221 static void create_platform_bus(VirtMachineState
*vms
, qemu_irq
*pic
)
1226 MemoryRegion
*sysmem
= get_system_memory();
1228 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1229 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1230 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1231 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1232 qdev_init_nofail(dev
);
1233 vms
->platform_bus_dev
= dev
;
1235 s
= SYS_BUS_DEVICE(dev
);
1236 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1237 int irqn
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1238 sysbus_connect_irq(s
, i
, pic
[irqn
]);
1241 memory_region_add_subregion(sysmem
,
1242 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1243 sysbus_mmio_get_region(s
, 0));
1246 static void create_secure_ram(VirtMachineState
*vms
,
1247 MemoryRegion
*secure_sysmem
)
1249 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1251 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1252 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1254 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1256 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1258 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1259 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1260 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "memory");
1261 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1262 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
1263 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
1268 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1270 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1273 *fdt_size
= board
->fdt_size
;
1277 static void virt_build_smbios(VirtMachineState
*vms
)
1279 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1280 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1281 uint8_t *smbios_tables
, *smbios_anchor
;
1282 size_t smbios_tables_len
, smbios_anchor_len
;
1283 const char *product
= "QEMU Virtual Machine";
1285 if (kvm_enabled()) {
1286 product
= "KVM Virtual Machine";
1289 smbios_set_defaults("QEMU", product
,
1290 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1291 true, SMBIOS_ENTRY_POINT_30
);
1293 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1294 &smbios_anchor
, &smbios_anchor_len
);
1296 if (smbios_anchor
) {
1297 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1298 smbios_tables
, smbios_tables_len
);
1299 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1300 smbios_anchor
, smbios_anchor_len
);
1305 void virt_machine_done(Notifier
*notifier
, void *data
)
1307 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1309 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1310 struct arm_boot_info
*info
= &vms
->bootinfo
;
1311 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1314 * If the user provided a dtb, we assume the dynamic sysbus nodes
1315 * already are integrated there. This corresponds to a use case where
1316 * the dynamic sysbus nodes are complex and their generation is not yet
1317 * supported. In that case the user can take charge of the guest dt
1318 * while qemu takes charge of the qom stuff.
1320 if (info
->dtb_filename
== NULL
) {
1321 platform_bus_add_all_fdt_nodes(vms
->fdt
, "/intc",
1322 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1323 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1324 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1326 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
) < 0) {
1330 virt_acpi_setup(vms
);
1331 virt_build_smbios(vms
);
1334 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1336 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1337 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1339 if (!vmc
->disallow_affinity_adjustment
) {
1340 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1341 * GIC's target-list limitations. 32-bit KVM hosts currently
1342 * always create clusters of 4 CPUs, but that is expected to
1343 * change when they gain support for gicv3. When KVM is enabled
1344 * it will override the changes we make here, therefore our
1345 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1346 * and to improve SGI efficiency.
1348 if (vms
->gic_version
== 3) {
1349 clustersz
= GICV3_TARGETLIST_BITS
;
1351 clustersz
= GIC_TARGETLIST_BITS
;
1354 return arm_cpu_mp_affinity(idx
, clustersz
);
1357 static void virt_set_memmap(VirtMachineState
*vms
)
1359 MachineState
*ms
= MACHINE(vms
);
1360 hwaddr base
, device_memory_base
, device_memory_size
;
1363 vms
->memmap
= extended_memmap
;
1365 for (i
= 0; i
< ARRAY_SIZE(base_memmap
); i
++) {
1366 vms
->memmap
[i
] = base_memmap
[i
];
1369 if (ms
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1370 error_report("unsupported number of memory slots: %"PRIu64
,
1376 * We compute the base of the high IO region depending on the
1377 * amount of initial and device memory. The device memory start/size
1378 * is aligned on 1GiB. We never put the high IO region below 256GiB
1379 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1380 * The device region size assumes 1GiB page max alignment per slot.
1382 device_memory_base
=
1383 ROUND_UP(vms
->memmap
[VIRT_MEM
].base
+ ms
->ram_size
, GiB
);
1384 device_memory_size
= ms
->maxram_size
- ms
->ram_size
+ ms
->ram_slots
* GiB
;
1386 /* Base address of the high IO region */
1387 base
= device_memory_base
+ ROUND_UP(device_memory_size
, GiB
);
1388 if (base
< device_memory_base
) {
1389 error_report("maxmem/slots too huge");
1392 if (base
< vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
) {
1393 base
= vms
->memmap
[VIRT_MEM
].base
+ LEGACY_RAMLIMIT_BYTES
;
1396 for (i
= VIRT_LOWMEMMAP_LAST
; i
< ARRAY_SIZE(extended_memmap
); i
++) {
1397 hwaddr size
= extended_memmap
[i
].size
;
1399 base
= ROUND_UP(base
, size
);
1400 vms
->memmap
[i
].base
= base
;
1401 vms
->memmap
[i
].size
= size
;
1404 vms
->highest_gpa
= base
- 1;
1405 if (device_memory_size
> 0) {
1406 ms
->device_memory
= g_malloc0(sizeof(*ms
->device_memory
));
1407 ms
->device_memory
->base
= device_memory_base
;
1408 memory_region_init(&ms
->device_memory
->mr
, OBJECT(vms
),
1409 "device-memory", device_memory_size
);
1413 static void machvirt_init(MachineState
*machine
)
1415 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1416 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1417 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1418 const CPUArchIdList
*possible_cpus
;
1419 qemu_irq pic
[NUM_IRQS
];
1420 MemoryRegion
*sysmem
= get_system_memory();
1421 MemoryRegion
*secure_sysmem
= NULL
;
1422 int n
, virt_max_cpus
;
1423 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1424 bool firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1425 bool aarch64
= true;
1428 * In accelerated mode, the memory map is computed earlier in kvm_type()
1429 * to create a VM with the right number of IPA bits.
1432 virt_set_memmap(vms
);
1435 /* We can probe only here because during property set
1436 * KVM is not available yet
1438 if (vms
->gic_version
<= 0) {
1439 /* "host" or "max" */
1440 if (!kvm_enabled()) {
1441 if (vms
->gic_version
== 0) {
1442 error_report("gic-version=host requires KVM");
1445 /* "max": currently means 3 for TCG */
1446 vms
->gic_version
= 3;
1449 vms
->gic_version
= kvm_arm_vgic_probe();
1450 if (!vms
->gic_version
) {
1452 "Unable to determine GIC version supported by host");
1458 if (!cpu_type_valid(machine
->cpu_type
)) {
1459 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
1463 /* If we have an EL3 boot ROM then the assumption is that it will
1464 * implement PSCI itself, so disable QEMU's internal implementation
1465 * so it doesn't get in the way. Instead of starting secondary
1466 * CPUs in PSCI powerdown state we will start them all running and
1467 * let the boot ROM sort them out.
1468 * The usual case is that we do use QEMU's PSCI implementation;
1469 * if the guest has EL2 then we will use SMC as the conduit,
1470 * and otherwise we will use HVC (for backwards compatibility and
1471 * because if we're using KVM then we must use HVC).
1473 if (vms
->secure
&& firmware_loaded
) {
1474 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
1475 } else if (vms
->virt
) {
1476 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
1478 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
1481 /* The maximum number of CPUs depends on the GIC version, or on how
1482 * many redistributors we can fit into the memory map.
1484 if (vms
->gic_version
== 3) {
1486 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
1488 vms
->memmap
[VIRT_HIGH_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
1490 virt_max_cpus
= GIC_NCPU
;
1493 if (max_cpus
> virt_max_cpus
) {
1494 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1495 "supported by machine 'mach-virt' (%d)",
1496 max_cpus
, virt_max_cpus
);
1500 vms
->smp_cpus
= smp_cpus
;
1502 if (vms
->virt
&& kvm_enabled()) {
1503 error_report("mach-virt: KVM does not support providing "
1504 "Virtualization extensions to the guest CPU");
1509 if (kvm_enabled()) {
1510 error_report("mach-virt: KVM does not support Security extensions");
1514 /* The Secure view of the world is the same as the NonSecure,
1515 * but with a few extra devices. Create it as a container region
1516 * containing the system memory at low priority; any secure-only
1517 * devices go in at higher priority and take precedence.
1519 secure_sysmem
= g_new(MemoryRegion
, 1);
1520 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1522 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1527 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
1528 for (n
= 0; n
< possible_cpus
->len
; n
++) {
1532 if (n
>= smp_cpus
) {
1536 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
1537 object_property_set_int(cpuobj
, possible_cpus
->cpus
[n
].arch_id
,
1538 "mp-affinity", NULL
);
1543 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
1546 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
1549 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1552 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2", NULL
)) {
1553 object_property_set_bool(cpuobj
, false, "has_el2", NULL
);
1556 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
) {
1557 object_property_set_int(cpuobj
, vms
->psci_conduit
,
1558 "psci-conduit", NULL
);
1560 /* Secondary CPUs start in PSCI powered-down state */
1562 object_property_set_bool(cpuobj
, true,
1563 "start-powered-off", NULL
);
1567 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu", NULL
)) {
1568 object_property_set_bool(cpuobj
, false, "pmu", NULL
);
1571 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1572 object_property_set_int(cpuobj
, vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1573 "reset-cbar", &error_abort
);
1576 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1579 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1580 "secure-memory", &error_abort
);
1583 object_property_set_bool(cpuobj
, true, "realized", &error_fatal
);
1584 object_unref(cpuobj
);
1586 fdt_add_timer_nodes(vms
);
1587 fdt_add_cpu_nodes(vms
);
1589 if (!kvm_enabled()) {
1590 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1591 bool aarch64
= object_property_get_bool(OBJECT(cpu
), "aarch64", NULL
);
1593 if (aarch64
&& vms
->highmem
) {
1594 int requested_pa_size
, pamax
= arm_pamax(cpu
);
1596 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
1597 if (pamax
< requested_pa_size
) {
1598 error_report("VCPU supports less PA bits (%d) than requested "
1599 "by the memory map (%d)", pamax
, requested_pa_size
);
1605 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1607 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
, ram
);
1608 if (machine
->device_memory
) {
1609 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
1610 &machine
->device_memory
->mr
);
1613 create_flash(vms
, sysmem
, secure_sysmem
? secure_sysmem
: sysmem
);
1615 create_gic(vms
, pic
);
1617 fdt_add_pmu_nodes(vms
);
1619 create_uart(vms
, pic
, VIRT_UART
, sysmem
, serial_hd(0));
1622 create_secure_ram(vms
, secure_sysmem
);
1623 create_uart(vms
, pic
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
1626 vms
->highmem_ecam
&= vms
->highmem
&& (!firmware_loaded
|| aarch64
);
1628 create_rtc(vms
, pic
);
1630 create_pcie(vms
, pic
);
1632 create_gpio(vms
, pic
);
1634 /* Create mmio transports, so the user can create virtio backends
1635 * (which will be automatically plugged in to the transports). If
1636 * no backend is created the transport will just sit harmlessly idle.
1638 create_virtio_devices(vms
, pic
);
1640 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
1641 rom_set_fw(vms
->fw_cfg
);
1643 create_platform_bus(vms
, pic
);
1645 vms
->bootinfo
.ram_size
= machine
->ram_size
;
1646 vms
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1647 vms
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1648 vms
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1649 vms
->bootinfo
.nb_cpus
= smp_cpus
;
1650 vms
->bootinfo
.board_id
= -1;
1651 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
1652 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
1653 vms
->bootinfo
.skip_dtb_autoload
= true;
1654 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
1655 arm_load_kernel(ARM_CPU(first_cpu
), &vms
->bootinfo
);
1657 vms
->machine_done
.notify
= virt_machine_done
;
1658 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
1661 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1663 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1668 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1670 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1672 vms
->secure
= value
;
1675 static bool virt_get_virt(Object
*obj
, Error
**errp
)
1677 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1682 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
1684 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1689 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1691 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1693 return vms
->highmem
;
1696 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1698 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1700 vms
->highmem
= value
;
1703 static bool virt_get_its(Object
*obj
, Error
**errp
)
1705 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1710 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
1712 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1717 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1719 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1720 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1722 return g_strdup(val
);
1725 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1727 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1729 if (!strcmp(value
, "3")) {
1730 vms
->gic_version
= 3;
1731 } else if (!strcmp(value
, "2")) {
1732 vms
->gic_version
= 2;
1733 } else if (!strcmp(value
, "host")) {
1734 vms
->gic_version
= 0; /* Will probe later */
1735 } else if (!strcmp(value
, "max")) {
1736 vms
->gic_version
= -1; /* Will probe later */
1738 error_setg(errp
, "Invalid gic-version value");
1739 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
1743 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
1745 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1747 switch (vms
->iommu
) {
1748 case VIRT_IOMMU_NONE
:
1749 return g_strdup("none");
1750 case VIRT_IOMMU_SMMUV3
:
1751 return g_strdup("smmuv3");
1753 g_assert_not_reached();
1757 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
1759 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1761 if (!strcmp(value
, "smmuv3")) {
1762 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
1763 } else if (!strcmp(value
, "none")) {
1764 vms
->iommu
= VIRT_IOMMU_NONE
;
1766 error_setg(errp
, "Invalid iommu value");
1767 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
1771 static CpuInstanceProperties
1772 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
1774 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
1775 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
1777 assert(cpu_index
< possible_cpus
->len
);
1778 return possible_cpus
->cpus
[cpu_index
].props
;
1781 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
1783 return idx
% nb_numa_nodes
;
1786 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
1789 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
1791 if (ms
->possible_cpus
) {
1792 assert(ms
->possible_cpus
->len
== max_cpus
);
1793 return ms
->possible_cpus
;
1796 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
1797 sizeof(CPUArchId
) * max_cpus
);
1798 ms
->possible_cpus
->len
= max_cpus
;
1799 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
1800 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
1801 ms
->possible_cpus
->cpus
[n
].arch_id
=
1802 virt_cpu_mp_affinity(vms
, n
);
1803 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
1804 ms
->possible_cpus
->cpus
[n
].props
.thread_id
= n
;
1806 return ms
->possible_cpus
;
1809 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
1810 DeviceState
*dev
, Error
**errp
)
1812 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
1814 if (vms
->platform_bus_dev
) {
1815 if (object_dynamic_cast(OBJECT(dev
), TYPE_SYS_BUS_DEVICE
)) {
1816 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
1817 SYS_BUS_DEVICE(dev
));
1822 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
1825 if (object_dynamic_cast(OBJECT(dev
), TYPE_SYS_BUS_DEVICE
)) {
1826 return HOTPLUG_HANDLER(machine
);
1833 * for arm64 kvm_type [7-0] encodes the requested number of bits
1834 * in the IPA address space
1836 static int virt_kvm_type(MachineState
*ms
, const char *type_str
)
1838 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
1839 int max_vm_pa_size
= kvm_arm_get_max_vm_ipa_size(ms
);
1840 int requested_pa_size
;
1842 /* we freeze the memory map to compute the highest gpa */
1843 virt_set_memmap(vms
);
1845 requested_pa_size
= 64 - clz64(vms
->highest_gpa
);
1847 if (requested_pa_size
> max_vm_pa_size
) {
1848 error_report("-m and ,maxmem option values "
1849 "require an IPA range (%d bits) larger than "
1850 "the one supported by the host (%d bits)",
1851 requested_pa_size
, max_vm_pa_size
);
1855 * By default we return 0 which corresponds to an implicit legacy
1856 * 40b IPA setting. Otherwise we return the actual requested PA
1859 return requested_pa_size
> 40 ? requested_pa_size
: 0;
1862 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1864 MachineClass
*mc
= MACHINE_CLASS(oc
);
1865 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
1867 mc
->init
= machvirt_init
;
1868 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
1869 * The value may be reduced later when we have more information about the
1870 * configuration of the particular instance.
1873 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
1874 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
1875 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
1876 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_PLATFORM
);
1877 mc
->block_default_type
= IF_VIRTIO
;
1879 mc
->pci_allow_0_address
= true;
1880 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1881 mc
->minimum_page_bits
= 12;
1882 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
1883 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
1884 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
1885 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
1886 mc
->kvm_type
= virt_kvm_type
;
1887 assert(!mc
->get_hotplug_handler
);
1888 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
1889 hc
->plug
= virt_machine_device_plug_cb
;
1892 static void virt_instance_init(Object
*obj
)
1894 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1895 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1897 /* EL3 is disabled by default on virt: this makes us consistent
1898 * between KVM and TCG for this board, and it also allows us to
1899 * boot UEFI blobs which assume no TrustZone support.
1901 vms
->secure
= false;
1902 object_property_add_bool(obj
, "secure", virt_get_secure
,
1903 virt_set_secure
, NULL
);
1904 object_property_set_description(obj
, "secure",
1905 "Set on/off to enable/disable the ARM "
1906 "Security Extensions (TrustZone)",
1909 /* EL2 is also disabled by default, for similar reasons */
1911 object_property_add_bool(obj
, "virtualization", virt_get_virt
,
1912 virt_set_virt
, NULL
);
1913 object_property_set_description(obj
, "virtualization",
1914 "Set on/off to enable/disable emulating a "
1915 "guest CPU which implements the ARM "
1916 "Virtualization Extensions",
1919 /* High memory is enabled by default */
1920 vms
->highmem
= true;
1921 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1922 virt_set_highmem
, NULL
);
1923 object_property_set_description(obj
, "highmem",
1924 "Set on/off to enable/disable using "
1925 "physical address space above 32 bits",
1927 /* Default GIC type is v2 */
1928 vms
->gic_version
= 2;
1929 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1930 virt_set_gic_version
, NULL
);
1931 object_property_set_description(obj
, "gic-version",
1933 "Valid values are 2, 3 and host", NULL
);
1935 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
1940 /* Default allows ITS instantiation */
1942 object_property_add_bool(obj
, "its", virt_get_its
,
1943 virt_set_its
, NULL
);
1944 object_property_set_description(obj
, "its",
1945 "Set on/off to enable/disable "
1946 "ITS instantiation",
1950 /* Default disallows iommu instantiation */
1951 vms
->iommu
= VIRT_IOMMU_NONE
;
1952 object_property_add_str(obj
, "iommu", virt_get_iommu
, virt_set_iommu
, NULL
);
1953 object_property_set_description(obj
, "iommu",
1954 "Set the IOMMU type. "
1955 "Valid values are none and smmuv3",
1958 vms
->irqmap
= a15irqmap
;
1961 static const TypeInfo virt_machine_info
= {
1962 .name
= TYPE_VIRT_MACHINE
,
1963 .parent
= TYPE_MACHINE
,
1965 .instance_size
= sizeof(VirtMachineState
),
1966 .class_size
= sizeof(VirtMachineClass
),
1967 .class_init
= virt_machine_class_init
,
1968 .instance_init
= virt_instance_init
,
1969 .interfaces
= (InterfaceInfo
[]) {
1970 { TYPE_HOTPLUG_HANDLER
},
1975 static void machvirt_machine_init(void)
1977 type_register_static(&virt_machine_info
);
1979 type_init(machvirt_machine_init
);
1981 static void virt_machine_4_0_options(MachineClass
*mc
)
1984 DEFINE_VIRT_MACHINE_AS_LATEST(4, 0)
1986 static void virt_machine_3_1_options(MachineClass
*mc
)
1988 virt_machine_4_0_options(mc
);
1989 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
1991 DEFINE_VIRT_MACHINE(3, 1)
1993 static void virt_machine_3_0_options(MachineClass
*mc
)
1995 virt_machine_3_1_options(mc
);
1996 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
1998 DEFINE_VIRT_MACHINE(3, 0)
2000 static void virt_machine_2_12_options(MachineClass
*mc
)
2002 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2004 virt_machine_3_0_options(mc
);
2005 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
2006 vmc
->no_highmem_ecam
= true;
2009 DEFINE_VIRT_MACHINE(2, 12)
2011 static void virt_machine_2_11_options(MachineClass
*mc
)
2013 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2015 virt_machine_2_12_options(mc
);
2016 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
2017 vmc
->smbios_old_sys_ver
= true;
2019 DEFINE_VIRT_MACHINE(2, 11)
2021 static void virt_machine_2_10_options(MachineClass
*mc
)
2023 virt_machine_2_11_options(mc
);
2024 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
2025 /* before 2.11 we never faulted accesses to bad addresses */
2026 mc
->ignore_memory_transaction_failures
= true;
2028 DEFINE_VIRT_MACHINE(2, 10)
2030 static void virt_machine_2_9_options(MachineClass
*mc
)
2032 virt_machine_2_10_options(mc
);
2033 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
2035 DEFINE_VIRT_MACHINE(2, 9)
2037 static void virt_machine_2_8_options(MachineClass
*mc
)
2039 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2041 virt_machine_2_9_options(mc
);
2042 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
2043 /* For 2.8 and earlier we falsely claimed in the DT that
2044 * our timers were edge-triggered, not level-triggered.
2046 vmc
->claim_edge_triggered_timers
= true;
2048 DEFINE_VIRT_MACHINE(2, 8)
2050 static void virt_machine_2_7_options(MachineClass
*mc
)
2052 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2054 virt_machine_2_8_options(mc
);
2055 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
2056 /* ITS was introduced with 2.8 */
2058 /* Stick with 1K pages for migration compatibility */
2059 mc
->minimum_page_bits
= 0;
2061 DEFINE_VIRT_MACHINE(2, 7)
2063 static void virt_machine_2_6_options(MachineClass
*mc
)
2065 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
2067 virt_machine_2_7_options(mc
);
2068 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
2069 vmc
->disallow_affinity_adjustment
= true;
2070 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2073 DEFINE_VIRT_MACHINE(2, 6)