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vhost-vdpa: remove the unused vhost_vdpa_get_acked_features()
[qemu/ar7.git] / hw / arm / xlnx-zynqmp.c
blob3597e8db4dedb6e9107c0cb0a6d580a7c0057f46
1 /*
2 * Xilinx Zynq MPSoC emulation
3 *
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu/module.h"
21 #include "hw/arm/xlnx-zynqmp.h"
22 #include "hw/intc/arm_gic_common.h"
23 #include "hw/boards.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/sysemu.h"
26 #include "kvm_arm.h"
27
28 #define GIC_NUM_SPI_INTR 160
29
30 #define ARM_PHYS_TIMER_PPI 30
31 #define ARM_VIRT_TIMER_PPI 27
32 #define ARM_HYP_TIMER_PPI 26
33 #define ARM_SEC_TIMER_PPI 29
34 #define GIC_MAINTENANCE_PPI 25
35
36 #define GEM_REVISION 0x40070106
37
38 #define GIC_BASE_ADDR 0xf9000000
39 #define GIC_DIST_ADDR 0xf9010000
40 #define GIC_CPU_ADDR 0xf9020000
41 #define GIC_VIFACE_ADDR 0xf9040000
42 #define GIC_VCPU_ADDR 0xf9060000
43
44 #define SATA_INTR 133
45 #define SATA_ADDR 0xFD0C0000
46 #define SATA_NUM_PORTS 2
47
48 #define QSPI_ADDR 0xff0f0000
49 #define LQSPI_ADDR 0xc0000000
50 #define QSPI_IRQ 15
51 #define QSPI_DMA_ADDR 0xff0f0800
52
53 #define DP_ADDR 0xfd4a0000
54 #define DP_IRQ 113
55
56 #define DPDMA_ADDR 0xfd4c0000
57 #define DPDMA_IRQ 116
58
59 #define IPI_ADDR 0xFF300000
60 #define IPI_IRQ 64
61
62 #define RTC_ADDR 0xffa60000
63 #define RTC_IRQ 26
64
65 #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
66
67 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
68 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
69 };
70
71 static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
72 57, 59, 61, 63,
73 };
74
75 static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
76 0xFF000000, 0xFF010000,
77 };
78
79 static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
80 21, 22,
81 };
82
83 static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = {
84 0xFF060000, 0xFF070000,
85 };
86
87 static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = {
88 23, 24,
89 };
90
91 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
92 0xFF160000, 0xFF170000,
93 };
94
95 static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
96 48, 49,
97 };
98
99 static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
100 0xFF040000, 0xFF050000,
101 };
102
103 static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
104 19, 20,
105 };
106
107 static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
108 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000,
109 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000
110 };
111
112 static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = {
113 124, 125, 126, 127, 128, 129, 130, 131
114 };
115
116 static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
117 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000,
118 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000
119 };
120
121 static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
122 77, 78, 79, 80, 81, 82, 83, 84
123 };
124
125 typedef struct XlnxZynqMPGICRegion {
126 int region_index;
127 uint32_t address;
128 uint32_t offset;
129 bool virt;
130 } XlnxZynqMPGICRegion;
131
132 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
133 /* Distributor */
134 {
135 .region_index = 0,
136 .address = GIC_DIST_ADDR,
137 .offset = 0,
138 .virt = false
139 },
140
141 /* CPU interface */
142 {
143 .region_index = 1,
144 .address = GIC_CPU_ADDR,
145 .offset = 0,
146 .virt = false
147 },
148 {
149 .region_index = 1,
150 .address = GIC_CPU_ADDR + 0x10000,
151 .offset = 0x1000,
152 .virt = false
153 },
154
155 /* Virtual interface */
156 {
157 .region_index = 2,
158 .address = GIC_VIFACE_ADDR,
159 .offset = 0,
160 .virt = true
161 },
162
163 /* Virtual CPU interface */
164 {
165 .region_index = 3,
166 .address = GIC_VCPU_ADDR,
167 .offset = 0,
168 .virt = true
169 },
170 {
171 .region_index = 3,
172 .address = GIC_VCPU_ADDR + 0x10000,
173 .offset = 0x1000,
174 .virt = true
175 },
176 };
177
178 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
179 {
180 return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
181 }
182
183 static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
184 const char *boot_cpu, Error **errp)
185 {
186 int i;
187 int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS,
188 XLNX_ZYNQMP_NUM_RPU_CPUS);
189
190 if (num_rpus <= 0) {
191 /* Don't create rpu-cluster object if there's nothing to put in it */
192 return;
193 }
194
195 object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster,
196 TYPE_CPU_CLUSTER);
197 qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1);
198
199 for (i = 0; i < num_rpus; i++) {
200 const char *name;
201
202 object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
203 &s->rpu_cpu[i],
204 ARM_CPU_TYPE_NAME("cortex-r5f"));
205
206 name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
207 if (strcmp(name, boot_cpu)) {
208 /* Secondary CPUs start in PSCI powered-down state */
209 object_property_set_bool(OBJECT(&s->rpu_cpu[i]),
210 "start-powered-off", true, &error_abort);
211 } else {
212 s->boot_cpu_ptr = &s->rpu_cpu[i];
213 }
214
215 object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true,
216 &error_abort);
217 if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) {
218 return;
219 }
220 }
221
222 qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
223 }
224
225 static void xlnx_zynqmp_init(Object *obj)
226 {
227 MachineState *ms = MACHINE(qdev_get_machine());
228 XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
229 int i;
230 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
231
232 object_initialize_child(obj, "apu-cluster", &s->apu_cluster,
233 TYPE_CPU_CLUSTER);
234 qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0);
235
236 for (i = 0; i < num_apus; i++) {
237 object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
238 &s->apu_cpu[i],
239 ARM_CPU_TYPE_NAME("cortex-a53"));
240 }
241
242 object_initialize_child(obj, "gic", &s->gic, gic_class_name());
243
244 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
245 object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM);
246 }
247
248 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
249 object_initialize_child(obj, "uart[*]", &s->uart[i],
250 TYPE_CADENCE_UART);
251 }
252
253 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
254 object_initialize_child(obj, "can[*]", &s->can[i],
255 TYPE_XLNX_ZYNQMP_CAN);
256 }
257
258 object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
259
260 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
261 object_initialize_child(obj, "sdhci[*]", &s->sdhci[i],
262 TYPE_SYSBUS_SDHCI);
263 }
264
265 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
266 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS);
267 }
268
269 object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS);
270
271 object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP);
272
273 object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA);
274
275 object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI);
276
277 object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC);
278
279 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
280 object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA);
281 }
282
283 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
284 object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA);
285 }
286
287 object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
288 }
289
290 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
291 {
292 MachineState *ms = MACHINE(qdev_get_machine());
293 XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
294 MemoryRegion *system_memory = get_system_memory();
295 uint8_t i;
296 uint64_t ram_size;
297 int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
298 const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
299 ram_addr_t ddr_low_size, ddr_high_size;
300 qemu_irq gic_spi[GIC_NUM_SPI_INTR];
301 Error *err = NULL;
302
303 ram_size = memory_region_size(s->ddr_ram);
304
305 /*
306 * Create the DDR Memory Regions. User friendly checks should happen at
307 * the board level
308 */
309 if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
310 /*
311 * The RAM size is above the maximum available for the low DDR.
312 * Create the high DDR memory region as well.
313 */
314 assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
315 ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
316 ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
317
318 memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev),
319 "ddr-ram-high", s->ddr_ram, ddr_low_size,
320 ddr_high_size);
321 memory_region_add_subregion(get_system_memory(),
322 XLNX_ZYNQMP_HIGH_RAM_START,
323 &s->ddr_ram_high);
324 } else {
325 /* RAM must be non-zero */
326 assert(ram_size);
327 ddr_low_size = ram_size;
328 }
329
330 memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low",
331 s->ddr_ram, 0, ddr_low_size);
332 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
333
334 /* Create the four OCM banks */
335 for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
336 char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
337
338 memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
339 XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
340 memory_region_add_subregion(get_system_memory(),
341 XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
342 i * XLNX_ZYNQMP_OCM_RAM_SIZE,
343 &s->ocm_ram[i]);
344
345 g_free(ocm_name);
346 }
347
348 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
349 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
350 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
351 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
352 qdev_prop_set_bit(DEVICE(&s->gic),
353 "has-virtualization-extensions", s->virt);
354
355 qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal);
356
357 /* Realize APUs before realizing the GIC. KVM requires this. */
358 for (i = 0; i < num_apus; i++) {
359 const char *name;
360
361 object_property_set_int(OBJECT(&s->apu_cpu[i]), "psci-conduit",
362 QEMU_PSCI_CONDUIT_SMC, &error_abort);
363
364 name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
365 if (strcmp(name, boot_cpu)) {
366 /* Secondary CPUs start in PSCI powered-down state */
367 object_property_set_bool(OBJECT(&s->apu_cpu[i]),
368 "start-powered-off", true, &error_abort);
369 } else {
370 s->boot_cpu_ptr = &s->apu_cpu[i];
371 }
372
373 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure,
374 NULL);
375 object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt,
376 NULL);
377 object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar",
378 GIC_BASE_ADDR, &error_abort);
379 object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count",
380 num_apus, &error_abort);
381 if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) {
382 return;
383 }
384 }
385
386 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
387 return;
388 }
389
390 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
391 for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
392 SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
393 const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
394 MemoryRegion *mr;
395 uint32_t addr = r->address;
396 int j;
397
398 if (r->virt && !s->virt) {
399 continue;
400 }
401
402 mr = sysbus_mmio_get_region(gic, r->region_index);
403 for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
404 MemoryRegion *alias = &s->gic_mr[i][j];
405
406 memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
407 r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
408 memory_region_add_subregion(system_memory, addr, alias);
409
410 addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
411 }
412 }
413
414 for (i = 0; i < num_apus; i++) {
415 qemu_irq irq;
416
417 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
418 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
419 ARM_CPU_IRQ));
420 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
421 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
422 ARM_CPU_FIQ));
423 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
424 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
425 ARM_CPU_VIRQ));
426 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
427 qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
428 ARM_CPU_VFIQ));
429 irq = qdev_get_gpio_in(DEVICE(&s->gic),
430 arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
431 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
432 irq = qdev_get_gpio_in(DEVICE(&s->gic),
433 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
434 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
435 irq = qdev_get_gpio_in(DEVICE(&s->gic),
436 arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
437 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
438 irq = qdev_get_gpio_in(DEVICE(&s->gic),
439 arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
440 qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
441
442 if (s->virt) {
443 irq = qdev_get_gpio_in(DEVICE(&s->gic),
444 arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
445 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
446 }
447 }
448
449 xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err);
450 if (err) {
451 error_propagate(errp, err);
452 return;
453 }
454
455 if (!s->boot_cpu_ptr) {
456 error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
457 return;
458 }
459
460 for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
461 gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
462 }
463
464 for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
465 NICInfo *nd = &nd_table[i];
466
467 /* FIXME use qdev NIC properties instead of nd_table[] */
468 if (nd->used) {
469 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
470 qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
471 }
472 object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
473 &error_abort);
474 object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
475 &error_abort);
476 object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
477 &error_abort);
478 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
479 return;
480 }
481 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
482 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
483 gic_spi[gem_intr[i]]);
484 }
485
486 for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
487 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
488 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {
489 return;
490 }
491 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
492 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
493 gic_spi[uart_intr[i]]);
494 }
495
496 for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
497 object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq",
498 XLNX_ZYNQMP_CAN_REF_CLK, &error_abort);
499
500 object_property_set_link(OBJECT(&s->can[i]), "canbus",
501 OBJECT(s->canbus[i]), &error_fatal);
502
503 sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err);
504 if (err) {
505 error_propagate(errp, err);
506 return;
507 }
508 sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]);
509 sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0,
510 gic_spi[can_intr[i]]);
511 }
512
513 object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
514 &error_abort);
515 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
516 return;
517 }
518
519 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
520 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
521
522 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
523 char *bus_name;
524 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
525 Object *sdhci = OBJECT(&s->sdhci[i]);
526
527 /*
528 * Compatible with:
529 * - SD Host Controller Specification Version 3.00
530 * - SDIO Specification Version 3.0
531 * - eMMC Specification Version 4.51
532 */
533 if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) {
534 return;
535 }
536 if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES,
537 errp)) {
538 return;
539 }
540 if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) {
541 return;
542 }
543 if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) {
544 return;
545 }
546 sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
547 sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
548
549 /* Alias controller SD bus to the SoC itself */
550 bus_name = g_strdup_printf("sd-bus%d", i);
551 object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus");
552 g_free(bus_name);
553 }
554
555 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
556 gchar *bus_name;
557
558 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
559 return;
560 }
561
562 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
563 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
564 gic_spi[spi_intr[i]]);
565
566 /* Alias controller SPI bus to the SoC itself */
567 bus_name = g_strdup_printf("spi%d", i);
568 object_property_add_alias(OBJECT(s), bus_name,
569 OBJECT(&s->spi[i]), "spi0");
570 g_free(bus_name);
571 }
572
573 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) {
574 return;
575 }
576 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
577 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
578 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
579
580 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
581 gchar *bus_name;
582 gchar *target_bus;
583
584 /* Alias controller SPI bus to the SoC itself */
585 bus_name = g_strdup_printf("qspi%d", i);
586 target_bus = g_strdup_printf("spi%d", i);
587 object_property_add_alias(OBJECT(s), bus_name,
588 OBJECT(&s->qspi), target_bus);
589 g_free(bus_name);
590 g_free(target_bus);
591 }
592
593 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) {
594 return;
595 }
596 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
597 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
598
599 if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) {
600 return;
601 }
602 object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma),
603 &error_abort);
604 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
605 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
606
607 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) {
608 return;
609 }
610 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
611 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
612
613 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
614 return;
615 }
616 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
617 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
618
619 for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
620 if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
621 errp)) {
622 return;
623 }
624 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) {
625 return;
626 }
627
628 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]);
629 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0,
630 gic_spi[gdma_ch_intr[i]]);
631 }
632
633 for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
634 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) {
635 return;
636 }
637
638 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]);
639 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0,
640 gic_spi[adma_ch_intr[i]]);
641 }
642
643 if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) {
644 return;
645 }
646
647 sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR);
648 sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, gic_spi[QSPI_IRQ]);
649 object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma",
650 OBJECT(&s->qspi_dma), errp);
651 }
652
653 static Property xlnx_zynqmp_props[] = {
654 DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
655 DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
656 DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
657 DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
658 MemoryRegion *),
659 DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS,
660 CanBusState *),
661 DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS,
662 CanBusState *),
663 DEFINE_PROP_END_OF_LIST()
664 };
665
666 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
667 {
668 DeviceClass *dc = DEVICE_CLASS(oc);
669
670 device_class_set_props(dc, xlnx_zynqmp_props);
671 dc->realize = xlnx_zynqmp_realize;
672 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
673 dc->user_creatable = false;
674 }
675
676 static const TypeInfo xlnx_zynqmp_type_info = {
677 .name = TYPE_XLNX_ZYNQMP,
678 .parent = TYPE_DEVICE,
679 .instance_size = sizeof(XlnxZynqMPState),
680 .instance_init = xlnx_zynqmp_init,
681 .class_init = xlnx_zynqmp_class_init,
682 };
683
684 static void xlnx_zynqmp_register_types(void)
685 {
686 type_register_static(&xlnx_zynqmp_type_info);
687 }
688
689 type_init(xlnx_zynqmp_register_types)
AR7 emulation for QEMU