2 * RISC-V Control and Status Registers.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "qemu/timer.h"
25 #include "time_helper.h"
26 #include "qemu/main-loop.h"
27 #include "exec/exec-all.h"
28 #include "exec/tb-flush.h"
29 #include "sysemu/cpu-timers.h"
30 #include "qemu/guest-random.h"
31 #include "qapi/error.h"
33 /* CSR function table public API */
34 void riscv_get_csr_ops(int csrno
, riscv_csr_operations
*ops
)
36 *ops
= csr_ops
[csrno
& (CSR_TABLE_SIZE
- 1)];
39 void riscv_set_csr_ops(int csrno
, riscv_csr_operations
*ops
)
41 csr_ops
[csrno
& (CSR_TABLE_SIZE
- 1)] = *ops
;
45 #if !defined(CONFIG_USER_ONLY)
46 RISCVException
smstateen_acc_ok(CPURISCVState
*env
, int index
, uint64_t bit
)
48 bool virt
= env
->virt_enabled
;
50 if (env
->priv
== PRV_M
|| !riscv_cpu_cfg(env
)->ext_smstateen
) {
51 return RISCV_EXCP_NONE
;
54 if (!(env
->mstateen
[index
] & bit
)) {
55 return RISCV_EXCP_ILLEGAL_INST
;
59 if (!(env
->hstateen
[index
] & bit
)) {
60 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
63 if (env
->priv
== PRV_U
&& !(env
->sstateen
[index
] & bit
)) {
64 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
68 if (env
->priv
== PRV_U
&& riscv_has_ext(env
, RVS
)) {
69 if (!(env
->sstateen
[index
] & bit
)) {
70 return RISCV_EXCP_ILLEGAL_INST
;
74 return RISCV_EXCP_NONE
;
78 static RISCVException
fs(CPURISCVState
*env
, int csrno
)
80 #if !defined(CONFIG_USER_ONLY)
81 if (!env
->debugger
&& !riscv_cpu_fp_enabled(env
) &&
82 !riscv_cpu_cfg(env
)->ext_zfinx
) {
83 return RISCV_EXCP_ILLEGAL_INST
;
86 return RISCV_EXCP_NONE
;
89 static RISCVException
vs(CPURISCVState
*env
, int csrno
)
91 if (riscv_cpu_cfg(env
)->ext_zve32f
) {
92 #if !defined(CONFIG_USER_ONLY)
93 if (!env
->debugger
&& !riscv_cpu_vector_enabled(env
)) {
94 return RISCV_EXCP_ILLEGAL_INST
;
97 return RISCV_EXCP_NONE
;
99 return RISCV_EXCP_ILLEGAL_INST
;
102 static RISCVException
ctr(CPURISCVState
*env
, int csrno
)
104 #if !defined(CONFIG_USER_ONLY)
105 RISCVCPU
*cpu
= env_archcpu(env
);
107 target_ulong ctr_mask
;
108 int base_csrno
= CSR_CYCLE
;
109 bool rv32
= riscv_cpu_mxl(env
) == MXL_RV32
? true : false;
111 if (rv32
&& csrno
>= CSR_CYCLEH
) {
112 /* Offset for RV32 hpmcounternh counters */
115 ctr_index
= csrno
- base_csrno
;
116 ctr_mask
= BIT(ctr_index
);
118 if ((csrno
>= CSR_CYCLE
&& csrno
<= CSR_INSTRET
) ||
119 (csrno
>= CSR_CYCLEH
&& csrno
<= CSR_INSTRETH
)) {
120 goto skip_ext_pmu_check
;
123 if (!(cpu
->pmu_avail_ctrs
& ctr_mask
)) {
124 /* No counter is enabled in PMU or the counter is out of range */
125 return RISCV_EXCP_ILLEGAL_INST
;
131 return RISCV_EXCP_NONE
;
134 if (env
->priv
< PRV_M
&& !get_field(env
->mcounteren
, ctr_mask
)) {
135 return RISCV_EXCP_ILLEGAL_INST
;
138 if (env
->virt_enabled
) {
139 if (!get_field(env
->hcounteren
, ctr_mask
) ||
140 (env
->priv
== PRV_U
&& !get_field(env
->scounteren
, ctr_mask
))) {
141 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
145 if (riscv_has_ext(env
, RVS
) && env
->priv
== PRV_U
&&
146 !get_field(env
->scounteren
, ctr_mask
)) {
147 return RISCV_EXCP_ILLEGAL_INST
;
151 return RISCV_EXCP_NONE
;
154 static RISCVException
ctr32(CPURISCVState
*env
, int csrno
)
156 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
157 return RISCV_EXCP_ILLEGAL_INST
;
160 return ctr(env
, csrno
);
163 static RISCVException
zcmt(CPURISCVState
*env
, int csrno
)
165 if (!riscv_cpu_cfg(env
)->ext_zcmt
) {
166 return RISCV_EXCP_ILLEGAL_INST
;
169 #if !defined(CONFIG_USER_ONLY)
170 RISCVException ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_JVT
);
171 if (ret
!= RISCV_EXCP_NONE
) {
176 return RISCV_EXCP_NONE
;
179 #if !defined(CONFIG_USER_ONLY)
180 static RISCVException
mctr(CPURISCVState
*env
, int csrno
)
182 int pmu_num
= riscv_cpu_cfg(env
)->pmu_num
;
184 int base_csrno
= CSR_MHPMCOUNTER3
;
186 if ((riscv_cpu_mxl(env
) == MXL_RV32
) && csrno
>= CSR_MCYCLEH
) {
187 /* Offset for RV32 mhpmcounternh counters */
190 ctr_index
= csrno
- base_csrno
;
191 if (!pmu_num
|| ctr_index
>= pmu_num
) {
192 /* The PMU is not enabled or counter is out of range */
193 return RISCV_EXCP_ILLEGAL_INST
;
196 return RISCV_EXCP_NONE
;
199 static RISCVException
mctr32(CPURISCVState
*env
, int csrno
)
201 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
202 return RISCV_EXCP_ILLEGAL_INST
;
205 return mctr(env
, csrno
);
208 static RISCVException
sscofpmf(CPURISCVState
*env
, int csrno
)
210 if (!riscv_cpu_cfg(env
)->ext_sscofpmf
) {
211 return RISCV_EXCP_ILLEGAL_INST
;
214 return RISCV_EXCP_NONE
;
217 static RISCVException
any(CPURISCVState
*env
, int csrno
)
219 return RISCV_EXCP_NONE
;
222 static RISCVException
any32(CPURISCVState
*env
, int csrno
)
224 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
225 return RISCV_EXCP_ILLEGAL_INST
;
228 return any(env
, csrno
);
232 static int aia_any(CPURISCVState
*env
, int csrno
)
234 if (!riscv_cpu_cfg(env
)->ext_smaia
) {
235 return RISCV_EXCP_ILLEGAL_INST
;
238 return any(env
, csrno
);
241 static int aia_any32(CPURISCVState
*env
, int csrno
)
243 if (!riscv_cpu_cfg(env
)->ext_smaia
) {
244 return RISCV_EXCP_ILLEGAL_INST
;
247 return any32(env
, csrno
);
250 static RISCVException
smode(CPURISCVState
*env
, int csrno
)
252 if (riscv_has_ext(env
, RVS
)) {
253 return RISCV_EXCP_NONE
;
256 return RISCV_EXCP_ILLEGAL_INST
;
259 static int smode32(CPURISCVState
*env
, int csrno
)
261 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
262 return RISCV_EXCP_ILLEGAL_INST
;
265 return smode(env
, csrno
);
268 static int aia_smode(CPURISCVState
*env
, int csrno
)
270 if (!riscv_cpu_cfg(env
)->ext_ssaia
) {
271 return RISCV_EXCP_ILLEGAL_INST
;
274 return smode(env
, csrno
);
277 static int aia_smode32(CPURISCVState
*env
, int csrno
)
279 if (!riscv_cpu_cfg(env
)->ext_ssaia
) {
280 return RISCV_EXCP_ILLEGAL_INST
;
283 return smode32(env
, csrno
);
286 static RISCVException
hmode(CPURISCVState
*env
, int csrno
)
288 if (riscv_has_ext(env
, RVH
)) {
289 return RISCV_EXCP_NONE
;
292 return RISCV_EXCP_ILLEGAL_INST
;
295 static RISCVException
hmode32(CPURISCVState
*env
, int csrno
)
297 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
298 return RISCV_EXCP_ILLEGAL_INST
;
301 return hmode(env
, csrno
);
305 static RISCVException
umode(CPURISCVState
*env
, int csrno
)
307 if (riscv_has_ext(env
, RVU
)) {
308 return RISCV_EXCP_NONE
;
311 return RISCV_EXCP_ILLEGAL_INST
;
314 static RISCVException
umode32(CPURISCVState
*env
, int csrno
)
316 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
317 return RISCV_EXCP_ILLEGAL_INST
;
320 return umode(env
, csrno
);
323 static RISCVException
mstateen(CPURISCVState
*env
, int csrno
)
325 if (!riscv_cpu_cfg(env
)->ext_smstateen
) {
326 return RISCV_EXCP_ILLEGAL_INST
;
329 return any(env
, csrno
);
332 static RISCVException
hstateen_pred(CPURISCVState
*env
, int csrno
, int base
)
334 if (!riscv_cpu_cfg(env
)->ext_smstateen
) {
335 return RISCV_EXCP_ILLEGAL_INST
;
338 RISCVException ret
= hmode(env
, csrno
);
339 if (ret
!= RISCV_EXCP_NONE
) {
344 return RISCV_EXCP_NONE
;
347 if (env
->priv
< PRV_M
) {
348 if (!(env
->mstateen
[csrno
- base
] & SMSTATEEN_STATEEN
)) {
349 return RISCV_EXCP_ILLEGAL_INST
;
353 return RISCV_EXCP_NONE
;
356 static RISCVException
hstateen(CPURISCVState
*env
, int csrno
)
358 return hstateen_pred(env
, csrno
, CSR_HSTATEEN0
);
361 static RISCVException
hstateenh(CPURISCVState
*env
, int csrno
)
363 return hstateen_pred(env
, csrno
, CSR_HSTATEEN0H
);
366 static RISCVException
sstateen(CPURISCVState
*env
, int csrno
)
368 bool virt
= env
->virt_enabled
;
369 int index
= csrno
- CSR_SSTATEEN0
;
371 if (!riscv_cpu_cfg(env
)->ext_smstateen
) {
372 return RISCV_EXCP_ILLEGAL_INST
;
375 RISCVException ret
= smode(env
, csrno
);
376 if (ret
!= RISCV_EXCP_NONE
) {
381 return RISCV_EXCP_NONE
;
384 if (env
->priv
< PRV_M
) {
385 if (!(env
->mstateen
[index
] & SMSTATEEN_STATEEN
)) {
386 return RISCV_EXCP_ILLEGAL_INST
;
390 if (!(env
->hstateen
[index
] & SMSTATEEN_STATEEN
)) {
391 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
396 return RISCV_EXCP_NONE
;
399 static RISCVException
sstc(CPURISCVState
*env
, int csrno
)
401 bool hmode_check
= false;
403 if (!riscv_cpu_cfg(env
)->ext_sstc
|| !env
->rdtime_fn
) {
404 return RISCV_EXCP_ILLEGAL_INST
;
407 if ((csrno
== CSR_VSTIMECMP
) || (csrno
== CSR_VSTIMECMPH
)) {
411 RISCVException ret
= hmode_check
? hmode(env
, csrno
) : smode(env
, csrno
);
412 if (ret
!= RISCV_EXCP_NONE
) {
417 return RISCV_EXCP_NONE
;
420 if (env
->priv
== PRV_M
) {
421 return RISCV_EXCP_NONE
;
425 * No need of separate function for rv32 as menvcfg stores both menvcfg
428 if (!(get_field(env
->mcounteren
, COUNTEREN_TM
) &&
429 get_field(env
->menvcfg
, MENVCFG_STCE
))) {
430 return RISCV_EXCP_ILLEGAL_INST
;
433 if (env
->virt_enabled
) {
434 if (!(get_field(env
->hcounteren
, COUNTEREN_TM
) &&
435 get_field(env
->henvcfg
, HENVCFG_STCE
))) {
436 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
440 return RISCV_EXCP_NONE
;
443 static RISCVException
sstc_32(CPURISCVState
*env
, int csrno
)
445 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
446 return RISCV_EXCP_ILLEGAL_INST
;
449 return sstc(env
, csrno
);
452 static RISCVException
satp(CPURISCVState
*env
, int csrno
)
454 if (env
->priv
== PRV_S
&& !env
->virt_enabled
&&
455 get_field(env
->mstatus
, MSTATUS_TVM
)) {
456 return RISCV_EXCP_ILLEGAL_INST
;
458 if (env
->priv
== PRV_S
&& env
->virt_enabled
&&
459 get_field(env
->hstatus
, HSTATUS_VTVM
)) {
460 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
463 return smode(env
, csrno
);
466 static RISCVException
hgatp(CPURISCVState
*env
, int csrno
)
468 if (env
->priv
== PRV_S
&& !env
->virt_enabled
&&
469 get_field(env
->mstatus
, MSTATUS_TVM
)) {
470 return RISCV_EXCP_ILLEGAL_INST
;
473 return hmode(env
, csrno
);
476 /* Checks if PointerMasking registers could be accessed */
477 static RISCVException
pointer_masking(CPURISCVState
*env
, int csrno
)
479 /* Check if j-ext is present */
480 if (riscv_has_ext(env
, RVJ
)) {
481 return RISCV_EXCP_NONE
;
483 return RISCV_EXCP_ILLEGAL_INST
;
486 static int aia_hmode(CPURISCVState
*env
, int csrno
)
488 if (!riscv_cpu_cfg(env
)->ext_ssaia
) {
489 return RISCV_EXCP_ILLEGAL_INST
;
492 return hmode(env
, csrno
);
495 static int aia_hmode32(CPURISCVState
*env
, int csrno
)
497 if (!riscv_cpu_cfg(env
)->ext_ssaia
) {
498 return RISCV_EXCP_ILLEGAL_INST
;
501 return hmode32(env
, csrno
);
504 static RISCVException
pmp(CPURISCVState
*env
, int csrno
)
506 if (riscv_cpu_cfg(env
)->pmp
) {
507 if (csrno
<= CSR_PMPCFG3
) {
508 uint32_t reg_index
= csrno
- CSR_PMPCFG0
;
510 /* TODO: RV128 restriction check */
511 if ((reg_index
& 1) && (riscv_cpu_mxl(env
) == MXL_RV64
)) {
512 return RISCV_EXCP_ILLEGAL_INST
;
516 return RISCV_EXCP_NONE
;
519 return RISCV_EXCP_ILLEGAL_INST
;
522 static RISCVException
epmp(CPURISCVState
*env
, int csrno
)
524 if (riscv_cpu_cfg(env
)->epmp
) {
525 return RISCV_EXCP_NONE
;
528 return RISCV_EXCP_ILLEGAL_INST
;
531 static RISCVException
debug(CPURISCVState
*env
, int csrno
)
533 if (riscv_cpu_cfg(env
)->debug
) {
534 return RISCV_EXCP_NONE
;
537 return RISCV_EXCP_ILLEGAL_INST
;
541 static RISCVException
seed(CPURISCVState
*env
, int csrno
)
543 if (!riscv_cpu_cfg(env
)->ext_zkr
) {
544 return RISCV_EXCP_ILLEGAL_INST
;
547 #if !defined(CONFIG_USER_ONLY)
549 return RISCV_EXCP_NONE
;
553 * With a CSR read-write instruction:
554 * 1) The seed CSR is always available in machine mode as normal.
555 * 2) Attempted access to seed from virtual modes VS and VU always raises
556 * an exception(virtual instruction exception only if mseccfg.sseed=1).
557 * 3) Without the corresponding access control bit set to 1, any attempted
558 * access to seed from U, S or HS modes will raise an illegal instruction
561 if (env
->priv
== PRV_M
) {
562 return RISCV_EXCP_NONE
;
563 } else if (env
->virt_enabled
) {
564 if (env
->mseccfg
& MSECCFG_SSEED
) {
565 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
567 return RISCV_EXCP_ILLEGAL_INST
;
570 if (env
->priv
== PRV_S
&& (env
->mseccfg
& MSECCFG_SSEED
)) {
571 return RISCV_EXCP_NONE
;
572 } else if (env
->priv
== PRV_U
&& (env
->mseccfg
& MSECCFG_USEED
)) {
573 return RISCV_EXCP_NONE
;
575 return RISCV_EXCP_ILLEGAL_INST
;
579 return RISCV_EXCP_NONE
;
583 /* User Floating-Point CSRs */
584 static RISCVException
read_fflags(CPURISCVState
*env
, int csrno
,
587 *val
= riscv_cpu_get_fflags(env
);
588 return RISCV_EXCP_NONE
;
591 static RISCVException
write_fflags(CPURISCVState
*env
, int csrno
,
594 #if !defined(CONFIG_USER_ONLY)
595 if (riscv_has_ext(env
, RVF
)) {
596 env
->mstatus
|= MSTATUS_FS
;
599 riscv_cpu_set_fflags(env
, val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
));
600 return RISCV_EXCP_NONE
;
603 static RISCVException
read_frm(CPURISCVState
*env
, int csrno
,
607 return RISCV_EXCP_NONE
;
610 static RISCVException
write_frm(CPURISCVState
*env
, int csrno
,
613 #if !defined(CONFIG_USER_ONLY)
614 if (riscv_has_ext(env
, RVF
)) {
615 env
->mstatus
|= MSTATUS_FS
;
618 env
->frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
619 return RISCV_EXCP_NONE
;
622 static RISCVException
read_fcsr(CPURISCVState
*env
, int csrno
,
625 *val
= (riscv_cpu_get_fflags(env
) << FSR_AEXC_SHIFT
)
626 | (env
->frm
<< FSR_RD_SHIFT
);
627 return RISCV_EXCP_NONE
;
630 static RISCVException
write_fcsr(CPURISCVState
*env
, int csrno
,
633 #if !defined(CONFIG_USER_ONLY)
634 if (riscv_has_ext(env
, RVF
)) {
635 env
->mstatus
|= MSTATUS_FS
;
638 env
->frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
639 riscv_cpu_set_fflags(env
, (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
);
640 return RISCV_EXCP_NONE
;
643 static RISCVException
read_vtype(CPURISCVState
*env
, int csrno
,
649 vill
= (uint32_t)env
->vill
<< 31;
652 vill
= (uint64_t)env
->vill
<< 63;
655 g_assert_not_reached();
657 *val
= (target_ulong
)vill
| env
->vtype
;
658 return RISCV_EXCP_NONE
;
661 static RISCVException
read_vl(CPURISCVState
*env
, int csrno
,
665 return RISCV_EXCP_NONE
;
668 static int read_vlenb(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
670 *val
= riscv_cpu_cfg(env
)->vlen
>> 3;
671 return RISCV_EXCP_NONE
;
674 static RISCVException
read_vxrm(CPURISCVState
*env
, int csrno
,
678 return RISCV_EXCP_NONE
;
681 static RISCVException
write_vxrm(CPURISCVState
*env
, int csrno
,
684 #if !defined(CONFIG_USER_ONLY)
685 env
->mstatus
|= MSTATUS_VS
;
688 return RISCV_EXCP_NONE
;
691 static RISCVException
read_vxsat(CPURISCVState
*env
, int csrno
,
695 return RISCV_EXCP_NONE
;
698 static RISCVException
write_vxsat(CPURISCVState
*env
, int csrno
,
701 #if !defined(CONFIG_USER_ONLY)
702 env
->mstatus
|= MSTATUS_VS
;
705 return RISCV_EXCP_NONE
;
708 static RISCVException
read_vstart(CPURISCVState
*env
, int csrno
,
712 return RISCV_EXCP_NONE
;
715 static RISCVException
write_vstart(CPURISCVState
*env
, int csrno
,
718 #if !defined(CONFIG_USER_ONLY)
719 env
->mstatus
|= MSTATUS_VS
;
722 * The vstart CSR is defined to have only enough writable bits
723 * to hold the largest element index, i.e. lg2(VLEN) bits.
725 env
->vstart
= val
& ~(~0ULL << ctzl(riscv_cpu_cfg(env
)->vlen
));
726 return RISCV_EXCP_NONE
;
729 static int read_vcsr(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
731 *val
= (env
->vxrm
<< VCSR_VXRM_SHIFT
) | (env
->vxsat
<< VCSR_VXSAT_SHIFT
);
732 return RISCV_EXCP_NONE
;
735 static int write_vcsr(CPURISCVState
*env
, int csrno
, target_ulong val
)
737 #if !defined(CONFIG_USER_ONLY)
738 env
->mstatus
|= MSTATUS_VS
;
740 env
->vxrm
= (val
& VCSR_VXRM
) >> VCSR_VXRM_SHIFT
;
741 env
->vxsat
= (val
& VCSR_VXSAT
) >> VCSR_VXSAT_SHIFT
;
742 return RISCV_EXCP_NONE
;
745 /* User Timers and Counters */
746 static target_ulong
get_ticks(bool shift
)
751 #if !defined(CONFIG_USER_ONLY)
752 if (icount_enabled()) {
755 val
= cpu_get_host_ticks();
758 val
= cpu_get_host_ticks();
770 #if defined(CONFIG_USER_ONLY)
771 static RISCVException
read_time(CPURISCVState
*env
, int csrno
,
774 *val
= cpu_get_host_ticks();
775 return RISCV_EXCP_NONE
;
778 static RISCVException
read_timeh(CPURISCVState
*env
, int csrno
,
781 *val
= cpu_get_host_ticks() >> 32;
782 return RISCV_EXCP_NONE
;
785 static int read_hpmcounter(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
787 *val
= get_ticks(false);
788 return RISCV_EXCP_NONE
;
791 static int read_hpmcounterh(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
793 *val
= get_ticks(true);
794 return RISCV_EXCP_NONE
;
797 #else /* CONFIG_USER_ONLY */
799 static int read_mhpmevent(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
801 int evt_index
= csrno
- CSR_MCOUNTINHIBIT
;
803 *val
= env
->mhpmevent_val
[evt_index
];
805 return RISCV_EXCP_NONE
;
808 static int write_mhpmevent(CPURISCVState
*env
, int csrno
, target_ulong val
)
810 int evt_index
= csrno
- CSR_MCOUNTINHIBIT
;
811 uint64_t mhpmevt_val
= val
;
813 env
->mhpmevent_val
[evt_index
] = val
;
815 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
816 mhpmevt_val
= mhpmevt_val
|
817 ((uint64_t)env
->mhpmeventh_val
[evt_index
] << 32);
819 riscv_pmu_update_event_map(env
, mhpmevt_val
, evt_index
);
821 return RISCV_EXCP_NONE
;
824 static int read_mhpmeventh(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
826 int evt_index
= csrno
- CSR_MHPMEVENT3H
+ 3;
828 *val
= env
->mhpmeventh_val
[evt_index
];
830 return RISCV_EXCP_NONE
;
833 static int write_mhpmeventh(CPURISCVState
*env
, int csrno
, target_ulong val
)
835 int evt_index
= csrno
- CSR_MHPMEVENT3H
+ 3;
836 uint64_t mhpmevth_val
= val
;
837 uint64_t mhpmevt_val
= env
->mhpmevent_val
[evt_index
];
839 mhpmevt_val
= mhpmevt_val
| (mhpmevth_val
<< 32);
840 env
->mhpmeventh_val
[evt_index
] = val
;
842 riscv_pmu_update_event_map(env
, mhpmevt_val
, evt_index
);
844 return RISCV_EXCP_NONE
;
847 static int write_mhpmcounter(CPURISCVState
*env
, int csrno
, target_ulong val
)
849 int ctr_idx
= csrno
- CSR_MCYCLE
;
850 PMUCTRState
*counter
= &env
->pmu_ctrs
[ctr_idx
];
851 uint64_t mhpmctr_val
= val
;
853 counter
->mhpmcounter_val
= val
;
854 if (riscv_pmu_ctr_monitor_cycles(env
, ctr_idx
) ||
855 riscv_pmu_ctr_monitor_instructions(env
, ctr_idx
)) {
856 counter
->mhpmcounter_prev
= get_ticks(false);
858 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
859 mhpmctr_val
= mhpmctr_val
|
860 ((uint64_t)counter
->mhpmcounterh_val
<< 32);
862 riscv_pmu_setup_timer(env
, mhpmctr_val
, ctr_idx
);
865 /* Other counters can keep incrementing from the given value */
866 counter
->mhpmcounter_prev
= val
;
869 return RISCV_EXCP_NONE
;
872 static int write_mhpmcounterh(CPURISCVState
*env
, int csrno
, target_ulong val
)
874 int ctr_idx
= csrno
- CSR_MCYCLEH
;
875 PMUCTRState
*counter
= &env
->pmu_ctrs
[ctr_idx
];
876 uint64_t mhpmctr_val
= counter
->mhpmcounter_val
;
877 uint64_t mhpmctrh_val
= val
;
879 counter
->mhpmcounterh_val
= val
;
880 mhpmctr_val
= mhpmctr_val
| (mhpmctrh_val
<< 32);
881 if (riscv_pmu_ctr_monitor_cycles(env
, ctr_idx
) ||
882 riscv_pmu_ctr_monitor_instructions(env
, ctr_idx
)) {
883 counter
->mhpmcounterh_prev
= get_ticks(true);
885 riscv_pmu_setup_timer(env
, mhpmctr_val
, ctr_idx
);
888 counter
->mhpmcounterh_prev
= val
;
891 return RISCV_EXCP_NONE
;
894 static RISCVException
riscv_pmu_read_ctr(CPURISCVState
*env
, target_ulong
*val
,
895 bool upper_half
, uint32_t ctr_idx
)
897 PMUCTRState counter
= env
->pmu_ctrs
[ctr_idx
];
898 target_ulong ctr_prev
= upper_half
? counter
.mhpmcounterh_prev
:
899 counter
.mhpmcounter_prev
;
900 target_ulong ctr_val
= upper_half
? counter
.mhpmcounterh_val
:
901 counter
.mhpmcounter_val
;
903 if (get_field(env
->mcountinhibit
, BIT(ctr_idx
))) {
905 * Counter should not increment if inhibit bit is set. We can't really
906 * stop the icount counting. Just return the counter value written by
907 * the supervisor to indicate that counter was not incremented.
909 if (!counter
.started
) {
911 return RISCV_EXCP_NONE
;
913 /* Mark that the counter has been stopped */
914 counter
.started
= false;
919 * The kernel computes the perf delta by subtracting the current value from
920 * the value it initialized previously (ctr_val).
922 if (riscv_pmu_ctr_monitor_cycles(env
, ctr_idx
) ||
923 riscv_pmu_ctr_monitor_instructions(env
, ctr_idx
)) {
924 *val
= get_ticks(upper_half
) - ctr_prev
+ ctr_val
;
929 return RISCV_EXCP_NONE
;
932 static int read_hpmcounter(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
936 if (csrno
>= CSR_MCYCLE
&& csrno
<= CSR_MHPMCOUNTER31
) {
937 ctr_index
= csrno
- CSR_MCYCLE
;
938 } else if (csrno
>= CSR_CYCLE
&& csrno
<= CSR_HPMCOUNTER31
) {
939 ctr_index
= csrno
- CSR_CYCLE
;
941 return RISCV_EXCP_ILLEGAL_INST
;
944 return riscv_pmu_read_ctr(env
, val
, false, ctr_index
);
947 static int read_hpmcounterh(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
951 if (csrno
>= CSR_MCYCLEH
&& csrno
<= CSR_MHPMCOUNTER31H
) {
952 ctr_index
= csrno
- CSR_MCYCLEH
;
953 } else if (csrno
>= CSR_CYCLEH
&& csrno
<= CSR_HPMCOUNTER31H
) {
954 ctr_index
= csrno
- CSR_CYCLEH
;
956 return RISCV_EXCP_ILLEGAL_INST
;
959 return riscv_pmu_read_ctr(env
, val
, true, ctr_index
);
962 static int read_scountovf(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
964 int mhpmevt_start
= CSR_MHPMEVENT3
- CSR_MCOUNTINHIBIT
;
967 target_ulong
*mhpm_evt_val
;
968 uint64_t of_bit_mask
;
970 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
971 mhpm_evt_val
= env
->mhpmeventh_val
;
972 of_bit_mask
= MHPMEVENTH_BIT_OF
;
974 mhpm_evt_val
= env
->mhpmevent_val
;
975 of_bit_mask
= MHPMEVENT_BIT_OF
;
978 for (i
= mhpmevt_start
; i
< RV_MAX_MHPMEVENTS
; i
++) {
979 if ((get_field(env
->mcounteren
, BIT(i
))) &&
980 (mhpm_evt_val
[i
] & of_bit_mask
)) {
985 return RISCV_EXCP_NONE
;
988 static RISCVException
read_time(CPURISCVState
*env
, int csrno
,
991 uint64_t delta
= env
->virt_enabled
? env
->htimedelta
: 0;
993 if (!env
->rdtime_fn
) {
994 return RISCV_EXCP_ILLEGAL_INST
;
997 *val
= env
->rdtime_fn(env
->rdtime_fn_arg
) + delta
;
998 return RISCV_EXCP_NONE
;
1001 static RISCVException
read_timeh(CPURISCVState
*env
, int csrno
,
1004 uint64_t delta
= env
->virt_enabled
? env
->htimedelta
: 0;
1006 if (!env
->rdtime_fn
) {
1007 return RISCV_EXCP_ILLEGAL_INST
;
1010 *val
= (env
->rdtime_fn(env
->rdtime_fn_arg
) + delta
) >> 32;
1011 return RISCV_EXCP_NONE
;
1014 static RISCVException
read_vstimecmp(CPURISCVState
*env
, int csrno
,
1017 *val
= env
->vstimecmp
;
1019 return RISCV_EXCP_NONE
;
1022 static RISCVException
read_vstimecmph(CPURISCVState
*env
, int csrno
,
1025 *val
= env
->vstimecmp
>> 32;
1027 return RISCV_EXCP_NONE
;
1030 static RISCVException
write_vstimecmp(CPURISCVState
*env
, int csrno
,
1033 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
1034 env
->vstimecmp
= deposit64(env
->vstimecmp
, 0, 32, (uint64_t)val
);
1036 env
->vstimecmp
= val
;
1039 riscv_timer_write_timecmp(env
, env
->vstimer
, env
->vstimecmp
,
1040 env
->htimedelta
, MIP_VSTIP
);
1042 return RISCV_EXCP_NONE
;
1045 static RISCVException
write_vstimecmph(CPURISCVState
*env
, int csrno
,
1048 env
->vstimecmp
= deposit64(env
->vstimecmp
, 32, 32, (uint64_t)val
);
1049 riscv_timer_write_timecmp(env
, env
->vstimer
, env
->vstimecmp
,
1050 env
->htimedelta
, MIP_VSTIP
);
1052 return RISCV_EXCP_NONE
;
1055 static RISCVException
read_stimecmp(CPURISCVState
*env
, int csrno
,
1058 if (env
->virt_enabled
) {
1059 *val
= env
->vstimecmp
;
1061 *val
= env
->stimecmp
;
1064 return RISCV_EXCP_NONE
;
1067 static RISCVException
read_stimecmph(CPURISCVState
*env
, int csrno
,
1070 if (env
->virt_enabled
) {
1071 *val
= env
->vstimecmp
>> 32;
1073 *val
= env
->stimecmp
>> 32;
1076 return RISCV_EXCP_NONE
;
1079 static RISCVException
write_stimecmp(CPURISCVState
*env
, int csrno
,
1082 if (env
->virt_enabled
) {
1083 if (env
->hvictl
& HVICTL_VTI
) {
1084 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
1086 return write_vstimecmp(env
, csrno
, val
);
1089 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
1090 env
->stimecmp
= deposit64(env
->stimecmp
, 0, 32, (uint64_t)val
);
1092 env
->stimecmp
= val
;
1095 riscv_timer_write_timecmp(env
, env
->stimer
, env
->stimecmp
, 0, MIP_STIP
);
1097 return RISCV_EXCP_NONE
;
1100 static RISCVException
write_stimecmph(CPURISCVState
*env
, int csrno
,
1103 if (env
->virt_enabled
) {
1104 if (env
->hvictl
& HVICTL_VTI
) {
1105 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
1107 return write_vstimecmph(env
, csrno
, val
);
1110 env
->stimecmp
= deposit64(env
->stimecmp
, 32, 32, (uint64_t)val
);
1111 riscv_timer_write_timecmp(env
, env
->stimer
, env
->stimecmp
, 0, MIP_STIP
);
1113 return RISCV_EXCP_NONE
;
1116 /* Machine constants */
1118 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
1119 #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP | \
1121 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
1122 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
1124 #define VSTOPI_NUM_SRCS 5
1126 static const uint64_t delegable_ints
= S_MODE_INTERRUPTS
|
1128 static const uint64_t vs_delegable_ints
= VS_MODE_INTERRUPTS
;
1129 static const uint64_t all_ints
= M_MODE_INTERRUPTS
| S_MODE_INTERRUPTS
|
1131 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
1132 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
1133 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
1134 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
1135 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
1136 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
1137 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
1138 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
1139 (1ULL << (RISCV_EXCP_U_ECALL)) | \
1140 (1ULL << (RISCV_EXCP_S_ECALL)) | \
1141 (1ULL << (RISCV_EXCP_VS_ECALL)) | \
1142 (1ULL << (RISCV_EXCP_M_ECALL)) | \
1143 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
1144 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
1145 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
1146 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
1147 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
1148 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
1149 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
1150 static const target_ulong vs_delegable_excps
= DELEGABLE_EXCPS
&
1151 ~((1ULL << (RISCV_EXCP_S_ECALL
)) |
1152 (1ULL << (RISCV_EXCP_VS_ECALL
)) |
1153 (1ULL << (RISCV_EXCP_M_ECALL
)) |
1154 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT
)) |
1155 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT
)) |
1156 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT
)) |
1157 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT
)));
1158 static const target_ulong sstatus_v1_10_mask
= SSTATUS_SIE
| SSTATUS_SPIE
|
1159 SSTATUS_UIE
| SSTATUS_UPIE
| SSTATUS_SPP
| SSTATUS_FS
| SSTATUS_XS
|
1160 SSTATUS_SUM
| SSTATUS_MXR
| SSTATUS_VS
;
1161 static const target_ulong sip_writable_mask
= SIP_SSIP
| MIP_USIP
| MIP_UEIP
|
1163 static const target_ulong hip_writable_mask
= MIP_VSSIP
;
1164 static const target_ulong hvip_writable_mask
= MIP_VSSIP
| MIP_VSTIP
|
1166 static const target_ulong vsip_writable_mask
= MIP_VSSIP
;
1168 const bool valid_vm_1_10_32
[16] = {
1169 [VM_1_10_MBARE
] = true,
1170 [VM_1_10_SV32
] = true
1173 const bool valid_vm_1_10_64
[16] = {
1174 [VM_1_10_MBARE
] = true,
1175 [VM_1_10_SV39
] = true,
1176 [VM_1_10_SV48
] = true,
1177 [VM_1_10_SV57
] = true
1180 /* Machine Information Registers */
1181 static RISCVException
read_zero(CPURISCVState
*env
, int csrno
,
1185 return RISCV_EXCP_NONE
;
1188 static RISCVException
write_ignore(CPURISCVState
*env
, int csrno
,
1191 return RISCV_EXCP_NONE
;
1194 static RISCVException
read_mvendorid(CPURISCVState
*env
, int csrno
,
1197 *val
= riscv_cpu_cfg(env
)->mvendorid
;
1198 return RISCV_EXCP_NONE
;
1201 static RISCVException
read_marchid(CPURISCVState
*env
, int csrno
,
1204 *val
= riscv_cpu_cfg(env
)->marchid
;
1205 return RISCV_EXCP_NONE
;
1208 static RISCVException
read_mimpid(CPURISCVState
*env
, int csrno
,
1211 *val
= riscv_cpu_cfg(env
)->mimpid
;
1212 return RISCV_EXCP_NONE
;
1215 static RISCVException
read_mhartid(CPURISCVState
*env
, int csrno
,
1218 *val
= env
->mhartid
;
1219 return RISCV_EXCP_NONE
;
1222 /* Machine Trap Setup */
1224 /* We do not store SD explicitly, only compute it on demand. */
1225 static uint64_t add_status_sd(RISCVMXL xl
, uint64_t status
)
1227 if ((status
& MSTATUS_FS
) == MSTATUS_FS
||
1228 (status
& MSTATUS_VS
) == MSTATUS_VS
||
1229 (status
& MSTATUS_XS
) == MSTATUS_XS
) {
1232 return status
| MSTATUS32_SD
;
1234 return status
| MSTATUS64_SD
;
1236 return MSTATUSH128_SD
;
1238 g_assert_not_reached();
1244 static RISCVException
read_mstatus(CPURISCVState
*env
, int csrno
,
1247 *val
= add_status_sd(riscv_cpu_mxl(env
), env
->mstatus
);
1248 return RISCV_EXCP_NONE
;
1251 static bool validate_vm(CPURISCVState
*env
, target_ulong vm
)
1253 return (vm
& 0xf) <=
1254 satp_mode_max_from_map(riscv_cpu_cfg(env
)->satp_mode
.map
);
1257 static target_ulong
legalize_mpp(CPURISCVState
*env
, target_ulong old_mpp
,
1261 target_ulong new_mpp
= get_field(val
, MSTATUS_MPP
);
1268 valid
= riscv_has_ext(env
, RVS
);
1271 valid
= riscv_has_ext(env
, RVU
);
1275 /* Remain field unchanged if new_mpp value is invalid */
1277 val
= set_field(val
, MSTATUS_MPP
, old_mpp
);
1283 static RISCVException
write_mstatus(CPURISCVState
*env
, int csrno
,
1286 uint64_t mstatus
= env
->mstatus
;
1288 RISCVMXL xl
= riscv_cpu_mxl(env
);
1291 * MPP field have been made WARL since priv version 1.11. However,
1292 * legalization for it will not break any software running on 1.10.
1294 val
= legalize_mpp(env
, get_field(mstatus
, MSTATUS_MPP
), val
);
1296 /* flush tlb on mstatus fields that affect VM */
1297 if ((val
^ mstatus
) & MSTATUS_MXR
) {
1298 tlb_flush(env_cpu(env
));
1300 mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
|
1301 MSTATUS_SPP
| MSTATUS_MPRV
| MSTATUS_SUM
|
1302 MSTATUS_MPP
| MSTATUS_MXR
| MSTATUS_TVM
| MSTATUS_TSR
|
1303 MSTATUS_TW
| MSTATUS_VS
;
1305 if (riscv_has_ext(env
, RVF
)) {
1309 if (xl
!= MXL_RV32
|| env
->debugger
) {
1311 * RV32: MPV and GVA are not in mstatus. The current plan is to
1312 * add them to mstatush. For now, we just don't support it.
1314 mask
|= MSTATUS_MPV
| MSTATUS_GVA
;
1315 if ((val
& MSTATUS64_UXL
) != 0) {
1316 mask
|= MSTATUS64_UXL
;
1320 mstatus
= (mstatus
& ~mask
) | (val
& mask
);
1322 if (xl
> MXL_RV32
) {
1323 /* SXL field is for now read only */
1324 mstatus
= set_field(mstatus
, MSTATUS64_SXL
, xl
);
1326 env
->mstatus
= mstatus
;
1327 env
->xl
= cpu_recompute_xl(env
);
1329 return RISCV_EXCP_NONE
;
1332 static RISCVException
read_mstatush(CPURISCVState
*env
, int csrno
,
1335 *val
= env
->mstatus
>> 32;
1336 return RISCV_EXCP_NONE
;
1339 static RISCVException
write_mstatush(CPURISCVState
*env
, int csrno
,
1342 uint64_t valh
= (uint64_t)val
<< 32;
1343 uint64_t mask
= MSTATUS_MPV
| MSTATUS_GVA
;
1345 env
->mstatus
= (env
->mstatus
& ~mask
) | (valh
& mask
);
1347 return RISCV_EXCP_NONE
;
1350 static RISCVException
read_mstatus_i128(CPURISCVState
*env
, int csrno
,
1353 *val
= int128_make128(env
->mstatus
, add_status_sd(MXL_RV128
,
1355 return RISCV_EXCP_NONE
;
1358 static RISCVException
read_misa_i128(CPURISCVState
*env
, int csrno
,
1361 *val
= int128_make128(env
->misa_ext
, (uint64_t)MXL_RV128
<< 62);
1362 return RISCV_EXCP_NONE
;
1365 static RISCVException
read_misa(CPURISCVState
*env
, int csrno
,
1370 switch (env
->misa_mxl
) {
1372 misa
= (target_ulong
)MXL_RV32
<< 30;
1374 #ifdef TARGET_RISCV64
1376 misa
= (target_ulong
)MXL_RV64
<< 62;
1380 g_assert_not_reached();
1383 *val
= misa
| env
->misa_ext
;
1384 return RISCV_EXCP_NONE
;
1387 static RISCVException
write_misa(CPURISCVState
*env
, int csrno
,
1390 if (!riscv_cpu_cfg(env
)->misa_w
) {
1391 /* drop write to misa */
1392 return RISCV_EXCP_NONE
;
1395 /* 'I' or 'E' must be present */
1396 if (!(val
& (RVI
| RVE
))) {
1397 /* It is not, drop write to misa */
1398 return RISCV_EXCP_NONE
;
1401 /* 'E' excludes all other extensions */
1404 * when we support 'E' we can do "val = RVE;" however
1405 * for now we just drop writes if 'E' is present.
1407 return RISCV_EXCP_NONE
;
1411 * misa.MXL writes are not supported by QEMU.
1412 * Drop writes to those bits.
1415 /* Mask extensions that are not supported by this hart */
1416 val
&= env
->misa_ext_mask
;
1418 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
1419 if ((val
& RVD
) && !(val
& RVF
)) {
1424 * Suppress 'C' if next instruction is not aligned
1425 * TODO: this should check next_pc
1427 if ((val
& RVC
) && (GETPC() & ~3) != 0) {
1431 /* If nothing changed, do nothing. */
1432 if (val
== env
->misa_ext
) {
1433 return RISCV_EXCP_NONE
;
1437 env
->mstatus
&= ~MSTATUS_FS
;
1440 /* flush translation cache */
1441 tb_flush(env_cpu(env
));
1442 env
->misa_ext
= val
;
1443 env
->xl
= riscv_cpu_mxl(env
);
1444 return RISCV_EXCP_NONE
;
1447 static RISCVException
read_medeleg(CPURISCVState
*env
, int csrno
,
1450 *val
= env
->medeleg
;
1451 return RISCV_EXCP_NONE
;
1454 static RISCVException
write_medeleg(CPURISCVState
*env
, int csrno
,
1457 env
->medeleg
= (env
->medeleg
& ~DELEGABLE_EXCPS
) | (val
& DELEGABLE_EXCPS
);
1458 return RISCV_EXCP_NONE
;
1461 static RISCVException
rmw_mideleg64(CPURISCVState
*env
, int csrno
,
1463 uint64_t new_val
, uint64_t wr_mask
)
1465 uint64_t mask
= wr_mask
& delegable_ints
;
1468 *ret_val
= env
->mideleg
;
1471 env
->mideleg
= (env
->mideleg
& ~mask
) | (new_val
& mask
);
1473 if (riscv_has_ext(env
, RVH
)) {
1474 env
->mideleg
|= HS_MODE_INTERRUPTS
;
1477 return RISCV_EXCP_NONE
;
1480 static RISCVException
rmw_mideleg(CPURISCVState
*env
, int csrno
,
1481 target_ulong
*ret_val
,
1482 target_ulong new_val
, target_ulong wr_mask
)
1487 ret
= rmw_mideleg64(env
, csrno
, &rval
, new_val
, wr_mask
);
1495 static RISCVException
rmw_midelegh(CPURISCVState
*env
, int csrno
,
1496 target_ulong
*ret_val
,
1497 target_ulong new_val
,
1498 target_ulong wr_mask
)
1503 ret
= rmw_mideleg64(env
, csrno
, &rval
,
1504 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
1506 *ret_val
= rval
>> 32;
1512 static RISCVException
rmw_mie64(CPURISCVState
*env
, int csrno
,
1514 uint64_t new_val
, uint64_t wr_mask
)
1516 uint64_t mask
= wr_mask
& all_ints
;
1519 *ret_val
= env
->mie
;
1522 env
->mie
= (env
->mie
& ~mask
) | (new_val
& mask
);
1524 if (!riscv_has_ext(env
, RVH
)) {
1525 env
->mie
&= ~((uint64_t)MIP_SGEIP
);
1528 return RISCV_EXCP_NONE
;
1531 static RISCVException
rmw_mie(CPURISCVState
*env
, int csrno
,
1532 target_ulong
*ret_val
,
1533 target_ulong new_val
, target_ulong wr_mask
)
1538 ret
= rmw_mie64(env
, csrno
, &rval
, new_val
, wr_mask
);
1546 static RISCVException
rmw_mieh(CPURISCVState
*env
, int csrno
,
1547 target_ulong
*ret_val
,
1548 target_ulong new_val
, target_ulong wr_mask
)
1553 ret
= rmw_mie64(env
, csrno
, &rval
,
1554 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
1556 *ret_val
= rval
>> 32;
1562 static int read_mtopi(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1567 irq
= riscv_cpu_mirq_pending(env
);
1568 if (irq
<= 0 || irq
> 63) {
1571 iprio
= env
->miprio
[irq
];
1573 if (riscv_cpu_default_priority(irq
) > IPRIO_DEFAULT_M
) {
1574 iprio
= IPRIO_MMAXIPRIO
;
1577 *val
= (irq
& TOPI_IID_MASK
) << TOPI_IID_SHIFT
;
1581 return RISCV_EXCP_NONE
;
1584 static int aia_xlate_vs_csrno(CPURISCVState
*env
, int csrno
)
1586 if (!env
->virt_enabled
) {
1592 return CSR_VSISELECT
;
1602 static int rmw_xiselect(CPURISCVState
*env
, int csrno
, target_ulong
*val
,
1603 target_ulong new_val
, target_ulong wr_mask
)
1605 target_ulong
*iselect
;
1607 /* Translate CSR number for VS-mode */
1608 csrno
= aia_xlate_vs_csrno(env
, csrno
);
1610 /* Find the iselect CSR based on CSR number */
1613 iselect
= &env
->miselect
;
1616 iselect
= &env
->siselect
;
1619 iselect
= &env
->vsiselect
;
1622 return RISCV_EXCP_ILLEGAL_INST
;
1629 wr_mask
&= ISELECT_MASK
;
1631 *iselect
= (*iselect
& ~wr_mask
) | (new_val
& wr_mask
);
1634 return RISCV_EXCP_NONE
;
1637 static int rmw_iprio(target_ulong xlen
,
1638 target_ulong iselect
, uint8_t *iprio
,
1639 target_ulong
*val
, target_ulong new_val
,
1640 target_ulong wr_mask
, int ext_irq_no
)
1643 target_ulong old_val
;
1645 if (iselect
< ISELECT_IPRIO0
|| ISELECT_IPRIO15
< iselect
) {
1648 if (xlen
!= 32 && iselect
& 0x1) {
1652 nirqs
= 4 * (xlen
/ 32);
1653 firq
= ((iselect
- ISELECT_IPRIO0
) / (xlen
/ 32)) * (nirqs
);
1656 for (i
= 0; i
< nirqs
; i
++) {
1657 old_val
|= ((target_ulong
)iprio
[firq
+ i
]) << (IPRIO_IRQ_BITS
* i
);
1665 new_val
= (old_val
& ~wr_mask
) | (new_val
& wr_mask
);
1666 for (i
= 0; i
< nirqs
; i
++) {
1668 * M-level and S-level external IRQ priority always read-only
1669 * zero. This means default priority order is always preferred
1670 * for M-level and S-level external IRQs.
1672 if ((firq
+ i
) == ext_irq_no
) {
1675 iprio
[firq
+ i
] = (new_val
>> (IPRIO_IRQ_BITS
* i
)) & 0xff;
1682 static int rmw_xireg(CPURISCVState
*env
, int csrno
, target_ulong
*val
,
1683 target_ulong new_val
, target_ulong wr_mask
)
1688 target_ulong priv
, isel
, vgein
;
1690 /* Translate CSR number for VS-mode */
1691 csrno
= aia_xlate_vs_csrno(env
, csrno
);
1693 /* Decode register details from CSR number */
1697 iprio
= env
->miprio
;
1698 isel
= env
->miselect
;
1702 iprio
= env
->siprio
;
1703 isel
= env
->siselect
;
1707 iprio
= env
->hviprio
;
1708 isel
= env
->vsiselect
;
1716 /* Find the selected guest interrupt file */
1717 vgein
= (virt
) ? get_field(env
->hstatus
, HSTATUS_VGEIN
) : 0;
1719 if (ISELECT_IPRIO0
<= isel
&& isel
<= ISELECT_IPRIO15
) {
1720 /* Local interrupt priority registers not available for VS-mode */
1722 ret
= rmw_iprio(riscv_cpu_mxl_bits(env
),
1723 isel
, iprio
, val
, new_val
, wr_mask
,
1724 (priv
== PRV_M
) ? IRQ_M_EXT
: IRQ_S_EXT
);
1726 } else if (ISELECT_IMSIC_FIRST
<= isel
&& isel
<= ISELECT_IMSIC_LAST
) {
1727 /* IMSIC registers only available when machine implements it. */
1728 if (env
->aia_ireg_rmw_fn
[priv
]) {
1729 /* Selected guest interrupt file should not be zero */
1730 if (virt
&& (!vgein
|| env
->geilen
< vgein
)) {
1733 /* Call machine specific IMSIC register emulation */
1734 ret
= env
->aia_ireg_rmw_fn
[priv
](env
->aia_ireg_rmw_fn_arg
[priv
],
1735 AIA_MAKE_IREG(isel
, priv
, virt
, vgein
,
1736 riscv_cpu_mxl_bits(env
)),
1737 val
, new_val
, wr_mask
);
1743 return (env
->virt_enabled
&& virt
) ?
1744 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
1746 return RISCV_EXCP_NONE
;
1749 static int rmw_xtopei(CPURISCVState
*env
, int csrno
, target_ulong
*val
,
1750 target_ulong new_val
, target_ulong wr_mask
)
1754 target_ulong priv
, vgein
;
1756 /* Translate CSR number for VS-mode */
1757 csrno
= aia_xlate_vs_csrno(env
, csrno
);
1759 /* Decode register details from CSR number */
1776 /* IMSIC CSRs only available when machine implements IMSIC. */
1777 if (!env
->aia_ireg_rmw_fn
[priv
]) {
1781 /* Find the selected guest interrupt file */
1782 vgein
= (virt
) ? get_field(env
->hstatus
, HSTATUS_VGEIN
) : 0;
1784 /* Selected guest interrupt file should be valid */
1785 if (virt
&& (!vgein
|| env
->geilen
< vgein
)) {
1789 /* Call machine specific IMSIC register emulation for TOPEI */
1790 ret
= env
->aia_ireg_rmw_fn
[priv
](env
->aia_ireg_rmw_fn_arg
[priv
],
1791 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI
, priv
, virt
, vgein
,
1792 riscv_cpu_mxl_bits(env
)),
1793 val
, new_val
, wr_mask
);
1797 return (env
->virt_enabled
&& virt
) ?
1798 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
1800 return RISCV_EXCP_NONE
;
1803 static RISCVException
read_mtvec(CPURISCVState
*env
, int csrno
,
1807 return RISCV_EXCP_NONE
;
1810 static RISCVException
write_mtvec(CPURISCVState
*env
, int csrno
,
1813 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
1814 if ((val
& 3) < 2) {
1817 qemu_log_mask(LOG_UNIMP
, "CSR_MTVEC: reserved mode not supported\n");
1819 return RISCV_EXCP_NONE
;
1822 static RISCVException
read_mcountinhibit(CPURISCVState
*env
, int csrno
,
1825 *val
= env
->mcountinhibit
;
1826 return RISCV_EXCP_NONE
;
1829 static RISCVException
write_mcountinhibit(CPURISCVState
*env
, int csrno
,
1833 PMUCTRState
*counter
;
1835 env
->mcountinhibit
= val
;
1837 /* Check if any other counter is also monitoring cycles/instructions */
1838 for (cidx
= 0; cidx
< RV_MAX_MHPMCOUNTERS
; cidx
++) {
1839 if (!get_field(env
->mcountinhibit
, BIT(cidx
))) {
1840 counter
= &env
->pmu_ctrs
[cidx
];
1841 counter
->started
= true;
1845 return RISCV_EXCP_NONE
;
1848 static RISCVException
read_mcounteren(CPURISCVState
*env
, int csrno
,
1851 *val
= env
->mcounteren
;
1852 return RISCV_EXCP_NONE
;
1855 static RISCVException
write_mcounteren(CPURISCVState
*env
, int csrno
,
1858 env
->mcounteren
= val
;
1859 return RISCV_EXCP_NONE
;
1862 /* Machine Trap Handling */
1863 static RISCVException
read_mscratch_i128(CPURISCVState
*env
, int csrno
,
1866 *val
= int128_make128(env
->mscratch
, env
->mscratchh
);
1867 return RISCV_EXCP_NONE
;
1870 static RISCVException
write_mscratch_i128(CPURISCVState
*env
, int csrno
,
1873 env
->mscratch
= int128_getlo(val
);
1874 env
->mscratchh
= int128_gethi(val
);
1875 return RISCV_EXCP_NONE
;
1878 static RISCVException
read_mscratch(CPURISCVState
*env
, int csrno
,
1881 *val
= env
->mscratch
;
1882 return RISCV_EXCP_NONE
;
1885 static RISCVException
write_mscratch(CPURISCVState
*env
, int csrno
,
1888 env
->mscratch
= val
;
1889 return RISCV_EXCP_NONE
;
1892 static RISCVException
read_mepc(CPURISCVState
*env
, int csrno
,
1896 return RISCV_EXCP_NONE
;
1899 static RISCVException
write_mepc(CPURISCVState
*env
, int csrno
,
1903 return RISCV_EXCP_NONE
;
1906 static RISCVException
read_mcause(CPURISCVState
*env
, int csrno
,
1910 return RISCV_EXCP_NONE
;
1913 static RISCVException
write_mcause(CPURISCVState
*env
, int csrno
,
1917 return RISCV_EXCP_NONE
;
1920 static RISCVException
read_mtval(CPURISCVState
*env
, int csrno
,
1924 return RISCV_EXCP_NONE
;
1927 static RISCVException
write_mtval(CPURISCVState
*env
, int csrno
,
1931 return RISCV_EXCP_NONE
;
1934 /* Execution environment configuration setup */
1935 static RISCVException
read_menvcfg(CPURISCVState
*env
, int csrno
,
1938 *val
= env
->menvcfg
;
1939 return RISCV_EXCP_NONE
;
1942 static RISCVException
write_menvcfg(CPURISCVState
*env
, int csrno
,
1945 const RISCVCPUConfig
*cfg
= riscv_cpu_cfg(env
);
1946 uint64_t mask
= MENVCFG_FIOM
| MENVCFG_CBIE
| MENVCFG_CBCFE
| MENVCFG_CBZE
;
1948 if (riscv_cpu_mxl(env
) == MXL_RV64
) {
1949 mask
|= (cfg
->ext_svpbmt
? MENVCFG_PBMTE
: 0) |
1950 (cfg
->ext_sstc
? MENVCFG_STCE
: 0) |
1951 (cfg
->ext_svadu
? MENVCFG_HADE
: 0);
1953 env
->menvcfg
= (env
->menvcfg
& ~mask
) | (val
& mask
);
1955 return RISCV_EXCP_NONE
;
1958 static RISCVException
read_menvcfgh(CPURISCVState
*env
, int csrno
,
1961 *val
= env
->menvcfg
>> 32;
1962 return RISCV_EXCP_NONE
;
1965 static RISCVException
write_menvcfgh(CPURISCVState
*env
, int csrno
,
1968 const RISCVCPUConfig
*cfg
= riscv_cpu_cfg(env
);
1969 uint64_t mask
= (cfg
->ext_svpbmt
? MENVCFG_PBMTE
: 0) |
1970 (cfg
->ext_sstc
? MENVCFG_STCE
: 0) |
1971 (cfg
->ext_svadu
? MENVCFG_HADE
: 0);
1972 uint64_t valh
= (uint64_t)val
<< 32;
1974 env
->menvcfg
= (env
->menvcfg
& ~mask
) | (valh
& mask
);
1976 return RISCV_EXCP_NONE
;
1979 static RISCVException
read_senvcfg(CPURISCVState
*env
, int csrno
,
1984 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
1985 if (ret
!= RISCV_EXCP_NONE
) {
1989 *val
= env
->senvcfg
;
1990 return RISCV_EXCP_NONE
;
1993 static RISCVException
write_senvcfg(CPURISCVState
*env
, int csrno
,
1996 uint64_t mask
= SENVCFG_FIOM
| SENVCFG_CBIE
| SENVCFG_CBCFE
| SENVCFG_CBZE
;
1999 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
2000 if (ret
!= RISCV_EXCP_NONE
) {
2004 env
->senvcfg
= (env
->senvcfg
& ~mask
) | (val
& mask
);
2005 return RISCV_EXCP_NONE
;
2008 static RISCVException
read_henvcfg(CPURISCVState
*env
, int csrno
,
2013 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
2014 if (ret
!= RISCV_EXCP_NONE
) {
2019 * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
2020 * henvcfg.stce is read_only 0 when menvcfg.stce = 0
2021 * henvcfg.hade is read_only 0 when menvcfg.hade = 0
2023 *val
= env
->henvcfg
& (~(HENVCFG_PBMTE
| HENVCFG_STCE
| HENVCFG_HADE
) |
2025 return RISCV_EXCP_NONE
;
2028 static RISCVException
write_henvcfg(CPURISCVState
*env
, int csrno
,
2031 uint64_t mask
= HENVCFG_FIOM
| HENVCFG_CBIE
| HENVCFG_CBCFE
| HENVCFG_CBZE
;
2034 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
2035 if (ret
!= RISCV_EXCP_NONE
) {
2039 if (riscv_cpu_mxl(env
) == MXL_RV64
) {
2040 mask
|= env
->menvcfg
& (HENVCFG_PBMTE
| HENVCFG_STCE
| HENVCFG_HADE
);
2043 env
->henvcfg
= (env
->henvcfg
& ~mask
) | (val
& mask
);
2045 return RISCV_EXCP_NONE
;
2048 static RISCVException
read_henvcfgh(CPURISCVState
*env
, int csrno
,
2053 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
2054 if (ret
!= RISCV_EXCP_NONE
) {
2058 *val
= (env
->henvcfg
& (~(HENVCFG_PBMTE
| HENVCFG_STCE
| HENVCFG_HADE
) |
2059 env
->menvcfg
)) >> 32;
2060 return RISCV_EXCP_NONE
;
2063 static RISCVException
write_henvcfgh(CPURISCVState
*env
, int csrno
,
2066 uint64_t mask
= env
->menvcfg
& (HENVCFG_PBMTE
| HENVCFG_STCE
|
2068 uint64_t valh
= (uint64_t)val
<< 32;
2071 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
2072 if (ret
!= RISCV_EXCP_NONE
) {
2076 env
->henvcfg
= (env
->henvcfg
& ~mask
) | (valh
& mask
);
2077 return RISCV_EXCP_NONE
;
2080 static RISCVException
read_mstateen(CPURISCVState
*env
, int csrno
,
2083 *val
= env
->mstateen
[csrno
- CSR_MSTATEEN0
];
2085 return RISCV_EXCP_NONE
;
2088 static RISCVException
write_mstateen(CPURISCVState
*env
, int csrno
,
2089 uint64_t wr_mask
, target_ulong new_val
)
2093 reg
= &env
->mstateen
[csrno
- CSR_MSTATEEN0
];
2094 *reg
= (*reg
& ~wr_mask
) | (new_val
& wr_mask
);
2096 return RISCV_EXCP_NONE
;
2099 static RISCVException
write_mstateen0(CPURISCVState
*env
, int csrno
,
2100 target_ulong new_val
)
2102 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2104 return write_mstateen(env
, csrno
, wr_mask
, new_val
);
2107 static RISCVException
write_mstateen_1_3(CPURISCVState
*env
, int csrno
,
2108 target_ulong new_val
)
2110 return write_mstateen(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2113 static RISCVException
read_mstateenh(CPURISCVState
*env
, int csrno
,
2116 *val
= env
->mstateen
[csrno
- CSR_MSTATEEN0H
] >> 32;
2118 return RISCV_EXCP_NONE
;
2121 static RISCVException
write_mstateenh(CPURISCVState
*env
, int csrno
,
2122 uint64_t wr_mask
, target_ulong new_val
)
2126 reg
= &env
->mstateen
[csrno
- CSR_MSTATEEN0H
];
2127 val
= (uint64_t)new_val
<< 32;
2128 val
|= *reg
& 0xFFFFFFFF;
2129 *reg
= (*reg
& ~wr_mask
) | (val
& wr_mask
);
2131 return RISCV_EXCP_NONE
;
2134 static RISCVException
write_mstateen0h(CPURISCVState
*env
, int csrno
,
2135 target_ulong new_val
)
2137 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2139 return write_mstateenh(env
, csrno
, wr_mask
, new_val
);
2142 static RISCVException
write_mstateenh_1_3(CPURISCVState
*env
, int csrno
,
2143 target_ulong new_val
)
2145 return write_mstateenh(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2148 static RISCVException
read_hstateen(CPURISCVState
*env
, int csrno
,
2151 int index
= csrno
- CSR_HSTATEEN0
;
2153 *val
= env
->hstateen
[index
] & env
->mstateen
[index
];
2155 return RISCV_EXCP_NONE
;
2158 static RISCVException
write_hstateen(CPURISCVState
*env
, int csrno
,
2159 uint64_t mask
, target_ulong new_val
)
2161 int index
= csrno
- CSR_HSTATEEN0
;
2162 uint64_t *reg
, wr_mask
;
2164 reg
= &env
->hstateen
[index
];
2165 wr_mask
= env
->mstateen
[index
] & mask
;
2166 *reg
= (*reg
& ~wr_mask
) | (new_val
& wr_mask
);
2168 return RISCV_EXCP_NONE
;
2171 static RISCVException
write_hstateen0(CPURISCVState
*env
, int csrno
,
2172 target_ulong new_val
)
2174 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2176 return write_hstateen(env
, csrno
, wr_mask
, new_val
);
2179 static RISCVException
write_hstateen_1_3(CPURISCVState
*env
, int csrno
,
2180 target_ulong new_val
)
2182 return write_hstateen(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2185 static RISCVException
read_hstateenh(CPURISCVState
*env
, int csrno
,
2188 int index
= csrno
- CSR_HSTATEEN0H
;
2190 *val
= (env
->hstateen
[index
] >> 32) & (env
->mstateen
[index
] >> 32);
2192 return RISCV_EXCP_NONE
;
2195 static RISCVException
write_hstateenh(CPURISCVState
*env
, int csrno
,
2196 uint64_t mask
, target_ulong new_val
)
2198 int index
= csrno
- CSR_HSTATEEN0H
;
2199 uint64_t *reg
, wr_mask
, val
;
2201 reg
= &env
->hstateen
[index
];
2202 val
= (uint64_t)new_val
<< 32;
2203 val
|= *reg
& 0xFFFFFFFF;
2204 wr_mask
= env
->mstateen
[index
] & mask
;
2205 *reg
= (*reg
& ~wr_mask
) | (val
& wr_mask
);
2207 return RISCV_EXCP_NONE
;
2210 static RISCVException
write_hstateen0h(CPURISCVState
*env
, int csrno
,
2211 target_ulong new_val
)
2213 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2215 return write_hstateenh(env
, csrno
, wr_mask
, new_val
);
2218 static RISCVException
write_hstateenh_1_3(CPURISCVState
*env
, int csrno
,
2219 target_ulong new_val
)
2221 return write_hstateenh(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2224 static RISCVException
read_sstateen(CPURISCVState
*env
, int csrno
,
2227 bool virt
= env
->virt_enabled
;
2228 int index
= csrno
- CSR_SSTATEEN0
;
2230 *val
= env
->sstateen
[index
] & env
->mstateen
[index
];
2232 *val
&= env
->hstateen
[index
];
2235 return RISCV_EXCP_NONE
;
2238 static RISCVException
write_sstateen(CPURISCVState
*env
, int csrno
,
2239 uint64_t mask
, target_ulong new_val
)
2241 bool virt
= env
->virt_enabled
;
2242 int index
= csrno
- CSR_SSTATEEN0
;
2246 wr_mask
= env
->mstateen
[index
] & mask
;
2248 wr_mask
&= env
->hstateen
[index
];
2251 reg
= &env
->sstateen
[index
];
2252 *reg
= (*reg
& ~wr_mask
) | (new_val
& wr_mask
);
2254 return RISCV_EXCP_NONE
;
2257 static RISCVException
write_sstateen0(CPURISCVState
*env
, int csrno
,
2258 target_ulong new_val
)
2260 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2262 return write_sstateen(env
, csrno
, wr_mask
, new_val
);
2265 static RISCVException
write_sstateen_1_3(CPURISCVState
*env
, int csrno
,
2266 target_ulong new_val
)
2268 return write_sstateen(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2271 static RISCVException
rmw_mip64(CPURISCVState
*env
, int csrno
,
2273 uint64_t new_val
, uint64_t wr_mask
)
2275 uint64_t old_mip
, mask
= wr_mask
& delegable_ints
;
2278 if (mask
& MIP_SEIP
) {
2279 env
->software_seip
= new_val
& MIP_SEIP
;
2280 new_val
|= env
->external_seip
* MIP_SEIP
;
2283 if (riscv_cpu_cfg(env
)->ext_sstc
&& (env
->priv
== PRV_M
) &&
2284 get_field(env
->menvcfg
, MENVCFG_STCE
)) {
2285 /* sstc extension forbids STIP & VSTIP to be writeable in mip */
2286 mask
= mask
& ~(MIP_STIP
| MIP_VSTIP
);
2290 old_mip
= riscv_cpu_update_mip(env
, mask
, (new_val
& mask
));
2295 if (csrno
!= CSR_HVIP
) {
2296 gin
= get_field(env
->hstatus
, HSTATUS_VGEIN
);
2297 old_mip
|= (env
->hgeip
& ((target_ulong
)1 << gin
)) ? MIP_VSEIP
: 0;
2298 old_mip
|= env
->vstime_irq
? MIP_VSTIP
: 0;
2305 return RISCV_EXCP_NONE
;
2308 static RISCVException
rmw_mip(CPURISCVState
*env
, int csrno
,
2309 target_ulong
*ret_val
,
2310 target_ulong new_val
, target_ulong wr_mask
)
2315 ret
= rmw_mip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2323 static RISCVException
rmw_miph(CPURISCVState
*env
, int csrno
,
2324 target_ulong
*ret_val
,
2325 target_ulong new_val
, target_ulong wr_mask
)
2330 ret
= rmw_mip64(env
, csrno
, &rval
,
2331 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2333 *ret_val
= rval
>> 32;
2339 /* Supervisor Trap Setup */
2340 static RISCVException
read_sstatus_i128(CPURISCVState
*env
, int csrno
,
2343 uint64_t mask
= sstatus_v1_10_mask
;
2344 uint64_t sstatus
= env
->mstatus
& mask
;
2345 if (env
->xl
!= MXL_RV32
|| env
->debugger
) {
2346 mask
|= SSTATUS64_UXL
;
2349 *val
= int128_make128(sstatus
, add_status_sd(MXL_RV128
, sstatus
));
2350 return RISCV_EXCP_NONE
;
2353 static RISCVException
read_sstatus(CPURISCVState
*env
, int csrno
,
2356 target_ulong mask
= (sstatus_v1_10_mask
);
2357 if (env
->xl
!= MXL_RV32
|| env
->debugger
) {
2358 mask
|= SSTATUS64_UXL
;
2360 /* TODO: Use SXL not MXL. */
2361 *val
= add_status_sd(riscv_cpu_mxl(env
), env
->mstatus
& mask
);
2362 return RISCV_EXCP_NONE
;
2365 static RISCVException
write_sstatus(CPURISCVState
*env
, int csrno
,
2368 target_ulong mask
= (sstatus_v1_10_mask
);
2370 if (env
->xl
!= MXL_RV32
|| env
->debugger
) {
2371 if ((val
& SSTATUS64_UXL
) != 0) {
2372 mask
|= SSTATUS64_UXL
;
2375 target_ulong newval
= (env
->mstatus
& ~mask
) | (val
& mask
);
2376 return write_mstatus(env
, CSR_MSTATUS
, newval
);
2379 static RISCVException
rmw_vsie64(CPURISCVState
*env
, int csrno
,
2381 uint64_t new_val
, uint64_t wr_mask
)
2384 uint64_t rval
, mask
= env
->hideleg
& VS_MODE_INTERRUPTS
;
2386 /* Bring VS-level bits to correct position */
2387 new_val
= (new_val
& (VS_MODE_INTERRUPTS
>> 1)) << 1;
2388 wr_mask
= (wr_mask
& (VS_MODE_INTERRUPTS
>> 1)) << 1;
2390 ret
= rmw_mie64(env
, csrno
, &rval
, new_val
, wr_mask
& mask
);
2392 *ret_val
= (rval
& mask
) >> 1;
2398 static RISCVException
rmw_vsie(CPURISCVState
*env
, int csrno
,
2399 target_ulong
*ret_val
,
2400 target_ulong new_val
, target_ulong wr_mask
)
2405 ret
= rmw_vsie64(env
, csrno
, &rval
, new_val
, wr_mask
);
2413 static RISCVException
rmw_vsieh(CPURISCVState
*env
, int csrno
,
2414 target_ulong
*ret_val
,
2415 target_ulong new_val
, target_ulong wr_mask
)
2420 ret
= rmw_vsie64(env
, csrno
, &rval
,
2421 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2423 *ret_val
= rval
>> 32;
2429 static RISCVException
rmw_sie64(CPURISCVState
*env
, int csrno
,
2431 uint64_t new_val
, uint64_t wr_mask
)
2434 uint64_t mask
= env
->mideleg
& S_MODE_INTERRUPTS
;
2436 if (env
->virt_enabled
) {
2437 if (env
->hvictl
& HVICTL_VTI
) {
2438 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
2440 ret
= rmw_vsie64(env
, CSR_VSIE
, ret_val
, new_val
, wr_mask
);
2442 ret
= rmw_mie64(env
, csrno
, ret_val
, new_val
, wr_mask
& mask
);
2452 static RISCVException
rmw_sie(CPURISCVState
*env
, int csrno
,
2453 target_ulong
*ret_val
,
2454 target_ulong new_val
, target_ulong wr_mask
)
2459 ret
= rmw_sie64(env
, csrno
, &rval
, new_val
, wr_mask
);
2460 if (ret
== RISCV_EXCP_NONE
&& ret_val
) {
2467 static RISCVException
rmw_sieh(CPURISCVState
*env
, int csrno
,
2468 target_ulong
*ret_val
,
2469 target_ulong new_val
, target_ulong wr_mask
)
2474 ret
= rmw_sie64(env
, csrno
, &rval
,
2475 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2477 *ret_val
= rval
>> 32;
2483 static RISCVException
read_stvec(CPURISCVState
*env
, int csrno
,
2487 return RISCV_EXCP_NONE
;
2490 static RISCVException
write_stvec(CPURISCVState
*env
, int csrno
,
2493 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
2494 if ((val
& 3) < 2) {
2497 qemu_log_mask(LOG_UNIMP
, "CSR_STVEC: reserved mode not supported\n");
2499 return RISCV_EXCP_NONE
;
2502 static RISCVException
read_scounteren(CPURISCVState
*env
, int csrno
,
2505 *val
= env
->scounteren
;
2506 return RISCV_EXCP_NONE
;
2509 static RISCVException
write_scounteren(CPURISCVState
*env
, int csrno
,
2512 env
->scounteren
= val
;
2513 return RISCV_EXCP_NONE
;
2516 /* Supervisor Trap Handling */
2517 static RISCVException
read_sscratch_i128(CPURISCVState
*env
, int csrno
,
2520 *val
= int128_make128(env
->sscratch
, env
->sscratchh
);
2521 return RISCV_EXCP_NONE
;
2524 static RISCVException
write_sscratch_i128(CPURISCVState
*env
, int csrno
,
2527 env
->sscratch
= int128_getlo(val
);
2528 env
->sscratchh
= int128_gethi(val
);
2529 return RISCV_EXCP_NONE
;
2532 static RISCVException
read_sscratch(CPURISCVState
*env
, int csrno
,
2535 *val
= env
->sscratch
;
2536 return RISCV_EXCP_NONE
;
2539 static RISCVException
write_sscratch(CPURISCVState
*env
, int csrno
,
2542 env
->sscratch
= val
;
2543 return RISCV_EXCP_NONE
;
2546 static RISCVException
read_sepc(CPURISCVState
*env
, int csrno
,
2550 return RISCV_EXCP_NONE
;
2553 static RISCVException
write_sepc(CPURISCVState
*env
, int csrno
,
2557 return RISCV_EXCP_NONE
;
2560 static RISCVException
read_scause(CPURISCVState
*env
, int csrno
,
2564 return RISCV_EXCP_NONE
;
2567 static RISCVException
write_scause(CPURISCVState
*env
, int csrno
,
2571 return RISCV_EXCP_NONE
;
2574 static RISCVException
read_stval(CPURISCVState
*env
, int csrno
,
2578 return RISCV_EXCP_NONE
;
2581 static RISCVException
write_stval(CPURISCVState
*env
, int csrno
,
2585 return RISCV_EXCP_NONE
;
2588 static RISCVException
rmw_vsip64(CPURISCVState
*env
, int csrno
,
2590 uint64_t new_val
, uint64_t wr_mask
)
2593 uint64_t rval
, mask
= env
->hideleg
& VS_MODE_INTERRUPTS
;
2595 /* Bring VS-level bits to correct position */
2596 new_val
= (new_val
& (VS_MODE_INTERRUPTS
>> 1)) << 1;
2597 wr_mask
= (wr_mask
& (VS_MODE_INTERRUPTS
>> 1)) << 1;
2599 ret
= rmw_mip64(env
, csrno
, &rval
, new_val
,
2600 wr_mask
& mask
& vsip_writable_mask
);
2602 *ret_val
= (rval
& mask
) >> 1;
2608 static RISCVException
rmw_vsip(CPURISCVState
*env
, int csrno
,
2609 target_ulong
*ret_val
,
2610 target_ulong new_val
, target_ulong wr_mask
)
2615 ret
= rmw_vsip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2623 static RISCVException
rmw_vsiph(CPURISCVState
*env
, int csrno
,
2624 target_ulong
*ret_val
,
2625 target_ulong new_val
, target_ulong wr_mask
)
2630 ret
= rmw_vsip64(env
, csrno
, &rval
,
2631 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2633 *ret_val
= rval
>> 32;
2639 static RISCVException
rmw_sip64(CPURISCVState
*env
, int csrno
,
2641 uint64_t new_val
, uint64_t wr_mask
)
2644 uint64_t mask
= env
->mideleg
& sip_writable_mask
;
2646 if (env
->virt_enabled
) {
2647 if (env
->hvictl
& HVICTL_VTI
) {
2648 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
2650 ret
= rmw_vsip64(env
, CSR_VSIP
, ret_val
, new_val
, wr_mask
);
2652 ret
= rmw_mip64(env
, csrno
, ret_val
, new_val
, wr_mask
& mask
);
2656 *ret_val
&= env
->mideleg
& S_MODE_INTERRUPTS
;
2662 static RISCVException
rmw_sip(CPURISCVState
*env
, int csrno
,
2663 target_ulong
*ret_val
,
2664 target_ulong new_val
, target_ulong wr_mask
)
2669 ret
= rmw_sip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2677 static RISCVException
rmw_siph(CPURISCVState
*env
, int csrno
,
2678 target_ulong
*ret_val
,
2679 target_ulong new_val
, target_ulong wr_mask
)
2684 ret
= rmw_sip64(env
, csrno
, &rval
,
2685 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2687 *ret_val
= rval
>> 32;
2693 /* Supervisor Protection and Translation */
2694 static RISCVException
read_satp(CPURISCVState
*env
, int csrno
,
2697 if (!riscv_cpu_cfg(env
)->mmu
) {
2699 return RISCV_EXCP_NONE
;
2702 return RISCV_EXCP_NONE
;
2705 static RISCVException
write_satp(CPURISCVState
*env
, int csrno
,
2711 if (!riscv_cpu_cfg(env
)->mmu
) {
2712 return RISCV_EXCP_NONE
;
2715 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
2716 vm
= validate_vm(env
, get_field(val
, SATP32_MODE
));
2717 mask
= (val
^ env
->satp
) & (SATP32_MODE
| SATP32_ASID
| SATP32_PPN
);
2719 vm
= validate_vm(env
, get_field(val
, SATP64_MODE
));
2720 mask
= (val
^ env
->satp
) & (SATP64_MODE
| SATP64_ASID
| SATP64_PPN
);
2725 * The ISA defines SATP.MODE=Bare as "no translation", but we still
2726 * pass these through QEMU's TLB emulation as it improves
2727 * performance. Flushing the TLB on SATP writes with paging
2728 * enabled avoids leaking those invalid cached mappings.
2730 tlb_flush(env_cpu(env
));
2733 return RISCV_EXCP_NONE
;
2736 static int read_vstopi(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
2740 uint64_t vseip
, vsgein
;
2741 uint32_t iid
, iprio
, hviid
, hviprio
, gein
;
2742 uint32_t s
, scount
= 0, siid
[VSTOPI_NUM_SRCS
], siprio
[VSTOPI_NUM_SRCS
];
2744 gein
= get_field(env
->hstatus
, HSTATUS_VGEIN
);
2745 hviid
= get_field(env
->hvictl
, HVICTL_IID
);
2746 hviprio
= get_field(env
->hvictl
, HVICTL_IPRIO
);
2749 vsgein
= (env
->hgeip
& (1ULL << gein
)) ? MIP_VSEIP
: 0;
2750 vseip
= env
->mie
& (env
->mip
| vsgein
) & MIP_VSEIP
;
2751 if (gein
<= env
->geilen
&& vseip
) {
2752 siid
[scount
] = IRQ_S_EXT
;
2753 siprio
[scount
] = IPRIO_MMAXIPRIO
+ 1;
2754 if (env
->aia_ireg_rmw_fn
[PRV_S
]) {
2756 * Call machine specific IMSIC register emulation for
2759 ret
= env
->aia_ireg_rmw_fn
[PRV_S
](
2760 env
->aia_ireg_rmw_fn_arg
[PRV_S
],
2761 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI
, PRV_S
, true, gein
,
2762 riscv_cpu_mxl_bits(env
)),
2764 if (!ret
&& topei
) {
2765 siprio
[scount
] = topei
& IMSIC_TOPEI_IPRIO_MASK
;
2771 if (hviid
== IRQ_S_EXT
&& hviprio
) {
2772 siid
[scount
] = IRQ_S_EXT
;
2773 siprio
[scount
] = hviprio
;
2778 if (env
->hvictl
& HVICTL_VTI
) {
2779 if (hviid
!= IRQ_S_EXT
) {
2780 siid
[scount
] = hviid
;
2781 siprio
[scount
] = hviprio
;
2785 irq
= riscv_cpu_vsirq_pending(env
);
2786 if (irq
!= IRQ_S_EXT
&& 0 < irq
&& irq
<= 63) {
2788 siprio
[scount
] = env
->hviprio
[irq
];
2795 for (s
= 0; s
< scount
; s
++) {
2796 if (siprio
[s
] < iprio
) {
2803 if (env
->hvictl
& HVICTL_IPRIOM
) {
2804 if (iprio
> IPRIO_MMAXIPRIO
) {
2805 iprio
= IPRIO_MMAXIPRIO
;
2808 if (riscv_cpu_default_priority(iid
) > IPRIO_DEFAULT_S
) {
2809 iprio
= IPRIO_MMAXIPRIO
;
2819 *val
= (iid
& TOPI_IID_MASK
) << TOPI_IID_SHIFT
;
2821 return RISCV_EXCP_NONE
;
2824 static int read_stopi(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
2829 if (env
->virt_enabled
) {
2830 return read_vstopi(env
, CSR_VSTOPI
, val
);
2833 irq
= riscv_cpu_sirq_pending(env
);
2834 if (irq
<= 0 || irq
> 63) {
2837 iprio
= env
->siprio
[irq
];
2839 if (riscv_cpu_default_priority(irq
) > IPRIO_DEFAULT_S
) {
2840 iprio
= IPRIO_MMAXIPRIO
;
2843 *val
= (irq
& TOPI_IID_MASK
) << TOPI_IID_SHIFT
;
2847 return RISCV_EXCP_NONE
;
2850 /* Hypervisor Extensions */
2851 static RISCVException
read_hstatus(CPURISCVState
*env
, int csrno
,
2854 *val
= env
->hstatus
;
2855 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
2856 /* We only support 64-bit VSXL */
2857 *val
= set_field(*val
, HSTATUS_VSXL
, 2);
2859 /* We only support little endian */
2860 *val
= set_field(*val
, HSTATUS_VSBE
, 0);
2861 return RISCV_EXCP_NONE
;
2864 static RISCVException
write_hstatus(CPURISCVState
*env
, int csrno
,
2868 if (riscv_cpu_mxl(env
) != MXL_RV32
&& get_field(val
, HSTATUS_VSXL
) != 2) {
2869 qemu_log_mask(LOG_UNIMP
,
2870 "QEMU does not support mixed HSXLEN options.");
2872 if (get_field(val
, HSTATUS_VSBE
) != 0) {
2873 qemu_log_mask(LOG_UNIMP
, "QEMU does not support big endian guests.");
2875 return RISCV_EXCP_NONE
;
2878 static RISCVException
read_hedeleg(CPURISCVState
*env
, int csrno
,
2881 *val
= env
->hedeleg
;
2882 return RISCV_EXCP_NONE
;
2885 static RISCVException
write_hedeleg(CPURISCVState
*env
, int csrno
,
2888 env
->hedeleg
= val
& vs_delegable_excps
;
2889 return RISCV_EXCP_NONE
;
2892 static RISCVException
rmw_hideleg64(CPURISCVState
*env
, int csrno
,
2894 uint64_t new_val
, uint64_t wr_mask
)
2896 uint64_t mask
= wr_mask
& vs_delegable_ints
;
2899 *ret_val
= env
->hideleg
& vs_delegable_ints
;
2902 env
->hideleg
= (env
->hideleg
& ~mask
) | (new_val
& mask
);
2903 return RISCV_EXCP_NONE
;
2906 static RISCVException
rmw_hideleg(CPURISCVState
*env
, int csrno
,
2907 target_ulong
*ret_val
,
2908 target_ulong new_val
, target_ulong wr_mask
)
2913 ret
= rmw_hideleg64(env
, csrno
, &rval
, new_val
, wr_mask
);
2921 static RISCVException
rmw_hidelegh(CPURISCVState
*env
, int csrno
,
2922 target_ulong
*ret_val
,
2923 target_ulong new_val
, target_ulong wr_mask
)
2928 ret
= rmw_hideleg64(env
, csrno
, &rval
,
2929 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2931 *ret_val
= rval
>> 32;
2937 static RISCVException
rmw_hvip64(CPURISCVState
*env
, int csrno
,
2939 uint64_t new_val
, uint64_t wr_mask
)
2943 ret
= rmw_mip64(env
, csrno
, ret_val
, new_val
,
2944 wr_mask
& hvip_writable_mask
);
2946 *ret_val
&= VS_MODE_INTERRUPTS
;
2952 static RISCVException
rmw_hvip(CPURISCVState
*env
, int csrno
,
2953 target_ulong
*ret_val
,
2954 target_ulong new_val
, target_ulong wr_mask
)
2959 ret
= rmw_hvip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2967 static RISCVException
rmw_hviph(CPURISCVState
*env
, int csrno
,
2968 target_ulong
*ret_val
,
2969 target_ulong new_val
, target_ulong wr_mask
)
2974 ret
= rmw_hvip64(env
, csrno
, &rval
,
2975 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2977 *ret_val
= rval
>> 32;
2983 static RISCVException
rmw_hip(CPURISCVState
*env
, int csrno
,
2984 target_ulong
*ret_value
,
2985 target_ulong new_value
, target_ulong write_mask
)
2987 int ret
= rmw_mip(env
, csrno
, ret_value
, new_value
,
2988 write_mask
& hip_writable_mask
);
2991 *ret_value
&= HS_MODE_INTERRUPTS
;
2996 static RISCVException
rmw_hie(CPURISCVState
*env
, int csrno
,
2997 target_ulong
*ret_val
,
2998 target_ulong new_val
, target_ulong wr_mask
)
3003 ret
= rmw_mie64(env
, csrno
, &rval
, new_val
, wr_mask
& HS_MODE_INTERRUPTS
);
3005 *ret_val
= rval
& HS_MODE_INTERRUPTS
;
3011 static RISCVException
read_hcounteren(CPURISCVState
*env
, int csrno
,
3014 *val
= env
->hcounteren
;
3015 return RISCV_EXCP_NONE
;
3018 static RISCVException
write_hcounteren(CPURISCVState
*env
, int csrno
,
3021 env
->hcounteren
= val
;
3022 return RISCV_EXCP_NONE
;
3025 static RISCVException
read_hgeie(CPURISCVState
*env
, int csrno
,
3031 return RISCV_EXCP_NONE
;
3034 static RISCVException
write_hgeie(CPURISCVState
*env
, int csrno
,
3037 /* Only GEILEN:1 bits implemented and BIT0 is never implemented */
3038 val
&= ((((target_ulong
)1) << env
->geilen
) - 1) << 1;
3040 /* Update mip.SGEIP bit */
3041 riscv_cpu_update_mip(env
, MIP_SGEIP
,
3042 BOOL_TO_MASK(!!(env
->hgeie
& env
->hgeip
)));
3043 return RISCV_EXCP_NONE
;
3046 static RISCVException
read_htval(CPURISCVState
*env
, int csrno
,
3050 return RISCV_EXCP_NONE
;
3053 static RISCVException
write_htval(CPURISCVState
*env
, int csrno
,
3057 return RISCV_EXCP_NONE
;
3060 static RISCVException
read_htinst(CPURISCVState
*env
, int csrno
,
3064 return RISCV_EXCP_NONE
;
3067 static RISCVException
write_htinst(CPURISCVState
*env
, int csrno
,
3070 return RISCV_EXCP_NONE
;
3073 static RISCVException
read_hgeip(CPURISCVState
*env
, int csrno
,
3079 return RISCV_EXCP_NONE
;
3082 static RISCVException
read_hgatp(CPURISCVState
*env
, int csrno
,
3086 return RISCV_EXCP_NONE
;
3089 static RISCVException
write_hgatp(CPURISCVState
*env
, int csrno
,
3093 return RISCV_EXCP_NONE
;
3096 static RISCVException
read_htimedelta(CPURISCVState
*env
, int csrno
,
3099 if (!env
->rdtime_fn
) {
3100 return RISCV_EXCP_ILLEGAL_INST
;
3103 *val
= env
->htimedelta
;
3104 return RISCV_EXCP_NONE
;
3107 static RISCVException
write_htimedelta(CPURISCVState
*env
, int csrno
,
3110 if (!env
->rdtime_fn
) {
3111 return RISCV_EXCP_ILLEGAL_INST
;
3114 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
3115 env
->htimedelta
= deposit64(env
->htimedelta
, 0, 32, (uint64_t)val
);
3117 env
->htimedelta
= val
;
3120 if (riscv_cpu_cfg(env
)->ext_sstc
&& env
->rdtime_fn
) {
3121 riscv_timer_write_timecmp(env
, env
->vstimer
, env
->vstimecmp
,
3122 env
->htimedelta
, MIP_VSTIP
);
3125 return RISCV_EXCP_NONE
;
3128 static RISCVException
read_htimedeltah(CPURISCVState
*env
, int csrno
,
3131 if (!env
->rdtime_fn
) {
3132 return RISCV_EXCP_ILLEGAL_INST
;
3135 *val
= env
->htimedelta
>> 32;
3136 return RISCV_EXCP_NONE
;
3139 static RISCVException
write_htimedeltah(CPURISCVState
*env
, int csrno
,
3142 if (!env
->rdtime_fn
) {
3143 return RISCV_EXCP_ILLEGAL_INST
;
3146 env
->htimedelta
= deposit64(env
->htimedelta
, 32, 32, (uint64_t)val
);
3148 if (riscv_cpu_cfg(env
)->ext_sstc
&& env
->rdtime_fn
) {
3149 riscv_timer_write_timecmp(env
, env
->vstimer
, env
->vstimecmp
,
3150 env
->htimedelta
, MIP_VSTIP
);
3153 return RISCV_EXCP_NONE
;
3156 static int read_hvictl(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3159 return RISCV_EXCP_NONE
;
3162 static int write_hvictl(CPURISCVState
*env
, int csrno
, target_ulong val
)
3164 env
->hvictl
= val
& HVICTL_VALID_MASK
;
3165 return RISCV_EXCP_NONE
;
3168 static int read_hvipriox(CPURISCVState
*env
, int first_index
,
3169 uint8_t *iprio
, target_ulong
*val
)
3171 int i
, irq
, rdzero
, num_irqs
= 4 * (riscv_cpu_mxl_bits(env
) / 32);
3173 /* First index has to be a multiple of number of irqs per register */
3174 if (first_index
% num_irqs
) {
3175 return (env
->virt_enabled
) ?
3176 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
3179 /* Fill-up return value */
3181 for (i
= 0; i
< num_irqs
; i
++) {
3182 if (riscv_cpu_hviprio_index2irq(first_index
+ i
, &irq
, &rdzero
)) {
3188 *val
|= ((target_ulong
)iprio
[irq
]) << (i
* 8);
3191 return RISCV_EXCP_NONE
;
3194 static int write_hvipriox(CPURISCVState
*env
, int first_index
,
3195 uint8_t *iprio
, target_ulong val
)
3197 int i
, irq
, rdzero
, num_irqs
= 4 * (riscv_cpu_mxl_bits(env
) / 32);
3199 /* First index has to be a multiple of number of irqs per register */
3200 if (first_index
% num_irqs
) {
3201 return (env
->virt_enabled
) ?
3202 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
3205 /* Fill-up priority arrary */
3206 for (i
= 0; i
< num_irqs
; i
++) {
3207 if (riscv_cpu_hviprio_index2irq(first_index
+ i
, &irq
, &rdzero
)) {
3213 iprio
[irq
] = (val
>> (i
* 8)) & 0xff;
3217 return RISCV_EXCP_NONE
;
3220 static int read_hviprio1(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3222 return read_hvipriox(env
, 0, env
->hviprio
, val
);
3225 static int write_hviprio1(CPURISCVState
*env
, int csrno
, target_ulong val
)
3227 return write_hvipriox(env
, 0, env
->hviprio
, val
);
3230 static int read_hviprio1h(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3232 return read_hvipriox(env
, 4, env
->hviprio
, val
);
3235 static int write_hviprio1h(CPURISCVState
*env
, int csrno
, target_ulong val
)
3237 return write_hvipriox(env
, 4, env
->hviprio
, val
);
3240 static int read_hviprio2(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3242 return read_hvipriox(env
, 8, env
->hviprio
, val
);
3245 static int write_hviprio2(CPURISCVState
*env
, int csrno
, target_ulong val
)
3247 return write_hvipriox(env
, 8, env
->hviprio
, val
);
3250 static int read_hviprio2h(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3252 return read_hvipriox(env
, 12, env
->hviprio
, val
);
3255 static int write_hviprio2h(CPURISCVState
*env
, int csrno
, target_ulong val
)
3257 return write_hvipriox(env
, 12, env
->hviprio
, val
);
3260 /* Virtual CSR Registers */
3261 static RISCVException
read_vsstatus(CPURISCVState
*env
, int csrno
,
3264 *val
= env
->vsstatus
;
3265 return RISCV_EXCP_NONE
;
3268 static RISCVException
write_vsstatus(CPURISCVState
*env
, int csrno
,
3271 uint64_t mask
= (target_ulong
)-1;
3272 if ((val
& VSSTATUS64_UXL
) == 0) {
3273 mask
&= ~VSSTATUS64_UXL
;
3275 env
->vsstatus
= (env
->vsstatus
& ~mask
) | (uint64_t)val
;
3276 return RISCV_EXCP_NONE
;
3279 static int read_vstvec(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3282 return RISCV_EXCP_NONE
;
3285 static RISCVException
write_vstvec(CPURISCVState
*env
, int csrno
,
3289 return RISCV_EXCP_NONE
;
3292 static RISCVException
read_vsscratch(CPURISCVState
*env
, int csrno
,
3295 *val
= env
->vsscratch
;
3296 return RISCV_EXCP_NONE
;
3299 static RISCVException
write_vsscratch(CPURISCVState
*env
, int csrno
,
3302 env
->vsscratch
= val
;
3303 return RISCV_EXCP_NONE
;
3306 static RISCVException
read_vsepc(CPURISCVState
*env
, int csrno
,
3310 return RISCV_EXCP_NONE
;
3313 static RISCVException
write_vsepc(CPURISCVState
*env
, int csrno
,
3317 return RISCV_EXCP_NONE
;
3320 static RISCVException
read_vscause(CPURISCVState
*env
, int csrno
,
3323 *val
= env
->vscause
;
3324 return RISCV_EXCP_NONE
;
3327 static RISCVException
write_vscause(CPURISCVState
*env
, int csrno
,
3331 return RISCV_EXCP_NONE
;
3334 static RISCVException
read_vstval(CPURISCVState
*env
, int csrno
,
3338 return RISCV_EXCP_NONE
;
3341 static RISCVException
write_vstval(CPURISCVState
*env
, int csrno
,
3345 return RISCV_EXCP_NONE
;
3348 static RISCVException
read_vsatp(CPURISCVState
*env
, int csrno
,
3352 return RISCV_EXCP_NONE
;
3355 static RISCVException
write_vsatp(CPURISCVState
*env
, int csrno
,
3359 return RISCV_EXCP_NONE
;
3362 static RISCVException
read_mtval2(CPURISCVState
*env
, int csrno
,
3366 return RISCV_EXCP_NONE
;
3369 static RISCVException
write_mtval2(CPURISCVState
*env
, int csrno
,
3373 return RISCV_EXCP_NONE
;
3376 static RISCVException
read_mtinst(CPURISCVState
*env
, int csrno
,
3380 return RISCV_EXCP_NONE
;
3383 static RISCVException
write_mtinst(CPURISCVState
*env
, int csrno
,
3387 return RISCV_EXCP_NONE
;
3390 /* Physical Memory Protection */
3391 static RISCVException
read_mseccfg(CPURISCVState
*env
, int csrno
,
3394 *val
= mseccfg_csr_read(env
);
3395 return RISCV_EXCP_NONE
;
3398 static RISCVException
write_mseccfg(CPURISCVState
*env
, int csrno
,
3401 mseccfg_csr_write(env
, val
);
3402 return RISCV_EXCP_NONE
;
3405 static RISCVException
read_pmpcfg(CPURISCVState
*env
, int csrno
,
3408 uint32_t reg_index
= csrno
- CSR_PMPCFG0
;
3410 *val
= pmpcfg_csr_read(env
, reg_index
);
3411 return RISCV_EXCP_NONE
;
3414 static RISCVException
write_pmpcfg(CPURISCVState
*env
, int csrno
,
3417 uint32_t reg_index
= csrno
- CSR_PMPCFG0
;
3419 pmpcfg_csr_write(env
, reg_index
, val
);
3420 return RISCV_EXCP_NONE
;
3423 static RISCVException
read_pmpaddr(CPURISCVState
*env
, int csrno
,
3426 *val
= pmpaddr_csr_read(env
, csrno
- CSR_PMPADDR0
);
3427 return RISCV_EXCP_NONE
;
3430 static RISCVException
write_pmpaddr(CPURISCVState
*env
, int csrno
,
3433 pmpaddr_csr_write(env
, csrno
- CSR_PMPADDR0
, val
);
3434 return RISCV_EXCP_NONE
;
3437 static RISCVException
read_tselect(CPURISCVState
*env
, int csrno
,
3440 *val
= tselect_csr_read(env
);
3441 return RISCV_EXCP_NONE
;
3444 static RISCVException
write_tselect(CPURISCVState
*env
, int csrno
,
3447 tselect_csr_write(env
, val
);
3448 return RISCV_EXCP_NONE
;
3451 static RISCVException
read_tdata(CPURISCVState
*env
, int csrno
,
3454 /* return 0 in tdata1 to end the trigger enumeration */
3455 if (env
->trigger_cur
>= RV_MAX_TRIGGERS
&& csrno
== CSR_TDATA1
) {
3457 return RISCV_EXCP_NONE
;
3460 if (!tdata_available(env
, csrno
- CSR_TDATA1
)) {
3461 return RISCV_EXCP_ILLEGAL_INST
;
3464 *val
= tdata_csr_read(env
, csrno
- CSR_TDATA1
);
3465 return RISCV_EXCP_NONE
;
3468 static RISCVException
write_tdata(CPURISCVState
*env
, int csrno
,
3471 if (!tdata_available(env
, csrno
- CSR_TDATA1
)) {
3472 return RISCV_EXCP_ILLEGAL_INST
;
3475 tdata_csr_write(env
, csrno
- CSR_TDATA1
, val
);
3476 return RISCV_EXCP_NONE
;
3479 static RISCVException
read_tinfo(CPURISCVState
*env
, int csrno
,
3482 *val
= tinfo_csr_read(env
);
3483 return RISCV_EXCP_NONE
;
3487 * Functions to access Pointer Masking feature registers
3488 * We have to check if current priv lvl could modify
3491 static bool check_pm_current_disabled(CPURISCVState
*env
, int csrno
)
3493 int csr_priv
= get_field(csrno
, 0x300);
3496 if (env
->debugger
) {
3500 * If priv lvls differ that means we're accessing csr from higher priv lvl,
3501 * so allow the access
3503 if (env
->priv
!= csr_priv
) {
3506 switch (env
->priv
) {
3508 pm_current
= get_field(env
->mmte
, M_PM_CURRENT
);
3511 pm_current
= get_field(env
->mmte
, S_PM_CURRENT
);
3514 pm_current
= get_field(env
->mmte
, U_PM_CURRENT
);
3517 g_assert_not_reached();
3519 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
3523 static RISCVException
read_mmte(CPURISCVState
*env
, int csrno
,
3526 *val
= env
->mmte
& MMTE_MASK
;
3527 return RISCV_EXCP_NONE
;
3530 static RISCVException
write_mmte(CPURISCVState
*env
, int csrno
,
3534 target_ulong wpri_val
= val
& MMTE_MASK
;
3536 if (val
!= wpri_val
) {
3537 qemu_log_mask(LOG_GUEST_ERROR
, "%s" TARGET_FMT_lx
" %s"
3538 TARGET_FMT_lx
"\n", "MMTE: WPRI violation written 0x",
3539 val
, "vs expected 0x", wpri_val
);
3541 /* for machine mode pm.current is hardwired to 1 */
3542 wpri_val
|= MMTE_M_PM_CURRENT
;
3544 /* hardwiring pm.instruction bit to 0, since it's not supported yet */
3545 wpri_val
&= ~(MMTE_M_PM_INSN
| MMTE_S_PM_INSN
| MMTE_U_PM_INSN
);
3546 env
->mmte
= wpri_val
| EXT_STATUS_DIRTY
;
3547 riscv_cpu_update_mask(env
);
3549 /* Set XS and SD bits, since PM CSRs are dirty */
3550 mstatus
= env
->mstatus
| MSTATUS_XS
;
3551 write_mstatus(env
, csrno
, mstatus
);
3552 return RISCV_EXCP_NONE
;
3555 static RISCVException
read_smte(CPURISCVState
*env
, int csrno
,
3558 *val
= env
->mmte
& SMTE_MASK
;
3559 return RISCV_EXCP_NONE
;
3562 static RISCVException
write_smte(CPURISCVState
*env
, int csrno
,
3565 target_ulong wpri_val
= val
& SMTE_MASK
;
3567 if (val
!= wpri_val
) {
3568 qemu_log_mask(LOG_GUEST_ERROR
, "%s" TARGET_FMT_lx
" %s"
3569 TARGET_FMT_lx
"\n", "SMTE: WPRI violation written 0x",
3570 val
, "vs expected 0x", wpri_val
);
3573 /* if pm.current==0 we can't modify current PM CSRs */
3574 if (check_pm_current_disabled(env
, csrno
)) {
3575 return RISCV_EXCP_NONE
;
3578 wpri_val
|= (env
->mmte
& ~SMTE_MASK
);
3579 write_mmte(env
, csrno
, wpri_val
);
3580 return RISCV_EXCP_NONE
;
3583 static RISCVException
read_umte(CPURISCVState
*env
, int csrno
,
3586 *val
= env
->mmte
& UMTE_MASK
;
3587 return RISCV_EXCP_NONE
;
3590 static RISCVException
write_umte(CPURISCVState
*env
, int csrno
,
3593 target_ulong wpri_val
= val
& UMTE_MASK
;
3595 if (val
!= wpri_val
) {
3596 qemu_log_mask(LOG_GUEST_ERROR
, "%s" TARGET_FMT_lx
" %s"
3597 TARGET_FMT_lx
"\n", "UMTE: WPRI violation written 0x",
3598 val
, "vs expected 0x", wpri_val
);
3601 if (check_pm_current_disabled(env
, csrno
)) {
3602 return RISCV_EXCP_NONE
;
3605 wpri_val
|= (env
->mmte
& ~UMTE_MASK
);
3606 write_mmte(env
, csrno
, wpri_val
);
3607 return RISCV_EXCP_NONE
;
3610 static RISCVException
read_mpmmask(CPURISCVState
*env
, int csrno
,
3613 *val
= env
->mpmmask
;
3614 return RISCV_EXCP_NONE
;
3617 static RISCVException
write_mpmmask(CPURISCVState
*env
, int csrno
,
3623 if ((env
->priv
== PRV_M
) && (env
->mmte
& M_PM_ENABLE
)) {
3624 env
->cur_pmmask
= val
;
3626 env
->mmte
|= EXT_STATUS_DIRTY
;
3628 /* Set XS and SD bits, since PM CSRs are dirty */
3629 mstatus
= env
->mstatus
| MSTATUS_XS
;
3630 write_mstatus(env
, csrno
, mstatus
);
3631 return RISCV_EXCP_NONE
;
3634 static RISCVException
read_spmmask(CPURISCVState
*env
, int csrno
,
3637 *val
= env
->spmmask
;
3638 return RISCV_EXCP_NONE
;
3641 static RISCVException
write_spmmask(CPURISCVState
*env
, int csrno
,
3646 /* if pm.current==0 we can't modify current PM CSRs */
3647 if (check_pm_current_disabled(env
, csrno
)) {
3648 return RISCV_EXCP_NONE
;
3651 if ((env
->priv
== PRV_S
) && (env
->mmte
& S_PM_ENABLE
)) {
3652 env
->cur_pmmask
= val
;
3654 env
->mmte
|= EXT_STATUS_DIRTY
;
3656 /* Set XS and SD bits, since PM CSRs are dirty */
3657 mstatus
= env
->mstatus
| MSTATUS_XS
;
3658 write_mstatus(env
, csrno
, mstatus
);
3659 return RISCV_EXCP_NONE
;
3662 static RISCVException
read_upmmask(CPURISCVState
*env
, int csrno
,
3665 *val
= env
->upmmask
;
3666 return RISCV_EXCP_NONE
;
3669 static RISCVException
write_upmmask(CPURISCVState
*env
, int csrno
,
3674 /* if pm.current==0 we can't modify current PM CSRs */
3675 if (check_pm_current_disabled(env
, csrno
)) {
3676 return RISCV_EXCP_NONE
;
3679 if ((env
->priv
== PRV_U
) && (env
->mmte
& U_PM_ENABLE
)) {
3680 env
->cur_pmmask
= val
;
3682 env
->mmte
|= EXT_STATUS_DIRTY
;
3684 /* Set XS and SD bits, since PM CSRs are dirty */
3685 mstatus
= env
->mstatus
| MSTATUS_XS
;
3686 write_mstatus(env
, csrno
, mstatus
);
3687 return RISCV_EXCP_NONE
;
3690 static RISCVException
read_mpmbase(CPURISCVState
*env
, int csrno
,
3693 *val
= env
->mpmbase
;
3694 return RISCV_EXCP_NONE
;
3697 static RISCVException
write_mpmbase(CPURISCVState
*env
, int csrno
,
3703 if ((env
->priv
== PRV_M
) && (env
->mmte
& M_PM_ENABLE
)) {
3704 env
->cur_pmbase
= val
;
3706 env
->mmte
|= EXT_STATUS_DIRTY
;
3708 /* Set XS and SD bits, since PM CSRs are dirty */
3709 mstatus
= env
->mstatus
| MSTATUS_XS
;
3710 write_mstatus(env
, csrno
, mstatus
);
3711 return RISCV_EXCP_NONE
;
3714 static RISCVException
read_spmbase(CPURISCVState
*env
, int csrno
,
3717 *val
= env
->spmbase
;
3718 return RISCV_EXCP_NONE
;
3721 static RISCVException
write_spmbase(CPURISCVState
*env
, int csrno
,
3726 /* if pm.current==0 we can't modify current PM CSRs */
3727 if (check_pm_current_disabled(env
, csrno
)) {
3728 return RISCV_EXCP_NONE
;
3731 if ((env
->priv
== PRV_S
) && (env
->mmte
& S_PM_ENABLE
)) {
3732 env
->cur_pmbase
= val
;
3734 env
->mmte
|= EXT_STATUS_DIRTY
;
3736 /* Set XS and SD bits, since PM CSRs are dirty */
3737 mstatus
= env
->mstatus
| MSTATUS_XS
;
3738 write_mstatus(env
, csrno
, mstatus
);
3739 return RISCV_EXCP_NONE
;
3742 static RISCVException
read_upmbase(CPURISCVState
*env
, int csrno
,
3745 *val
= env
->upmbase
;
3746 return RISCV_EXCP_NONE
;
3749 static RISCVException
write_upmbase(CPURISCVState
*env
, int csrno
,
3754 /* if pm.current==0 we can't modify current PM CSRs */
3755 if (check_pm_current_disabled(env
, csrno
)) {
3756 return RISCV_EXCP_NONE
;
3759 if ((env
->priv
== PRV_U
) && (env
->mmte
& U_PM_ENABLE
)) {
3760 env
->cur_pmbase
= val
;
3762 env
->mmte
|= EXT_STATUS_DIRTY
;
3764 /* Set XS and SD bits, since PM CSRs are dirty */
3765 mstatus
= env
->mstatus
| MSTATUS_XS
;
3766 write_mstatus(env
, csrno
, mstatus
);
3767 return RISCV_EXCP_NONE
;
3772 /* Crypto Extension */
3773 static RISCVException
rmw_seed(CPURISCVState
*env
, int csrno
,
3774 target_ulong
*ret_value
,
3775 target_ulong new_value
,
3776 target_ulong write_mask
)
3779 Error
*random_e
= NULL
;
3783 random_r
= qemu_guest_getrandom(&random_v
, 2, &random_e
);
3784 if (unlikely(random_r
< 0)) {
3786 * Failed, for unknown reasons in the crypto subsystem.
3787 * The best we can do is log the reason and return a
3788 * failure indication to the guest. There is no reason
3789 * we know to expect the failure to be transitory, so
3790 * indicate DEAD to avoid having the guest spin on WAIT.
3792 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
3793 __func__
, error_get_pretty(random_e
));
3794 error_free(random_e
);
3795 rval
= SEED_OPST_DEAD
;
3797 rval
= random_v
| SEED_OPST_ES16
;
3804 return RISCV_EXCP_NONE
;
3808 * riscv_csrrw - read and/or update control and status register
3810 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0);
3811 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1);
3812 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value);
3813 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value);
3816 static inline RISCVException
riscv_csrrw_check(CPURISCVState
*env
,
3820 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
3821 bool read_only
= get_field(csrno
, 0xC00) == 3;
3822 int csr_min_priv
= csr_ops
[csrno
].min_priv_ver
;
3824 /* ensure the CSR extension is enabled */
3825 if (!riscv_cpu_cfg(env
)->ext_icsr
) {
3826 return RISCV_EXCP_ILLEGAL_INST
;
3829 /* ensure CSR is implemented by checking predicate */
3830 if (!csr_ops
[csrno
].predicate
) {
3831 return RISCV_EXCP_ILLEGAL_INST
;
3834 /* privileged spec version check */
3835 if (env
->priv_ver
< csr_min_priv
) {
3836 return RISCV_EXCP_ILLEGAL_INST
;
3839 /* read / write check */
3840 if (write_mask
&& read_only
) {
3841 return RISCV_EXCP_ILLEGAL_INST
;
3845 * The predicate() not only does existence check but also does some
3846 * access control check which triggers for example virtual instruction
3847 * exception in some cases. When writing read-only CSRs in those cases
3848 * illegal instruction exception should be triggered instead of virtual
3849 * instruction exception. Hence this comes after the read / write check.
3851 RISCVException ret
= csr_ops
[csrno
].predicate(env
, csrno
);
3852 if (ret
!= RISCV_EXCP_NONE
) {
3856 #if !defined(CONFIG_USER_ONLY)
3857 int csr_priv
, effective_priv
= env
->priv
;
3859 if (riscv_has_ext(env
, RVH
) && env
->priv
== PRV_S
&&
3860 !env
->virt_enabled
) {
3862 * We are in HS mode. Add 1 to the effective privledge level to
3863 * allow us to access the Hypervisor CSRs.
3868 csr_priv
= get_field(csrno
, 0x300);
3869 if (!env
->debugger
&& (effective_priv
< csr_priv
)) {
3870 if (csr_priv
== (PRV_S
+ 1) && env
->virt_enabled
) {
3871 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
3873 return RISCV_EXCP_ILLEGAL_INST
;
3876 return RISCV_EXCP_NONE
;
3879 static RISCVException
riscv_csrrw_do64(CPURISCVState
*env
, int csrno
,
3880 target_ulong
*ret_value
,
3881 target_ulong new_value
,
3882 target_ulong write_mask
)
3885 target_ulong old_value
;
3887 /* execute combined read/write operation if it exists */
3888 if (csr_ops
[csrno
].op
) {
3889 return csr_ops
[csrno
].op(env
, csrno
, ret_value
, new_value
, write_mask
);
3892 /* if no accessor exists then return failure */
3893 if (!csr_ops
[csrno
].read
) {
3894 return RISCV_EXCP_ILLEGAL_INST
;
3896 /* read old value */
3897 ret
= csr_ops
[csrno
].read(env
, csrno
, &old_value
);
3898 if (ret
!= RISCV_EXCP_NONE
) {
3902 /* write value if writable and write mask set, otherwise drop writes */
3904 new_value
= (old_value
& ~write_mask
) | (new_value
& write_mask
);
3905 if (csr_ops
[csrno
].write
) {
3906 ret
= csr_ops
[csrno
].write(env
, csrno
, new_value
);
3907 if (ret
!= RISCV_EXCP_NONE
) {
3913 /* return old value */
3915 *ret_value
= old_value
;
3918 return RISCV_EXCP_NONE
;
3921 RISCVException
riscv_csrrw(CPURISCVState
*env
, int csrno
,
3922 target_ulong
*ret_value
,
3923 target_ulong new_value
, target_ulong write_mask
)
3925 RISCVException ret
= riscv_csrrw_check(env
, csrno
, write_mask
);
3926 if (ret
!= RISCV_EXCP_NONE
) {
3930 return riscv_csrrw_do64(env
, csrno
, ret_value
, new_value
, write_mask
);
3933 static RISCVException
riscv_csrrw_do128(CPURISCVState
*env
, int csrno
,
3941 /* read old value */
3942 ret
= csr_ops
[csrno
].read128(env
, csrno
, &old_value
);
3943 if (ret
!= RISCV_EXCP_NONE
) {
3947 /* write value if writable and write mask set, otherwise drop writes */
3948 if (int128_nz(write_mask
)) {
3949 new_value
= int128_or(int128_and(old_value
, int128_not(write_mask
)),
3950 int128_and(new_value
, write_mask
));
3951 if (csr_ops
[csrno
].write128
) {
3952 ret
= csr_ops
[csrno
].write128(env
, csrno
, new_value
);
3953 if (ret
!= RISCV_EXCP_NONE
) {
3956 } else if (csr_ops
[csrno
].write
) {
3957 /* avoids having to write wrappers for all registers */
3958 ret
= csr_ops
[csrno
].write(env
, csrno
, int128_getlo(new_value
));
3959 if (ret
!= RISCV_EXCP_NONE
) {
3965 /* return old value */
3967 *ret_value
= old_value
;
3970 return RISCV_EXCP_NONE
;
3973 RISCVException
riscv_csrrw_i128(CPURISCVState
*env
, int csrno
,
3975 Int128 new_value
, Int128 write_mask
)
3979 ret
= riscv_csrrw_check(env
, csrno
, int128_nz(write_mask
));
3980 if (ret
!= RISCV_EXCP_NONE
) {
3984 if (csr_ops
[csrno
].read128
) {
3985 return riscv_csrrw_do128(env
, csrno
, ret_value
, new_value
, write_mask
);
3989 * Fall back to 64-bit version for now, if the 128-bit alternative isn't
3991 * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
3992 * significant), for those, this fallback is correctly handling the
3995 target_ulong old_value
;
3996 ret
= riscv_csrrw_do64(env
, csrno
, &old_value
,
3997 int128_getlo(new_value
),
3998 int128_getlo(write_mask
));
3999 if (ret
== RISCV_EXCP_NONE
&& ret_value
) {
4000 *ret_value
= int128_make64(old_value
);
4006 * Debugger support. If not in user mode, set env->debugger before the
4007 * riscv_csrrw call and clear it after the call.
4009 RISCVException
riscv_csrrw_debug(CPURISCVState
*env
, int csrno
,
4010 target_ulong
*ret_value
,
4011 target_ulong new_value
,
4012 target_ulong write_mask
)
4015 #if !defined(CONFIG_USER_ONLY)
4016 env
->debugger
= true;
4018 ret
= riscv_csrrw(env
, csrno
, ret_value
, new_value
, write_mask
);
4019 #if !defined(CONFIG_USER_ONLY)
4020 env
->debugger
= false;
4025 static RISCVException
read_jvt(CPURISCVState
*env
, int csrno
,
4029 return RISCV_EXCP_NONE
;
4032 static RISCVException
write_jvt(CPURISCVState
*env
, int csrno
,
4036 return RISCV_EXCP_NONE
;
4040 * Control and Status Register function table
4041 * riscv_csr_operations::predicate() must be provided for an implemented CSR
4043 riscv_csr_operations csr_ops
[CSR_TABLE_SIZE
] = {
4044 /* User Floating-Point CSRs */
4045 [CSR_FFLAGS
] = { "fflags", fs
, read_fflags
, write_fflags
},
4046 [CSR_FRM
] = { "frm", fs
, read_frm
, write_frm
},
4047 [CSR_FCSR
] = { "fcsr", fs
, read_fcsr
, write_fcsr
},
4049 [CSR_VSTART
] = { "vstart", vs
, read_vstart
, write_vstart
},
4050 [CSR_VXSAT
] = { "vxsat", vs
, read_vxsat
, write_vxsat
},
4051 [CSR_VXRM
] = { "vxrm", vs
, read_vxrm
, write_vxrm
},
4052 [CSR_VCSR
] = { "vcsr", vs
, read_vcsr
, write_vcsr
},
4053 [CSR_VL
] = { "vl", vs
, read_vl
},
4054 [CSR_VTYPE
] = { "vtype", vs
, read_vtype
},
4055 [CSR_VLENB
] = { "vlenb", vs
, read_vlenb
},
4056 /* User Timers and Counters */
4057 [CSR_CYCLE
] = { "cycle", ctr
, read_hpmcounter
},
4058 [CSR_INSTRET
] = { "instret", ctr
, read_hpmcounter
},
4059 [CSR_CYCLEH
] = { "cycleh", ctr32
, read_hpmcounterh
},
4060 [CSR_INSTRETH
] = { "instreth", ctr32
, read_hpmcounterh
},
4063 * In privileged mode, the monitor will have to emulate TIME CSRs only if
4064 * rdtime callback is not provided by machine/platform emulation.
4066 [CSR_TIME
] = { "time", ctr
, read_time
},
4067 [CSR_TIMEH
] = { "timeh", ctr32
, read_timeh
},
4069 /* Crypto Extension */
4070 [CSR_SEED
] = { "seed", seed
, NULL
, NULL
, rmw_seed
},
4072 /* Zcmt Extension */
4073 [CSR_JVT
] = {"jvt", zcmt
, read_jvt
, write_jvt
},
4075 #if !defined(CONFIG_USER_ONLY)
4076 /* Machine Timers and Counters */
4077 [CSR_MCYCLE
] = { "mcycle", any
, read_hpmcounter
,
4078 write_mhpmcounter
},
4079 [CSR_MINSTRET
] = { "minstret", any
, read_hpmcounter
,
4080 write_mhpmcounter
},
4081 [CSR_MCYCLEH
] = { "mcycleh", any32
, read_hpmcounterh
,
4082 write_mhpmcounterh
},
4083 [CSR_MINSTRETH
] = { "minstreth", any32
, read_hpmcounterh
,
4084 write_mhpmcounterh
},
4086 /* Machine Information Registers */
4087 [CSR_MVENDORID
] = { "mvendorid", any
, read_mvendorid
},
4088 [CSR_MARCHID
] = { "marchid", any
, read_marchid
},
4089 [CSR_MIMPID
] = { "mimpid", any
, read_mimpid
},
4090 [CSR_MHARTID
] = { "mhartid", any
, read_mhartid
},
4092 [CSR_MCONFIGPTR
] = { "mconfigptr", any
, read_zero
,
4093 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4094 /* Machine Trap Setup */
4095 [CSR_MSTATUS
] = { "mstatus", any
, read_mstatus
, write_mstatus
,
4096 NULL
, read_mstatus_i128
},
4097 [CSR_MISA
] = { "misa", any
, read_misa
, write_misa
,
4098 NULL
, read_misa_i128
},
4099 [CSR_MIDELEG
] = { "mideleg", any
, NULL
, NULL
, rmw_mideleg
},
4100 [CSR_MEDELEG
] = { "medeleg", any
, read_medeleg
, write_medeleg
},
4101 [CSR_MIE
] = { "mie", any
, NULL
, NULL
, rmw_mie
},
4102 [CSR_MTVEC
] = { "mtvec", any
, read_mtvec
, write_mtvec
},
4103 [CSR_MCOUNTEREN
] = { "mcounteren", umode
, read_mcounteren
,
4106 [CSR_MSTATUSH
] = { "mstatush", any32
, read_mstatush
,
4109 /* Machine Trap Handling */
4110 [CSR_MSCRATCH
] = { "mscratch", any
, read_mscratch
, write_mscratch
,
4111 NULL
, read_mscratch_i128
, write_mscratch_i128
},
4112 [CSR_MEPC
] = { "mepc", any
, read_mepc
, write_mepc
},
4113 [CSR_MCAUSE
] = { "mcause", any
, read_mcause
, write_mcause
},
4114 [CSR_MTVAL
] = { "mtval", any
, read_mtval
, write_mtval
},
4115 [CSR_MIP
] = { "mip", any
, NULL
, NULL
, rmw_mip
},
4117 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
4118 [CSR_MISELECT
] = { "miselect", aia_any
, NULL
, NULL
, rmw_xiselect
},
4119 [CSR_MIREG
] = { "mireg", aia_any
, NULL
, NULL
, rmw_xireg
},
4121 /* Machine-Level Interrupts (AIA) */
4122 [CSR_MTOPEI
] = { "mtopei", aia_any
, NULL
, NULL
, rmw_xtopei
},
4123 [CSR_MTOPI
] = { "mtopi", aia_any
, read_mtopi
},
4125 /* Virtual Interrupts for Supervisor Level (AIA) */
4126 [CSR_MVIEN
] = { "mvien", aia_any
, read_zero
, write_ignore
},
4127 [CSR_MVIP
] = { "mvip", aia_any
, read_zero
, write_ignore
},
4129 /* Machine-Level High-Half CSRs (AIA) */
4130 [CSR_MIDELEGH
] = { "midelegh", aia_any32
, NULL
, NULL
, rmw_midelegh
},
4131 [CSR_MIEH
] = { "mieh", aia_any32
, NULL
, NULL
, rmw_mieh
},
4132 [CSR_MVIENH
] = { "mvienh", aia_any32
, read_zero
, write_ignore
},
4133 [CSR_MVIPH
] = { "mviph", aia_any32
, read_zero
, write_ignore
},
4134 [CSR_MIPH
] = { "miph", aia_any32
, NULL
, NULL
, rmw_miph
},
4136 /* Execution environment configuration */
4137 [CSR_MENVCFG
] = { "menvcfg", umode
, read_menvcfg
, write_menvcfg
,
4138 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4139 [CSR_MENVCFGH
] = { "menvcfgh", umode32
, read_menvcfgh
, write_menvcfgh
,
4140 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4141 [CSR_SENVCFG
] = { "senvcfg", smode
, read_senvcfg
, write_senvcfg
,
4142 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4143 [CSR_HENVCFG
] = { "henvcfg", hmode
, read_henvcfg
, write_henvcfg
,
4144 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4145 [CSR_HENVCFGH
] = { "henvcfgh", hmode32
, read_henvcfgh
, write_henvcfgh
,
4146 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4148 /* Smstateen extension CSRs */
4149 [CSR_MSTATEEN0
] = { "mstateen0", mstateen
, read_mstateen
, write_mstateen0
,
4150 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4151 [CSR_MSTATEEN0H
] = { "mstateen0h", mstateen
, read_mstateenh
,
4153 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4154 [CSR_MSTATEEN1
] = { "mstateen1", mstateen
, read_mstateen
,
4156 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4157 [CSR_MSTATEEN1H
] = { "mstateen1h", mstateen
, read_mstateenh
,
4158 write_mstateenh_1_3
,
4159 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4160 [CSR_MSTATEEN2
] = { "mstateen2", mstateen
, read_mstateen
,
4162 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4163 [CSR_MSTATEEN2H
] = { "mstateen2h", mstateen
, read_mstateenh
,
4164 write_mstateenh_1_3
,
4165 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4166 [CSR_MSTATEEN3
] = { "mstateen3", mstateen
, read_mstateen
,
4168 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4169 [CSR_MSTATEEN3H
] = { "mstateen3h", mstateen
, read_mstateenh
,
4170 write_mstateenh_1_3
,
4171 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4172 [CSR_HSTATEEN0
] = { "hstateen0", hstateen
, read_hstateen
, write_hstateen0
,
4173 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4174 [CSR_HSTATEEN0H
] = { "hstateen0h", hstateenh
, read_hstateenh
,
4176 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4177 [CSR_HSTATEEN1
] = { "hstateen1", hstateen
, read_hstateen
,
4179 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4180 [CSR_HSTATEEN1H
] = { "hstateen1h", hstateenh
, read_hstateenh
,
4181 write_hstateenh_1_3
,
4182 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4183 [CSR_HSTATEEN2
] = { "hstateen2", hstateen
, read_hstateen
,
4185 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4186 [CSR_HSTATEEN2H
] = { "hstateen2h", hstateenh
, read_hstateenh
,
4187 write_hstateenh_1_3
,
4188 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4189 [CSR_HSTATEEN3
] = { "hstateen3", hstateen
, read_hstateen
,
4191 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4192 [CSR_HSTATEEN3H
] = { "hstateen3h", hstateenh
, read_hstateenh
,
4193 write_hstateenh_1_3
,
4194 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4195 [CSR_SSTATEEN0
] = { "sstateen0", sstateen
, read_sstateen
, write_sstateen0
,
4196 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4197 [CSR_SSTATEEN1
] = { "sstateen1", sstateen
, read_sstateen
,
4199 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4200 [CSR_SSTATEEN2
] = { "sstateen2", sstateen
, read_sstateen
,
4202 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4203 [CSR_SSTATEEN3
] = { "sstateen3", sstateen
, read_sstateen
,
4205 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4207 /* Supervisor Trap Setup */
4208 [CSR_SSTATUS
] = { "sstatus", smode
, read_sstatus
, write_sstatus
,
4209 NULL
, read_sstatus_i128
},
4210 [CSR_SIE
] = { "sie", smode
, NULL
, NULL
, rmw_sie
},
4211 [CSR_STVEC
] = { "stvec", smode
, read_stvec
, write_stvec
},
4212 [CSR_SCOUNTEREN
] = { "scounteren", smode
, read_scounteren
,
4215 /* Supervisor Trap Handling */
4216 [CSR_SSCRATCH
] = { "sscratch", smode
, read_sscratch
, write_sscratch
,
4217 NULL
, read_sscratch_i128
, write_sscratch_i128
},
4218 [CSR_SEPC
] = { "sepc", smode
, read_sepc
, write_sepc
},
4219 [CSR_SCAUSE
] = { "scause", smode
, read_scause
, write_scause
},
4220 [CSR_STVAL
] = { "stval", smode
, read_stval
, write_stval
},
4221 [CSR_SIP
] = { "sip", smode
, NULL
, NULL
, rmw_sip
},
4222 [CSR_STIMECMP
] = { "stimecmp", sstc
, read_stimecmp
, write_stimecmp
,
4223 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4224 [CSR_STIMECMPH
] = { "stimecmph", sstc_32
, read_stimecmph
, write_stimecmph
,
4225 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4226 [CSR_VSTIMECMP
] = { "vstimecmp", sstc
, read_vstimecmp
,
4228 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4229 [CSR_VSTIMECMPH
] = { "vstimecmph", sstc_32
, read_vstimecmph
,
4231 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4233 /* Supervisor Protection and Translation */
4234 [CSR_SATP
] = { "satp", satp
, read_satp
, write_satp
},
4236 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
4237 [CSR_SISELECT
] = { "siselect", aia_smode
, NULL
, NULL
, rmw_xiselect
},
4238 [CSR_SIREG
] = { "sireg", aia_smode
, NULL
, NULL
, rmw_xireg
},
4240 /* Supervisor-Level Interrupts (AIA) */
4241 [CSR_STOPEI
] = { "stopei", aia_smode
, NULL
, NULL
, rmw_xtopei
},
4242 [CSR_STOPI
] = { "stopi", aia_smode
, read_stopi
},
4244 /* Supervisor-Level High-Half CSRs (AIA) */
4245 [CSR_SIEH
] = { "sieh", aia_smode32
, NULL
, NULL
, rmw_sieh
},
4246 [CSR_SIPH
] = { "siph", aia_smode32
, NULL
, NULL
, rmw_siph
},
4248 [CSR_HSTATUS
] = { "hstatus", hmode
, read_hstatus
, write_hstatus
,
4249 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4250 [CSR_HEDELEG
] = { "hedeleg", hmode
, read_hedeleg
, write_hedeleg
,
4251 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4252 [CSR_HIDELEG
] = { "hideleg", hmode
, NULL
, NULL
, rmw_hideleg
,
4253 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4254 [CSR_HVIP
] = { "hvip", hmode
, NULL
, NULL
, rmw_hvip
,
4255 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4256 [CSR_HIP
] = { "hip", hmode
, NULL
, NULL
, rmw_hip
,
4257 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4258 [CSR_HIE
] = { "hie", hmode
, NULL
, NULL
, rmw_hie
,
4259 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4260 [CSR_HCOUNTEREN
] = { "hcounteren", hmode
, read_hcounteren
,
4262 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4263 [CSR_HGEIE
] = { "hgeie", hmode
, read_hgeie
, write_hgeie
,
4264 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4265 [CSR_HTVAL
] = { "htval", hmode
, read_htval
, write_htval
,
4266 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4267 [CSR_HTINST
] = { "htinst", hmode
, read_htinst
, write_htinst
,
4268 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4269 [CSR_HGEIP
] = { "hgeip", hmode
, read_hgeip
,
4270 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4271 [CSR_HGATP
] = { "hgatp", hgatp
, read_hgatp
, write_hgatp
,
4272 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4273 [CSR_HTIMEDELTA
] = { "htimedelta", hmode
, read_htimedelta
,
4275 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4276 [CSR_HTIMEDELTAH
] = { "htimedeltah", hmode32
, read_htimedeltah
,
4278 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4280 [CSR_VSSTATUS
] = { "vsstatus", hmode
, read_vsstatus
,
4282 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4283 [CSR_VSIP
] = { "vsip", hmode
, NULL
, NULL
, rmw_vsip
,
4284 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4285 [CSR_VSIE
] = { "vsie", hmode
, NULL
, NULL
, rmw_vsie
,
4286 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4287 [CSR_VSTVEC
] = { "vstvec", hmode
, read_vstvec
, write_vstvec
,
4288 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4289 [CSR_VSSCRATCH
] = { "vsscratch", hmode
, read_vsscratch
,
4291 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4292 [CSR_VSEPC
] = { "vsepc", hmode
, read_vsepc
, write_vsepc
,
4293 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4294 [CSR_VSCAUSE
] = { "vscause", hmode
, read_vscause
, write_vscause
,
4295 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4296 [CSR_VSTVAL
] = { "vstval", hmode
, read_vstval
, write_vstval
,
4297 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4298 [CSR_VSATP
] = { "vsatp", hmode
, read_vsatp
, write_vsatp
,
4299 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4301 [CSR_MTVAL2
] = { "mtval2", hmode
, read_mtval2
, write_mtval2
,
4302 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4303 [CSR_MTINST
] = { "mtinst", hmode
, read_mtinst
, write_mtinst
,
4304 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4306 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
4307 [CSR_HVIEN
] = { "hvien", aia_hmode
, read_zero
, write_ignore
},
4308 [CSR_HVICTL
] = { "hvictl", aia_hmode
, read_hvictl
,
4310 [CSR_HVIPRIO1
] = { "hviprio1", aia_hmode
, read_hviprio1
,
4312 [CSR_HVIPRIO2
] = { "hviprio2", aia_hmode
, read_hviprio2
,
4316 * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)
4318 [CSR_VSISELECT
] = { "vsiselect", aia_hmode
, NULL
, NULL
,
4320 [CSR_VSIREG
] = { "vsireg", aia_hmode
, NULL
, NULL
, rmw_xireg
},
4322 /* VS-Level Interrupts (H-extension with AIA) */
4323 [CSR_VSTOPEI
] = { "vstopei", aia_hmode
, NULL
, NULL
, rmw_xtopei
},
4324 [CSR_VSTOPI
] = { "vstopi", aia_hmode
, read_vstopi
},
4326 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
4327 [CSR_HIDELEGH
] = { "hidelegh", aia_hmode32
, NULL
, NULL
,
4329 [CSR_HVIENH
] = { "hvienh", aia_hmode32
, read_zero
,
4331 [CSR_HVIPH
] = { "hviph", aia_hmode32
, NULL
, NULL
, rmw_hviph
},
4332 [CSR_HVIPRIO1H
] = { "hviprio1h", aia_hmode32
, read_hviprio1h
,
4334 [CSR_HVIPRIO2H
] = { "hviprio2h", aia_hmode32
, read_hviprio2h
,
4336 [CSR_VSIEH
] = { "vsieh", aia_hmode32
, NULL
, NULL
, rmw_vsieh
},
4337 [CSR_VSIPH
] = { "vsiph", aia_hmode32
, NULL
, NULL
, rmw_vsiph
},
4339 /* Physical Memory Protection */
4340 [CSR_MSECCFG
] = { "mseccfg", epmp
, read_mseccfg
, write_mseccfg
,
4341 .min_priv_ver
= PRIV_VERSION_1_11_0
},
4342 [CSR_PMPCFG0
] = { "pmpcfg0", pmp
, read_pmpcfg
, write_pmpcfg
},
4343 [CSR_PMPCFG1
] = { "pmpcfg1", pmp
, read_pmpcfg
, write_pmpcfg
},
4344 [CSR_PMPCFG2
] = { "pmpcfg2", pmp
, read_pmpcfg
, write_pmpcfg
},
4345 [CSR_PMPCFG3
] = { "pmpcfg3", pmp
, read_pmpcfg
, write_pmpcfg
},
4346 [CSR_PMPADDR0
] = { "pmpaddr0", pmp
, read_pmpaddr
, write_pmpaddr
},
4347 [CSR_PMPADDR1
] = { "pmpaddr1", pmp
, read_pmpaddr
, write_pmpaddr
},
4348 [CSR_PMPADDR2
] = { "pmpaddr2", pmp
, read_pmpaddr
, write_pmpaddr
},
4349 [CSR_PMPADDR3
] = { "pmpaddr3", pmp
, read_pmpaddr
, write_pmpaddr
},
4350 [CSR_PMPADDR4
] = { "pmpaddr4", pmp
, read_pmpaddr
, write_pmpaddr
},
4351 [CSR_PMPADDR5
] = { "pmpaddr5", pmp
, read_pmpaddr
, write_pmpaddr
},
4352 [CSR_PMPADDR6
] = { "pmpaddr6", pmp
, read_pmpaddr
, write_pmpaddr
},
4353 [CSR_PMPADDR7
] = { "pmpaddr7", pmp
, read_pmpaddr
, write_pmpaddr
},
4354 [CSR_PMPADDR8
] = { "pmpaddr8", pmp
, read_pmpaddr
, write_pmpaddr
},
4355 [CSR_PMPADDR9
] = { "pmpaddr9", pmp
, read_pmpaddr
, write_pmpaddr
},
4356 [CSR_PMPADDR10
] = { "pmpaddr10", pmp
, read_pmpaddr
, write_pmpaddr
},
4357 [CSR_PMPADDR11
] = { "pmpaddr11", pmp
, read_pmpaddr
, write_pmpaddr
},
4358 [CSR_PMPADDR12
] = { "pmpaddr12", pmp
, read_pmpaddr
, write_pmpaddr
},
4359 [CSR_PMPADDR13
] = { "pmpaddr13", pmp
, read_pmpaddr
, write_pmpaddr
},
4360 [CSR_PMPADDR14
] = { "pmpaddr14", pmp
, read_pmpaddr
, write_pmpaddr
},
4361 [CSR_PMPADDR15
] = { "pmpaddr15", pmp
, read_pmpaddr
, write_pmpaddr
},
4364 [CSR_TSELECT
] = { "tselect", debug
, read_tselect
, write_tselect
},
4365 [CSR_TDATA1
] = { "tdata1", debug
, read_tdata
, write_tdata
},
4366 [CSR_TDATA2
] = { "tdata2", debug
, read_tdata
, write_tdata
},
4367 [CSR_TDATA3
] = { "tdata3", debug
, read_tdata
, write_tdata
},
4368 [CSR_TINFO
] = { "tinfo", debug
, read_tinfo
, write_ignore
},
4370 /* User Pointer Masking */
4371 [CSR_UMTE
] = { "umte", pointer_masking
, read_umte
, write_umte
},
4372 [CSR_UPMMASK
] = { "upmmask", pointer_masking
, read_upmmask
,
4374 [CSR_UPMBASE
] = { "upmbase", pointer_masking
, read_upmbase
,
4376 /* Machine Pointer Masking */
4377 [CSR_MMTE
] = { "mmte", pointer_masking
, read_mmte
, write_mmte
},
4378 [CSR_MPMMASK
] = { "mpmmask", pointer_masking
, read_mpmmask
,
4380 [CSR_MPMBASE
] = { "mpmbase", pointer_masking
, read_mpmbase
,
4382 /* Supervisor Pointer Masking */
4383 [CSR_SMTE
] = { "smte", pointer_masking
, read_smte
, write_smte
},
4384 [CSR_SPMMASK
] = { "spmmask", pointer_masking
, read_spmmask
,
4386 [CSR_SPMBASE
] = { "spmbase", pointer_masking
, read_spmbase
,
4389 /* Performance Counters */
4390 [CSR_HPMCOUNTER3
] = { "hpmcounter3", ctr
, read_hpmcounter
},
4391 [CSR_HPMCOUNTER4
] = { "hpmcounter4", ctr
, read_hpmcounter
},
4392 [CSR_HPMCOUNTER5
] = { "hpmcounter5", ctr
, read_hpmcounter
},
4393 [CSR_HPMCOUNTER6
] = { "hpmcounter6", ctr
, read_hpmcounter
},
4394 [CSR_HPMCOUNTER7
] = { "hpmcounter7", ctr
, read_hpmcounter
},
4395 [CSR_HPMCOUNTER8
] = { "hpmcounter8", ctr
, read_hpmcounter
},
4396 [CSR_HPMCOUNTER9
] = { "hpmcounter9", ctr
, read_hpmcounter
},
4397 [CSR_HPMCOUNTER10
] = { "hpmcounter10", ctr
, read_hpmcounter
},
4398 [CSR_HPMCOUNTER11
] = { "hpmcounter11", ctr
, read_hpmcounter
},
4399 [CSR_HPMCOUNTER12
] = { "hpmcounter12", ctr
, read_hpmcounter
},
4400 [CSR_HPMCOUNTER13
] = { "hpmcounter13", ctr
, read_hpmcounter
},
4401 [CSR_HPMCOUNTER14
] = { "hpmcounter14", ctr
, read_hpmcounter
},
4402 [CSR_HPMCOUNTER15
] = { "hpmcounter15", ctr
, read_hpmcounter
},
4403 [CSR_HPMCOUNTER16
] = { "hpmcounter16", ctr
, read_hpmcounter
},
4404 [CSR_HPMCOUNTER17
] = { "hpmcounter17", ctr
, read_hpmcounter
},
4405 [CSR_HPMCOUNTER18
] = { "hpmcounter18", ctr
, read_hpmcounter
},
4406 [CSR_HPMCOUNTER19
] = { "hpmcounter19", ctr
, read_hpmcounter
},
4407 [CSR_HPMCOUNTER20
] = { "hpmcounter20", ctr
, read_hpmcounter
},
4408 [CSR_HPMCOUNTER21
] = { "hpmcounter21", ctr
, read_hpmcounter
},
4409 [CSR_HPMCOUNTER22
] = { "hpmcounter22", ctr
, read_hpmcounter
},
4410 [CSR_HPMCOUNTER23
] = { "hpmcounter23", ctr
, read_hpmcounter
},
4411 [CSR_HPMCOUNTER24
] = { "hpmcounter24", ctr
, read_hpmcounter
},
4412 [CSR_HPMCOUNTER25
] = { "hpmcounter25", ctr
, read_hpmcounter
},
4413 [CSR_HPMCOUNTER26
] = { "hpmcounter26", ctr
, read_hpmcounter
},
4414 [CSR_HPMCOUNTER27
] = { "hpmcounter27", ctr
, read_hpmcounter
},
4415 [CSR_HPMCOUNTER28
] = { "hpmcounter28", ctr
, read_hpmcounter
},
4416 [CSR_HPMCOUNTER29
] = { "hpmcounter29", ctr
, read_hpmcounter
},
4417 [CSR_HPMCOUNTER30
] = { "hpmcounter30", ctr
, read_hpmcounter
},
4418 [CSR_HPMCOUNTER31
] = { "hpmcounter31", ctr
, read_hpmcounter
},
4420 [CSR_MHPMCOUNTER3
] = { "mhpmcounter3", mctr
, read_hpmcounter
,
4421 write_mhpmcounter
},
4422 [CSR_MHPMCOUNTER4
] = { "mhpmcounter4", mctr
, read_hpmcounter
,
4423 write_mhpmcounter
},
4424 [CSR_MHPMCOUNTER5
] = { "mhpmcounter5", mctr
, read_hpmcounter
,
4425 write_mhpmcounter
},
4426 [CSR_MHPMCOUNTER6
] = { "mhpmcounter6", mctr
, read_hpmcounter
,
4427 write_mhpmcounter
},
4428 [CSR_MHPMCOUNTER7
] = { "mhpmcounter7", mctr
, read_hpmcounter
,
4429 write_mhpmcounter
},
4430 [CSR_MHPMCOUNTER8
] = { "mhpmcounter8", mctr
, read_hpmcounter
,
4431 write_mhpmcounter
},
4432 [CSR_MHPMCOUNTER9
] = { "mhpmcounter9", mctr
, read_hpmcounter
,
4433 write_mhpmcounter
},
4434 [CSR_MHPMCOUNTER10
] = { "mhpmcounter10", mctr
, read_hpmcounter
,
4435 write_mhpmcounter
},
4436 [CSR_MHPMCOUNTER11
] = { "mhpmcounter11", mctr
, read_hpmcounter
,
4437 write_mhpmcounter
},
4438 [CSR_MHPMCOUNTER12
] = { "mhpmcounter12", mctr
, read_hpmcounter
,
4439 write_mhpmcounter
},
4440 [CSR_MHPMCOUNTER13
] = { "mhpmcounter13", mctr
, read_hpmcounter
,
4441 write_mhpmcounter
},
4442 [CSR_MHPMCOUNTER14
] = { "mhpmcounter14", mctr
, read_hpmcounter
,
4443 write_mhpmcounter
},
4444 [CSR_MHPMCOUNTER15
] = { "mhpmcounter15", mctr
, read_hpmcounter
,
4445 write_mhpmcounter
},
4446 [CSR_MHPMCOUNTER16
] = { "mhpmcounter16", mctr
, read_hpmcounter
,
4447 write_mhpmcounter
},
4448 [CSR_MHPMCOUNTER17
] = { "mhpmcounter17", mctr
, read_hpmcounter
,
4449 write_mhpmcounter
},
4450 [CSR_MHPMCOUNTER18
] = { "mhpmcounter18", mctr
, read_hpmcounter
,
4451 write_mhpmcounter
},
4452 [CSR_MHPMCOUNTER19
] = { "mhpmcounter19", mctr
, read_hpmcounter
,
4453 write_mhpmcounter
},
4454 [CSR_MHPMCOUNTER20
] = { "mhpmcounter20", mctr
, read_hpmcounter
,
4455 write_mhpmcounter
},
4456 [CSR_MHPMCOUNTER21
] = { "mhpmcounter21", mctr
, read_hpmcounter
,
4457 write_mhpmcounter
},
4458 [CSR_MHPMCOUNTER22
] = { "mhpmcounter22", mctr
, read_hpmcounter
,
4459 write_mhpmcounter
},
4460 [CSR_MHPMCOUNTER23
] = { "mhpmcounter23", mctr
, read_hpmcounter
,
4461 write_mhpmcounter
},
4462 [CSR_MHPMCOUNTER24
] = { "mhpmcounter24", mctr
, read_hpmcounter
,
4463 write_mhpmcounter
},
4464 [CSR_MHPMCOUNTER25
] = { "mhpmcounter25", mctr
, read_hpmcounter
,
4465 write_mhpmcounter
},
4466 [CSR_MHPMCOUNTER26
] = { "mhpmcounter26", mctr
, read_hpmcounter
,
4467 write_mhpmcounter
},
4468 [CSR_MHPMCOUNTER27
] = { "mhpmcounter27", mctr
, read_hpmcounter
,
4469 write_mhpmcounter
},
4470 [CSR_MHPMCOUNTER28
] = { "mhpmcounter28", mctr
, read_hpmcounter
,
4471 write_mhpmcounter
},
4472 [CSR_MHPMCOUNTER29
] = { "mhpmcounter29", mctr
, read_hpmcounter
,
4473 write_mhpmcounter
},
4474 [CSR_MHPMCOUNTER30
] = { "mhpmcounter30", mctr
, read_hpmcounter
,
4475 write_mhpmcounter
},
4476 [CSR_MHPMCOUNTER31
] = { "mhpmcounter31", mctr
, read_hpmcounter
,
4477 write_mhpmcounter
},
4479 [CSR_MCOUNTINHIBIT
] = { "mcountinhibit", any
, read_mcountinhibit
,
4480 write_mcountinhibit
,
4481 .min_priv_ver
= PRIV_VERSION_1_11_0
},
4483 [CSR_MHPMEVENT3
] = { "mhpmevent3", any
, read_mhpmevent
,
4485 [CSR_MHPMEVENT4
] = { "mhpmevent4", any
, read_mhpmevent
,
4487 [CSR_MHPMEVENT5
] = { "mhpmevent5", any
, read_mhpmevent
,
4489 [CSR_MHPMEVENT6
] = { "mhpmevent6", any
, read_mhpmevent
,
4491 [CSR_MHPMEVENT7
] = { "mhpmevent7", any
, read_mhpmevent
,
4493 [CSR_MHPMEVENT8
] = { "mhpmevent8", any
, read_mhpmevent
,
4495 [CSR_MHPMEVENT9
] = { "mhpmevent9", any
, read_mhpmevent
,
4497 [CSR_MHPMEVENT10
] = { "mhpmevent10", any
, read_mhpmevent
,
4499 [CSR_MHPMEVENT11
] = { "mhpmevent11", any
, read_mhpmevent
,
4501 [CSR_MHPMEVENT12
] = { "mhpmevent12", any
, read_mhpmevent
,
4503 [CSR_MHPMEVENT13
] = { "mhpmevent13", any
, read_mhpmevent
,
4505 [CSR_MHPMEVENT14
] = { "mhpmevent14", any
, read_mhpmevent
,
4507 [CSR_MHPMEVENT15
] = { "mhpmevent15", any
, read_mhpmevent
,
4509 [CSR_MHPMEVENT16
] = { "mhpmevent16", any
, read_mhpmevent
,
4511 [CSR_MHPMEVENT17
] = { "mhpmevent17", any
, read_mhpmevent
,
4513 [CSR_MHPMEVENT18
] = { "mhpmevent18", any
, read_mhpmevent
,
4515 [CSR_MHPMEVENT19
] = { "mhpmevent19", any
, read_mhpmevent
,
4517 [CSR_MHPMEVENT20
] = { "mhpmevent20", any
, read_mhpmevent
,
4519 [CSR_MHPMEVENT21
] = { "mhpmevent21", any
, read_mhpmevent
,
4521 [CSR_MHPMEVENT22
] = { "mhpmevent22", any
, read_mhpmevent
,
4523 [CSR_MHPMEVENT23
] = { "mhpmevent23", any
, read_mhpmevent
,
4525 [CSR_MHPMEVENT24
] = { "mhpmevent24", any
, read_mhpmevent
,
4527 [CSR_MHPMEVENT25
] = { "mhpmevent25", any
, read_mhpmevent
,
4529 [CSR_MHPMEVENT26
] = { "mhpmevent26", any
, read_mhpmevent
,
4531 [CSR_MHPMEVENT27
] = { "mhpmevent27", any
, read_mhpmevent
,
4533 [CSR_MHPMEVENT28
] = { "mhpmevent28", any
, read_mhpmevent
,
4535 [CSR_MHPMEVENT29
] = { "mhpmevent29", any
, read_mhpmevent
,
4537 [CSR_MHPMEVENT30
] = { "mhpmevent30", any
, read_mhpmevent
,
4539 [CSR_MHPMEVENT31
] = { "mhpmevent31", any
, read_mhpmevent
,
4542 [CSR_MHPMEVENT3H
] = { "mhpmevent3h", sscofpmf
, read_mhpmeventh
,
4544 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4545 [CSR_MHPMEVENT4H
] = { "mhpmevent4h", sscofpmf
, read_mhpmeventh
,
4547 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4548 [CSR_MHPMEVENT5H
] = { "mhpmevent5h", sscofpmf
, read_mhpmeventh
,
4550 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4551 [CSR_MHPMEVENT6H
] = { "mhpmevent6h", sscofpmf
, read_mhpmeventh
,
4553 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4554 [CSR_MHPMEVENT7H
] = { "mhpmevent7h", sscofpmf
, read_mhpmeventh
,
4556 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4557 [CSR_MHPMEVENT8H
] = { "mhpmevent8h", sscofpmf
, read_mhpmeventh
,
4559 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4560 [CSR_MHPMEVENT9H
] = { "mhpmevent9h", sscofpmf
, read_mhpmeventh
,
4562 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4563 [CSR_MHPMEVENT10H
] = { "mhpmevent10h", sscofpmf
, read_mhpmeventh
,
4565 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4566 [CSR_MHPMEVENT11H
] = { "mhpmevent11h", sscofpmf
, read_mhpmeventh
,
4568 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4569 [CSR_MHPMEVENT12H
] = { "mhpmevent12h", sscofpmf
, read_mhpmeventh
,
4571 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4572 [CSR_MHPMEVENT13H
] = { "mhpmevent13h", sscofpmf
, read_mhpmeventh
,
4574 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4575 [CSR_MHPMEVENT14H
] = { "mhpmevent14h", sscofpmf
, read_mhpmeventh
,
4577 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4578 [CSR_MHPMEVENT15H
] = { "mhpmevent15h", sscofpmf
, read_mhpmeventh
,
4580 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4581 [CSR_MHPMEVENT16H
] = { "mhpmevent16h", sscofpmf
, read_mhpmeventh
,
4583 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4584 [CSR_MHPMEVENT17H
] = { "mhpmevent17h", sscofpmf
, read_mhpmeventh
,
4586 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4587 [CSR_MHPMEVENT18H
] = { "mhpmevent18h", sscofpmf
, read_mhpmeventh
,
4589 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4590 [CSR_MHPMEVENT19H
] = { "mhpmevent19h", sscofpmf
, read_mhpmeventh
,
4592 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4593 [CSR_MHPMEVENT20H
] = { "mhpmevent20h", sscofpmf
, read_mhpmeventh
,
4595 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4596 [CSR_MHPMEVENT21H
] = { "mhpmevent21h", sscofpmf
, read_mhpmeventh
,
4598 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4599 [CSR_MHPMEVENT22H
] = { "mhpmevent22h", sscofpmf
, read_mhpmeventh
,
4601 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4602 [CSR_MHPMEVENT23H
] = { "mhpmevent23h", sscofpmf
, read_mhpmeventh
,
4604 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4605 [CSR_MHPMEVENT24H
] = { "mhpmevent24h", sscofpmf
, read_mhpmeventh
,
4607 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4608 [CSR_MHPMEVENT25H
] = { "mhpmevent25h", sscofpmf
, read_mhpmeventh
,
4610 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4611 [CSR_MHPMEVENT26H
] = { "mhpmevent26h", sscofpmf
, read_mhpmeventh
,
4613 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4614 [CSR_MHPMEVENT27H
] = { "mhpmevent27h", sscofpmf
, read_mhpmeventh
,
4616 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4617 [CSR_MHPMEVENT28H
] = { "mhpmevent28h", sscofpmf
, read_mhpmeventh
,
4619 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4620 [CSR_MHPMEVENT29H
] = { "mhpmevent29h", sscofpmf
, read_mhpmeventh
,
4622 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4623 [CSR_MHPMEVENT30H
] = { "mhpmevent30h", sscofpmf
, read_mhpmeventh
,
4625 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4626 [CSR_MHPMEVENT31H
] = { "mhpmevent31h", sscofpmf
, read_mhpmeventh
,
4628 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4630 [CSR_HPMCOUNTER3H
] = { "hpmcounter3h", ctr32
, read_hpmcounterh
},
4631 [CSR_HPMCOUNTER4H
] = { "hpmcounter4h", ctr32
, read_hpmcounterh
},
4632 [CSR_HPMCOUNTER5H
] = { "hpmcounter5h", ctr32
, read_hpmcounterh
},
4633 [CSR_HPMCOUNTER6H
] = { "hpmcounter6h", ctr32
, read_hpmcounterh
},
4634 [CSR_HPMCOUNTER7H
] = { "hpmcounter7h", ctr32
, read_hpmcounterh
},
4635 [CSR_HPMCOUNTER8H
] = { "hpmcounter8h", ctr32
, read_hpmcounterh
},
4636 [CSR_HPMCOUNTER9H
] = { "hpmcounter9h", ctr32
, read_hpmcounterh
},
4637 [CSR_HPMCOUNTER10H
] = { "hpmcounter10h", ctr32
, read_hpmcounterh
},
4638 [CSR_HPMCOUNTER11H
] = { "hpmcounter11h", ctr32
, read_hpmcounterh
},
4639 [CSR_HPMCOUNTER12H
] = { "hpmcounter12h", ctr32
, read_hpmcounterh
},
4640 [CSR_HPMCOUNTER13H
] = { "hpmcounter13h", ctr32
, read_hpmcounterh
},
4641 [CSR_HPMCOUNTER14H
] = { "hpmcounter14h", ctr32
, read_hpmcounterh
},
4642 [CSR_HPMCOUNTER15H
] = { "hpmcounter15h", ctr32
, read_hpmcounterh
},
4643 [CSR_HPMCOUNTER16H
] = { "hpmcounter16h", ctr32
, read_hpmcounterh
},
4644 [CSR_HPMCOUNTER17H
] = { "hpmcounter17h", ctr32
, read_hpmcounterh
},
4645 [CSR_HPMCOUNTER18H
] = { "hpmcounter18h", ctr32
, read_hpmcounterh
},
4646 [CSR_HPMCOUNTER19H
] = { "hpmcounter19h", ctr32
, read_hpmcounterh
},
4647 [CSR_HPMCOUNTER20H
] = { "hpmcounter20h", ctr32
, read_hpmcounterh
},
4648 [CSR_HPMCOUNTER21H
] = { "hpmcounter21h", ctr32
, read_hpmcounterh
},
4649 [CSR_HPMCOUNTER22H
] = { "hpmcounter22h", ctr32
, read_hpmcounterh
},
4650 [CSR_HPMCOUNTER23H
] = { "hpmcounter23h", ctr32
, read_hpmcounterh
},
4651 [CSR_HPMCOUNTER24H
] = { "hpmcounter24h", ctr32
, read_hpmcounterh
},
4652 [CSR_HPMCOUNTER25H
] = { "hpmcounter25h", ctr32
, read_hpmcounterh
},
4653 [CSR_HPMCOUNTER26H
] = { "hpmcounter26h", ctr32
, read_hpmcounterh
},
4654 [CSR_HPMCOUNTER27H
] = { "hpmcounter27h", ctr32
, read_hpmcounterh
},
4655 [CSR_HPMCOUNTER28H
] = { "hpmcounter28h", ctr32
, read_hpmcounterh
},
4656 [CSR_HPMCOUNTER29H
] = { "hpmcounter29h", ctr32
, read_hpmcounterh
},
4657 [CSR_HPMCOUNTER30H
] = { "hpmcounter30h", ctr32
, read_hpmcounterh
},
4658 [CSR_HPMCOUNTER31H
] = { "hpmcounter31h", ctr32
, read_hpmcounterh
},
4660 [CSR_MHPMCOUNTER3H
] = { "mhpmcounter3h", mctr32
, read_hpmcounterh
,
4661 write_mhpmcounterh
},
4662 [CSR_MHPMCOUNTER4H
] = { "mhpmcounter4h", mctr32
, read_hpmcounterh
,
4663 write_mhpmcounterh
},
4664 [CSR_MHPMCOUNTER5H
] = { "mhpmcounter5h", mctr32
, read_hpmcounterh
,
4665 write_mhpmcounterh
},
4666 [CSR_MHPMCOUNTER6H
] = { "mhpmcounter6h", mctr32
, read_hpmcounterh
,
4667 write_mhpmcounterh
},
4668 [CSR_MHPMCOUNTER7H
] = { "mhpmcounter7h", mctr32
, read_hpmcounterh
,
4669 write_mhpmcounterh
},
4670 [CSR_MHPMCOUNTER8H
] = { "mhpmcounter8h", mctr32
, read_hpmcounterh
,
4671 write_mhpmcounterh
},
4672 [CSR_MHPMCOUNTER9H
] = { "mhpmcounter9h", mctr32
, read_hpmcounterh
,
4673 write_mhpmcounterh
},
4674 [CSR_MHPMCOUNTER10H
] = { "mhpmcounter10h", mctr32
, read_hpmcounterh
,
4675 write_mhpmcounterh
},
4676 [CSR_MHPMCOUNTER11H
] = { "mhpmcounter11h", mctr32
, read_hpmcounterh
,
4677 write_mhpmcounterh
},
4678 [CSR_MHPMCOUNTER12H
] = { "mhpmcounter12h", mctr32
, read_hpmcounterh
,
4679 write_mhpmcounterh
},
4680 [CSR_MHPMCOUNTER13H
] = { "mhpmcounter13h", mctr32
, read_hpmcounterh
,
4681 write_mhpmcounterh
},
4682 [CSR_MHPMCOUNTER14H
] = { "mhpmcounter14h", mctr32
, read_hpmcounterh
,
4683 write_mhpmcounterh
},
4684 [CSR_MHPMCOUNTER15H
] = { "mhpmcounter15h", mctr32
, read_hpmcounterh
,
4685 write_mhpmcounterh
},
4686 [CSR_MHPMCOUNTER16H
] = { "mhpmcounter16h", mctr32
, read_hpmcounterh
,
4687 write_mhpmcounterh
},
4688 [CSR_MHPMCOUNTER17H
] = { "mhpmcounter17h", mctr32
, read_hpmcounterh
,
4689 write_mhpmcounterh
},
4690 [CSR_MHPMCOUNTER18H
] = { "mhpmcounter18h", mctr32
, read_hpmcounterh
,
4691 write_mhpmcounterh
},
4692 [CSR_MHPMCOUNTER19H
] = { "mhpmcounter19h", mctr32
, read_hpmcounterh
,
4693 write_mhpmcounterh
},
4694 [CSR_MHPMCOUNTER20H
] = { "mhpmcounter20h", mctr32
, read_hpmcounterh
,
4695 write_mhpmcounterh
},
4696 [CSR_MHPMCOUNTER21H
] = { "mhpmcounter21h", mctr32
, read_hpmcounterh
,
4697 write_mhpmcounterh
},
4698 [CSR_MHPMCOUNTER22H
] = { "mhpmcounter22h", mctr32
, read_hpmcounterh
,
4699 write_mhpmcounterh
},
4700 [CSR_MHPMCOUNTER23H
] = { "mhpmcounter23h", mctr32
, read_hpmcounterh
,
4701 write_mhpmcounterh
},
4702 [CSR_MHPMCOUNTER24H
] = { "mhpmcounter24h", mctr32
, read_hpmcounterh
,
4703 write_mhpmcounterh
},
4704 [CSR_MHPMCOUNTER25H
] = { "mhpmcounter25h", mctr32
, read_hpmcounterh
,
4705 write_mhpmcounterh
},
4706 [CSR_MHPMCOUNTER26H
] = { "mhpmcounter26h", mctr32
, read_hpmcounterh
,
4707 write_mhpmcounterh
},
4708 [CSR_MHPMCOUNTER27H
] = { "mhpmcounter27h", mctr32
, read_hpmcounterh
,
4709 write_mhpmcounterh
},
4710 [CSR_MHPMCOUNTER28H
] = { "mhpmcounter28h", mctr32
, read_hpmcounterh
,
4711 write_mhpmcounterh
},
4712 [CSR_MHPMCOUNTER29H
] = { "mhpmcounter29h", mctr32
, read_hpmcounterh
,
4713 write_mhpmcounterh
},
4714 [CSR_MHPMCOUNTER30H
] = { "mhpmcounter30h", mctr32
, read_hpmcounterh
,
4715 write_mhpmcounterh
},
4716 [CSR_MHPMCOUNTER31H
] = { "mhpmcounter31h", mctr32
, read_hpmcounterh
,
4717 write_mhpmcounterh
},
4718 [CSR_SCOUNTOVF
] = { "scountovf", sscofpmf
, read_scountovf
,
4719 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4721 #endif /* !CONFIG_USER_ONLY */