hw/arm/xlnx-versal-virt.c

   1 /*
   2  * Xilinx Versal Virtual board.
   3  *
   4  * Copyright (c) 2018 Xilinx Inc.
   5  * Written by Edgar E. Iglesias
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 or
   9  * (at your option) any later version.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qemu/log.h"
  14 #include "qemu/error-report.h"
  15 #include "qapi/error.h"
  16 #include "sysemu/device_tree.h"
  17 #include "exec/address-spaces.h"
  18 #include "hw/boards.h"
  19 #include "hw/sysbus.h"
  20 #include "hw/arm/sysbus-fdt.h"
  21 #include "hw/arm/fdt.h"
  22 #include "cpu.h"
  23 #include "hw/qdev-properties.h"
  24 #include "hw/arm/xlnx-versal.h"
  25
  26 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
  27 #define XLNX_VERSAL_VIRT_MACHINE(obj) \
  28     OBJECT_CHECK(VersalVirt, (obj), TYPE_XLNX_VERSAL_VIRT_MACHINE)
  29
  30 typedef struct VersalVirt {
  31     MachineState parent_obj;
  32
  33     Versal soc;
  34
  35     void *fdt;
  36     int fdt_size;
  37     struct {
  38         uint32_t gic;
  39         uint32_t ethernet_phy[2];
  40         uint32_t clk_125Mhz;
  41         uint32_t clk_25Mhz;
  42     } phandle;
  43     struct arm_boot_info binfo;
  44
  45     struct {
  46         bool secure;
  47     } cfg;
  48 } VersalVirt;
  49
  50 static void fdt_create(VersalVirt *s)
  51 {
  52     MachineClass *mc = MACHINE_GET_CLASS(s);
  53     int i;
  54
  55     s->fdt = create_device_tree(&s->fdt_size);
  56     if (!s->fdt) {
  57         error_report("create_device_tree() failed");
  58         exit(1);
  59     }
  60
  61     /* Allocate all phandles.  */
  62     s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt);
  63     for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) {
  64         s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt);
  65     }
  66     s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
  67     s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
  68
  69     /* Create /chosen node for load_dtb.  */
  70     qemu_fdt_add_subnode(s->fdt, "/chosen");
  71
  72     /* Header */
  73     qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic);
  74     qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2);
  75     qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2);
  76     qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc);
  77     qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt");
  78 }
  79
  80 static void fdt_add_clk_node(VersalVirt *s, const char *name,
  81                              unsigned int freq_hz, uint32_t phandle)
  82 {
  83     qemu_fdt_add_subnode(s->fdt, name);
  84     qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
  85     qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz);
  86     qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0);
  87     qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock");
  88     qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
  89 }
  90
  91 static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
  92 {
  93     int i;
  94
  95     qemu_fdt_add_subnode(s->fdt, "/cpus");
  96     qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0);
  97     qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1);
  98
  99     for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) {
 100         char *name = g_strdup_printf("/cpus/cpu@%d", i);
 101         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
 102
 103         qemu_fdt_add_subnode(s->fdt, name);
 104         qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
 105         if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
 106             qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci");
 107         }
 108         qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu");
 109         qemu_fdt_setprop_string(s->fdt, name, "compatible",
 110                                 armcpu->dtb_compatible);
 111         g_free(name);
 112     }
 113 }
 114
 115 static void fdt_add_gic_nodes(VersalVirt *s)
 116 {
 117     char *nodename;
 118
 119     nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN);
 120     qemu_fdt_add_subnode(s->fdt, nodename);
 121     qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic);
 122     qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts",
 123                            GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ,
 124                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 125     qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0);
 126     qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
 127                                  2, MM_GIC_APU_DIST_MAIN,
 128                                  2, MM_GIC_APU_DIST_MAIN_SIZE,
 129                                  2, MM_GIC_APU_REDIST_0,
 130                                  2, MM_GIC_APU_REDIST_0_SIZE);
 131     qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3);
 132     qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3");
 133     g_free(nodename);
 134 }
 135
 136 static void fdt_add_timer_nodes(VersalVirt *s)
 137 {
 138     const char compat[] = "arm,armv8-timer";
 139     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
 140
 141     qemu_fdt_add_subnode(s->fdt, "/timer");
 142     qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts",
 143             GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags,
 144             GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags,
 145             GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags,
 146             GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags);
 147     qemu_fdt_setprop(s->fdt, "/timer", "compatible",
 148                      compat, sizeof(compat));
 149 }
 150
 151 static void fdt_add_uart_nodes(VersalVirt *s)
 152 {
 153     uint64_t addrs[] = { MM_UART1, MM_UART0 };
 154     unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 };
 155     const char compat[] = "arm,pl011\0arm,sbsa-uart";
 156     const char clocknames[] = "uartclk\0apb_pclk";
 157     int i;
 158
 159     for (i = 0; i < ARRAY_SIZE(addrs); i++) {
 160         char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]);
 161         qemu_fdt_add_subnode(s->fdt, name);
 162         qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200);
 163         qemu_fdt_setprop_cells(s->fdt, name, "clocks",
 164                                s->phandle.clk_125Mhz, s->phandle.clk_125Mhz);
 165         qemu_fdt_setprop(s->fdt, name, "clock-names",
 166                          clocknames, sizeof(clocknames));
 167
 168         qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
 169                                GIC_FDT_IRQ_TYPE_SPI, irqs[i],
 170                                GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 171         qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 172                                      2, addrs[i], 2, 0x1000);
 173         qemu_fdt_setprop(s->fdt, name, "compatible",
 174                          compat, sizeof(compat));
 175         qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
 176
 177         if (addrs[i] == MM_UART0) {
 178             /* Select UART0.  */
 179             qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name);
 180         }
 181         g_free(name);
 182     }
 183 }
 184
 185 static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname,
 186                                      uint32_t phandle)
 187 {
 188     char *name = g_strdup_printf("%s/fixed-link", gemname);
 189
 190     qemu_fdt_add_subnode(s->fdt, name);
 191     qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
 192     qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0);
 193     qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000);
 194     g_free(name);
 195 }
 196
 197 static void fdt_add_gem_nodes(VersalVirt *s)
 198 {
 199     uint64_t addrs[] = { MM_GEM1, MM_GEM0 };
 200     unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 };
 201     const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk";
 202     const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem";
 203     int i;
 204
 205     for (i = 0; i < ARRAY_SIZE(addrs); i++) {
 206         char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]);
 207         qemu_fdt_add_subnode(s->fdt, name);
 208
 209         fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]);
 210         qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id");
 211         qemu_fdt_setprop_cell(s->fdt, name, "phy-handle",
 212                               s->phandle.ethernet_phy[i]);
 213         qemu_fdt_setprop_cells(s->fdt, name, "clocks",
 214                                s->phandle.clk_25Mhz, s->phandle.clk_25Mhz,
 215                                s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
 216         qemu_fdt_setprop(s->fdt, name, "clock-names",
 217                          clocknames, sizeof(clocknames));
 218         qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
 219                                GIC_FDT_IRQ_TYPE_SPI, irqs[i],
 220                                GIC_FDT_IRQ_FLAGS_LEVEL_HI,
 221                                GIC_FDT_IRQ_TYPE_SPI, irqs[i],
 222                                GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 223         qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 224                                      2, addrs[i], 2, 0x1000);
 225         qemu_fdt_setprop(s->fdt, name, "compatible",
 226                          compat_gem, sizeof(compat_gem));
 227         qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1);
 228         qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0);
 229         g_free(name);
 230     }
 231 }
 232
 233 static void fdt_add_zdma_nodes(VersalVirt *s)
 234 {
 235     const char clocknames[] = "clk_main\0clk_apb";
 236     const char compat[] = "xlnx,zynqmp-dma-1.0";
 237     int i;
 238
 239     for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) {
 240         uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i;
 241         char *name = g_strdup_printf("/dma@%" PRIx64, addr);
 242
 243         qemu_fdt_add_subnode(s->fdt, name);
 244
 245         qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64);
 246         qemu_fdt_setprop_cells(s->fdt, name, "clocks",
 247                                s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
 248         qemu_fdt_setprop(s->fdt, name, "clock-names",
 249                          clocknames, sizeof(clocknames));
 250         qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
 251                                GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i,
 252                                GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 253         qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 254                                      2, addr, 2, 0x1000);
 255         qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
 256         g_free(name);
 257     }
 258 }
 259
 260 static void fdt_add_sd_nodes(VersalVirt *s)
 261 {
 262     const char clocknames[] = "clk_xin\0clk_ahb";
 263     const char compat[] = "arasan,sdhci-8.9a";
 264     int i;
 265
 266     for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) {
 267         uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i;
 268         char *name = g_strdup_printf("/sdhci@%" PRIx64, addr);
 269
 270         qemu_fdt_add_subnode(s->fdt, name);
 271
 272         qemu_fdt_setprop_cells(s->fdt, name, "clocks",
 273                                s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
 274         qemu_fdt_setprop(s->fdt, name, "clock-names",
 275                          clocknames, sizeof(clocknames));
 276         qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
 277                                GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2,
 278                                GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 279         qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 280                                      2, addr, 2, MM_PMC_SD0_SIZE);
 281         qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
 282         g_free(name);
 283     }
 284 }
 285
 286 static void fdt_add_rtc_node(VersalVirt *s)
 287 {
 288     const char compat[] = "xlnx,zynqmp-rtc";
 289     const char interrupt_names[] = "alarm\0sec";
 290     char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC);
 291
 292     qemu_fdt_add_subnode(s->fdt, name);
 293
 294     qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
 295                            GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ,
 296                            GIC_FDT_IRQ_FLAGS_LEVEL_HI,
 297                            GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ,
 298                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 299     qemu_fdt_setprop(s->fdt, name, "interrupt-names",
 300                      interrupt_names, sizeof(interrupt_names));
 301     qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 302                                  2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE);
 303     qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
 304     g_free(name);
 305 }
 306
 307 static void fdt_nop_memory_nodes(void *fdt, Error **errp)
 308 {
 309     Error *err = NULL;
 310     char **node_path;
 311     int n = 0;
 312
 313     node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
 314     if (err) {
 315         error_propagate(errp, err);
 316         return;
 317     }
 318     while (node_path[n]) {
 319         if (g_str_has_prefix(node_path[n], "/memory")) {
 320             qemu_fdt_nop_node(fdt, node_path[n]);
 321         }
 322         n++;
 323     }
 324     g_strfreev(node_path);
 325 }
 326
 327 static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size)
 328 {
 329     /* Describes the various split DDR access regions.  */
 330     static const struct {
 331         uint64_t base;
 332         uint64_t size;
 333     } addr_ranges[] = {
 334         { MM_TOP_DDR, MM_TOP_DDR_SIZE },
 335         { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
 336         { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
 337         { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
 338     };
 339     uint64_t mem_reg_prop[8] = {0};
 340     uint64_t size = ram_size;
 341     Error *err = NULL;
 342     char *name;
 343     int i;
 344
 345     fdt_nop_memory_nodes(fdt, &err);
 346     if (err) {
 347         error_report_err(err);
 348         return;
 349     }
 350
 351     name = g_strdup_printf("/memory@%x", MM_TOP_DDR);
 352     for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
 353         uint64_t mapsize;
 354
 355         mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
 356
 357         mem_reg_prop[i * 2] = addr_ranges[i].base;
 358         mem_reg_prop[i * 2 + 1] = mapsize;
 359         size -= mapsize;
 360     }
 361     qemu_fdt_add_subnode(fdt, name);
 362     qemu_fdt_setprop_string(fdt, name, "device_type", "memory");
 363
 364     switch (i) {
 365     case 1:
 366         qemu_fdt_setprop_sized_cells(fdt, name, "reg",
 367                                      2, mem_reg_prop[0],
 368                                      2, mem_reg_prop[1]);
 369         break;
 370     case 2:
 371         qemu_fdt_setprop_sized_cells(fdt, name, "reg",
 372                                      2, mem_reg_prop[0],
 373                                      2, mem_reg_prop[1],
 374                                      2, mem_reg_prop[2],
 375                                      2, mem_reg_prop[3]);
 376         break;
 377     case 3:
 378         qemu_fdt_setprop_sized_cells(fdt, name, "reg",
 379                                      2, mem_reg_prop[0],
 380                                      2, mem_reg_prop[1],
 381                                      2, mem_reg_prop[2],
 382                                      2, mem_reg_prop[3],
 383                                      2, mem_reg_prop[4],
 384                                      2, mem_reg_prop[5]);
 385         break;
 386     case 4:
 387         qemu_fdt_setprop_sized_cells(fdt, name, "reg",
 388                                      2, mem_reg_prop[0],
 389                                      2, mem_reg_prop[1],
 390                                      2, mem_reg_prop[2],
 391                                      2, mem_reg_prop[3],
 392                                      2, mem_reg_prop[4],
 393                                      2, mem_reg_prop[5],
 394                                      2, mem_reg_prop[6],
 395                                      2, mem_reg_prop[7]);
 396         break;
 397     default:
 398         g_assert_not_reached();
 399     }
 400     g_free(name);
 401 }
 402
 403 static void versal_virt_modify_dtb(const struct arm_boot_info *binfo,
 404                                     void *fdt)
 405 {
 406     VersalVirt *s = container_of(binfo, VersalVirt, binfo);
 407
 408     fdt_add_memory_nodes(s, fdt, binfo->ram_size);
 409 }
 410
 411 static void *versal_virt_get_dtb(const struct arm_boot_info *binfo,
 412                                   int *fdt_size)
 413 {
 414     const VersalVirt *board = container_of(binfo, VersalVirt, binfo);
 415
 416     *fdt_size = board->fdt_size;
 417     return board->fdt;
 418 }
 419
 420 #define NUM_VIRTIO_TRANSPORT 8
 421 static void create_virtio_regions(VersalVirt *s)
 422 {
 423     int virtio_mmio_size = 0x200;
 424     int i;
 425
 426     for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
 427         char *name = g_strdup_printf("virtio%d", i);
 428         hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
 429         int irq = VERSAL_RSVD_IRQ_FIRST + i;
 430         MemoryRegion *mr;
 431         DeviceState *dev;
 432         qemu_irq pic_irq;
 433
 434         pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
 435         dev = qdev_new("virtio-mmio");
 436         object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev));
 437         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 438         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
 439         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 440         memory_region_add_subregion(&s->soc.mr_ps, base, mr);
 441         g_free(name);
 442     }
 443
 444     for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
 445         hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
 446         int irq = VERSAL_RSVD_IRQ_FIRST + i;
 447         char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
 448
 449         qemu_fdt_add_subnode(s->fdt, name);
 450         qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0);
 451         qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
 452                                GIC_FDT_IRQ_TYPE_SPI, irq,
 453                                GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
 454         qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 455                                      2, base, 2, virtio_mmio_size);
 456         qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio");
 457         g_free(name);
 458     }
 459 }
 460
 461 static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
 462 {
 463     BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
 464     DeviceState *card;
 465
 466     card = qdev_new(TYPE_SD_CARD);
 467     object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card));
 468     qdev_prop_set_drive_err(card, "drive", blk, &error_fatal);
 469     qdev_realize_and_unref(card, qdev_get_child_bus(DEVICE(sd), "sd-bus"),
 470                            &error_fatal);
 471 }
 472
 473 static void versal_virt_init(MachineState *machine)
 474 {
 475     VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine);
 476     int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
 477     int i;
 478
 479     /*
 480      * If the user provides an Operating System to be loaded, we expect them
 481      * to use the -kernel command line option.
 482      *
 483      * Users can load firmware or boot-loaders with the -device loader options.
 484      *
 485      * When loading an OS, we generate a dtb and let arm_load_kernel() select
 486      * where it gets loaded. This dtb will be passed to the kernel in x0.
 487      *
 488      * If there's no -kernel option, we generate a DTB and place it at 0x1000
 489      * for the bootloaders or firmware to pick up.
 490      *
 491      * If users want to provide their own DTB, they can use the -dtb option.
 492      * These dtb's will have their memory nodes modified to match QEMU's
 493      * selected ram_size option before they get passed to the kernel or fw.
 494      *
 495      * When loading an OS, we turn on QEMU's PSCI implementation with SMC
 496      * as the PSCI conduit. When there's no -kernel, we assume the user
 497      * provides EL3 firmware to handle PSCI.
 498      */
 499     if (machine->kernel_filename) {
 500         psci_conduit = QEMU_PSCI_CONDUIT_SMC;
 501     }
 502
 503     object_initialize_child(OBJECT(machine), "xlnx-versal", &s->soc,
 504                             TYPE_XLNX_VERSAL);
 505     object_property_set_link(OBJECT(&s->soc), "ddr", OBJECT(machine->ram),
 506                              &error_abort);
 507     object_property_set_int(OBJECT(&s->soc), "psci-conduit", psci_conduit,
 508                             &error_abort);
 509     sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
 510
 511     fdt_create(s);
 512     create_virtio_regions(s);
 513     fdt_add_gem_nodes(s);
 514     fdt_add_uart_nodes(s);
 515     fdt_add_gic_nodes(s);
 516     fdt_add_timer_nodes(s);
 517     fdt_add_zdma_nodes(s);
 518     fdt_add_sd_nodes(s);
 519     fdt_add_rtc_node(s);
 520     fdt_add_cpu_nodes(s, psci_conduit);
 521     fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
 522     fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
 523
 524     /* Make the APU cpu address space visible to virtio and other
 525      * modules unaware of muliple address-spaces.  */
 526     memory_region_add_subregion_overlap(get_system_memory(),
 527                                         0, &s->soc.fpd.apu.mr, 0);
 528
 529     /* Plugin SD cards.  */
 530     for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
 531         sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
 532     }
 533
 534     s->binfo.ram_size = machine->ram_size;
 535     s->binfo.loader_start = 0x0;
 536     s->binfo.get_dtb = versal_virt_get_dtb;
 537     s->binfo.modify_dtb = versal_virt_modify_dtb;
 538     if (machine->kernel_filename) {
 539         arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo);
 540     } else {
 541         AddressSpace *as = arm_boot_address_space(&s->soc.fpd.apu.cpu[0],
 542                                                   &s->binfo);
 543         /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
 544          * Offset things by 4K.  */
 545         s->binfo.loader_start = 0x1000;
 546         s->binfo.dtb_limit = 0x1000000;
 547         if (arm_load_dtb(s->binfo.loader_start,
 548                          &s->binfo, s->binfo.dtb_limit, as, machine) < 0) {
 549             exit(EXIT_FAILURE);
 550         }
 551     }
 552 }
 553
 554 static void versal_virt_machine_instance_init(Object *obj)
 555 {
 556 }
 557
 558 static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
 559 {
 560     MachineClass *mc = MACHINE_CLASS(oc);
 561
 562     mc->desc = "Xilinx Versal Virtual development board";
 563     mc->init = versal_virt_init;
 564     mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
 565     mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
 566     mc->no_cdrom = true;
 567     mc->default_ram_id = "ddr";
 568 }
 569
 570 static const TypeInfo versal_virt_machine_init_typeinfo = {
 571     .name       = TYPE_XLNX_VERSAL_VIRT_MACHINE,
 572     .parent     = TYPE_MACHINE,
 573     .class_init = versal_virt_machine_class_init,
 574     .instance_init = versal_virt_machine_instance_init,
 575     .instance_size = sizeof(VersalVirt),
 576 };
 577
 578 static void versal_virt_machine_init_register_types(void)
 579 {
 580     type_register_static(&versal_virt_machine_init_typeinfo);
 581 }
 582
 583 type_init(versal_virt_machine_init_register_types)
 584