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hw/riscv: Move sifive_u_otp model to hw/misc
[qemu/ar7.git] / disas / libvixl / vixl / a64 / constants-a64.h
blob2caa73af87f2856dc45e2b7b1ba84c2fb4cfe7a9
1 // Copyright 2015, ARM Limited
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 // * Redistributions of source code must retain the above copyright notice,
8 // this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above copyright notice,
10 // this list of conditions and the following disclaimer in the documentation
11 // and/or other materials provided with the distribution.
12 // * Neither the name of ARM Limited nor the names of its contributors may be
13 // used to endorse or promote products derived from this software without
14 // specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 #ifndef VIXL_A64_CONSTANTS_A64_H_
28 #define VIXL_A64_CONSTANTS_A64_H_
29
30 namespace vixl {
31
32 const unsigned kNumberOfRegisters = 32;
33 const unsigned kNumberOfVRegisters = 32;
34 const unsigned kNumberOfFPRegisters = kNumberOfVRegisters;
35 // Callee saved registers are x21-x30(lr).
36 const int kNumberOfCalleeSavedRegisters = 10;
37 const int kFirstCalleeSavedRegisterIndex = 21;
38 // Callee saved FP registers are d8-d15.
39 const int kNumberOfCalleeSavedFPRegisters = 8;
40 const int kFirstCalleeSavedFPRegisterIndex = 8;
41
42 #define REGISTER_CODE_LIST(R) \
43 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
44 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \
45 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \
46 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
47
48 #define INSTRUCTION_FIELDS_LIST(V_) \
49 /* Register fields */ \
50 V_(Rd, 4, 0, Bits) /* Destination register. */ \
51 V_(Rn, 9, 5, Bits) /* First source register. */ \
52 V_(Rm, 20, 16, Bits) /* Second source register. */ \
53 V_(Ra, 14, 10, Bits) /* Third source register. */ \
54 V_(Rt, 4, 0, Bits) /* Load/store register. */ \
55 V_(Rt2, 14, 10, Bits) /* Load/store second register. */ \
56 V_(Rs, 20, 16, Bits) /* Exclusive access status. */ \
57 \
58 /* Common bits */ \
59 V_(SixtyFourBits, 31, 31, Bits) \
60 V_(FlagsUpdate, 29, 29, Bits) \
61 \
62 /* PC relative addressing */ \
63 V_(ImmPCRelHi, 23, 5, SignedBits) \
64 V_(ImmPCRelLo, 30, 29, Bits) \
65 \
66 /* Add/subtract/logical shift register */ \
67 V_(ShiftDP, 23, 22, Bits) \
68 V_(ImmDPShift, 15, 10, Bits) \
69 \
70 /* Add/subtract immediate */ \
71 V_(ImmAddSub, 21, 10, Bits) \
72 V_(ShiftAddSub, 23, 22, Bits) \
73 \
74 /* Add/substract extend */ \
75 V_(ImmExtendShift, 12, 10, Bits) \
76 V_(ExtendMode, 15, 13, Bits) \
77 \
78 /* Move wide */ \
79 V_(ImmMoveWide, 20, 5, Bits) \
80 V_(ShiftMoveWide, 22, 21, Bits) \
81 \
82 /* Logical immediate, bitfield and extract */ \
83 V_(BitN, 22, 22, Bits) \
84 V_(ImmRotate, 21, 16, Bits) \
85 V_(ImmSetBits, 15, 10, Bits) \
86 V_(ImmR, 21, 16, Bits) \
87 V_(ImmS, 15, 10, Bits) \
88 \
89 /* Test and branch immediate */ \
90 V_(ImmTestBranch, 18, 5, SignedBits) \
91 V_(ImmTestBranchBit40, 23, 19, Bits) \
92 V_(ImmTestBranchBit5, 31, 31, Bits) \
93 \
94 /* Conditionals */ \
95 V_(Condition, 15, 12, Bits) \
96 V_(ConditionBranch, 3, 0, Bits) \
97 V_(Nzcv, 3, 0, Bits) \
98 V_(ImmCondCmp, 20, 16, Bits) \
99 V_(ImmCondBranch, 23, 5, SignedBits) \
100 \
101 /* Floating point */ \
102 V_(FPType, 23, 22, Bits) \
103 V_(ImmFP, 20, 13, Bits) \
104 V_(FPScale, 15, 10, Bits) \
105 \
106 /* Load Store */ \
107 V_(ImmLS, 20, 12, SignedBits) \
108 V_(ImmLSUnsigned, 21, 10, Bits) \
109 V_(ImmLSPair, 21, 15, SignedBits) \
110 V_(ImmShiftLS, 12, 12, Bits) \
111 V_(LSOpc, 23, 22, Bits) \
112 V_(LSVector, 26, 26, Bits) \
113 V_(LSSize, 31, 30, Bits) \
114 V_(ImmPrefetchOperation, 4, 0, Bits) \
115 V_(PrefetchHint, 4, 3, Bits) \
116 V_(PrefetchTarget, 2, 1, Bits) \
117 V_(PrefetchStream, 0, 0, Bits) \
118 \
119 /* Other immediates */ \
120 V_(ImmUncondBranch, 25, 0, SignedBits) \
121 V_(ImmCmpBranch, 23, 5, SignedBits) \
122 V_(ImmLLiteral, 23, 5, SignedBits) \
123 V_(ImmException, 20, 5, Bits) \
124 V_(ImmHint, 11, 5, Bits) \
125 V_(ImmBarrierDomain, 11, 10, Bits) \
126 V_(ImmBarrierType, 9, 8, Bits) \
127 \
128 /* System (MRS, MSR, SYS) */ \
129 V_(ImmSystemRegister, 19, 5, Bits) \
130 V_(SysO0, 19, 19, Bits) \
131 V_(SysOp, 18, 5, Bits) \
132 V_(SysOp1, 18, 16, Bits) \
133 V_(SysOp2, 7, 5, Bits) \
134 V_(CRn, 15, 12, Bits) \
135 V_(CRm, 11, 8, Bits) \
136 \
137 /* Load-/store-exclusive */ \
138 V_(LdStXLoad, 22, 22, Bits) \
139 V_(LdStXNotExclusive, 23, 23, Bits) \
140 V_(LdStXAcquireRelease, 15, 15, Bits) \
141 V_(LdStXSizeLog2, 31, 30, Bits) \
142 V_(LdStXPair, 21, 21, Bits) \
143 \
144 /* NEON generic fields */ \
145 V_(NEONQ, 30, 30, Bits) \
146 V_(NEONSize, 23, 22, Bits) \
147 V_(NEONLSSize, 11, 10, Bits) \
148 V_(NEONS, 12, 12, Bits) \
149 V_(NEONL, 21, 21, Bits) \
150 V_(NEONM, 20, 20, Bits) \
151 V_(NEONH, 11, 11, Bits) \
152 V_(ImmNEONExt, 14, 11, Bits) \
153 V_(ImmNEON5, 20, 16, Bits) \
154 V_(ImmNEON4, 14, 11, Bits) \
155 \
156 /* NEON Modified Immediate fields */ \
157 V_(ImmNEONabc, 18, 16, Bits) \
158 V_(ImmNEONdefgh, 9, 5, Bits) \
159 V_(NEONModImmOp, 29, 29, Bits) \
160 V_(NEONCmode, 15, 12, Bits) \
161 \
162 /* NEON Shift Immediate fields */ \
163 V_(ImmNEONImmhImmb, 22, 16, Bits) \
164 V_(ImmNEONImmh, 22, 19, Bits) \
165 V_(ImmNEONImmb, 18, 16, Bits)
166
167 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
168 /* NZCV */ \
169 V_(Flags, 31, 28, Bits) \
170 V_(N, 31, 31, Bits) \
171 V_(Z, 30, 30, Bits) \
172 V_(C, 29, 29, Bits) \
173 V_(V, 28, 28, Bits) \
174 M_(NZCV, Flags_mask) \
175 /* FPCR */ \
176 V_(AHP, 26, 26, Bits) \
177 V_(DN, 25, 25, Bits) \
178 V_(FZ, 24, 24, Bits) \
179 V_(RMode, 23, 22, Bits) \
180 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
181
182 // Fields offsets.
183 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \
184 const int Name##_offset = LowBit; \
185 const int Name##_width = HighBit - LowBit + 1; \
186 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;
187 #define NOTHING(A, B)
188 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS)
189 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING)
190 #undef NOTHING
191 #undef DECLARE_FIELDS_BITS
192
193 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed
194 // from ImmPCRelLo and ImmPCRelHi.
195 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask;
196
197 // Condition codes.
198 enum Condition {
199 eq = 0, // Z set Equal.
200 ne = 1, // Z clear Not equal.
201 cs = 2, // C set Carry set.
202 cc = 3, // C clear Carry clear.
203 mi = 4, // N set Negative.
204 pl = 5, // N clear Positive or zero.
205 vs = 6, // V set Overflow.
206 vc = 7, // V clear No overflow.
207 hi = 8, // C set, Z clear Unsigned higher.
208 ls = 9, // C clear or Z set Unsigned lower or same.
209 ge = 10, // N == V Greater or equal.
210 lt = 11, // N != V Less than.
211 gt = 12, // Z clear, N == V Greater than.
212 le = 13, // Z set or N != V Less then or equal
213 al = 14, // Always.
214 nv = 15, // Behaves as always/al.
215
216 // Aliases.
217 hs = cs, // C set Unsigned higher or same.
218 lo = cc // C clear Unsigned lower.
219 };
220
221 inline Condition InvertCondition(Condition cond) {
222 // Conditions al and nv behave identically, as "always true". They can't be
223 // inverted, because there is no "always false" condition.
224 VIXL_ASSERT((cond != al) && (cond != nv));
225 return static_cast<Condition>(cond ^ 1);
226 }
227
228 enum FPTrapFlags {
229 EnableTrap = 1,
230 DisableTrap = 0
231 };
232
233 enum FlagsUpdate {
234 SetFlags = 1,
235 LeaveFlags = 0
236 };
237
238 enum StatusFlags {
239 NoFlag = 0,
240
241 // Derive the flag combinations from the system register bit descriptions.
242 NFlag = N_mask,
243 ZFlag = Z_mask,
244 CFlag = C_mask,
245 VFlag = V_mask,
246 NZFlag = NFlag | ZFlag,
247 NCFlag = NFlag | CFlag,
248 NVFlag = NFlag | VFlag,
249 ZCFlag = ZFlag | CFlag,
250 ZVFlag = ZFlag | VFlag,
251 CVFlag = CFlag | VFlag,
252 NZCFlag = NFlag | ZFlag | CFlag,
253 NZVFlag = NFlag | ZFlag | VFlag,
254 NCVFlag = NFlag | CFlag | VFlag,
255 ZCVFlag = ZFlag | CFlag | VFlag,
256 NZCVFlag = NFlag | ZFlag | CFlag | VFlag,
257
258 // Floating-point comparison results.
259 FPEqualFlag = ZCFlag,
260 FPLessThanFlag = NFlag,
261 FPGreaterThanFlag = CFlag,
262 FPUnorderedFlag = CVFlag
263 };
264
265 enum Shift {
266 NO_SHIFT = -1,
267 LSL = 0x0,
268 LSR = 0x1,
269 ASR = 0x2,
270 ROR = 0x3,
271 MSL = 0x4
272 };
273
274 enum Extend {
275 NO_EXTEND = -1,
276 UXTB = 0,
277 UXTH = 1,
278 UXTW = 2,
279 UXTX = 3,
280 SXTB = 4,
281 SXTH = 5,
282 SXTW = 6,
283 SXTX = 7
284 };
285
286 enum SystemHint {
287 NOP = 0,
288 YIELD = 1,
289 WFE = 2,
290 WFI = 3,
291 SEV = 4,
292 SEVL = 5
293 };
294
295 enum BarrierDomain {
296 OuterShareable = 0,
297 NonShareable = 1,
298 InnerShareable = 2,
299 FullSystem = 3
300 };
301
302 enum BarrierType {
303 BarrierOther = 0,
304 BarrierReads = 1,
305 BarrierWrites = 2,
306 BarrierAll = 3
307 };
308
309 enum PrefetchOperation {
310 PLDL1KEEP = 0x00,
311 PLDL1STRM = 0x01,
312 PLDL2KEEP = 0x02,
313 PLDL2STRM = 0x03,
314 PLDL3KEEP = 0x04,
315 PLDL3STRM = 0x05,
316
317 PLIL1KEEP = 0x08,
318 PLIL1STRM = 0x09,
319 PLIL2KEEP = 0x0a,
320 PLIL2STRM = 0x0b,
321 PLIL3KEEP = 0x0c,
322 PLIL3STRM = 0x0d,
323
324 PSTL1KEEP = 0x10,
325 PSTL1STRM = 0x11,
326 PSTL2KEEP = 0x12,
327 PSTL2STRM = 0x13,
328 PSTL3KEEP = 0x14,
329 PSTL3STRM = 0x15
330 };
331
332 // System/special register names.
333 // This information is not encoded as one field but as the concatenation of
334 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2).
335 enum SystemRegister {
336 NZCV = ((0x1 << SysO0_offset) |
337 (0x3 << SysOp1_offset) |
338 (0x4 << CRn_offset) |
339 (0x2 << CRm_offset) |
340 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset,
341 FPCR = ((0x1 << SysO0_offset) |
342 (0x3 << SysOp1_offset) |
343 (0x4 << CRn_offset) |
344 (0x4 << CRm_offset) |
345 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset
346 };
347
348 enum InstructionCacheOp {
349 IVAU = ((0x3 << SysOp1_offset) |
350 (0x7 << CRn_offset) |
351 (0x5 << CRm_offset) |
352 (0x1 << SysOp2_offset)) >> SysOp_offset
353 };
354
355 enum DataCacheOp {
356 CVAC = ((0x3 << SysOp1_offset) |
357 (0x7 << CRn_offset) |
358 (0xa << CRm_offset) |
359 (0x1 << SysOp2_offset)) >> SysOp_offset,
360 CVAU = ((0x3 << SysOp1_offset) |
361 (0x7 << CRn_offset) |
362 (0xb << CRm_offset) |
363 (0x1 << SysOp2_offset)) >> SysOp_offset,
364 CIVAC = ((0x3 << SysOp1_offset) |
365 (0x7 << CRn_offset) |
366 (0xe << CRm_offset) |
367 (0x1 << SysOp2_offset)) >> SysOp_offset,
368 ZVA = ((0x3 << SysOp1_offset) |
369 (0x7 << CRn_offset) |
370 (0x4 << CRm_offset) |
371 (0x1 << SysOp2_offset)) >> SysOp_offset
372 };
373
374 // Instruction enumerations.
375 //
376 // These are the masks that define a class of instructions, and the list of
377 // instructions within each class. Each enumeration has a Fixed, FMask and
378 // Mask value.
379 //
380 // Fixed: The fixed bits in this instruction class.
381 // FMask: The mask used to extract the fixed bits in the class.
382 // Mask: The mask used to identify the instructions within a class.
383 //
384 // The enumerations can be used like this:
385 //
386 // VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
387 // switch(instr->Mask(PCRelAddressingMask)) {
388 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
389 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break;
390 // default: printf("Unknown instruction\n");
391 // }
392
393
394 // Generic fields.
395 enum GenericInstrField {
396 SixtyFourBits = 0x80000000,
397 ThirtyTwoBits = 0x00000000,
398 FP32 = 0x00000000,
399 FP64 = 0x00400000
400 };
401
402 enum NEONFormatField {
403 NEONFormatFieldMask = 0x40C00000,
404 NEON_Q = 0x40000000,
405 NEON_8B = 0x00000000,
406 NEON_16B = NEON_8B | NEON_Q,
407 NEON_4H = 0x00400000,
408 NEON_8H = NEON_4H | NEON_Q,
409 NEON_2S = 0x00800000,
410 NEON_4S = NEON_2S | NEON_Q,
411 NEON_1D = 0x00C00000,
412 NEON_2D = 0x00C00000 | NEON_Q
413 };
414
415 enum NEONFPFormatField {
416 NEONFPFormatFieldMask = 0x40400000,
417 NEON_FP_2S = FP32,
418 NEON_FP_4S = FP32 | NEON_Q,
419 NEON_FP_2D = FP64 | NEON_Q
420 };
421
422 enum NEONLSFormatField {
423 NEONLSFormatFieldMask = 0x40000C00,
424 LS_NEON_8B = 0x00000000,
425 LS_NEON_16B = LS_NEON_8B | NEON_Q,
426 LS_NEON_4H = 0x00000400,
427 LS_NEON_8H = LS_NEON_4H | NEON_Q,
428 LS_NEON_2S = 0x00000800,
429 LS_NEON_4S = LS_NEON_2S | NEON_Q,
430 LS_NEON_1D = 0x00000C00,
431 LS_NEON_2D = LS_NEON_1D | NEON_Q
432 };
433
434 enum NEONScalarFormatField {
435 NEONScalarFormatFieldMask = 0x00C00000,
436 NEONScalar = 0x10000000,
437 NEON_B = 0x00000000,
438 NEON_H = 0x00400000,
439 NEON_S = 0x00800000,
440 NEON_D = 0x00C00000
441 };
442
443 // PC relative addressing.
444 enum PCRelAddressingOp {
445 PCRelAddressingFixed = 0x10000000,
446 PCRelAddressingFMask = 0x1F000000,
447 PCRelAddressingMask = 0x9F000000,
448 ADR = PCRelAddressingFixed | 0x00000000,
449 ADRP = PCRelAddressingFixed | 0x80000000
450 };
451
452 // Add/sub (immediate, shifted and extended.)
453 const int kSFOffset = 31;
454 enum AddSubOp {
455 AddSubOpMask = 0x60000000,
456 AddSubSetFlagsBit = 0x20000000,
457 ADD = 0x00000000,
458 ADDS = ADD | AddSubSetFlagsBit,
459 SUB = 0x40000000,
460 SUBS = SUB | AddSubSetFlagsBit
461 };
462
463 #define ADD_SUB_OP_LIST(V) \
464 V(ADD), \
465 V(ADDS), \
466 V(SUB), \
467 V(SUBS)
468
469 enum AddSubImmediateOp {
470 AddSubImmediateFixed = 0x11000000,
471 AddSubImmediateFMask = 0x1F000000,
472 AddSubImmediateMask = 0xFF000000,
473 #define ADD_SUB_IMMEDIATE(A) \
474 A##_w_imm = AddSubImmediateFixed | A, \
475 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits
476 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE)
477 #undef ADD_SUB_IMMEDIATE
478 };
479
480 enum AddSubShiftedOp {
481 AddSubShiftedFixed = 0x0B000000,
482 AddSubShiftedFMask = 0x1F200000,
483 AddSubShiftedMask = 0xFF200000,
484 #define ADD_SUB_SHIFTED(A) \
485 A##_w_shift = AddSubShiftedFixed | A, \
486 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits
487 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED)
488 #undef ADD_SUB_SHIFTED
489 };
490
491 enum AddSubExtendedOp {
492 AddSubExtendedFixed = 0x0B200000,
493 AddSubExtendedFMask = 0x1F200000,
494 AddSubExtendedMask = 0xFFE00000,
495 #define ADD_SUB_EXTENDED(A) \
496 A##_w_ext = AddSubExtendedFixed | A, \
497 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits
498 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED)
499 #undef ADD_SUB_EXTENDED
500 };
501
502 // Add/sub with carry.
503 enum AddSubWithCarryOp {
504 AddSubWithCarryFixed = 0x1A000000,
505 AddSubWithCarryFMask = 0x1FE00000,
506 AddSubWithCarryMask = 0xFFE0FC00,
507 ADC_w = AddSubWithCarryFixed | ADD,
508 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits,
509 ADC = ADC_w,
510 ADCS_w = AddSubWithCarryFixed | ADDS,
511 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
512 SBC_w = AddSubWithCarryFixed | SUB,
513 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits,
514 SBC = SBC_w,
515 SBCS_w = AddSubWithCarryFixed | SUBS,
516 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits
517 };
518
519
520 // Logical (immediate and shifted register).
521 enum LogicalOp {
522 LogicalOpMask = 0x60200000,
523 NOT = 0x00200000,
524 AND = 0x00000000,
525 BIC = AND | NOT,
526 ORR = 0x20000000,
527 ORN = ORR | NOT,
528 EOR = 0x40000000,
529 EON = EOR | NOT,
530 ANDS = 0x60000000,
531 BICS = ANDS | NOT
532 };
533
534 // Logical immediate.
535 enum LogicalImmediateOp {
536 LogicalImmediateFixed = 0x12000000,
537 LogicalImmediateFMask = 0x1F800000,
538 LogicalImmediateMask = 0xFF800000,
539 AND_w_imm = LogicalImmediateFixed | AND,
540 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits,
541 ORR_w_imm = LogicalImmediateFixed | ORR,
542 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits,
543 EOR_w_imm = LogicalImmediateFixed | EOR,
544 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits,
545 ANDS_w_imm = LogicalImmediateFixed | ANDS,
546 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
547 };
548
549 // Logical shifted register.
550 enum LogicalShiftedOp {
551 LogicalShiftedFixed = 0x0A000000,
552 LogicalShiftedFMask = 0x1F000000,
553 LogicalShiftedMask = 0xFF200000,
554 AND_w = LogicalShiftedFixed | AND,
555 AND_x = LogicalShiftedFixed | AND | SixtyFourBits,
556 AND_shift = AND_w,
557 BIC_w = LogicalShiftedFixed | BIC,
558 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits,
559 BIC_shift = BIC_w,
560 ORR_w = LogicalShiftedFixed | ORR,
561 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits,
562 ORR_shift = ORR_w,
563 ORN_w = LogicalShiftedFixed | ORN,
564 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits,
565 ORN_shift = ORN_w,
566 EOR_w = LogicalShiftedFixed | EOR,
567 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits,
568 EOR_shift = EOR_w,
569 EON_w = LogicalShiftedFixed | EON,
570 EON_x = LogicalShiftedFixed | EON | SixtyFourBits,
571 EON_shift = EON_w,
572 ANDS_w = LogicalShiftedFixed | ANDS,
573 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
574 ANDS_shift = ANDS_w,
575 BICS_w = LogicalShiftedFixed | BICS,
576 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits,
577 BICS_shift = BICS_w
578 };
579
580 // Move wide immediate.
581 enum MoveWideImmediateOp {
582 MoveWideImmediateFixed = 0x12800000,
583 MoveWideImmediateFMask = 0x1F800000,
584 MoveWideImmediateMask = 0xFF800000,
585 MOVN = 0x00000000,
586 MOVZ = 0x40000000,
587 MOVK = 0x60000000,
588 MOVN_w = MoveWideImmediateFixed | MOVN,
589 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
590 MOVZ_w = MoveWideImmediateFixed | MOVZ,
591 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
592 MOVK_w = MoveWideImmediateFixed | MOVK,
593 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits
594 };
595
596 // Bitfield.
597 const int kBitfieldNOffset = 22;
598 enum BitfieldOp {
599 BitfieldFixed = 0x13000000,
600 BitfieldFMask = 0x1F800000,
601 BitfieldMask = 0xFF800000,
602 SBFM_w = BitfieldFixed | 0x00000000,
603 SBFM_x = BitfieldFixed | 0x80000000,
604 SBFM = SBFM_w,
605 BFM_w = BitfieldFixed | 0x20000000,
606 BFM_x = BitfieldFixed | 0xA0000000,
607 BFM = BFM_w,
608 UBFM_w = BitfieldFixed | 0x40000000,
609 UBFM_x = BitfieldFixed | 0xC0000000,
610 UBFM = UBFM_w
611 // Bitfield N field.
612 };
613
614 // Extract.
615 enum ExtractOp {
616 ExtractFixed = 0x13800000,
617 ExtractFMask = 0x1F800000,
618 ExtractMask = 0xFFA00000,
619 EXTR_w = ExtractFixed | 0x00000000,
620 EXTR_x = ExtractFixed | 0x80000000,
621 EXTR = EXTR_w
622 };
623
624 // Unconditional branch.
625 enum UnconditionalBranchOp {
626 UnconditionalBranchFixed = 0x14000000,
627 UnconditionalBranchFMask = 0x7C000000,
628 UnconditionalBranchMask = 0xFC000000,
629 B = UnconditionalBranchFixed | 0x00000000,
630 BL = UnconditionalBranchFixed | 0x80000000
631 };
632
633 // Unconditional branch to register.
634 enum UnconditionalBranchToRegisterOp {
635 UnconditionalBranchToRegisterFixed = 0xD6000000,
636 UnconditionalBranchToRegisterFMask = 0xFE000000,
637 UnconditionalBranchToRegisterMask = 0xFFFFFC1F,
638 BR = UnconditionalBranchToRegisterFixed | 0x001F0000,
639 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000,
640 RET = UnconditionalBranchToRegisterFixed | 0x005F0000
641 };
642
643 // Compare and branch.
644 enum CompareBranchOp {
645 CompareBranchFixed = 0x34000000,
646 CompareBranchFMask = 0x7E000000,
647 CompareBranchMask = 0xFF000000,
648 CBZ_w = CompareBranchFixed | 0x00000000,
649 CBZ_x = CompareBranchFixed | 0x80000000,
650 CBZ = CBZ_w,
651 CBNZ_w = CompareBranchFixed | 0x01000000,
652 CBNZ_x = CompareBranchFixed | 0x81000000,
653 CBNZ = CBNZ_w
654 };
655
656 // Test and branch.
657 enum TestBranchOp {
658 TestBranchFixed = 0x36000000,
659 TestBranchFMask = 0x7E000000,
660 TestBranchMask = 0x7F000000,
661 TBZ = TestBranchFixed | 0x00000000,
662 TBNZ = TestBranchFixed | 0x01000000
663 };
664
665 // Conditional branch.
666 enum ConditionalBranchOp {
667 ConditionalBranchFixed = 0x54000000,
668 ConditionalBranchFMask = 0xFE000000,
669 ConditionalBranchMask = 0xFF000010,
670 B_cond = ConditionalBranchFixed | 0x00000000
671 };
672
673 // System.
674 // System instruction encoding is complicated because some instructions use op
675 // and CR fields to encode parameters. To handle this cleanly, the system
676 // instructions are split into more than one enum.
677
678 enum SystemOp {
679 SystemFixed = 0xD5000000,
680 SystemFMask = 0xFFC00000
681 };
682
683 enum SystemSysRegOp {
684 SystemSysRegFixed = 0xD5100000,
685 SystemSysRegFMask = 0xFFD00000,
686 SystemSysRegMask = 0xFFF00000,
687 MRS = SystemSysRegFixed | 0x00200000,
688 MSR = SystemSysRegFixed | 0x00000000
689 };
690
691 enum SystemHintOp {
692 SystemHintFixed = 0xD503201F,
693 SystemHintFMask = 0xFFFFF01F,
694 SystemHintMask = 0xFFFFF01F,
695 HINT = SystemHintFixed | 0x00000000
696 };
697
698 enum SystemSysOp {
699 SystemSysFixed = 0xD5080000,
700 SystemSysFMask = 0xFFF80000,
701 SystemSysMask = 0xFFF80000,
702 SYS = SystemSysFixed | 0x00000000
703 };
704
705 // Exception.
706 enum ExceptionOp {
707 ExceptionFixed = 0xD4000000,
708 ExceptionFMask = 0xFF000000,
709 ExceptionMask = 0xFFE0001F,
710 HLT = ExceptionFixed | 0x00400000,
711 BRK = ExceptionFixed | 0x00200000,
712 SVC = ExceptionFixed | 0x00000001,
713 HVC = ExceptionFixed | 0x00000002,
714 SMC = ExceptionFixed | 0x00000003,
715 DCPS1 = ExceptionFixed | 0x00A00001,
716 DCPS2 = ExceptionFixed | 0x00A00002,
717 DCPS3 = ExceptionFixed | 0x00A00003
718 };
719
720 enum MemBarrierOp {
721 MemBarrierFixed = 0xD503309F,
722 MemBarrierFMask = 0xFFFFF09F,
723 MemBarrierMask = 0xFFFFF0FF,
724 DSB = MemBarrierFixed | 0x00000000,
725 DMB = MemBarrierFixed | 0x00000020,
726 ISB = MemBarrierFixed | 0x00000040
727 };
728
729 enum SystemExclusiveMonitorOp {
730 SystemExclusiveMonitorFixed = 0xD503305F,
731 SystemExclusiveMonitorFMask = 0xFFFFF0FF,
732 SystemExclusiveMonitorMask = 0xFFFFF0FF,
733 CLREX = SystemExclusiveMonitorFixed
734 };
735
736 // Any load or store.
737 enum LoadStoreAnyOp {
738 LoadStoreAnyFMask = 0x0a000000,
739 LoadStoreAnyFixed = 0x08000000
740 };
741
742 // Any load pair or store pair.
743 enum LoadStorePairAnyOp {
744 LoadStorePairAnyFMask = 0x3a000000,
745 LoadStorePairAnyFixed = 0x28000000
746 };
747
748 #define LOAD_STORE_PAIR_OP_LIST(V) \
749 V(STP, w, 0x00000000), \
750 V(LDP, w, 0x00400000), \
751 V(LDPSW, x, 0x40400000), \
752 V(STP, x, 0x80000000), \
753 V(LDP, x, 0x80400000), \
754 V(STP, s, 0x04000000), \
755 V(LDP, s, 0x04400000), \
756 V(STP, d, 0x44000000), \
757 V(LDP, d, 0x44400000), \
758 V(STP, q, 0x84000000), \
759 V(LDP, q, 0x84400000)
760
761 // Load/store pair (post, pre and offset.)
762 enum LoadStorePairOp {
763 LoadStorePairMask = 0xC4400000,
764 LoadStorePairLBit = 1 << 22,
765 #define LOAD_STORE_PAIR(A, B, C) \
766 A##_##B = C
767 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR)
768 #undef LOAD_STORE_PAIR
769 };
770
771 enum LoadStorePairPostIndexOp {
772 LoadStorePairPostIndexFixed = 0x28800000,
773 LoadStorePairPostIndexFMask = 0x3B800000,
774 LoadStorePairPostIndexMask = 0xFFC00000,
775 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \
776 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B
777 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX)
778 #undef LOAD_STORE_PAIR_POST_INDEX
779 };
780
781 enum LoadStorePairPreIndexOp {
782 LoadStorePairPreIndexFixed = 0x29800000,
783 LoadStorePairPreIndexFMask = 0x3B800000,
784 LoadStorePairPreIndexMask = 0xFFC00000,
785 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \
786 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B
787 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX)
788 #undef LOAD_STORE_PAIR_PRE_INDEX
789 };
790
791 enum LoadStorePairOffsetOp {
792 LoadStorePairOffsetFixed = 0x29000000,
793 LoadStorePairOffsetFMask = 0x3B800000,
794 LoadStorePairOffsetMask = 0xFFC00000,
795 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \
796 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B
797 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET)
798 #undef LOAD_STORE_PAIR_OFFSET
799 };
800
801 enum LoadStorePairNonTemporalOp {
802 LoadStorePairNonTemporalFixed = 0x28000000,
803 LoadStorePairNonTemporalFMask = 0x3B800000,
804 LoadStorePairNonTemporalMask = 0xFFC00000,
805 LoadStorePairNonTemporalLBit = 1 << 22,
806 STNP_w = LoadStorePairNonTemporalFixed | STP_w,
807 LDNP_w = LoadStorePairNonTemporalFixed | LDP_w,
808 STNP_x = LoadStorePairNonTemporalFixed | STP_x,
809 LDNP_x = LoadStorePairNonTemporalFixed | LDP_x,
810 STNP_s = LoadStorePairNonTemporalFixed | STP_s,
811 LDNP_s = LoadStorePairNonTemporalFixed | LDP_s,
812 STNP_d = LoadStorePairNonTemporalFixed | STP_d,
813 LDNP_d = LoadStorePairNonTemporalFixed | LDP_d,
814 STNP_q = LoadStorePairNonTemporalFixed | STP_q,
815 LDNP_q = LoadStorePairNonTemporalFixed | LDP_q
816 };
817
818 // Load literal.
819 enum LoadLiteralOp {
820 LoadLiteralFixed = 0x18000000,
821 LoadLiteralFMask = 0x3B000000,
822 LoadLiteralMask = 0xFF000000,
823 LDR_w_lit = LoadLiteralFixed | 0x00000000,
824 LDR_x_lit = LoadLiteralFixed | 0x40000000,
825 LDRSW_x_lit = LoadLiteralFixed | 0x80000000,
826 PRFM_lit = LoadLiteralFixed | 0xC0000000,
827 LDR_s_lit = LoadLiteralFixed | 0x04000000,
828 LDR_d_lit = LoadLiteralFixed | 0x44000000,
829 LDR_q_lit = LoadLiteralFixed | 0x84000000
830 };
831
832 #define LOAD_STORE_OP_LIST(V) \
833 V(ST, RB, w, 0x00000000), \
834 V(ST, RH, w, 0x40000000), \
835 V(ST, R, w, 0x80000000), \
836 V(ST, R, x, 0xC0000000), \
837 V(LD, RB, w, 0x00400000), \
838 V(LD, RH, w, 0x40400000), \
839 V(LD, R, w, 0x80400000), \
840 V(LD, R, x, 0xC0400000), \
841 V(LD, RSB, x, 0x00800000), \
842 V(LD, RSH, x, 0x40800000), \
843 V(LD, RSW, x, 0x80800000), \
844 V(LD, RSB, w, 0x00C00000), \
845 V(LD, RSH, w, 0x40C00000), \
846 V(ST, R, b, 0x04000000), \
847 V(ST, R, h, 0x44000000), \
848 V(ST, R, s, 0x84000000), \
849 V(ST, R, d, 0xC4000000), \
850 V(ST, R, q, 0x04800000), \
851 V(LD, R, b, 0x04400000), \
852 V(LD, R, h, 0x44400000), \
853 V(LD, R, s, 0x84400000), \
854 V(LD, R, d, 0xC4400000), \
855 V(LD, R, q, 0x04C00000)
856
857 // Load/store (post, pre, offset and unsigned.)
858 enum LoadStoreOp {
859 LoadStoreMask = 0xC4C00000,
860 LoadStoreVMask = 0x04000000,
861 #define LOAD_STORE(A, B, C, D) \
862 A##B##_##C = D
863 LOAD_STORE_OP_LIST(LOAD_STORE),
864 #undef LOAD_STORE
865 PRFM = 0xC0800000
866 };
867
868 // Load/store unscaled offset.
869 enum LoadStoreUnscaledOffsetOp {
870 LoadStoreUnscaledOffsetFixed = 0x38000000,
871 LoadStoreUnscaledOffsetFMask = 0x3B200C00,
872 LoadStoreUnscaledOffsetMask = 0xFFE00C00,
873 PRFUM = LoadStoreUnscaledOffsetFixed | PRFM,
874 #define LOAD_STORE_UNSCALED(A, B, C, D) \
875 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D
876 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED)
877 #undef LOAD_STORE_UNSCALED
878 };
879
880 // Load/store post index.
881 enum LoadStorePostIndex {
882 LoadStorePostIndexFixed = 0x38000400,
883 LoadStorePostIndexFMask = 0x3B200C00,
884 LoadStorePostIndexMask = 0xFFE00C00,
885 #define LOAD_STORE_POST_INDEX(A, B, C, D) \
886 A##B##_##C##_post = LoadStorePostIndexFixed | D
887 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX)
888 #undef LOAD_STORE_POST_INDEX
889 };
890
891 // Load/store pre index.
892 enum LoadStorePreIndex {
893 LoadStorePreIndexFixed = 0x38000C00,
894 LoadStorePreIndexFMask = 0x3B200C00,
895 LoadStorePreIndexMask = 0xFFE00C00,
896 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \
897 A##B##_##C##_pre = LoadStorePreIndexFixed | D
898 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX)
899 #undef LOAD_STORE_PRE_INDEX
900 };
901
902 // Load/store unsigned offset.
903 enum LoadStoreUnsignedOffset {
904 LoadStoreUnsignedOffsetFixed = 0x39000000,
905 LoadStoreUnsignedOffsetFMask = 0x3B000000,
906 LoadStoreUnsignedOffsetMask = 0xFFC00000,
907 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM,
908 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \
909 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D
910 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET)
911 #undef LOAD_STORE_UNSIGNED_OFFSET
912 };
913
914 // Load/store register offset.
915 enum LoadStoreRegisterOffset {
916 LoadStoreRegisterOffsetFixed = 0x38200800,
917 LoadStoreRegisterOffsetFMask = 0x3B200C00,
918 LoadStoreRegisterOffsetMask = 0xFFE00C00,
919 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM,
920 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \
921 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D
922 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET)
923 #undef LOAD_STORE_REGISTER_OFFSET
924 };
925
926 enum LoadStoreExclusive {
927 LoadStoreExclusiveFixed = 0x08000000,
928 LoadStoreExclusiveFMask = 0x3F000000,
929 LoadStoreExclusiveMask = 0xFFE08000,
930 STXRB_w = LoadStoreExclusiveFixed | 0x00000000,
931 STXRH_w = LoadStoreExclusiveFixed | 0x40000000,
932 STXR_w = LoadStoreExclusiveFixed | 0x80000000,
933 STXR_x = LoadStoreExclusiveFixed | 0xC0000000,
934 LDXRB_w = LoadStoreExclusiveFixed | 0x00400000,
935 LDXRH_w = LoadStoreExclusiveFixed | 0x40400000,
936 LDXR_w = LoadStoreExclusiveFixed | 0x80400000,
937 LDXR_x = LoadStoreExclusiveFixed | 0xC0400000,
938 STXP_w = LoadStoreExclusiveFixed | 0x80200000,
939 STXP_x = LoadStoreExclusiveFixed | 0xC0200000,
940 LDXP_w = LoadStoreExclusiveFixed | 0x80600000,
941 LDXP_x = LoadStoreExclusiveFixed | 0xC0600000,
942 STLXRB_w = LoadStoreExclusiveFixed | 0x00008000,
943 STLXRH_w = LoadStoreExclusiveFixed | 0x40008000,
944 STLXR_w = LoadStoreExclusiveFixed | 0x80008000,
945 STLXR_x = LoadStoreExclusiveFixed | 0xC0008000,
946 LDAXRB_w = LoadStoreExclusiveFixed | 0x00408000,
947 LDAXRH_w = LoadStoreExclusiveFixed | 0x40408000,
948 LDAXR_w = LoadStoreExclusiveFixed | 0x80408000,
949 LDAXR_x = LoadStoreExclusiveFixed | 0xC0408000,
950 STLXP_w = LoadStoreExclusiveFixed | 0x80208000,
951 STLXP_x = LoadStoreExclusiveFixed | 0xC0208000,
952 LDAXP_w = LoadStoreExclusiveFixed | 0x80608000,
953 LDAXP_x = LoadStoreExclusiveFixed | 0xC0608000,
954 STLRB_w = LoadStoreExclusiveFixed | 0x00808000,
955 STLRH_w = LoadStoreExclusiveFixed | 0x40808000,
956 STLR_w = LoadStoreExclusiveFixed | 0x80808000,
957 STLR_x = LoadStoreExclusiveFixed | 0xC0808000,
958 LDARB_w = LoadStoreExclusiveFixed | 0x00C08000,
959 LDARH_w = LoadStoreExclusiveFixed | 0x40C08000,
960 LDAR_w = LoadStoreExclusiveFixed | 0x80C08000,
961 LDAR_x = LoadStoreExclusiveFixed | 0xC0C08000
962 };
963
964 // Conditional compare.
965 enum ConditionalCompareOp {
966 ConditionalCompareMask = 0x60000000,
967 CCMN = 0x20000000,
968 CCMP = 0x60000000
969 };
970
971 // Conditional compare register.
972 enum ConditionalCompareRegisterOp {
973 ConditionalCompareRegisterFixed = 0x1A400000,
974 ConditionalCompareRegisterFMask = 0x1FE00800,
975 ConditionalCompareRegisterMask = 0xFFE00C10,
976 CCMN_w = ConditionalCompareRegisterFixed | CCMN,
977 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN,
978 CCMP_w = ConditionalCompareRegisterFixed | CCMP,
979 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP
980 };
981
982 // Conditional compare immediate.
983 enum ConditionalCompareImmediateOp {
984 ConditionalCompareImmediateFixed = 0x1A400800,
985 ConditionalCompareImmediateFMask = 0x1FE00800,
986 ConditionalCompareImmediateMask = 0xFFE00C10,
987 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN,
988 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN,
989 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP,
990 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP
991 };
992
993 // Conditional select.
994 enum ConditionalSelectOp {
995 ConditionalSelectFixed = 0x1A800000,
996 ConditionalSelectFMask = 0x1FE00000,
997 ConditionalSelectMask = 0xFFE00C00,
998 CSEL_w = ConditionalSelectFixed | 0x00000000,
999 CSEL_x = ConditionalSelectFixed | 0x80000000,
1000 CSEL = CSEL_w,
1001 CSINC_w = ConditionalSelectFixed | 0x00000400,
1002 CSINC_x = ConditionalSelectFixed | 0x80000400,
1003 CSINC = CSINC_w,
1004 CSINV_w = ConditionalSelectFixed | 0x40000000,
1005 CSINV_x = ConditionalSelectFixed | 0xC0000000,
1006 CSINV = CSINV_w,
1007 CSNEG_w = ConditionalSelectFixed | 0x40000400,
1008 CSNEG_x = ConditionalSelectFixed | 0xC0000400,
1009 CSNEG = CSNEG_w
1010 };
1011
1012 // Data processing 1 source.
1013 enum DataProcessing1SourceOp {
1014 DataProcessing1SourceFixed = 0x5AC00000,
1015 DataProcessing1SourceFMask = 0x5FE00000,
1016 DataProcessing1SourceMask = 0xFFFFFC00,
1017 RBIT = DataProcessing1SourceFixed | 0x00000000,
1018 RBIT_w = RBIT,
1019 RBIT_x = RBIT | SixtyFourBits,
1020 REV16 = DataProcessing1SourceFixed | 0x00000400,
1021 REV16_w = REV16,
1022 REV16_x = REV16 | SixtyFourBits,
1023 REV = DataProcessing1SourceFixed | 0x00000800,
1024 REV_w = REV,
1025 REV32_x = REV | SixtyFourBits,
1026 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00,
1027 CLZ = DataProcessing1SourceFixed | 0x00001000,
1028 CLZ_w = CLZ,
1029 CLZ_x = CLZ | SixtyFourBits,
1030 CLS = DataProcessing1SourceFixed | 0x00001400,
1031 CLS_w = CLS,
1032 CLS_x = CLS | SixtyFourBits
1033 };
1034
1035 // Data processing 2 source.
1036 enum DataProcessing2SourceOp {
1037 DataProcessing2SourceFixed = 0x1AC00000,
1038 DataProcessing2SourceFMask = 0x5FE00000,
1039 DataProcessing2SourceMask = 0xFFE0FC00,
1040 UDIV_w = DataProcessing2SourceFixed | 0x00000800,
1041 UDIV_x = DataProcessing2SourceFixed | 0x80000800,
1042 UDIV = UDIV_w,
1043 SDIV_w = DataProcessing2SourceFixed | 0x00000C00,
1044 SDIV_x = DataProcessing2SourceFixed | 0x80000C00,
1045 SDIV = SDIV_w,
1046 LSLV_w = DataProcessing2SourceFixed | 0x00002000,
1047 LSLV_x = DataProcessing2SourceFixed | 0x80002000,
1048 LSLV = LSLV_w,
1049 LSRV_w = DataProcessing2SourceFixed | 0x00002400,
1050 LSRV_x = DataProcessing2SourceFixed | 0x80002400,
1051 LSRV = LSRV_w,
1052 ASRV_w = DataProcessing2SourceFixed | 0x00002800,
1053 ASRV_x = DataProcessing2SourceFixed | 0x80002800,
1054 ASRV = ASRV_w,
1055 RORV_w = DataProcessing2SourceFixed | 0x00002C00,
1056 RORV_x = DataProcessing2SourceFixed | 0x80002C00,
1057 RORV = RORV_w,
1058 CRC32B = DataProcessing2SourceFixed | 0x00004000,
1059 CRC32H = DataProcessing2SourceFixed | 0x00004400,
1060 CRC32W = DataProcessing2SourceFixed | 0x00004800,
1061 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00,
1062 CRC32CB = DataProcessing2SourceFixed | 0x00005000,
1063 CRC32CH = DataProcessing2SourceFixed | 0x00005400,
1064 CRC32CW = DataProcessing2SourceFixed | 0x00005800,
1065 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00
1066 };
1067
1068 // Data processing 3 source.
1069 enum DataProcessing3SourceOp {
1070 DataProcessing3SourceFixed = 0x1B000000,
1071 DataProcessing3SourceFMask = 0x1F000000,
1072 DataProcessing3SourceMask = 0xFFE08000,
1073 MADD_w = DataProcessing3SourceFixed | 0x00000000,
1074 MADD_x = DataProcessing3SourceFixed | 0x80000000,
1075 MADD = MADD_w,
1076 MSUB_w = DataProcessing3SourceFixed | 0x00008000,
1077 MSUB_x = DataProcessing3SourceFixed | 0x80008000,
1078 MSUB = MSUB_w,
1079 SMADDL_x = DataProcessing3SourceFixed | 0x80200000,
1080 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000,
1081 SMULH_x = DataProcessing3SourceFixed | 0x80400000,
1082 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000,
1083 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000,
1084 UMULH_x = DataProcessing3SourceFixed | 0x80C00000
1085 };
1086
1087 // Floating point compare.
1088 enum FPCompareOp {
1089 FPCompareFixed = 0x1E202000,
1090 FPCompareFMask = 0x5F203C00,
1091 FPCompareMask = 0xFFE0FC1F,
1092 FCMP_s = FPCompareFixed | 0x00000000,
1093 FCMP_d = FPCompareFixed | FP64 | 0x00000000,
1094 FCMP = FCMP_s,
1095 FCMP_s_zero = FPCompareFixed | 0x00000008,
1096 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008,
1097 FCMP_zero = FCMP_s_zero,
1098 FCMPE_s = FPCompareFixed | 0x00000010,
1099 FCMPE_d = FPCompareFixed | FP64 | 0x00000010,
1100 FCMPE = FCMPE_s,
1101 FCMPE_s_zero = FPCompareFixed | 0x00000018,
1102 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018,
1103 FCMPE_zero = FCMPE_s_zero
1104 };
1105
1106 // Floating point conditional compare.
1107 enum FPConditionalCompareOp {
1108 FPConditionalCompareFixed = 0x1E200400,
1109 FPConditionalCompareFMask = 0x5F200C00,
1110 FPConditionalCompareMask = 0xFFE00C10,
1111 FCCMP_s = FPConditionalCompareFixed | 0x00000000,
1112 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000,
1113 FCCMP = FCCMP_s,
1114 FCCMPE_s = FPConditionalCompareFixed | 0x00000010,
1115 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010,
1116 FCCMPE = FCCMPE_s
1117 };
1118
1119 // Floating point conditional select.
1120 enum FPConditionalSelectOp {
1121 FPConditionalSelectFixed = 0x1E200C00,
1122 FPConditionalSelectFMask = 0x5F200C00,
1123 FPConditionalSelectMask = 0xFFE00C00,
1124 FCSEL_s = FPConditionalSelectFixed | 0x00000000,
1125 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000,
1126 FCSEL = FCSEL_s
1127 };
1128
1129 // Floating point immediate.
1130 enum FPImmediateOp {
1131 FPImmediateFixed = 0x1E201000,
1132 FPImmediateFMask = 0x5F201C00,
1133 FPImmediateMask = 0xFFE01C00,
1134 FMOV_s_imm = FPImmediateFixed | 0x00000000,
1135 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000
1136 };
1137
1138 // Floating point data processing 1 source.
1139 enum FPDataProcessing1SourceOp {
1140 FPDataProcessing1SourceFixed = 0x1E204000,
1141 FPDataProcessing1SourceFMask = 0x5F207C00,
1142 FPDataProcessing1SourceMask = 0xFFFFFC00,
1143 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000,
1144 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000,
1145 FMOV = FMOV_s,
1146 FABS_s = FPDataProcessing1SourceFixed | 0x00008000,
1147 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000,
1148 FABS = FABS_s,
1149 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000,
1150 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000,
1151 FNEG = FNEG_s,
1152 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000,
1153 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000,
1154 FSQRT = FSQRT_s,
1155 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000,
1156 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000,
1157 FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000,
1158 FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000,
1159 FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000,
1160 FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000,
1161 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000,
1162 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000,
1163 FRINTN = FRINTN_s,
1164 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000,
1165 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000,
1166 FRINTP = FRINTP_s,
1167 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
1168 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000,
1169 FRINTM = FRINTM_s,
1170 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000,
1171 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
1172 FRINTZ = FRINTZ_s,
1173 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000,
1174 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000,
1175 FRINTA = FRINTA_s,
1176 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000,
1177 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000,
1178 FRINTX = FRINTX_s,
1179 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
1180 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000,
1181 FRINTI = FRINTI_s
1182 };
1183
1184 // Floating point data processing 2 source.
1185 enum FPDataProcessing2SourceOp {
1186 FPDataProcessing2SourceFixed = 0x1E200800,
1187 FPDataProcessing2SourceFMask = 0x5F200C00,
1188 FPDataProcessing2SourceMask = 0xFFE0FC00,
1189 FMUL = FPDataProcessing2SourceFixed | 0x00000000,
1190 FMUL_s = FMUL,
1191 FMUL_d = FMUL | FP64,
1192 FDIV = FPDataProcessing2SourceFixed | 0x00001000,
1193 FDIV_s = FDIV,
1194 FDIV_d = FDIV | FP64,
1195 FADD = FPDataProcessing2SourceFixed | 0x00002000,
1196 FADD_s = FADD,
1197 FADD_d = FADD | FP64,
1198 FSUB = FPDataProcessing2SourceFixed | 0x00003000,
1199 FSUB_s = FSUB,
1200 FSUB_d = FSUB | FP64,
1201 FMAX = FPDataProcessing2SourceFixed | 0x00004000,
1202 FMAX_s = FMAX,
1203 FMAX_d = FMAX | FP64,
1204 FMIN = FPDataProcessing2SourceFixed | 0x00005000,
1205 FMIN_s = FMIN,
1206 FMIN_d = FMIN | FP64,
1207 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000,
1208 FMAXNM_s = FMAXNM,
1209 FMAXNM_d = FMAXNM | FP64,
1210 FMINNM = FPDataProcessing2SourceFixed | 0x00007000,
1211 FMINNM_s = FMINNM,
1212 FMINNM_d = FMINNM | FP64,
1213 FNMUL = FPDataProcessing2SourceFixed | 0x00008000,
1214 FNMUL_s = FNMUL,
1215 FNMUL_d = FNMUL | FP64
1216 };
1217
1218 // Floating point data processing 3 source.
1219 enum FPDataProcessing3SourceOp {
1220 FPDataProcessing3SourceFixed = 0x1F000000,
1221 FPDataProcessing3SourceFMask = 0x5F000000,
1222 FPDataProcessing3SourceMask = 0xFFE08000,
1223 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000,
1224 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000,
1225 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000,
1226 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000,
1227 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000,
1228 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000,
1229 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000,
1230 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000
1231 };
1232
1233 // Conversion between floating point and integer.
1234 enum FPIntegerConvertOp {
1235 FPIntegerConvertFixed = 0x1E200000,
1236 FPIntegerConvertFMask = 0x5F20FC00,
1237 FPIntegerConvertMask = 0xFFFFFC00,
1238 FCVTNS = FPIntegerConvertFixed | 0x00000000,
1239 FCVTNS_ws = FCVTNS,
1240 FCVTNS_xs = FCVTNS | SixtyFourBits,
1241 FCVTNS_wd = FCVTNS | FP64,
1242 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64,
1243 FCVTNU = FPIntegerConvertFixed | 0x00010000,
1244 FCVTNU_ws = FCVTNU,
1245 FCVTNU_xs = FCVTNU | SixtyFourBits,
1246 FCVTNU_wd = FCVTNU | FP64,
1247 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64,
1248 FCVTPS = FPIntegerConvertFixed | 0x00080000,
1249 FCVTPS_ws = FCVTPS,
1250 FCVTPS_xs = FCVTPS | SixtyFourBits,
1251 FCVTPS_wd = FCVTPS | FP64,
1252 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64,
1253 FCVTPU = FPIntegerConvertFixed | 0x00090000,
1254 FCVTPU_ws = FCVTPU,
1255 FCVTPU_xs = FCVTPU | SixtyFourBits,
1256 FCVTPU_wd = FCVTPU | FP64,
1257 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64,
1258 FCVTMS = FPIntegerConvertFixed | 0x00100000,
1259 FCVTMS_ws = FCVTMS,
1260 FCVTMS_xs = FCVTMS | SixtyFourBits,
1261 FCVTMS_wd = FCVTMS | FP64,
1262 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64,
1263 FCVTMU = FPIntegerConvertFixed | 0x00110000,
1264 FCVTMU_ws = FCVTMU,
1265 FCVTMU_xs = FCVTMU | SixtyFourBits,
1266 FCVTMU_wd = FCVTMU | FP64,
1267 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64,
1268 FCVTZS = FPIntegerConvertFixed | 0x00180000,
1269 FCVTZS_ws = FCVTZS,
1270 FCVTZS_xs = FCVTZS | SixtyFourBits,
1271 FCVTZS_wd = FCVTZS | FP64,
1272 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64,
1273 FCVTZU = FPIntegerConvertFixed | 0x00190000,
1274 FCVTZU_ws = FCVTZU,
1275 FCVTZU_xs = FCVTZU | SixtyFourBits,
1276 FCVTZU_wd = FCVTZU | FP64,
1277 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64,
1278 SCVTF = FPIntegerConvertFixed | 0x00020000,
1279 SCVTF_sw = SCVTF,
1280 SCVTF_sx = SCVTF | SixtyFourBits,
1281 SCVTF_dw = SCVTF | FP64,
1282 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
1283 UCVTF = FPIntegerConvertFixed | 0x00030000,
1284 UCVTF_sw = UCVTF,
1285 UCVTF_sx = UCVTF | SixtyFourBits,
1286 UCVTF_dw = UCVTF | FP64,
1287 UCVTF_dx = UCVTF | SixtyFourBits | FP64,
1288 FCVTAS = FPIntegerConvertFixed | 0x00040000,
1289 FCVTAS_ws = FCVTAS,
1290 FCVTAS_xs = FCVTAS | SixtyFourBits,
1291 FCVTAS_wd = FCVTAS | FP64,
1292 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64,
1293 FCVTAU = FPIntegerConvertFixed | 0x00050000,
1294 FCVTAU_ws = FCVTAU,
1295 FCVTAU_xs = FCVTAU | SixtyFourBits,
1296 FCVTAU_wd = FCVTAU | FP64,
1297 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64,
1298 FMOV_ws = FPIntegerConvertFixed | 0x00060000,
1299 FMOV_sw = FPIntegerConvertFixed | 0x00070000,
1300 FMOV_xd = FMOV_ws | SixtyFourBits | FP64,
1301 FMOV_dx = FMOV_sw | SixtyFourBits | FP64,
1302 FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000,
1303 FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000
1304 };
1305
1306 // Conversion between fixed point and floating point.
1307 enum FPFixedPointConvertOp {
1308 FPFixedPointConvertFixed = 0x1E000000,
1309 FPFixedPointConvertFMask = 0x5F200000,
1310 FPFixedPointConvertMask = 0xFFFF0000,
1311 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000,
1312 FCVTZS_ws_fixed = FCVTZS_fixed,
1313 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits,
1314 FCVTZS_wd_fixed = FCVTZS_fixed | FP64,
1315 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64,
1316 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000,
1317 FCVTZU_ws_fixed = FCVTZU_fixed,
1318 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits,
1319 FCVTZU_wd_fixed = FCVTZU_fixed | FP64,
1320 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64,
1321 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000,
1322 SCVTF_sw_fixed = SCVTF_fixed,
1323 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits,
1324 SCVTF_dw_fixed = SCVTF_fixed | FP64,
1325 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64,
1326 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000,
1327 UCVTF_sw_fixed = UCVTF_fixed,
1328 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits,
1329 UCVTF_dw_fixed = UCVTF_fixed | FP64,
1330 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64
1331 };
1332
1333 // Crypto - two register SHA.
1334 enum Crypto2RegSHAOp {
1335 Crypto2RegSHAFixed = 0x5E280800,
1336 Crypto2RegSHAFMask = 0xFF3E0C00
1337 };
1338
1339 // Crypto - three register SHA.
1340 enum Crypto3RegSHAOp {
1341 Crypto3RegSHAFixed = 0x5E000000,
1342 Crypto3RegSHAFMask = 0xFF208C00
1343 };
1344
1345 // Crypto - AES.
1346 enum CryptoAESOp {
1347 CryptoAESFixed = 0x4E280800,
1348 CryptoAESFMask = 0xFF3E0C00
1349 };
1350
1351 // NEON instructions with two register operands.
1352 enum NEON2RegMiscOp {
1353 NEON2RegMiscFixed = 0x0E200800,
1354 NEON2RegMiscFMask = 0x9F3E0C00,
1355 NEON2RegMiscMask = 0xBF3FFC00,
1356 NEON2RegMiscUBit = 0x20000000,
1357 NEON_REV64 = NEON2RegMiscFixed | 0x00000000,
1358 NEON_REV32 = NEON2RegMiscFixed | 0x20000000,
1359 NEON_REV16 = NEON2RegMiscFixed | 0x00001000,
1360 NEON_SADDLP = NEON2RegMiscFixed | 0x00002000,
1361 NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit,
1362 NEON_SUQADD = NEON2RegMiscFixed | 0x00003000,
1363 NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit,
1364 NEON_CLS = NEON2RegMiscFixed | 0x00004000,
1365 NEON_CLZ = NEON2RegMiscFixed | 0x20004000,
1366 NEON_CNT = NEON2RegMiscFixed | 0x00005000,
1367 NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000,
1368 NEON_SADALP = NEON2RegMiscFixed | 0x00006000,
1369 NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit,
1370 NEON_SQABS = NEON2RegMiscFixed | 0x00007000,
1371 NEON_SQNEG = NEON2RegMiscFixed | 0x20007000,
1372 NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000,
1373 NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000,
1374 NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000,
1375 NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000,
1376 NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000,
1377 NEON_ABS = NEON2RegMiscFixed | 0x0000B000,
1378 NEON_NEG = NEON2RegMiscFixed | 0x2000B000,
1379 NEON_XTN = NEON2RegMiscFixed | 0x00012000,
1380 NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000,
1381 NEON_SHLL = NEON2RegMiscFixed | 0x20013000,
1382 NEON_SQXTN = NEON2RegMiscFixed | 0x00014000,
1383 NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit,
1384
1385 NEON2RegMiscOpcode = 0x0001F000,
1386 NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode,
1387 NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode,
1388 NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode,
1389 NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode,
1390
1391 // These instructions use only one bit of the size field. The other bit is
1392 // used to distinguish between instructions.
1393 NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000,
1394 NEON_FABS = NEON2RegMiscFixed | 0x0080F000,
1395 NEON_FNEG = NEON2RegMiscFixed | 0x2080F000,
1396 NEON_FCVTN = NEON2RegMiscFixed | 0x00016000,
1397 NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000,
1398 NEON_FCVTL = NEON2RegMiscFixed | 0x00017000,
1399 NEON_FRINTN = NEON2RegMiscFixed | 0x00018000,
1400 NEON_FRINTA = NEON2RegMiscFixed | 0x20018000,
1401 NEON_FRINTP = NEON2RegMiscFixed | 0x00818000,
1402 NEON_FRINTM = NEON2RegMiscFixed | 0x00019000,
1403 NEON_FRINTX = NEON2RegMiscFixed | 0x20019000,
1404 NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000,
1405 NEON_FRINTI = NEON2RegMiscFixed | 0x20819000,
1406 NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000,
1407 NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit,
1408 NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000,
1409 NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit,
1410 NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000,
1411 NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit,
1412 NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000,
1413 NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit,
1414 NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000,
1415 NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit,
1416 NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000,
1417 NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000,
1418 NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit,
1419 NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000,
1420 NEON_URECPE = NEON2RegMiscFixed | 0x0081C000,
1421 NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000,
1422 NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000,
1423 NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000,
1424 NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000,
1425 NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000,
1426 NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000,
1427 NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000,
1428
1429 NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode,
1430 NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode
1431 };
1432
1433 // NEON instructions with three same-type operands.
1434 enum NEON3SameOp {
1435 NEON3SameFixed = 0x0E200400,
1436 NEON3SameFMask = 0x9F200400,
1437 NEON3SameMask = 0xBF20FC00,
1438 NEON3SameUBit = 0x20000000,
1439 NEON_ADD = NEON3SameFixed | 0x00008000,
1440 NEON_ADDP = NEON3SameFixed | 0x0000B800,
1441 NEON_SHADD = NEON3SameFixed | 0x00000000,
1442 NEON_SHSUB = NEON3SameFixed | 0x00002000,
1443 NEON_SRHADD = NEON3SameFixed | 0x00001000,
1444 NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800,
1445 NEON_CMGE = NEON3SameFixed | 0x00003800,
1446 NEON_CMGT = NEON3SameFixed | 0x00003000,
1447 NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT,
1448 NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE,
1449 NEON_CMTST = NEON3SameFixed | 0x00008800,
1450 NEON_MLA = NEON3SameFixed | 0x00009000,
1451 NEON_MLS = NEON3SameFixed | 0x20009000,
1452 NEON_MUL = NEON3SameFixed | 0x00009800,
1453 NEON_PMUL = NEON3SameFixed | 0x20009800,
1454 NEON_SRSHL = NEON3SameFixed | 0x00005000,
1455 NEON_SQSHL = NEON3SameFixed | 0x00004800,
1456 NEON_SQRSHL = NEON3SameFixed | 0x00005800,
1457 NEON_SSHL = NEON3SameFixed | 0x00004000,
1458 NEON_SMAX = NEON3SameFixed | 0x00006000,
1459 NEON_SMAXP = NEON3SameFixed | 0x0000A000,
1460 NEON_SMIN = NEON3SameFixed | 0x00006800,
1461 NEON_SMINP = NEON3SameFixed | 0x0000A800,
1462 NEON_SABD = NEON3SameFixed | 0x00007000,
1463 NEON_SABA = NEON3SameFixed | 0x00007800,
1464 NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD,
1465 NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA,
1466 NEON_SQADD = NEON3SameFixed | 0x00000800,
1467 NEON_SQSUB = NEON3SameFixed | 0x00002800,
1468 NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000,
1469 NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD,
1470 NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB,
1471 NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD,
1472 NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX,
1473 NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP,
1474 NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN,
1475 NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP,
1476 NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL,
1477 NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD,
1478 NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL,
1479 NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL,
1480 NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB,
1481 NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL,
1482 NEON_SQDMULH = NEON3SameFixed | 0x0000B000,
1483 NEON_SQRDMULH = NEON3SameFixed | 0x2000B000,
1484
1485 // NEON floating point instructions with three same-type operands.
1486 NEON3SameFPFixed = NEON3SameFixed | 0x0000C000,
1487 NEON3SameFPFMask = NEON3SameFMask | 0x0000C000,
1488 NEON3SameFPMask = NEON3SameMask | 0x00800000,
1489 NEON_FADD = NEON3SameFixed | 0x0000D000,
1490 NEON_FSUB = NEON3SameFixed | 0x0080D000,
1491 NEON_FMUL = NEON3SameFixed | 0x2000D800,
1492 NEON_FDIV = NEON3SameFixed | 0x2000F800,
1493 NEON_FMAX = NEON3SameFixed | 0x0000F000,
1494 NEON_FMAXNM = NEON3SameFixed | 0x0000C000,
1495 NEON_FMAXP = NEON3SameFixed | 0x2000F000,
1496 NEON_FMAXNMP = NEON3SameFixed | 0x2000C000,
1497 NEON_FMIN = NEON3SameFixed | 0x0080F000,
1498 NEON_FMINNM = NEON3SameFixed | 0x0080C000,
1499 NEON_FMINP = NEON3SameFixed | 0x2080F000,
1500 NEON_FMINNMP = NEON3SameFixed | 0x2080C000,
1501 NEON_FMLA = NEON3SameFixed | 0x0000C800,
1502 NEON_FMLS = NEON3SameFixed | 0x0080C800,
1503 NEON_FMULX = NEON3SameFixed | 0x0000D800,
1504 NEON_FRECPS = NEON3SameFixed | 0x0000F800,
1505 NEON_FRSQRTS = NEON3SameFixed | 0x0080F800,
1506 NEON_FABD = NEON3SameFixed | 0x2080D000,
1507 NEON_FADDP = NEON3SameFixed | 0x2000D000,
1508 NEON_FCMEQ = NEON3SameFixed | 0x0000E000,
1509 NEON_FCMGE = NEON3SameFixed | 0x2000E000,
1510 NEON_FCMGT = NEON3SameFixed | 0x2080E000,
1511 NEON_FACGE = NEON3SameFixed | 0x2000E800,
1512 NEON_FACGT = NEON3SameFixed | 0x2080E800,
1513
1514 // NEON logical instructions with three same-type operands.
1515 NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800,
1516 NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800,
1517 NEON3SameLogicalMask = 0xBFE0FC00,
1518 NEON3SameLogicalFormatMask = NEON_Q,
1519 NEON_AND = NEON3SameLogicalFixed | 0x00000000,
1520 NEON_ORR = NEON3SameLogicalFixed | 0x00A00000,
1521 NEON_ORN = NEON3SameLogicalFixed | 0x00C00000,
1522 NEON_EOR = NEON3SameLogicalFixed | 0x20000000,
1523 NEON_BIC = NEON3SameLogicalFixed | 0x00400000,
1524 NEON_BIF = NEON3SameLogicalFixed | 0x20C00000,
1525 NEON_BIT = NEON3SameLogicalFixed | 0x20800000,
1526 NEON_BSL = NEON3SameLogicalFixed | 0x20400000
1527 };
1528
1529 // NEON instructions with three different-type operands.
1530 enum NEON3DifferentOp {
1531 NEON3DifferentFixed = 0x0E200000,
1532 NEON3DifferentFMask = 0x9F200C00,
1533 NEON3DifferentMask = 0xFF20FC00,
1534 NEON_ADDHN = NEON3DifferentFixed | 0x00004000,
1535 NEON_ADDHN2 = NEON_ADDHN | NEON_Q,
1536 NEON_PMULL = NEON3DifferentFixed | 0x0000E000,
1537 NEON_PMULL2 = NEON_PMULL | NEON_Q,
1538 NEON_RADDHN = NEON3DifferentFixed | 0x20004000,
1539 NEON_RADDHN2 = NEON_RADDHN | NEON_Q,
1540 NEON_RSUBHN = NEON3DifferentFixed | 0x20006000,
1541 NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q,
1542 NEON_SABAL = NEON3DifferentFixed | 0x00005000,
1543 NEON_SABAL2 = NEON_SABAL | NEON_Q,
1544 NEON_SABDL = NEON3DifferentFixed | 0x00007000,
1545 NEON_SABDL2 = NEON_SABDL | NEON_Q,
1546 NEON_SADDL = NEON3DifferentFixed | 0x00000000,
1547 NEON_SADDL2 = NEON_SADDL | NEON_Q,
1548 NEON_SADDW = NEON3DifferentFixed | 0x00001000,
1549 NEON_SADDW2 = NEON_SADDW | NEON_Q,
1550 NEON_SMLAL = NEON3DifferentFixed | 0x00008000,
1551 NEON_SMLAL2 = NEON_SMLAL | NEON_Q,
1552 NEON_SMLSL = NEON3DifferentFixed | 0x0000A000,
1553 NEON_SMLSL2 = NEON_SMLSL | NEON_Q,
1554 NEON_SMULL = NEON3DifferentFixed | 0x0000C000,
1555 NEON_SMULL2 = NEON_SMULL | NEON_Q,
1556 NEON_SSUBL = NEON3DifferentFixed | 0x00002000,
1557 NEON_SSUBL2 = NEON_SSUBL | NEON_Q,
1558 NEON_SSUBW = NEON3DifferentFixed | 0x00003000,
1559 NEON_SSUBW2 = NEON_SSUBW | NEON_Q,
1560 NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000,
1561 NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q,
1562 NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000,
1563 NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q,
1564 NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000,
1565 NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q,
1566 NEON_SUBHN = NEON3DifferentFixed | 0x00006000,
1567 NEON_SUBHN2 = NEON_SUBHN | NEON_Q,
1568 NEON_UABAL = NEON_SABAL | NEON3SameUBit,
1569 NEON_UABAL2 = NEON_UABAL | NEON_Q,
1570 NEON_UABDL = NEON_SABDL | NEON3SameUBit,
1571 NEON_UABDL2 = NEON_UABDL | NEON_Q,
1572 NEON_UADDL = NEON_SADDL | NEON3SameUBit,
1573 NEON_UADDL2 = NEON_UADDL | NEON_Q,
1574 NEON_UADDW = NEON_SADDW | NEON3SameUBit,
1575 NEON_UADDW2 = NEON_UADDW | NEON_Q,
1576 NEON_UMLAL = NEON_SMLAL | NEON3SameUBit,
1577 NEON_UMLAL2 = NEON_UMLAL | NEON_Q,
1578 NEON_UMLSL = NEON_SMLSL | NEON3SameUBit,
1579 NEON_UMLSL2 = NEON_UMLSL | NEON_Q,
1580 NEON_UMULL = NEON_SMULL | NEON3SameUBit,
1581 NEON_UMULL2 = NEON_UMULL | NEON_Q,
1582 NEON_USUBL = NEON_SSUBL | NEON3SameUBit,
1583 NEON_USUBL2 = NEON_USUBL | NEON_Q,
1584 NEON_USUBW = NEON_SSUBW | NEON3SameUBit,
1585 NEON_USUBW2 = NEON_USUBW | NEON_Q
1586 };
1587
1588 // NEON instructions operating across vectors.
1589 enum NEONAcrossLanesOp {
1590 NEONAcrossLanesFixed = 0x0E300800,
1591 NEONAcrossLanesFMask = 0x9F3E0C00,
1592 NEONAcrossLanesMask = 0xBF3FFC00,
1593 NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000,
1594 NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000,
1595 NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000,
1596 NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000,
1597 NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000,
1598 NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000,
1599 NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000,
1600
1601 // NEON floating point across instructions.
1602 NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x0000C000,
1603 NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x0000C000,
1604 NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x00800000,
1605
1606 NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000,
1607 NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000,
1608 NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000,
1609 NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000
1610 };
1611
1612 // NEON instructions with indexed element operand.
1613 enum NEONByIndexedElementOp {
1614 NEONByIndexedElementFixed = 0x0F000000,
1615 NEONByIndexedElementFMask = 0x9F000400,
1616 NEONByIndexedElementMask = 0xBF00F400,
1617 NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000,
1618 NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000,
1619 NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000,
1620 NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000,
1621 NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000,
1622 NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000,
1623 NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000,
1624 NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000,
1625 NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000,
1626 NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000,
1627 NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000,
1628 NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000,
1629 NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000,
1630 NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000,
1631
1632 // Floating point instructions.
1633 NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000,
1634 NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000,
1635 NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000,
1636 NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000,
1637 NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000,
1638 NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000
1639 };
1640
1641 // NEON register copy.
1642 enum NEONCopyOp {
1643 NEONCopyFixed = 0x0E000400,
1644 NEONCopyFMask = 0x9FE08400,
1645 NEONCopyMask = 0x3FE08400,
1646 NEONCopyInsElementMask = NEONCopyMask | 0x40000000,
1647 NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800,
1648 NEONCopyDupElementMask = NEONCopyMask | 0x20007800,
1649 NEONCopyDupGeneralMask = NEONCopyDupElementMask,
1650 NEONCopyUmovMask = NEONCopyMask | 0x20007800,
1651 NEONCopySmovMask = NEONCopyMask | 0x20007800,
1652 NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000,
1653 NEON_INS_GENERAL = NEONCopyFixed | 0x40001800,
1654 NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000,
1655 NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800,
1656 NEON_SMOV = NEONCopyFixed | 0x00002800,
1657 NEON_UMOV = NEONCopyFixed | 0x00003800
1658 };
1659
1660 // NEON extract.
1661 enum NEONExtractOp {
1662 NEONExtractFixed = 0x2E000000,
1663 NEONExtractFMask = 0xBF208400,
1664 NEONExtractMask = 0xBFE08400,
1665 NEON_EXT = NEONExtractFixed | 0x00000000
1666 };
1667
1668 enum NEONLoadStoreMultiOp {
1669 NEONLoadStoreMultiL = 0x00400000,
1670 NEONLoadStoreMulti1_1v = 0x00007000,
1671 NEONLoadStoreMulti1_2v = 0x0000A000,
1672 NEONLoadStoreMulti1_3v = 0x00006000,
1673 NEONLoadStoreMulti1_4v = 0x00002000,
1674 NEONLoadStoreMulti2 = 0x00008000,
1675 NEONLoadStoreMulti3 = 0x00004000,
1676 NEONLoadStoreMulti4 = 0x00000000
1677 };
1678
1679 // NEON load/store multiple structures.
1680 enum NEONLoadStoreMultiStructOp {
1681 NEONLoadStoreMultiStructFixed = 0x0C000000,
1682 NEONLoadStoreMultiStructFMask = 0xBFBF0000,
1683 NEONLoadStoreMultiStructMask = 0xBFFFF000,
1684 NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed,
1685 NEONLoadStoreMultiStructLoad = NEONLoadStoreMultiStructFixed |
1686 NEONLoadStoreMultiL,
1687 NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v,
1688 NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v,
1689 NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v,
1690 NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v,
1691 NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2,
1692 NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3,
1693 NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4,
1694 NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v,
1695 NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v,
1696 NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v,
1697 NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v,
1698 NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2,
1699 NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3,
1700 NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4
1701 };
1702
1703 // NEON load/store multiple structures with post-index addressing.
1704 enum NEONLoadStoreMultiStructPostIndexOp {
1705 NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000,
1706 NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000,
1707 NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000,
1708 NEONLoadStoreMultiStructPostIndex = 0x00800000,
1709 NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex,
1710 NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex,
1711 NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex,
1712 NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex,
1713 NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex,
1714 NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex,
1715 NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex,
1716 NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex,
1717 NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex,
1718 NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex,
1719 NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex,
1720 NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex,
1721 NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex,
1722 NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex
1723 };
1724
1725 enum NEONLoadStoreSingleOp {
1726 NEONLoadStoreSingle1 = 0x00000000,
1727 NEONLoadStoreSingle2 = 0x00200000,
1728 NEONLoadStoreSingle3 = 0x00002000,
1729 NEONLoadStoreSingle4 = 0x00202000,
1730 NEONLoadStoreSingleL = 0x00400000,
1731 NEONLoadStoreSingle_b = 0x00000000,
1732 NEONLoadStoreSingle_h = 0x00004000,
1733 NEONLoadStoreSingle_s = 0x00008000,
1734 NEONLoadStoreSingle_d = 0x00008400,
1735 NEONLoadStoreSingleAllLanes = 0x0000C000,
1736 NEONLoadStoreSingleLenMask = 0x00202000
1737 };
1738
1739 // NEON load/store single structure.
1740 enum NEONLoadStoreSingleStructOp {
1741 NEONLoadStoreSingleStructFixed = 0x0D000000,
1742 NEONLoadStoreSingleStructFMask = 0xBF9F0000,
1743 NEONLoadStoreSingleStructMask = 0xBFFFE000,
1744 NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed,
1745 NEONLoadStoreSingleStructLoad = NEONLoadStoreSingleStructFixed |
1746 NEONLoadStoreSingleL,
1747 NEONLoadStoreSingleStructLoad1 = NEONLoadStoreSingle1 |
1748 NEONLoadStoreSingleStructLoad,
1749 NEONLoadStoreSingleStructLoad2 = NEONLoadStoreSingle2 |
1750 NEONLoadStoreSingleStructLoad,
1751 NEONLoadStoreSingleStructLoad3 = NEONLoadStoreSingle3 |
1752 NEONLoadStoreSingleStructLoad,
1753 NEONLoadStoreSingleStructLoad4 = NEONLoadStoreSingle4 |
1754 NEONLoadStoreSingleStructLoad,
1755 NEONLoadStoreSingleStructStore1 = NEONLoadStoreSingle1 |
1756 NEONLoadStoreSingleStructFixed,
1757 NEONLoadStoreSingleStructStore2 = NEONLoadStoreSingle2 |
1758 NEONLoadStoreSingleStructFixed,
1759 NEONLoadStoreSingleStructStore3 = NEONLoadStoreSingle3 |
1760 NEONLoadStoreSingleStructFixed,
1761 NEONLoadStoreSingleStructStore4 = NEONLoadStoreSingle4 |
1762 NEONLoadStoreSingleStructFixed,
1763 NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b,
1764 NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h,
1765 NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s,
1766 NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d,
1767 NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes,
1768 NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b,
1769 NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h,
1770 NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s,
1771 NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d,
1772
1773 NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b,
1774 NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h,
1775 NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s,
1776 NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d,
1777 NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes,
1778 NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b,
1779 NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h,
1780 NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s,
1781 NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d,
1782
1783 NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b,
1784 NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h,
1785 NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s,
1786 NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d,
1787 NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes,
1788 NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b,
1789 NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h,
1790 NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s,
1791 NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d,
1792
1793 NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b,
1794 NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h,
1795 NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s,
1796 NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d,
1797 NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes,
1798 NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b,
1799 NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h,
1800 NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s,
1801 NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d
1802 };
1803
1804 // NEON load/store single structure with post-index addressing.
1805 enum NEONLoadStoreSingleStructPostIndexOp {
1806 NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000,
1807 NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000,
1808 NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000,
1809 NEONLoadStoreSingleStructPostIndex = 0x00800000,
1810 NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex,
1811 NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex,
1812 NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex,
1813 NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex,
1814 NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex,
1815 NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex,
1816 NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex,
1817 NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex,
1818 NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex,
1819
1820 NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex,
1821 NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex,
1822 NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex,
1823 NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex,
1824 NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex,
1825 NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex,
1826 NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex,
1827 NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex,
1828 NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex,
1829
1830 NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex,
1831 NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex,
1832 NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex,
1833 NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex,
1834 NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex,
1835 NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex,
1836 NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex,
1837 NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex,
1838 NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex,
1839
1840 NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex,
1841 NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex,
1842 NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex,
1843 NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex,
1844 NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex,
1845 NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex,
1846 NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex,
1847 NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex,
1848 NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex
1849 };
1850
1851 // NEON modified immediate.
1852 enum NEONModifiedImmediateOp {
1853 NEONModifiedImmediateFixed = 0x0F000400,
1854 NEONModifiedImmediateFMask = 0x9FF80400,
1855 NEONModifiedImmediateOpBit = 0x20000000,
1856 NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000,
1857 NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000,
1858 NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000,
1859 NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000
1860 };
1861
1862 // NEON shift immediate.
1863 enum NEONShiftImmediateOp {
1864 NEONShiftImmediateFixed = 0x0F000400,
1865 NEONShiftImmediateFMask = 0x9F800400,
1866 NEONShiftImmediateMask = 0xBF80FC00,
1867 NEONShiftImmediateUBit = 0x20000000,
1868 NEON_SHL = NEONShiftImmediateFixed | 0x00005000,
1869 NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000,
1870 NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000,
1871 NEON_SLI = NEONShiftImmediateFixed | 0x20005000,
1872 NEON_SRI = NEONShiftImmediateFixed | 0x20004000,
1873 NEON_SHRN = NEONShiftImmediateFixed | 0x00008000,
1874 NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800,
1875 NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000,
1876 NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800,
1877 NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000,
1878 NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800,
1879 NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000,
1880 NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800,
1881 NEON_SSHR = NEONShiftImmediateFixed | 0x00000000,
1882 NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000,
1883 NEON_USHR = NEONShiftImmediateFixed | 0x20000000,
1884 NEON_URSHR = NEONShiftImmediateFixed | 0x20002000,
1885 NEON_SSRA = NEONShiftImmediateFixed | 0x00001000,
1886 NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000,
1887 NEON_USRA = NEONShiftImmediateFixed | 0x20001000,
1888 NEON_URSRA = NEONShiftImmediateFixed | 0x20003000,
1889 NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000,
1890 NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000,
1891 NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000,
1892 NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800,
1893 NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800,
1894 NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000,
1895 NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000
1896 };
1897
1898 // NEON table.
1899 enum NEONTableOp {
1900 NEONTableFixed = 0x0E000000,
1901 NEONTableFMask = 0xBF208C00,
1902 NEONTableExt = 0x00001000,
1903 NEONTableMask = 0xBF20FC00,
1904 NEON_TBL_1v = NEONTableFixed | 0x00000000,
1905 NEON_TBL_2v = NEONTableFixed | 0x00002000,
1906 NEON_TBL_3v = NEONTableFixed | 0x00004000,
1907 NEON_TBL_4v = NEONTableFixed | 0x00006000,
1908 NEON_TBX_1v = NEON_TBL_1v | NEONTableExt,
1909 NEON_TBX_2v = NEON_TBL_2v | NEONTableExt,
1910 NEON_TBX_3v = NEON_TBL_3v | NEONTableExt,
1911 NEON_TBX_4v = NEON_TBL_4v | NEONTableExt
1912 };
1913
1914 // NEON perm.
1915 enum NEONPermOp {
1916 NEONPermFixed = 0x0E000800,
1917 NEONPermFMask = 0xBF208C00,
1918 NEONPermMask = 0x3F20FC00,
1919 NEON_UZP1 = NEONPermFixed | 0x00001000,
1920 NEON_TRN1 = NEONPermFixed | 0x00002000,
1921 NEON_ZIP1 = NEONPermFixed | 0x00003000,
1922 NEON_UZP2 = NEONPermFixed | 0x00005000,
1923 NEON_TRN2 = NEONPermFixed | 0x00006000,
1924 NEON_ZIP2 = NEONPermFixed | 0x00007000
1925 };
1926
1927 // NEON scalar instructions with two register operands.
1928 enum NEONScalar2RegMiscOp {
1929 NEONScalar2RegMiscFixed = 0x5E200800,
1930 NEONScalar2RegMiscFMask = 0xDF3E0C00,
1931 NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask,
1932 NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero,
1933 NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero,
1934 NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero,
1935 NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero,
1936 NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero,
1937 NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS,
1938 NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS,
1939 NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG,
1940 NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG,
1941 NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN,
1942 NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN,
1943 NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN,
1944 NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD,
1945 NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD,
1946
1947 NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode,
1948 NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode,
1949
1950 NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000,
1951 NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE,
1952 NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE,
1953 NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF,
1954 NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF,
1955 NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero,
1956 NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero,
1957 NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero,
1958 NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero,
1959 NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero,
1960 NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000,
1961 NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS,
1962 NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU,
1963 NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS,
1964 NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU,
1965 NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS,
1966 NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU,
1967 NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS,
1968 NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU,
1969 NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS,
1970 NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU,
1971 NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN
1972 };
1973
1974 // NEON scalar instructions with three same-type operands.
1975 enum NEONScalar3SameOp {
1976 NEONScalar3SameFixed = 0x5E200400,
1977 NEONScalar3SameFMask = 0xDF200400,
1978 NEONScalar3SameMask = 0xFF20FC00,
1979 NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD,
1980 NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ,
1981 NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE,
1982 NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT,
1983 NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI,
1984 NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS,
1985 NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST,
1986 NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB,
1987 NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD,
1988 NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD,
1989 NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB,
1990 NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB,
1991 NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL,
1992 NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL,
1993 NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL,
1994 NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL,
1995 NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL,
1996 NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL,
1997 NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL,
1998 NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL,
1999 NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH,
2000 NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH,
2001
2002 // NEON floating point scalar instructions with three same-type operands.
2003 NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000,
2004 NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000,
2005 NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000,
2006 NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE,
2007 NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT,
2008 NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ,
2009 NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE,
2010 NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT,
2011 NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX,
2012 NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS,
2013 NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS,
2014 NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD
2015 };
2016
2017 // NEON scalar instructions with three different-type operands.
2018 enum NEONScalar3DiffOp {
2019 NEONScalar3DiffFixed = 0x5E200000,
2020 NEONScalar3DiffFMask = 0xDF200C00,
2021 NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask,
2022 NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL,
2023 NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL,
2024 NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL
2025 };
2026
2027 // NEON scalar instructions with indexed element operand.
2028 enum NEONScalarByIndexedElementOp {
2029 NEONScalarByIndexedElementFixed = 0x5F000000,
2030 NEONScalarByIndexedElementFMask = 0xDF000400,
2031 NEONScalarByIndexedElementMask = 0xFF00F400,
2032 NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement,
2033 NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement,
2034 NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement,
2035 NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement,
2036 NEON_SQRDMULH_byelement_scalar
2037 = NEON_Q | NEONScalar | NEON_SQRDMULH_byelement,
2038
2039 // Floating point instructions.
2040 NEONScalarByIndexedElementFPFixed
2041 = NEONScalarByIndexedElementFixed | 0x00800000,
2042 NEONScalarByIndexedElementFPMask
2043 = NEONScalarByIndexedElementMask | 0x00800000,
2044 NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement,
2045 NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement,
2046 NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement,
2047 NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement
2048 };
2049
2050 // NEON scalar register copy.
2051 enum NEONScalarCopyOp {
2052 NEONScalarCopyFixed = 0x5E000400,
2053 NEONScalarCopyFMask = 0xDFE08400,
2054 NEONScalarCopyMask = 0xFFE0FC00,
2055 NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT
2056 };
2057
2058 // NEON scalar pairwise instructions.
2059 enum NEONScalarPairwiseOp {
2060 NEONScalarPairwiseFixed = 0x5E300800,
2061 NEONScalarPairwiseFMask = 0xDF3E0C00,
2062 NEONScalarPairwiseMask = 0xFFB1F800,
2063 NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000,
2064 NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000,
2065 NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000,
2066 NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000,
2067 NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000,
2068 NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000
2069 };
2070
2071 // NEON scalar shift immediate.
2072 enum NEONScalarShiftImmediateOp {
2073 NEONScalarShiftImmediateFixed = 0x5F000400,
2074 NEONScalarShiftImmediateFMask = 0xDF800400,
2075 NEONScalarShiftImmediateMask = 0xFF80FC00,
2076 NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL,
2077 NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI,
2078 NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI,
2079 NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR,
2080 NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR,
2081 NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR,
2082 NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR,
2083 NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA,
2084 NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA,
2085 NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA,
2086 NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA,
2087 NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN,
2088 NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN,
2089 NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN,
2090 NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN,
2091 NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN,
2092 NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN,
2093 NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU,
2094 NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm,
2095 NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm,
2096 NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm,
2097 NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm,
2098 NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm,
2099 NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm
2100 };
2101
2102 // Unimplemented and unallocated instructions. These are defined to make fixed
2103 // bit assertion easier.
2104 enum UnimplementedOp {
2105 UnimplementedFixed = 0x00000000,
2106 UnimplementedFMask = 0x00000000
2107 };
2108
2109 enum UnallocatedOp {
2110 UnallocatedFixed = 0x00000000,
2111 UnallocatedFMask = 0x00000000
2112 };
2113
2114 } // namespace vixl
2115
2116 #endif // VIXL_A64_CONSTANTS_A64_H_
AR7 emulation for QEMU