target/riscv/csr.c

   1 /*
   2  * RISC-V Control and Status Registers.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "cpu.h"
  23 #include "qemu/main-loop.h"
  24 #include "exec/exec-all.h"
  25
  26 /* CSR function table public API */
  27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
  28 {
  29     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
  30 }
  31
  32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
  33 {
  34     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
  35 }
  36
  37 /* Predicates */
  38 static int fs(CPURISCVState *env, int csrno)
  39 {
  40 #if !defined(CONFIG_USER_ONLY)
  41     /* loose check condition for fcsr in vector extension */
  42     if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
  43         return 0;
  44     }
  45     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
  46         return -RISCV_EXCP_ILLEGAL_INST;
  47     }
  48 #endif
  49     return 0;
  50 }
  51
  52 static int vs(CPURISCVState *env, int csrno)
  53 {
  54     if (env->misa & RVV) {
  55         return 0;
  56     }
  57     return -1;
  58 }
  59
  60 static int ctr(CPURISCVState *env, int csrno)
  61 {
  62 #if !defined(CONFIG_USER_ONLY)
  63     CPUState *cs = env_cpu(env);
  64     RISCVCPU *cpu = RISCV_CPU(cs);
  65
  66     if (!cpu->cfg.ext_counters) {
  67         /* The Counters extensions is not enabled */
  68         return -RISCV_EXCP_ILLEGAL_INST;
  69     }
  70
  71     if (riscv_cpu_virt_enabled(env)) {
  72         switch (csrno) {
  73         case CSR_CYCLE:
  74             if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
  75                 get_field(env->mcounteren, HCOUNTEREN_CY)) {
  76                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  77             }
  78             break;
  79         case CSR_TIME:
  80             if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
  81                 get_field(env->mcounteren, HCOUNTEREN_TM)) {
  82                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  83             }
  84             break;
  85         case CSR_INSTRET:
  86             if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
  87                 get_field(env->mcounteren, HCOUNTEREN_IR)) {
  88                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  89             }
  90             break;
  91         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
  92             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
  93                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
  94                 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  95             }
  96             break;
  97         }
  98         if (riscv_cpu_is_32bit(env)) {
  99             switch (csrno) {
 100             case CSR_CYCLEH:
 101                 if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
 102                     get_field(env->mcounteren, HCOUNTEREN_CY)) {
 103                     return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 104                 }
 105                 break;
 106             case CSR_TIMEH:
 107                 if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
 108                     get_field(env->mcounteren, HCOUNTEREN_TM)) {
 109                     return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 110                 }
 111                 break;
 112             case CSR_INSTRETH:
 113                 if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
 114                     get_field(env->mcounteren, HCOUNTEREN_IR)) {
 115                     return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 116                 }
 117                 break;
 118             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
 119                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
 120                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
 121                     return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 122                 }
 123                 break;
 124             }
 125         }
 126     }
 127 #endif
 128     return 0;
 129 }
 130
 131 static int ctr32(CPURISCVState *env, int csrno)
 132 {
 133     if (!riscv_cpu_is_32bit(env)) {
 134         return -RISCV_EXCP_ILLEGAL_INST;
 135     }
 136
 137     return ctr(env, csrno);
 138 }
 139
 140 #if !defined(CONFIG_USER_ONLY)
 141 static int any(CPURISCVState *env, int csrno)
 142 {
 143     return 0;
 144 }
 145
 146 static int any32(CPURISCVState *env, int csrno)
 147 {
 148     if (!riscv_cpu_is_32bit(env)) {
 149         return -RISCV_EXCP_ILLEGAL_INST;
 150     }
 151
 152     return any(env, csrno);
 153
 154 }
 155
 156 static int smode(CPURISCVState *env, int csrno)
 157 {
 158     return -!riscv_has_ext(env, RVS);
 159 }
 160
 161 static int hmode(CPURISCVState *env, int csrno)
 162 {
 163     if (riscv_has_ext(env, RVS) &&
 164         riscv_has_ext(env, RVH)) {
 165         /* Hypervisor extension is supported */
 166         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 167             env->priv == PRV_M) {
 168             return 0;
 169         } else {
 170             return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 171         }
 172     }
 173
 174     return -RISCV_EXCP_ILLEGAL_INST;
 175 }
 176
 177 static int hmode32(CPURISCVState *env, int csrno)
 178 {
 179     if (!riscv_cpu_is_32bit(env)) {
 180         return 0;
 181     }
 182
 183     return hmode(env, csrno);
 184
 185 }
 186
 187 static int pmp(CPURISCVState *env, int csrno)
 188 {
 189     return -!riscv_feature(env, RISCV_FEATURE_PMP);
 190 }
 191 #endif
 192
 193 /* User Floating-Point CSRs */
 194 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
 195 {
 196 #if !defined(CONFIG_USER_ONLY)
 197     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 198         return -RISCV_EXCP_ILLEGAL_INST;
 199     }
 200 #endif
 201     *val = riscv_cpu_get_fflags(env);
 202     return 0;
 203 }
 204
 205 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
 206 {
 207 #if !defined(CONFIG_USER_ONLY)
 208     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 209         return -RISCV_EXCP_ILLEGAL_INST;
 210     }
 211     env->mstatus |= MSTATUS_FS;
 212 #endif
 213     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
 214     return 0;
 215 }
 216
 217 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
 218 {
 219 #if !defined(CONFIG_USER_ONLY)
 220     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 221         return -RISCV_EXCP_ILLEGAL_INST;
 222     }
 223 #endif
 224     *val = env->frm;
 225     return 0;
 226 }
 227
 228 static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
 229 {
 230 #if !defined(CONFIG_USER_ONLY)
 231     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 232         return -RISCV_EXCP_ILLEGAL_INST;
 233     }
 234     env->mstatus |= MSTATUS_FS;
 235 #endif
 236     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
 237     return 0;
 238 }
 239
 240 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
 241 {
 242 #if !defined(CONFIG_USER_ONLY)
 243     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 244         return -RISCV_EXCP_ILLEGAL_INST;
 245     }
 246 #endif
 247     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
 248         | (env->frm << FSR_RD_SHIFT);
 249     if (vs(env, csrno) >= 0) {
 250         *val |= (env->vxrm << FSR_VXRM_SHIFT)
 251                 | (env->vxsat << FSR_VXSAT_SHIFT);
 252     }
 253     return 0;
 254 }
 255
 256 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
 257 {
 258 #if !defined(CONFIG_USER_ONLY)
 259     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 260         return -RISCV_EXCP_ILLEGAL_INST;
 261     }
 262     env->mstatus |= MSTATUS_FS;
 263 #endif
 264     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 265     if (vs(env, csrno) >= 0) {
 266         env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
 267         env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
 268     }
 269     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
 270     return 0;
 271 }
 272
 273 static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
 274 {
 275     *val = env->vtype;
 276     return 0;
 277 }
 278
 279 static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
 280 {
 281     *val = env->vl;
 282     return 0;
 283 }
 284
 285 static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
 286 {
 287     *val = env->vxrm;
 288     return 0;
 289 }
 290
 291 static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
 292 {
 293     env->vxrm = val;
 294     return 0;
 295 }
 296
 297 static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
 298 {
 299     *val = env->vxsat;
 300     return 0;
 301 }
 302
 303 static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
 304 {
 305     env->vxsat = val;
 306     return 0;
 307 }
 308
 309 static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
 310 {
 311     *val = env->vstart;
 312     return 0;
 313 }
 314
 315 static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
 316 {
 317     env->vstart = val;
 318     return 0;
 319 }
 320
 321 /* User Timers and Counters */
 322 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
 323 {
 324 #if !defined(CONFIG_USER_ONLY)
 325     if (icount_enabled()) {
 326         *val = icount_get();
 327     } else {
 328         *val = cpu_get_host_ticks();
 329     }
 330 #else
 331     *val = cpu_get_host_ticks();
 332 #endif
 333     return 0;
 334 }
 335
 336 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
 337 {
 338 #if !defined(CONFIG_USER_ONLY)
 339     if (icount_enabled()) {
 340         *val = icount_get() >> 32;
 341     } else {
 342         *val = cpu_get_host_ticks() >> 32;
 343     }
 344 #else
 345     *val = cpu_get_host_ticks() >> 32;
 346 #endif
 347     return 0;
 348 }
 349
 350 #if defined(CONFIG_USER_ONLY)
 351 static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
 352 {
 353     *val = cpu_get_host_ticks();
 354     return 0;
 355 }
 356
 357 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
 358 {
 359     *val = cpu_get_host_ticks() >> 32;
 360     return 0;
 361 }
 362
 363 #else /* CONFIG_USER_ONLY */
 364
 365 static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
 366 {
 367     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 368
 369     if (!env->rdtime_fn) {
 370         return -RISCV_EXCP_ILLEGAL_INST;
 371     }
 372
 373     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
 374     return 0;
 375 }
 376
 377 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
 378 {
 379     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 380
 381     if (!env->rdtime_fn) {
 382         return -RISCV_EXCP_ILLEGAL_INST;
 383     }
 384
 385     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
 386     return 0;
 387 }
 388
 389 /* Machine constants */
 390
 391 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
 392 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
 393 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
 394
 395 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
 396                                            VS_MODE_INTERRUPTS;
 397 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
 398                                      VS_MODE_INTERRUPTS;
 399 static const target_ulong delegable_excps =
 400     (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) |
 401     (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) |
 402     (1ULL << (RISCV_EXCP_ILLEGAL_INST)) |
 403     (1ULL << (RISCV_EXCP_BREAKPOINT)) |
 404     (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) |
 405     (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) |
 406     (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) |
 407     (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) |
 408     (1ULL << (RISCV_EXCP_U_ECALL)) |
 409     (1ULL << (RISCV_EXCP_S_ECALL)) |
 410     (1ULL << (RISCV_EXCP_VS_ECALL)) |
 411     (1ULL << (RISCV_EXCP_M_ECALL)) |
 412     (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) |
 413     (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) |
 414     (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
 415     (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
 416     (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
 417     (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
 418     (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
 419 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
 420     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
 421     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
 422 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
 423 static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 424 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 425
 426 static const char valid_vm_1_10_32[16] = {
 427     [VM_1_10_MBARE] = 1,
 428     [VM_1_10_SV32] = 1
 429 };
 430
 431 static const char valid_vm_1_10_64[16] = {
 432     [VM_1_10_MBARE] = 1,
 433     [VM_1_10_SV39] = 1,
 434     [VM_1_10_SV48] = 1,
 435     [VM_1_10_SV57] = 1
 436 };
 437
 438 /* Machine Information Registers */
 439 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
 440 {
 441     return *val = 0;
 442 }
 443
 444 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val)
 445 {
 446     *val = env->mhartid;
 447     return 0;
 448 }
 449
 450 /* Machine Trap Setup */
 451 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
 452 {
 453     *val = env->mstatus;
 454     return 0;
 455 }
 456
 457 static int validate_vm(CPURISCVState *env, target_ulong vm)
 458 {
 459     if (riscv_cpu_is_32bit(env)) {
 460         return valid_vm_1_10_32[vm & 0xf];
 461     } else {
 462         return valid_vm_1_10_64[vm & 0xf];
 463     }
 464 }
 465
 466 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
 467 {
 468     uint64_t mstatus = env->mstatus;
 469     uint64_t mask = 0;
 470     int dirty;
 471
 472     /* flush tlb on mstatus fields that affect VM */
 473     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
 474             MSTATUS_MPRV | MSTATUS_SUM)) {
 475         tlb_flush(env_cpu(env));
 476     }
 477     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
 478         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
 479         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
 480         MSTATUS_TW;
 481
 482     if (!riscv_cpu_is_32bit(env)) {
 483         /*
 484          * RV32: MPV and GVA are not in mstatus. The current plan is to
 485          * add them to mstatush. For now, we just don't support it.
 486          */
 487         mask |= MSTATUS_MPV | MSTATUS_GVA;
 488     }
 489
 490     mstatus = (mstatus & ~mask) | (val & mask);
 491
 492     dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
 493             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
 494     mstatus = set_field(mstatus, MSTATUS_SD, dirty);
 495     env->mstatus = mstatus;
 496
 497     return 0;
 498 }
 499
 500 static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
 501 {
 502     *val = env->mstatus >> 32;
 503     return 0;
 504 }
 505
 506 static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
 507 {
 508     uint64_t valh = (uint64_t)val << 32;
 509     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
 510
 511     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
 512         tlb_flush(env_cpu(env));
 513     }
 514
 515     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
 516
 517     return 0;
 518 }
 519
 520 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
 521 {
 522     *val = env->misa;
 523     return 0;
 524 }
 525
 526 static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
 527 {
 528     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
 529         /* drop write to misa */
 530         return 0;
 531     }
 532
 533     /* 'I' or 'E' must be present */
 534     if (!(val & (RVI | RVE))) {
 535         /* It is not, drop write to misa */
 536         return 0;
 537     }
 538
 539     /* 'E' excludes all other extensions */
 540     if (val & RVE) {
 541         /* when we support 'E' we can do "val = RVE;" however
 542          * for now we just drop writes if 'E' is present.
 543          */
 544         return 0;
 545     }
 546
 547     /* Mask extensions that are not supported by this hart */
 548     val &= env->misa_mask;
 549
 550     /* Mask extensions that are not supported by QEMU */
 551     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 552
 553     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
 554     if ((val & RVD) && !(val & RVF)) {
 555         val &= ~RVD;
 556     }
 557
 558     /* Suppress 'C' if next instruction is not aligned
 559      * TODO: this should check next_pc
 560      */
 561     if ((val & RVC) && (GETPC() & ~3) != 0) {
 562         val &= ~RVC;
 563     }
 564
 565     /* misa.MXL writes are not supported by QEMU */
 566     val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
 567
 568     /* flush translation cache */
 569     if (val != env->misa) {
 570         tb_flush(env_cpu(env));
 571     }
 572
 573     env->misa = val;
 574
 575     return 0;
 576 }
 577
 578 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
 579 {
 580     *val = env->medeleg;
 581     return 0;
 582 }
 583
 584 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val)
 585 {
 586     env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
 587     return 0;
 588 }
 589
 590 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
 591 {
 592     *val = env->mideleg;
 593     return 0;
 594 }
 595
 596 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
 597 {
 598     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
 599     if (riscv_has_ext(env, RVH)) {
 600         env->mideleg |= VS_MODE_INTERRUPTS;
 601     }
 602     return 0;
 603 }
 604
 605 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
 606 {
 607     *val = env->mie;
 608     return 0;
 609 }
 610
 611 static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
 612 {
 613     env->mie = (env->mie & ~all_ints) | (val & all_ints);
 614     return 0;
 615 }
 616
 617 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
 618 {
 619     *val = env->mtvec;
 620     return 0;
 621 }
 622
 623 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
 624 {
 625     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
 626     if ((val & 3) < 2) {
 627         env->mtvec = val;
 628     } else {
 629         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
 630     }
 631     return 0;
 632 }
 633
 634 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
 635 {
 636     *val = env->mcounteren;
 637     return 0;
 638 }
 639
 640 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
 641 {
 642     env->mcounteren = val;
 643     return 0;
 644 }
 645
 646 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 647 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
 648 {
 649     if (env->priv_ver < PRIV_VERSION_1_11_0) {
 650         return -RISCV_EXCP_ILLEGAL_INST;
 651     }
 652     *val = env->mcounteren;
 653     return 0;
 654 }
 655
 656 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
 657 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
 658 {
 659     if (env->priv_ver < PRIV_VERSION_1_11_0) {
 660         return -RISCV_EXCP_ILLEGAL_INST;
 661     }
 662     env->mcounteren = val;
 663     return 0;
 664 }
 665
 666 /* Machine Trap Handling */
 667 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
 668 {
 669     *val = env->mscratch;
 670     return 0;
 671 }
 672
 673 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val)
 674 {
 675     env->mscratch = val;
 676     return 0;
 677 }
 678
 679 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val)
 680 {
 681     *val = env->mepc;
 682     return 0;
 683 }
 684
 685 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val)
 686 {
 687     env->mepc = val;
 688     return 0;
 689 }
 690
 691 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val)
 692 {
 693     *val = env->mcause;
 694     return 0;
 695 }
 696
 697 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
 698 {
 699     env->mcause = val;
 700     return 0;
 701 }
 702
 703 static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
 704 {
 705     *val = env->mbadaddr;
 706     return 0;
 707 }
 708
 709 static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 710 {
 711     env->mbadaddr = val;
 712     return 0;
 713 }
 714
 715 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 716                    target_ulong new_value, target_ulong write_mask)
 717 {
 718     RISCVCPU *cpu = env_archcpu(env);
 719     /* Allow software control of delegable interrupts not claimed by hardware */
 720     target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
 721     uint32_t old_mip;
 722
 723     if (mask) {
 724         old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
 725     } else {
 726         old_mip = env->mip;
 727     }
 728
 729     if (ret_value) {
 730         *ret_value = old_mip;
 731     }
 732
 733     return 0;
 734 }
 735
 736 /* Supervisor Trap Setup */
 737 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
 738 {
 739     target_ulong mask = (sstatus_v1_10_mask);
 740     *val = env->mstatus & mask;
 741     return 0;
 742 }
 743
 744 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
 745 {
 746     target_ulong mask = (sstatus_v1_10_mask);
 747     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
 748     return write_mstatus(env, CSR_MSTATUS, newval);
 749 }
 750
 751 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
 752 {
 753     if (riscv_cpu_virt_enabled(env)) {
 754         /* Tell the guest the VS bits, shifted to the S bit locations */
 755         *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
 756     } else {
 757         *val = env->mie & env->mideleg;
 758     }
 759     return 0;
 760 }
 761
 762 static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 763 {
 764     target_ulong newval;
 765
 766     if (riscv_cpu_virt_enabled(env)) {
 767         /* Shift the guests S bits to VS */
 768         newval = (env->mie & ~VS_MODE_INTERRUPTS) |
 769                  ((val << 1) & VS_MODE_INTERRUPTS);
 770     } else {
 771         newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
 772     }
 773
 774     return write_mie(env, CSR_MIE, newval);
 775 }
 776
 777 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
 778 {
 779     *val = env->stvec;
 780     return 0;
 781 }
 782
 783 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
 784 {
 785     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
 786     if ((val & 3) < 2) {
 787         env->stvec = val;
 788     } else {
 789         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
 790     }
 791     return 0;
 792 }
 793
 794 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
 795 {
 796     *val = env->scounteren;
 797     return 0;
 798 }
 799
 800 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
 801 {
 802     env->scounteren = val;
 803     return 0;
 804 }
 805
 806 /* Supervisor Trap Handling */
 807 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val)
 808 {
 809     *val = env->sscratch;
 810     return 0;
 811 }
 812
 813 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val)
 814 {
 815     env->sscratch = val;
 816     return 0;
 817 }
 818
 819 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val)
 820 {
 821     *val = env->sepc;
 822     return 0;
 823 }
 824
 825 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val)
 826 {
 827     env->sepc = val;
 828     return 0;
 829 }
 830
 831 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val)
 832 {
 833     *val = env->scause;
 834     return 0;
 835 }
 836
 837 static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
 838 {
 839     env->scause = val;
 840     return 0;
 841 }
 842
 843 static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
 844 {
 845     *val = env->sbadaddr;
 846     return 0;
 847 }
 848
 849 static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
 850 {
 851     env->sbadaddr = val;
 852     return 0;
 853 }
 854
 855 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 856                    target_ulong new_value, target_ulong write_mask)
 857 {
 858     int ret;
 859
 860     if (riscv_cpu_virt_enabled(env)) {
 861         /* Shift the new values to line up with the VS bits */
 862         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
 863                       (write_mask & sip_writable_mask) << 1 & env->mideleg);
 864         ret &= vsip_writable_mask;
 865         ret >>= 1;
 866     } else {
 867         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
 868                       write_mask & env->mideleg & sip_writable_mask);
 869     }
 870
 871     *ret_value &= env->mideleg;
 872     return ret;
 873 }
 874
 875 /* Supervisor Protection and Translation */
 876 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
 877 {
 878     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
 879         *val = 0;
 880         return 0;
 881     }
 882
 883     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
 884         return -RISCV_EXCP_ILLEGAL_INST;
 885     } else {
 886         *val = env->satp;
 887     }
 888
 889     return 0;
 890 }
 891
 892 static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
 893 {
 894     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
 895         return 0;
 896     }
 897     if (validate_vm(env, get_field(val, SATP_MODE)) &&
 898         ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
 899     {
 900         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
 901             return -RISCV_EXCP_ILLEGAL_INST;
 902         } else {
 903             if ((val ^ env->satp) & SATP_ASID) {
 904                 tlb_flush(env_cpu(env));
 905             }
 906             env->satp = val;
 907         }
 908     }
 909     return 0;
 910 }
 911
 912 /* Hypervisor Extensions */
 913 static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
 914 {
 915     *val = env->hstatus;
 916     if (!riscv_cpu_is_32bit(env)) {
 917         /* We only support 64-bit VSXL */
 918         *val = set_field(*val, HSTATUS_VSXL, 2);
 919     }
 920     /* We only support little endian */
 921     *val = set_field(*val, HSTATUS_VSBE, 0);
 922     return 0;
 923 }
 924
 925 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
 926 {
 927     env->hstatus = val;
 928     if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
 929         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
 930     }
 931     if (get_field(val, HSTATUS_VSBE) != 0) {
 932         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
 933     }
 934     return 0;
 935 }
 936
 937 static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
 938 {
 939     *val = env->hedeleg;
 940     return 0;
 941 }
 942
 943 static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
 944 {
 945     env->hedeleg = val;
 946     return 0;
 947 }
 948
 949 static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
 950 {
 951     *val = env->hideleg;
 952     return 0;
 953 }
 954
 955 static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
 956 {
 957     env->hideleg = val;
 958     return 0;
 959 }
 960
 961 static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 962                    target_ulong new_value, target_ulong write_mask)
 963 {
 964     int ret = rmw_mip(env, 0, ret_value, new_value,
 965                       write_mask & hip_writable_mask);
 966
 967     *ret_value &= hip_writable_mask;
 968
 969     return ret;
 970 }
 971
 972 static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
 973                    target_ulong new_value, target_ulong write_mask)
 974 {
 975     int ret = rmw_mip(env, 0, ret_value, new_value,
 976                       write_mask & hip_writable_mask);
 977
 978     *ret_value &= hip_writable_mask;
 979
 980     return ret;
 981 }
 982
 983 static int read_hie(CPURISCVState *env, int csrno, target_ulong *val)
 984 {
 985     *val = env->mie & VS_MODE_INTERRUPTS;
 986     return 0;
 987 }
 988
 989 static int write_hie(CPURISCVState *env, int csrno, target_ulong val)
 990 {
 991     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
 992     return write_mie(env, CSR_MIE, newval);
 993 }
 994
 995 static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val)
 996 {
 997     *val = env->hcounteren;
 998     return 0;
 999 }
1000
1001 static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
1002 {
1003     env->hcounteren = val;
1004     return 0;
1005 }
1006
1007 static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
1008 {
1009     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1010     return 0;
1011 }
1012
1013 static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
1014 {
1015     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1016     return 0;
1017 }
1018
1019 static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
1020 {
1021     *val = env->htval;
1022     return 0;
1023 }
1024
1025 static int write_htval(CPURISCVState *env, int csrno, target_ulong val)
1026 {
1027     env->htval = val;
1028     return 0;
1029 }
1030
1031 static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
1032 {
1033     *val = env->htinst;
1034     return 0;
1035 }
1036
1037 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
1038 {
1039     return 0;
1040 }
1041
1042 static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
1043 {
1044     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1045     return 0;
1046 }
1047
1048 static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
1049 {
1050     qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1051     return 0;
1052 }
1053
1054 static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
1055 {
1056     *val = env->hgatp;
1057     return 0;
1058 }
1059
1060 static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
1061 {
1062     env->hgatp = val;
1063     return 0;
1064 }
1065
1066 static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
1067 {
1068     if (!env->rdtime_fn) {
1069         return -RISCV_EXCP_ILLEGAL_INST;
1070     }
1071
1072     *val = env->htimedelta;
1073     return 0;
1074 }
1075
1076 static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
1077 {
1078     if (!env->rdtime_fn) {
1079         return -RISCV_EXCP_ILLEGAL_INST;
1080     }
1081
1082     if (riscv_cpu_is_32bit(env)) {
1083         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1084     } else {
1085         env->htimedelta = val;
1086     }
1087     return 0;
1088 }
1089
1090 static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
1091 {
1092     if (!env->rdtime_fn) {
1093         return -RISCV_EXCP_ILLEGAL_INST;
1094     }
1095
1096     *val = env->htimedelta >> 32;
1097     return 0;
1098 }
1099
1100 static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
1101 {
1102     if (!env->rdtime_fn) {
1103         return -RISCV_EXCP_ILLEGAL_INST;
1104     }
1105
1106     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1107     return 0;
1108 }
1109
1110 /* Virtual CSR Registers */
1111 static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
1112 {
1113     *val = env->vsstatus;
1114     return 0;
1115 }
1116
1117 static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
1118 {
1119     uint64_t mask = (target_ulong)-1;
1120     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1121     return 0;
1122 }
1123
1124 static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
1125                     target_ulong new_value, target_ulong write_mask)
1126 {
1127     int ret = rmw_mip(env, 0, ret_value, new_value,
1128                       write_mask & env->mideleg & vsip_writable_mask);
1129     return ret;
1130 }
1131
1132 static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
1133 {
1134     *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
1135     return 0;
1136 }
1137
1138 static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
1139 {
1140     target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
1141     return write_mie(env, CSR_MIE, newval);
1142 }
1143
1144 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1145 {
1146     *val = env->vstvec;
1147     return 0;
1148 }
1149
1150 static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val)
1151 {
1152     env->vstvec = val;
1153     return 0;
1154 }
1155
1156 static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val)
1157 {
1158     *val = env->vsscratch;
1159     return 0;
1160 }
1161
1162 static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val)
1163 {
1164     env->vsscratch = val;
1165     return 0;
1166 }
1167
1168 static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val)
1169 {
1170     *val = env->vsepc;
1171     return 0;
1172 }
1173
1174 static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val)
1175 {
1176     env->vsepc = val;
1177     return 0;
1178 }
1179
1180 static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val)
1181 {
1182     *val = env->vscause;
1183     return 0;
1184 }
1185
1186 static int write_vscause(CPURISCVState *env, int csrno, target_ulong val)
1187 {
1188     env->vscause = val;
1189     return 0;
1190 }
1191
1192 static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val)
1193 {
1194     *val = env->vstval;
1195     return 0;
1196 }
1197
1198 static int write_vstval(CPURISCVState *env, int csrno, target_ulong val)
1199 {
1200     env->vstval = val;
1201     return 0;
1202 }
1203
1204 static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val)
1205 {
1206     *val = env->vsatp;
1207     return 0;
1208 }
1209
1210 static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val)
1211 {
1212     env->vsatp = val;
1213     return 0;
1214 }
1215
1216 static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
1217 {
1218     *val = env->mtval2;
1219     return 0;
1220 }
1221
1222 static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
1223 {
1224     env->mtval2 = val;
1225     return 0;
1226 }
1227
1228 static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
1229 {
1230     *val = env->mtinst;
1231     return 0;
1232 }
1233
1234 static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
1235 {
1236     env->mtinst = val;
1237     return 0;
1238 }
1239
1240 /* Physical Memory Protection */
1241 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
1242 {
1243     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1244     return 0;
1245 }
1246
1247 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val)
1248 {
1249     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1250     return 0;
1251 }
1252
1253 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val)
1254 {
1255     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1256     return 0;
1257 }
1258
1259 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
1260 {
1261     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1262     return 0;
1263 }
1264
1265 #endif
1266
1267 /*
1268  * riscv_csrrw - read and/or update control and status register
1269  *
1270  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
1271  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
1272  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
1273  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
1274  */
1275
1276 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
1277                 target_ulong new_value, target_ulong write_mask)
1278 {
1279     int ret;
1280     target_ulong old_value;
1281     RISCVCPU *cpu = env_archcpu(env);
1282
1283     /* check privileges and return -1 if check fails */
1284 #if !defined(CONFIG_USER_ONLY)
1285     int effective_priv = env->priv;
1286     int read_only = get_field(csrno, 0xC00) == 3;
1287
1288     if (riscv_has_ext(env, RVH) &&
1289         env->priv == PRV_S &&
1290         !riscv_cpu_virt_enabled(env)) {
1291         /*
1292          * We are in S mode without virtualisation, therefore we are in HS Mode.
1293          * Add 1 to the effective privledge level to allow us to access the
1294          * Hypervisor CSRs.
1295          */
1296         effective_priv++;
1297     }
1298
1299     if ((write_mask && read_only) ||
1300         (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
1301         return -RISCV_EXCP_ILLEGAL_INST;
1302     }
1303 #endif
1304
1305     /* ensure the CSR extension is enabled. */
1306     if (!cpu->cfg.ext_icsr) {
1307         return -RISCV_EXCP_ILLEGAL_INST;
1308     }
1309
1310     /* check predicate */
1311     if (!csr_ops[csrno].predicate) {
1312         return -RISCV_EXCP_ILLEGAL_INST;
1313     }
1314     ret = csr_ops[csrno].predicate(env, csrno);
1315     if (ret < 0) {
1316         return ret;
1317     }
1318
1319     /* execute combined read/write operation if it exists */
1320     if (csr_ops[csrno].op) {
1321         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1322     }
1323
1324     /* if no accessor exists then return failure */
1325     if (!csr_ops[csrno].read) {
1326         return -RISCV_EXCP_ILLEGAL_INST;
1327     }
1328
1329     /* read old value */
1330     ret = csr_ops[csrno].read(env, csrno, &old_value);
1331     if (ret < 0) {
1332         return ret;
1333     }
1334
1335     /* write value if writable and write mask set, otherwise drop writes */
1336     if (write_mask) {
1337         new_value = (old_value & ~write_mask) | (new_value & write_mask);
1338         if (csr_ops[csrno].write) {
1339             ret = csr_ops[csrno].write(env, csrno, new_value);
1340             if (ret < 0) {
1341                 return ret;
1342             }
1343         }
1344     }
1345
1346     /* return old value */
1347     if (ret_value) {
1348         *ret_value = old_value;
1349     }
1350
1351     return 0;
1352 }
1353
1354 /*
1355  * Debugger support.  If not in user mode, set env->debugger before the
1356  * riscv_csrrw call and clear it after the call.
1357  */
1358 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
1359                 target_ulong new_value, target_ulong write_mask)
1360 {
1361     int ret;
1362 #if !defined(CONFIG_USER_ONLY)
1363     env->debugger = true;
1364 #endif
1365     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
1366 #if !defined(CONFIG_USER_ONLY)
1367     env->debugger = false;
1368 #endif
1369     return ret;
1370 }
1371
1372 /* Control and Status Register function table */
1373 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
1374     /* User Floating-Point CSRs */
1375     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
1376     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
1377     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
1378     /* Vector CSRs */
1379     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
1380     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
1381     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
1382     [CSR_VL]       = { "vl",       vs,     read_vl                    },
1383     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
1384     /* User Timers and Counters */
1385     [CSR_CYCLE]    = { "cycle",    ctr,    read_instret  },
1386     [CSR_INSTRET]  = { "instret",  ctr,    read_instret  },
1387     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_instreth },
1388     [CSR_INSTRETH] = { "instreth", ctr32,  read_instreth },
1389
1390     /*
1391      * In privileged mode, the monitor will have to emulate TIME CSRs only if
1392      * rdtime callback is not provided by machine/platform emulation.
1393      */
1394     [CSR_TIME]  = { "time",  ctr,   read_time  },
1395     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
1396
1397 #if !defined(CONFIG_USER_ONLY)
1398     /* Machine Timers and Counters */
1399     [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
1400     [CSR_MINSTRET]  = { "minstret",  any,   read_instret  },
1401     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_instreth },
1402     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
1403
1404     /* Machine Information Registers */
1405     [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
1406     [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
1407     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
1408     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
1409
1410     /* Machine Trap Setup */
1411     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus     },
1412     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa        },
1413     [CSR_MIDELEG]     = { "mideleg",    any,   read_mideleg,     write_mideleg     },
1414     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
1415     [CSR_MIE]         = { "mie",        any,   read_mie,         write_mie         },
1416     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
1417     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
1418
1419     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
1420
1421     [CSR_MSCOUNTEREN] = { "msounteren", any,   read_mscounteren, write_mscounteren },
1422
1423     /* Machine Trap Handling */
1424     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch, write_mscratch },
1425     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
1426     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
1427     [CSR_MBADADDR] = { "mbadaddr", any,  read_mbadaddr, write_mbadaddr },
1428     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
1429
1430     /* Supervisor Trap Setup */
1431     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus    },
1432     [CSR_SIE]        = { "sie",        smode, read_sie,        write_sie        },
1433     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
1434     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
1435
1436     /* Supervisor Trap Handling */
1437     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
1438     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
1439     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
1440     [CSR_SBADADDR] = { "sbadaddr", smode, read_sbadaddr, write_sbadaddr },
1441     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
1442
1443     /* Supervisor Protection and Translation */
1444     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
1445
1446     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
1447     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
1448     [CSR_HIDELEG]     = { "hideleg",     hmode,   read_hideleg,     write_hideleg     },
1449     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
1450     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
1451     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
1452     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
1453     [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },
1454     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
1455     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
1456     [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,       write_hgeip       },
1457     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
1458     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
1459     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
1460
1461     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
1462     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
1463     [CSR_VSIE]        = { "vsie",        hmode,   read_vsie,        write_vsie        },
1464     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
1465     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
1466     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
1467     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,     write_vscause     },
1468     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,      write_vstval      },
1469     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,       write_vsatp       },
1470
1471     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
1472     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
1473
1474     /* Physical Memory Protection */
1475     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
1476     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
1477     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
1478     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
1479     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
1480     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
1481     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
1482     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
1483     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
1484     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
1485     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
1486     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
1487     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
1488     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
1489     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
1490     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
1491     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
1492     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
1493     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
1494     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
1495
1496     /* Performance Counters */
1497     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_zero },
1498     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_zero },
1499     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_zero },
1500     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_zero },
1501     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_zero },
1502     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_zero },
1503     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_zero },
1504     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_zero },
1505     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_zero },
1506     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_zero },
1507     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_zero },
1508     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_zero },
1509     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_zero },
1510     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_zero },
1511     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_zero },
1512     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_zero },
1513     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_zero },
1514     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_zero },
1515     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_zero },
1516     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_zero },
1517     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_zero },
1518     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_zero },
1519     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_zero },
1520     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_zero },
1521     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_zero },
1522     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_zero },
1523     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_zero },
1524     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_zero },
1525     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_zero },
1526
1527     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   any,    read_zero },
1528     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   any,    read_zero },
1529     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   any,    read_zero },
1530     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   any,    read_zero },
1531     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   any,    read_zero },
1532     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   any,    read_zero },
1533     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   any,    read_zero },
1534     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  any,    read_zero },
1535     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  any,    read_zero },
1536     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  any,    read_zero },
1537     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  any,    read_zero },
1538     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  any,    read_zero },
1539     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  any,    read_zero },
1540     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  any,    read_zero },
1541     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  any,    read_zero },
1542     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  any,    read_zero },
1543     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  any,    read_zero },
1544     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  any,    read_zero },
1545     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  any,    read_zero },
1546     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  any,    read_zero },
1547     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  any,    read_zero },
1548     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  any,    read_zero },
1549     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  any,    read_zero },
1550     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  any,    read_zero },
1551     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  any,    read_zero },
1552     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  any,    read_zero },
1553     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  any,    read_zero },
1554     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  any,    read_zero },
1555     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  any,    read_zero },
1556
1557     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_zero },
1558     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_zero },
1559     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_zero },
1560     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_zero },
1561     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_zero },
1562     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_zero },
1563     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_zero },
1564     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_zero },
1565     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_zero },
1566     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_zero },
1567     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_zero },
1568     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_zero },
1569     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_zero },
1570     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_zero },
1571     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_zero },
1572     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_zero },
1573     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_zero },
1574     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_zero },
1575     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_zero },
1576     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_zero },
1577     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_zero },
1578     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_zero },
1579     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_zero },
1580     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_zero },
1581     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_zero },
1582     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_zero },
1583     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_zero },
1584     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_zero },
1585     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_zero },
1586
1587     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_zero },
1588     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_zero },
1589     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_zero },
1590     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_zero },
1591     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_zero },
1592     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_zero },
1593     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_zero },
1594     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_zero },
1595     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_zero },
1596     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_zero },
1597     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_zero },
1598     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_zero },
1599     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_zero },
1600     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_zero },
1601     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_zero },
1602     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_zero },
1603     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_zero },
1604     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_zero },
1605     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_zero },
1606     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_zero },
1607     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_zero },
1608     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_zero },
1609     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_zero },
1610     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_zero },
1611     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_zero },
1612     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_zero },
1613     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_zero },
1614     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_zero },
1615     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_zero },
1616
1617     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  any32,  read_zero },
1618     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  any32,  read_zero },
1619     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  any32,  read_zero },
1620     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  any32,  read_zero },
1621     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  any32,  read_zero },
1622     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  any32,  read_zero },
1623     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  any32,  read_zero },
1624     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32,  read_zero },
1625     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32,  read_zero },
1626     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32,  read_zero },
1627     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32,  read_zero },
1628     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32,  read_zero },
1629     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32,  read_zero },
1630     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32,  read_zero },
1631     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32,  read_zero },
1632     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32,  read_zero },
1633     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32,  read_zero },
1634     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32,  read_zero },
1635     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32,  read_zero },
1636     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32,  read_zero },
1637     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32,  read_zero },
1638     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32,  read_zero },
1639     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32,  read_zero },
1640     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32,  read_zero },
1641     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32,  read_zero },
1642     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32,  read_zero },
1643     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
1644     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
1645     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
1646 #endif /* !CONFIG_USER_ONLY */
1647 };