include/hw/arm/aspeed_soc.h

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #ifndef ASPEED_SOC_H
  13 #define ASPEED_SOC_H
  14
  15 #include "hw/cpu/a15mpcore.h"
  16 #include "hw/intc/aspeed_vic.h"
  17 #include "hw/misc/aspeed_scu.h"
  18 #include "hw/misc/aspeed_sdmc.h"
  19 #include "hw/misc/aspeed_xdma.h"
  20 #include "hw/timer/aspeed_timer.h"
  21 #include "hw/rtc/aspeed_rtc.h"
  22 #include "hw/i2c/aspeed_i2c.h"
  23 #include "hw/ssi/aspeed_smc.h"
  24 #include "hw/watchdog/wdt_aspeed.h"
  25 #include "hw/net/ftgmac100.h"
  26 #include "target/arm/cpu.h"
  27 #include "hw/gpio/aspeed_gpio.h"
  28 #include "hw/sd/aspeed_sdhci.h"
  29 #include "hw/usb/hcd-ehci.h"
  30 #include "qom/object.h"
  31
  32 #define ASPEED_SPIS_NUM  2
  33 #define ASPEED_EHCIS_NUM 2
  34 #define ASPEED_WDTS_NUM  4
  35 #define ASPEED_CPUS_NUM  2
  36 #define ASPEED_MACS_NUM  4
  37
  38 struct AspeedSoCState {
  39     /*< private >*/
  40     DeviceState parent;
  41
  42     /*< public >*/
  43     ARMCPU cpu[ASPEED_CPUS_NUM];
  44     A15MPPrivState     a7mpcore;
  45     MemoryRegion *dram_mr;
  46     MemoryRegion sram;
  47     AspeedVICState vic;
  48     AspeedRtcState rtc;
  49     AspeedTimerCtrlState timerctrl;
  50     AspeedI2CState i2c;
  51     AspeedSCUState scu;
  52     AspeedXDMAState xdma;
  53     AspeedSMCState fmc;
  54     AspeedSMCState spi[ASPEED_SPIS_NUM];
  55     EHCISysBusState ehci[ASPEED_EHCIS_NUM];
  56     AspeedSDMCState sdmc;
  57     AspeedWDTState wdt[ASPEED_WDTS_NUM];
  58     FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
  59     AspeedMiiState mii[ASPEED_MACS_NUM];
  60     AspeedGPIOState gpio;
  61     AspeedGPIOState gpio_1_8v;
  62     AspeedSDHCIState sdhci;
  63     AspeedSDHCIState emmc;
  64 };
  65
  66 #define TYPE_ASPEED_SOC "aspeed-soc"
  67 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
  68
  69 struct AspeedSoCClass {
  70     DeviceClass parent_class;
  71
  72     const char *name;
  73     const char *cpu_type;
  74     uint32_t silicon_rev;
  75     uint64_t sram_size;
  76     int spis_num;
  77     int ehcis_num;
  78     int wdts_num;
  79     int macs_num;
  80     const int *irqmap;
  81     const hwaddr *memmap;
  82     uint32_t num_cpus;
  83 };
  84
  85
  86 enum {
  87     ASPEED_DEV_IOMEM,
  88     ASPEED_DEV_UART1,
  89     ASPEED_DEV_UART2,
  90     ASPEED_DEV_UART3,
  91     ASPEED_DEV_UART4,
  92     ASPEED_DEV_UART5,
  93     ASPEED_DEV_VUART,
  94     ASPEED_DEV_FMC,
  95     ASPEED_DEV_SPI1,
  96     ASPEED_DEV_SPI2,
  97     ASPEED_DEV_EHCI1,
  98     ASPEED_DEV_EHCI2,
  99     ASPEED_DEV_VIC,
 100     ASPEED_DEV_SDMC,
 101     ASPEED_DEV_SCU,
 102     ASPEED_DEV_ADC,
 103     ASPEED_DEV_VIDEO,
 104     ASPEED_DEV_SRAM,
 105     ASPEED_DEV_SDHCI,
 106     ASPEED_DEV_GPIO,
 107     ASPEED_DEV_GPIO_1_8V,
 108     ASPEED_DEV_RTC,
 109     ASPEED_DEV_TIMER1,
 110     ASPEED_DEV_TIMER2,
 111     ASPEED_DEV_TIMER3,
 112     ASPEED_DEV_TIMER4,
 113     ASPEED_DEV_TIMER5,
 114     ASPEED_DEV_TIMER6,
 115     ASPEED_DEV_TIMER7,
 116     ASPEED_DEV_TIMER8,
 117     ASPEED_DEV_WDT,
 118     ASPEED_DEV_PWM,
 119     ASPEED_DEV_LPC,
 120     ASPEED_DEV_IBT,
 121     ASPEED_DEV_I2C,
 122     ASPEED_DEV_ETH1,
 123     ASPEED_DEV_ETH2,
 124     ASPEED_DEV_ETH3,
 125     ASPEED_DEV_ETH4,
 126     ASPEED_DEV_MII1,
 127     ASPEED_DEV_MII2,
 128     ASPEED_DEV_MII3,
 129     ASPEED_DEV_MII4,
 130     ASPEED_DEV_SDRAM,
 131     ASPEED_DEV_XDMA,
 132     ASPEED_DEV_EMMC,
 133 };
 134
 135 #endif /* ASPEED_SOC_H */