2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "hw/sysbus.h"
34 #include "hw/arm/arm.h"
35 #include "hw/arm/primecell.h"
36 #include "hw/arm/virt.h"
37 #include "hw/vfio/vfio-calxeda-xgmac.h"
38 #include "hw/vfio/vfio-amd-xgbe.h"
39 #include "hw/display/ramfb.h"
40 #include "hw/devices.h"
42 #include "sysemu/device_tree.h"
43 #include "sysemu/numa.h"
44 #include "sysemu/sysemu.h"
45 #include "sysemu/kvm.h"
46 #include "hw/compat.h"
47 #include "hw/loader.h"
48 #include "exec/address-spaces.h"
49 #include "qemu/bitops.h"
50 #include "qemu/error-report.h"
51 #include "hw/pci-host/gpex.h"
52 #include "hw/arm/sysbus-fdt.h"
53 #include "hw/platform-bus.h"
54 #include "hw/arm/fdt.h"
55 #include "hw/intc/arm_gic.h"
56 #include "hw/intc/arm_gicv3_common.h"
58 #include "hw/smbios/smbios.h"
59 #include "qapi/visitor.h"
60 #include "standard-headers/linux/input.h"
61 #include "hw/arm/smmuv3.h"
63 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
64 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
67 MachineClass *mc = MACHINE_CLASS(oc); \
68 virt_machine_##major##_##minor##_options(mc); \
69 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
74 static const TypeInfo machvirt_##major##_##minor##_info = { \
75 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
76 .parent = TYPE_VIRT_MACHINE, \
77 .instance_init = virt_##major##_##minor##_instance_init, \
78 .class_init = virt_##major##_##minor##_class_init, \
80 static void machvirt_machine_##major##_##minor##_init(void) \
82 type_register_static(&machvirt_##major##_##minor##_info); \
84 type_init(machvirt_machine_##major##_##minor##_init);
86 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
87 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
88 #define DEFINE_VIRT_MACHINE(major, minor) \
89 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
92 /* Number of external interrupt lines to configure the GIC with */
95 #define PLATFORM_BUS_NUM_IRQS 64
97 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
98 * RAM can go up to the 256GB mark, leaving 256GB of the physical
99 * address space unallocated and free for future use between 256G and 512G.
100 * If we need to provide more RAM to VMs in the future then we need to:
101 * * allocate a second bank of RAM starting at 2TB and working up
102 * * fix the DT and ACPI table generation code in QEMU to correctly
103 * report two split lumps of RAM to the guest
104 * * fix KVM in the host kernel to allow guests with >40 bit address spaces
105 * (We don't want to fill all the way up to 512GB with RAM because
106 * we might want it for non-RAM purposes later. Conversely it seems
107 * reasonable to assume that anybody configuring a VM with a quarter
108 * of a terabyte of RAM will be doing it on a host with more than a
109 * terabyte of physical address space.)
111 #define RAMLIMIT_GB 255
112 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
114 /* Addresses and sizes of our components.
115 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
116 * 128MB..256MB is used for miscellaneous device I/O.
117 * 256MB..1GB is reserved for possible future PCI support (ie where the
118 * PCI memory window will go if we add a PCI host controller).
119 * 1GB and up is RAM (which may happily spill over into the
120 * high memory region beyond 4GB).
121 * This represents a compromise between how much RAM can be given to
122 * a 32 bit VM and leaving space for expansion and in particular for PCI.
123 * Note that devices should generally be placed at multiples of 0x10000,
124 * to accommodate guests using 64K pages.
126 static const MemMapEntry a15memmap
[] = {
127 /* Space up to 0x8000000 is reserved for a boot ROM */
128 [VIRT_FLASH
] = { 0, 0x08000000 },
129 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
130 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
131 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
132 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
133 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
134 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
135 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
136 /* This redistributor space allows up to 2*64kB*123 CPUs */
137 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
138 [VIRT_UART
] = { 0x09000000, 0x00001000 },
139 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
140 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
141 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
142 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
143 [VIRT_SMMU
] = { 0x09050000, 0x00020000 },
144 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
145 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
146 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
147 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
148 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
149 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
150 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
151 [VIRT_MEM
] = { 0x40000000, RAMLIMIT_BYTES
},
152 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
153 [VIRT_GIC_REDIST2
] = { 0x4000000000ULL
, 0x4000000 },
154 [VIRT_PCIE_ECAM_HIGH
] = { 0x4010000000ULL
, 0x10000000 },
155 /* Second PCIe window, 512GB wide at the 512GB boundary */
156 [VIRT_PCIE_MMIO_HIGH
] = { 0x8000000000ULL
, 0x8000000000ULL
},
159 static const int a15irqmap
[] = {
162 [VIRT_PCIE
] = 3, /* ... to 6 */
164 [VIRT_SECURE_UART
] = 8,
165 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
166 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
167 [VIRT_SMMU
] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
168 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
171 static const char *valid_cpus
[] = {
172 ARM_CPU_TYPE_NAME("cortex-a15"),
173 ARM_CPU_TYPE_NAME("cortex-a53"),
174 ARM_CPU_TYPE_NAME("cortex-a57"),
175 ARM_CPU_TYPE_NAME("host"),
176 ARM_CPU_TYPE_NAME("max"),
179 static bool cpu_type_valid(const char *cpu
)
183 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
184 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
191 static void create_fdt(VirtMachineState
*vms
)
193 void *fdt
= create_device_tree(&vms
->fdt_size
);
196 error_report("create_device_tree() failed");
203 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
204 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
205 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
208 * /chosen and /memory nodes must exist for load_dtb
209 * to fill in necessary properties later
211 qemu_fdt_add_subnode(fdt
, "/chosen");
212 qemu_fdt_add_subnode(fdt
, "/memory");
213 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
215 /* Clock node, for the benefit of the UART. The kernel device tree
216 * binding documentation claims the PL011 node clock properties are
217 * optional but in practice if you omit them the kernel refuses to
218 * probe for the device.
220 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
221 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
222 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
223 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
224 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
225 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
227 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
229 if (have_numa_distance
) {
230 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
231 uint32_t *matrix
= g_malloc0(size
);
234 for (i
= 0; i
< nb_numa_nodes
; i
++) {
235 for (j
= 0; j
< nb_numa_nodes
; j
++) {
236 idx
= (i
* nb_numa_nodes
+ j
) * 3;
237 matrix
[idx
+ 0] = cpu_to_be32(i
);
238 matrix
[idx
+ 1] = cpu_to_be32(j
);
239 matrix
[idx
+ 2] = cpu_to_be32(numa_info
[i
].distance
[j
]);
243 qemu_fdt_add_subnode(fdt
, "/distance-map");
244 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
245 "numa-distance-map-v1");
246 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
252 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
254 /* On real hardware these interrupts are level-triggered.
255 * On KVM they were edge-triggered before host kernel version 4.4,
256 * and level-triggered afterwards.
257 * On emulated QEMU they are level-triggered.
259 * Getting the DTB info about them wrong is awkward for some
261 * pre-4.8 ignore the DT and leave the interrupt configured
262 * with whatever the GIC reset value (or the bootloader) left it at
263 * 4.8 before rc6 honour the incorrect data by programming it back
264 * into the GIC, causing problems
265 * 4.8rc6 and later ignore the DT and always write "level triggered"
268 * For backwards-compatibility, virt-2.8 and earlier will continue
269 * to say these are edge-triggered, but later machines will report
270 * the correct information.
273 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
274 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
276 if (vmc
->claim_edge_triggered_timers
) {
277 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
280 if (vms
->gic_version
== 2) {
281 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
282 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
283 (1 << vms
->smp_cpus
) - 1);
286 qemu_fdt_add_subnode(vms
->fdt
, "/timer");
288 armcpu
= ARM_CPU(qemu_get_cpu(0));
289 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
290 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
291 qemu_fdt_setprop(vms
->fdt
, "/timer", "compatible",
292 compat
, sizeof(compat
));
294 qemu_fdt_setprop_string(vms
->fdt
, "/timer", "compatible",
297 qemu_fdt_setprop(vms
->fdt
, "/timer", "always-on", NULL
, 0);
298 qemu_fdt_setprop_cells(vms
->fdt
, "/timer", "interrupts",
299 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
300 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
301 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
302 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
305 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
309 const MachineState
*ms
= MACHINE(vms
);
312 * From Documentation/devicetree/bindings/arm/cpus.txt
313 * On ARM v8 64-bit systems value should be set to 2,
314 * that corresponds to the MPIDR_EL1 register size.
315 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
316 * in the system, #address-cells can be set to 1, since
317 * MPIDR_EL1[63:32] bits are not used for CPUs
320 * Here we actually don't know whether our system is 32- or 64-bit one.
321 * The simplest way to go is to examine affinity IDs of all our CPUs. If
322 * at least one of them has Aff3 populated, we set #address-cells to 2.
324 for (cpu
= 0; cpu
< vms
->smp_cpus
; cpu
++) {
325 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
327 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
333 qemu_fdt_add_subnode(vms
->fdt
, "/cpus");
334 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#address-cells", addr_cells
);
335 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#size-cells", 0x0);
337 for (cpu
= vms
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
338 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
339 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
340 CPUState
*cs
= CPU(armcpu
);
342 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
343 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "cpu");
344 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
345 armcpu
->dtb_compatible
);
347 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
348 && vms
->smp_cpus
> 1) {
349 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
350 "enable-method", "psci");
353 if (addr_cells
== 2) {
354 qemu_fdt_setprop_u64(vms
->fdt
, nodename
, "reg",
355 armcpu
->mp_affinity
);
357 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "reg",
358 armcpu
->mp_affinity
);
361 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
362 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "numa-node-id",
363 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
370 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
372 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
373 qemu_fdt_add_subnode(vms
->fdt
, "/intc/its");
374 qemu_fdt_setprop_string(vms
->fdt
, "/intc/its", "compatible",
376 qemu_fdt_setprop(vms
->fdt
, "/intc/its", "msi-controller", NULL
, 0);
377 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/its", "reg",
378 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
379 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
380 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/its", "phandle", vms
->msi_phandle
);
383 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
385 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
386 qemu_fdt_add_subnode(vms
->fdt
, "/intc/v2m");
387 qemu_fdt_setprop_string(vms
->fdt
, "/intc/v2m", "compatible",
388 "arm,gic-v2m-frame");
389 qemu_fdt_setprop(vms
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
390 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/v2m", "reg",
391 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
392 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
393 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/v2m", "phandle", vms
->msi_phandle
);
396 static void fdt_add_gic_node(VirtMachineState
*vms
)
398 vms
->gic_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
399 qemu_fdt_setprop_cell(vms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
401 qemu_fdt_add_subnode(vms
->fdt
, "/intc");
402 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#interrupt-cells", 3);
403 qemu_fdt_setprop(vms
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
404 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#address-cells", 0x2);
405 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#size-cells", 0x2);
406 qemu_fdt_setprop(vms
->fdt
, "/intc", "ranges", NULL
, 0);
407 if (vms
->gic_version
== 3) {
408 int nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
410 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
413 qemu_fdt_setprop_cell(vms
->fdt
, "/intc",
414 "#redistributor-regions", nb_redist_regions
);
416 if (nb_redist_regions
== 1) {
417 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
418 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
419 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
420 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
421 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
423 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
424 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
425 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
426 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
427 2, vms
->memmap
[VIRT_GIC_REDIST
].size
,
428 2, vms
->memmap
[VIRT_GIC_REDIST2
].base
,
429 2, vms
->memmap
[VIRT_GIC_REDIST2
].size
);
433 qemu_fdt_setprop_cells(vms
->fdt
, "/intc", "interrupts",
434 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GICV3_MAINT_IRQ
,
435 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
438 /* 'cortex-a15-gic' means 'GIC v2' */
439 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
440 "arm,cortex-a15-gic");
441 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
442 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
443 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
444 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
445 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
448 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "phandle", vms
->gic_phandle
);
451 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
455 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
458 armcpu
= ARM_CPU(cpu
);
459 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
)) {
463 if (kvm_irqchip_in_kernel()) {
464 kvm_arm_pmu_set_irq(cpu
, PPI(VIRTUAL_PMU_IRQ
));
466 kvm_arm_pmu_init(cpu
);
470 if (vms
->gic_version
== 2) {
471 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
472 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
473 (1 << vms
->smp_cpus
) - 1);
476 armcpu
= ARM_CPU(qemu_get_cpu(0));
477 qemu_fdt_add_subnode(vms
->fdt
, "/pmu");
478 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
479 const char compat
[] = "arm,armv8-pmuv3";
480 qemu_fdt_setprop(vms
->fdt
, "/pmu", "compatible",
481 compat
, sizeof(compat
));
482 qemu_fdt_setprop_cells(vms
->fdt
, "/pmu", "interrupts",
483 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
487 static void create_its(VirtMachineState
*vms
, DeviceState
*gicdev
)
489 const char *itsclass
= its_class_name();
493 /* Do nothing if not supported */
497 dev
= qdev_create(NULL
, itsclass
);
499 object_property_set_link(OBJECT(dev
), OBJECT(gicdev
), "parent-gicv3",
501 qdev_init_nofail(dev
);
502 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
504 fdt_add_its_gic_node(vms
);
507 static void create_v2m(VirtMachineState
*vms
, qemu_irq
*pic
)
510 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
513 dev
= qdev_create(NULL
, "arm-gicv2m");
514 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
515 qdev_prop_set_uint32(dev
, "base-spi", irq
);
516 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
517 qdev_init_nofail(dev
);
519 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
520 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
523 fdt_add_v2m_gic_node(vms
);
526 static void create_gic(VirtMachineState
*vms
, qemu_irq
*pic
)
528 /* We create a standalone GIC */
530 SysBusDevice
*gicbusdev
;
532 int type
= vms
->gic_version
, i
;
533 uint32_t nb_redist_regions
= 0;
535 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
537 gicdev
= qdev_create(NULL
, gictype
);
538 qdev_prop_set_uint32(gicdev
, "revision", type
);
539 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
540 /* Note that the num-irq property counts both internal and external
541 * interrupts; there are always 32 of the former (mandated by GIC spec).
543 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
544 if (!kvm_irqchip_in_kernel()) {
545 qdev_prop_set_bit(gicdev
, "has-security-extensions", vms
->secure
);
549 uint32_t redist0_capacity
=
550 vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
551 uint32_t redist0_count
= MIN(smp_cpus
, redist0_capacity
);
553 nb_redist_regions
= virt_gicv3_redist_region_count(vms
);
555 qdev_prop_set_uint32(gicdev
, "len-redist-region-count",
557 qdev_prop_set_uint32(gicdev
, "redist-region-count[0]", redist0_count
);
559 if (nb_redist_regions
== 2) {
560 uint32_t redist1_capacity
=
561 vms
->memmap
[VIRT_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
563 qdev_prop_set_uint32(gicdev
, "redist-region-count[1]",
564 MIN(smp_cpus
- redist0_count
, redist1_capacity
));
567 qdev_init_nofail(gicdev
);
568 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
569 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
571 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
572 if (nb_redist_regions
== 2) {
573 sysbus_mmio_map(gicbusdev
, 2, vms
->memmap
[VIRT_GIC_REDIST2
].base
);
576 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
579 /* Wire the outputs from each CPU's generic timer and the GICv3
580 * maintenance interrupt signal to the appropriate GIC PPI inputs,
581 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
583 for (i
= 0; i
< smp_cpus
; i
++) {
584 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
585 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
587 /* Mapping from the output timer irq lines from the CPU to the
588 * GIC PPI inputs we use for the virt board.
590 const int timer_irq
[] = {
591 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
592 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
593 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
594 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
597 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
598 qdev_connect_gpio_out(cpudev
, irq
,
599 qdev_get_gpio_in(gicdev
,
600 ppibase
+ timer_irq
[irq
]));
603 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt", 0,
604 qdev_get_gpio_in(gicdev
, ppibase
605 + ARCH_GICV3_MAINT_IRQ
));
606 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
607 qdev_get_gpio_in(gicdev
, ppibase
610 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
611 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
612 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
613 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
614 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
615 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
616 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
619 for (i
= 0; i
< NUM_IRQS
; i
++) {
620 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
623 fdt_add_gic_node(vms
);
625 if (type
== 3 && vms
->its
) {
626 create_its(vms
, gicdev
);
627 } else if (type
== 2) {
628 create_v2m(vms
, pic
);
632 static void create_uart(const VirtMachineState
*vms
, qemu_irq
*pic
, int uart
,
633 MemoryRegion
*mem
, Chardev
*chr
)
636 hwaddr base
= vms
->memmap
[uart
].base
;
637 hwaddr size
= vms
->memmap
[uart
].size
;
638 int irq
= vms
->irqmap
[uart
];
639 const char compat
[] = "arm,pl011\0arm,primecell";
640 const char clocknames
[] = "uartclk\0apb_pclk";
641 DeviceState
*dev
= qdev_create(NULL
, "pl011");
642 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
644 qdev_prop_set_chr(dev
, "chardev", chr
);
645 qdev_init_nofail(dev
);
646 memory_region_add_subregion(mem
, base
,
647 sysbus_mmio_get_region(s
, 0));
648 sysbus_connect_irq(s
, 0, pic
[irq
]);
650 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
651 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
652 /* Note that we can't use setprop_string because of the embedded NUL */
653 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible",
654 compat
, sizeof(compat
));
655 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
657 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
658 GIC_FDT_IRQ_TYPE_SPI
, irq
,
659 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
660 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "clocks",
661 vms
->clock_phandle
, vms
->clock_phandle
);
662 qemu_fdt_setprop(vms
->fdt
, nodename
, "clock-names",
663 clocknames
, sizeof(clocknames
));
665 if (uart
== VIRT_UART
) {
666 qemu_fdt_setprop_string(vms
->fdt
, "/chosen", "stdout-path", nodename
);
668 /* Mark as not usable by the normal world */
669 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
670 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
676 static void create_rtc(const VirtMachineState
*vms
, qemu_irq
*pic
)
679 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
680 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
681 int irq
= vms
->irqmap
[VIRT_RTC
];
682 const char compat
[] = "arm,pl031\0arm,primecell";
684 sysbus_create_simple("pl031", base
, pic
[irq
]);
686 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
687 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
688 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
689 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
691 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
692 GIC_FDT_IRQ_TYPE_SPI
, irq
,
693 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
694 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
695 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
699 static DeviceState
*gpio_key_dev
;
700 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
702 /* use gpio Pin 3 for power button event */
703 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
706 static Notifier virt_system_powerdown_notifier
= {
707 .notify
= virt_powerdown_req
710 static void create_gpio(const VirtMachineState
*vms
, qemu_irq
*pic
)
713 DeviceState
*pl061_dev
;
714 hwaddr base
= vms
->memmap
[VIRT_GPIO
].base
;
715 hwaddr size
= vms
->memmap
[VIRT_GPIO
].size
;
716 int irq
= vms
->irqmap
[VIRT_GPIO
];
717 const char compat
[] = "arm,pl061\0arm,primecell";
719 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
721 uint32_t phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
722 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
723 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
724 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
726 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
727 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#gpio-cells", 2);
728 qemu_fdt_setprop(vms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
729 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
730 GIC_FDT_IRQ_TYPE_SPI
, irq
,
731 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
732 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
733 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
734 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", phandle
);
736 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
737 qdev_get_gpio_in(pl061_dev
, 3));
738 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys");
739 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
740 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#size-cells", 0);
741 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#address-cells", 1);
743 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys/poweroff");
744 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys/poweroff",
745 "label", "GPIO Key Poweroff");
746 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys/poweroff", "linux,code",
748 qemu_fdt_setprop_cells(vms
->fdt
, "/gpio-keys/poweroff",
749 "gpios", phandle
, 3, 0);
751 /* connect powerdown request */
752 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
757 static void create_virtio_devices(const VirtMachineState
*vms
, qemu_irq
*pic
)
760 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
762 /* We create the transports in forwards order. Since qbus_realize()
763 * prepends (not appends) new child buses, the incrementing loop below will
764 * create a list of virtio-mmio buses with decreasing base addresses.
766 * When a -device option is processed from the command line,
767 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
768 * order. The upshot is that -device options in increasing command line
769 * order are mapped to virtio-mmio buses with decreasing base addresses.
771 * When this code was originally written, that arrangement ensured that the
772 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
773 * the first -device on the command line. (The end-to-end order is a
774 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
775 * guest kernel's name-to-address assignment strategy.)
777 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
778 * the message, if not necessarily the code, of commit 70161ff336.
779 * Therefore the loop now establishes the inverse of the original intent.
781 * Unfortunately, we can't counteract the kernel change by reversing the
782 * loop; it would break existing command lines.
784 * In any case, the kernel makes no guarantee about the stability of
785 * enumeration order of virtio devices (as demonstrated by it changing
786 * between kernel versions). For reliable and stable identification
787 * of disks users must use UUIDs or similar mechanisms.
789 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
790 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
791 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
793 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
796 /* We add dtb nodes in reverse order so that they appear in the finished
797 * device tree lowest address first.
799 * Note that this mapping is independent of the loop above. The previous
800 * loop influences virtio device to virtio transport assignment, whereas
801 * this loop controls how virtio transports are laid out in the dtb.
803 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
805 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
806 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
808 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
809 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
810 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
811 "compatible", "virtio,mmio");
812 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
814 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
815 GIC_FDT_IRQ_TYPE_SPI
, irq
,
816 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
817 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
822 static void create_one_flash(const char *name
, hwaddr flashbase
,
823 hwaddr flashsize
, const char *file
,
824 MemoryRegion
*sysmem
)
826 /* Create and map a single flash device. We use the same
827 * parameters as the flash devices on the Versatile Express board.
829 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
830 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
831 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
832 const uint64_t sectorlength
= 256 * 1024;
835 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
839 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
840 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
841 qdev_prop_set_uint8(dev
, "width", 4);
842 qdev_prop_set_uint8(dev
, "device-width", 2);
843 qdev_prop_set_bit(dev
, "big-endian", false);
844 qdev_prop_set_uint16(dev
, "id0", 0x89);
845 qdev_prop_set_uint16(dev
, "id1", 0x18);
846 qdev_prop_set_uint16(dev
, "id2", 0x00);
847 qdev_prop_set_uint16(dev
, "id3", 0x00);
848 qdev_prop_set_string(dev
, "name", name
);
849 qdev_init_nofail(dev
);
851 memory_region_add_subregion(sysmem
, flashbase
,
852 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0));
858 if (drive_get(IF_PFLASH
, 0, 0)) {
859 error_report("The contents of the first flash device may be "
860 "specified with -bios or with -drive if=pflash... "
861 "but you cannot use both options at once");
864 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, file
);
866 error_report("Could not find ROM image '%s'", file
);
869 image_size
= load_image_mr(fn
, sysbus_mmio_get_region(sbd
, 0));
871 if (image_size
< 0) {
872 error_report("Could not load ROM image '%s'", file
);
878 static void create_flash(const VirtMachineState
*vms
,
879 MemoryRegion
*sysmem
,
880 MemoryRegion
*secure_sysmem
)
882 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
883 * Any file passed via -bios goes in the first of these.
884 * sysmem is the system memory space. secure_sysmem is the secure view
885 * of the system, and the first flash device should be made visible only
886 * there. The second flash device is visible to both secure and nonsecure.
887 * If sysmem == secure_sysmem this means there is no separate Secure
888 * address space and both flash devices are generally visible.
890 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
891 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
894 create_one_flash("virt.flash0", flashbase
, flashsize
,
895 bios_name
, secure_sysmem
);
896 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
,
899 if (sysmem
== secure_sysmem
) {
900 /* Report both flash devices as a single node in the DT */
901 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
902 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
903 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
904 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
905 2, flashbase
, 2, flashsize
,
906 2, flashbase
+ flashsize
, 2, flashsize
);
907 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
910 /* Report the devices as separate nodes so we can mark one as
911 * only visible to the secure world.
913 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
914 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
915 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
916 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
917 2, flashbase
, 2, flashsize
);
918 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
919 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
920 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
923 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
924 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
925 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
926 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
927 2, flashbase
+ flashsize
, 2, flashsize
);
928 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
933 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
935 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
936 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
940 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
941 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)smp_cpus
);
943 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
944 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
945 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
946 "compatible", "qemu,fw-cfg-mmio");
947 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
949 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
954 static void create_pcie_irq_map(const VirtMachineState
*vms
,
955 uint32_t gic_phandle
,
956 int first_irq
, const char *nodename
)
959 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
960 uint32_t *irq_map
= full_irq_map
;
962 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
963 for (pin
= 0; pin
< 4; pin
++) {
964 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
965 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
966 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
970 devfn
<< 8, 0, 0, /* devfn */
971 pin
+ 1, /* PCI pin */
972 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
974 /* Convert map to big endian */
975 for (i
= 0; i
< 10; i
++) {
976 irq_map
[i
] = cpu_to_be32(map
[i
]);
982 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-map",
983 full_irq_map
, sizeof(full_irq_map
));
985 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupt-map-mask",
986 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
990 static void create_smmu(const VirtMachineState
*vms
, qemu_irq
*pic
,
994 const char compat
[] = "arm,smmu-v3";
995 int irq
= vms
->irqmap
[VIRT_SMMU
];
997 hwaddr base
= vms
->memmap
[VIRT_SMMU
].base
;
998 hwaddr size
= vms
->memmap
[VIRT_SMMU
].size
;
999 const char irq_names
[] = "eventq\0priq\0cmdq-sync\0gerror";
1002 if (vms
->iommu
!= VIRT_IOMMU_SMMUV3
|| !vms
->iommu_phandle
) {
1006 dev
= qdev_create(NULL
, "arm-smmuv3");
1008 object_property_set_link(OBJECT(dev
), OBJECT(bus
), "primary-bus",
1010 qdev_init_nofail(dev
);
1011 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
1012 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
1013 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
1016 node
= g_strdup_printf("/smmuv3@%" PRIx64
, base
);
1017 qemu_fdt_add_subnode(vms
->fdt
, node
);
1018 qemu_fdt_setprop(vms
->fdt
, node
, "compatible", compat
, sizeof(compat
));
1019 qemu_fdt_setprop_sized_cells(vms
->fdt
, node
, "reg", 2, base
, 2, size
);
1021 qemu_fdt_setprop_cells(vms
->fdt
, node
, "interrupts",
1022 GIC_FDT_IRQ_TYPE_SPI
, irq
, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1023 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1024 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
,
1025 GIC_FDT_IRQ_TYPE_SPI
, irq
+ 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
1027 qemu_fdt_setprop(vms
->fdt
, node
, "interrupt-names", irq_names
,
1030 qemu_fdt_setprop_cell(vms
->fdt
, node
, "clocks", vms
->clock_phandle
);
1031 qemu_fdt_setprop_string(vms
->fdt
, node
, "clock-names", "apb_pclk");
1032 qemu_fdt_setprop(vms
->fdt
, node
, "dma-coherent", NULL
, 0);
1034 qemu_fdt_setprop_cell(vms
->fdt
, node
, "#iommu-cells", 1);
1036 qemu_fdt_setprop_cell(vms
->fdt
, node
, "phandle", vms
->iommu_phandle
);
1040 static void create_pcie(VirtMachineState
*vms
, qemu_irq
*pic
)
1042 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1043 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1044 hwaddr base_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
1045 hwaddr size_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
1046 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1047 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1048 hwaddr base_ecam
, size_ecam
;
1049 hwaddr base
= base_mmio
;
1051 int irq
= vms
->irqmap
[VIRT_PCIE
];
1052 MemoryRegion
*mmio_alias
;
1053 MemoryRegion
*mmio_reg
;
1054 MemoryRegion
*ecam_alias
;
1055 MemoryRegion
*ecam_reg
;
1061 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
1062 qdev_init_nofail(dev
);
1064 ecam_id
= VIRT_ECAM_ID(vms
->highmem_ecam
);
1065 base_ecam
= vms
->memmap
[ecam_id
].base
;
1066 size_ecam
= vms
->memmap
[ecam_id
].size
;
1067 nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1068 /* Map only the first size_ecam bytes of ECAM space */
1069 ecam_alias
= g_new0(MemoryRegion
, 1);
1070 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1071 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1072 ecam_reg
, 0, size_ecam
);
1073 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1075 /* Map the MMIO window into system address space so as to expose
1076 * the section of PCI MMIO space which starts at the same base address
1077 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1080 mmio_alias
= g_new0(MemoryRegion
, 1);
1081 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1082 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1083 mmio_reg
, base_mmio
, size_mmio
);
1084 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1087 /* Map high MMIO space */
1088 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1090 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1091 mmio_reg
, base_mmio_high
, size_mmio_high
);
1092 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1096 /* Map IO port space */
1097 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1099 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1100 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
1101 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
1104 pci
= PCI_HOST_BRIDGE(dev
);
1106 for (i
= 0; i
< nb_nics
; i
++) {
1107 NICInfo
*nd
= &nd_table
[i
];
1110 nd
->model
= g_strdup("virtio");
1113 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1117 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1118 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1119 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1120 "compatible", "pci-host-ecam-generic");
1121 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "pci");
1122 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 3);
1123 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 2);
1124 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "linux,pci-domain", 0);
1125 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "bus-range", 0,
1127 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1129 if (vms
->msi_phandle
) {
1130 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "msi-parent",
1134 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1135 2, base_ecam
, 2, size_ecam
);
1138 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1139 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1140 2, base_pio
, 2, size_pio
,
1141 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1142 2, base_mmio
, 2, size_mmio
,
1143 1, FDT_PCI_RANGE_MMIO_64BIT
,
1145 2, base_mmio_high
, 2, size_mmio_high
);
1147 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1148 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1149 2, base_pio
, 2, size_pio
,
1150 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1151 2, base_mmio
, 2, size_mmio
);
1154 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 1);
1155 create_pcie_irq_map(vms
, vms
->gic_phandle
, irq
, nodename
);
1158 vms
->iommu_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
1160 create_smmu(vms
, pic
, pci
->bus
);
1162 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "iommu-map",
1163 0x0, vms
->iommu_phandle
, 0x0, 0x10000);
1169 static void create_platform_bus(VirtMachineState
*vms
, qemu_irq
*pic
)
1174 MemoryRegion
*sysmem
= get_system_memory();
1176 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1177 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1178 qdev_prop_set_uint32(dev
, "num_irqs", PLATFORM_BUS_NUM_IRQS
);
1179 qdev_prop_set_uint32(dev
, "mmio_size", vms
->memmap
[VIRT_PLATFORM_BUS
].size
);
1180 qdev_init_nofail(dev
);
1181 vms
->platform_bus_dev
= dev
;
1183 s
= SYS_BUS_DEVICE(dev
);
1184 for (i
= 0; i
< PLATFORM_BUS_NUM_IRQS
; i
++) {
1185 int irqn
= vms
->irqmap
[VIRT_PLATFORM_BUS
] + i
;
1186 sysbus_connect_irq(s
, i
, pic
[irqn
]);
1189 memory_region_add_subregion(sysmem
,
1190 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1191 sysbus_mmio_get_region(s
, 0));
1194 static void create_secure_ram(VirtMachineState
*vms
,
1195 MemoryRegion
*secure_sysmem
)
1197 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1199 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1200 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1202 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1204 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1206 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1207 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1208 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "memory");
1209 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1210 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
1211 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
1216 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1218 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1221 *fdt_size
= board
->fdt_size
;
1225 static void virt_build_smbios(VirtMachineState
*vms
)
1227 MachineClass
*mc
= MACHINE_GET_CLASS(vms
);
1228 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1229 uint8_t *smbios_tables
, *smbios_anchor
;
1230 size_t smbios_tables_len
, smbios_anchor_len
;
1231 const char *product
= "QEMU Virtual Machine";
1237 if (kvm_enabled()) {
1238 product
= "KVM Virtual Machine";
1241 smbios_set_defaults("QEMU", product
,
1242 vmc
->smbios_old_sys_ver
? "1.0" : mc
->name
, false,
1243 true, SMBIOS_ENTRY_POINT_30
);
1245 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1246 &smbios_anchor
, &smbios_anchor_len
);
1248 if (smbios_anchor
) {
1249 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1250 smbios_tables
, smbios_tables_len
);
1251 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1252 smbios_anchor
, smbios_anchor_len
);
1257 void virt_machine_done(Notifier
*notifier
, void *data
)
1259 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1261 ARMCPU
*cpu
= ARM_CPU(first_cpu
);
1262 struct arm_boot_info
*info
= &vms
->bootinfo
;
1263 AddressSpace
*as
= arm_boot_address_space(cpu
, info
);
1266 * If the user provided a dtb, we assume the dynamic sysbus nodes
1267 * already are integrated there. This corresponds to a use case where
1268 * the dynamic sysbus nodes are complex and their generation is not yet
1269 * supported. In that case the user can take charge of the guest dt
1270 * while qemu takes charge of the qom stuff.
1272 if (info
->dtb_filename
== NULL
) {
1273 platform_bus_add_all_fdt_nodes(vms
->fdt
, "/intc",
1274 vms
->memmap
[VIRT_PLATFORM_BUS
].base
,
1275 vms
->memmap
[VIRT_PLATFORM_BUS
].size
,
1276 vms
->irqmap
[VIRT_PLATFORM_BUS
]);
1278 if (arm_load_dtb(info
->dtb_start
, info
, info
->dtb_limit
, as
) < 0) {
1282 virt_acpi_setup(vms
);
1283 virt_build_smbios(vms
);
1286 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1288 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1289 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1291 if (!vmc
->disallow_affinity_adjustment
) {
1292 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1293 * GIC's target-list limitations. 32-bit KVM hosts currently
1294 * always create clusters of 4 CPUs, but that is expected to
1295 * change when they gain support for gicv3. When KVM is enabled
1296 * it will override the changes we make here, therefore our
1297 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1298 * and to improve SGI efficiency.
1300 if (vms
->gic_version
== 3) {
1301 clustersz
= GICV3_TARGETLIST_BITS
;
1303 clustersz
= GIC_TARGETLIST_BITS
;
1306 return arm_cpu_mp_affinity(idx
, clustersz
);
1309 static void machvirt_init(MachineState
*machine
)
1311 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1312 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1313 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1314 const CPUArchIdList
*possible_cpus
;
1315 qemu_irq pic
[NUM_IRQS
];
1316 MemoryRegion
*sysmem
= get_system_memory();
1317 MemoryRegion
*secure_sysmem
= NULL
;
1318 int n
, virt_max_cpus
;
1319 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1320 bool firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1321 bool aarch64
= true;
1323 /* We can probe only here because during property set
1324 * KVM is not available yet
1326 if (vms
->gic_version
<= 0) {
1327 /* "host" or "max" */
1328 if (!kvm_enabled()) {
1329 if (vms
->gic_version
== 0) {
1330 error_report("gic-version=host requires KVM");
1333 /* "max": currently means 3 for TCG */
1334 vms
->gic_version
= 3;
1337 vms
->gic_version
= kvm_arm_vgic_probe();
1338 if (!vms
->gic_version
) {
1340 "Unable to determine GIC version supported by host");
1346 if (!cpu_type_valid(machine
->cpu_type
)) {
1347 error_report("mach-virt: CPU type %s not supported", machine
->cpu_type
);
1351 /* If we have an EL3 boot ROM then the assumption is that it will
1352 * implement PSCI itself, so disable QEMU's internal implementation
1353 * so it doesn't get in the way. Instead of starting secondary
1354 * CPUs in PSCI powerdown state we will start them all running and
1355 * let the boot ROM sort them out.
1356 * The usual case is that we do use QEMU's PSCI implementation;
1357 * if the guest has EL2 then we will use SMC as the conduit,
1358 * and otherwise we will use HVC (for backwards compatibility and
1359 * because if we're using KVM then we must use HVC).
1361 if (vms
->secure
&& firmware_loaded
) {
1362 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
1363 } else if (vms
->virt
) {
1364 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
1366 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
1369 /* The maximum number of CPUs depends on the GIC version, or on how
1370 * many redistributors we can fit into the memory map.
1372 if (vms
->gic_version
== 3) {
1373 virt_max_cpus
= vms
->memmap
[VIRT_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
1374 virt_max_cpus
+= vms
->memmap
[VIRT_GIC_REDIST2
].size
/ GICV3_REDIST_SIZE
;
1376 virt_max_cpus
= GIC_NCPU
;
1379 if (max_cpus
> virt_max_cpus
) {
1380 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1381 "supported by machine 'mach-virt' (%d)",
1382 max_cpus
, virt_max_cpus
);
1386 vms
->smp_cpus
= smp_cpus
;
1388 if (machine
->ram_size
> vms
->memmap
[VIRT_MEM
].size
) {
1389 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB
);
1393 if (vms
->virt
&& kvm_enabled()) {
1394 error_report("mach-virt: KVM does not support providing "
1395 "Virtualization extensions to the guest CPU");
1400 if (kvm_enabled()) {
1401 error_report("mach-virt: KVM does not support Security extensions");
1405 /* The Secure view of the world is the same as the NonSecure,
1406 * but with a few extra devices. Create it as a container region
1407 * containing the system memory at low priority; any secure-only
1408 * devices go in at higher priority and take precedence.
1410 secure_sysmem
= g_new(MemoryRegion
, 1);
1411 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1413 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1418 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
1419 for (n
= 0; n
< possible_cpus
->len
; n
++) {
1423 if (n
>= smp_cpus
) {
1427 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
1428 object_property_set_int(cpuobj
, possible_cpus
->cpus
[n
].arch_id
,
1429 "mp-affinity", NULL
);
1434 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
1437 aarch64
&= object_property_get_bool(cpuobj
, "aarch64", NULL
);
1440 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1443 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2", NULL
)) {
1444 object_property_set_bool(cpuobj
, false, "has_el2", NULL
);
1447 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
) {
1448 object_property_set_int(cpuobj
, vms
->psci_conduit
,
1449 "psci-conduit", NULL
);
1451 /* Secondary CPUs start in PSCI powered-down state */
1453 object_property_set_bool(cpuobj
, true,
1454 "start-powered-off", NULL
);
1458 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu", NULL
)) {
1459 object_property_set_bool(cpuobj
, false, "pmu", NULL
);
1462 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1463 object_property_set_int(cpuobj
, vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1464 "reset-cbar", &error_abort
);
1467 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1470 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1471 "secure-memory", &error_abort
);
1474 object_property_set_bool(cpuobj
, true, "realized", &error_fatal
);
1475 object_unref(cpuobj
);
1477 fdt_add_timer_nodes(vms
);
1478 fdt_add_cpu_nodes(vms
);
1480 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1482 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
, ram
);
1484 create_flash(vms
, sysmem
, secure_sysmem
? secure_sysmem
: sysmem
);
1486 create_gic(vms
, pic
);
1488 fdt_add_pmu_nodes(vms
);
1490 create_uart(vms
, pic
, VIRT_UART
, sysmem
, serial_hd(0));
1493 create_secure_ram(vms
, secure_sysmem
);
1494 create_uart(vms
, pic
, VIRT_SECURE_UART
, secure_sysmem
, serial_hd(1));
1497 vms
->highmem_ecam
&= vms
->highmem
&& (!firmware_loaded
|| aarch64
);
1499 create_rtc(vms
, pic
);
1501 create_pcie(vms
, pic
);
1503 create_gpio(vms
, pic
);
1505 /* Create mmio transports, so the user can create virtio backends
1506 * (which will be automatically plugged in to the transports). If
1507 * no backend is created the transport will just sit harmlessly idle.
1509 create_virtio_devices(vms
, pic
);
1511 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
1512 rom_set_fw(vms
->fw_cfg
);
1514 create_platform_bus(vms
, pic
);
1516 vms
->bootinfo
.ram_size
= machine
->ram_size
;
1517 vms
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1518 vms
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1519 vms
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1520 vms
->bootinfo
.nb_cpus
= smp_cpus
;
1521 vms
->bootinfo
.board_id
= -1;
1522 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
1523 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
1524 vms
->bootinfo
.skip_dtb_autoload
= true;
1525 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
1526 arm_load_kernel(ARM_CPU(first_cpu
), &vms
->bootinfo
);
1528 vms
->machine_done
.notify
= virt_machine_done
;
1529 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
1532 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1534 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1539 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1541 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1543 vms
->secure
= value
;
1546 static bool virt_get_virt(Object
*obj
, Error
**errp
)
1548 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1553 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
1555 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1560 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1562 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1564 return vms
->highmem
;
1567 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1569 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1571 vms
->highmem
= value
;
1574 static bool virt_get_its(Object
*obj
, Error
**errp
)
1576 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1581 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
1583 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1588 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1590 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1591 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1593 return g_strdup(val
);
1596 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1598 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1600 if (!strcmp(value
, "3")) {
1601 vms
->gic_version
= 3;
1602 } else if (!strcmp(value
, "2")) {
1603 vms
->gic_version
= 2;
1604 } else if (!strcmp(value
, "host")) {
1605 vms
->gic_version
= 0; /* Will probe later */
1606 } else if (!strcmp(value
, "max")) {
1607 vms
->gic_version
= -1; /* Will probe later */
1609 error_setg(errp
, "Invalid gic-version value");
1610 error_append_hint(errp
, "Valid values are 3, 2, host, max.\n");
1614 static char *virt_get_iommu(Object
*obj
, Error
**errp
)
1616 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1618 switch (vms
->iommu
) {
1619 case VIRT_IOMMU_NONE
:
1620 return g_strdup("none");
1621 case VIRT_IOMMU_SMMUV3
:
1622 return g_strdup("smmuv3");
1624 g_assert_not_reached();
1628 static void virt_set_iommu(Object
*obj
, const char *value
, Error
**errp
)
1630 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1632 if (!strcmp(value
, "smmuv3")) {
1633 vms
->iommu
= VIRT_IOMMU_SMMUV3
;
1634 } else if (!strcmp(value
, "none")) {
1635 vms
->iommu
= VIRT_IOMMU_NONE
;
1637 error_setg(errp
, "Invalid iommu value");
1638 error_append_hint(errp
, "Valid values are none, smmuv3.\n");
1642 static CpuInstanceProperties
1643 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
1645 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
1646 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
1648 assert(cpu_index
< possible_cpus
->len
);
1649 return possible_cpus
->cpus
[cpu_index
].props
;
1652 static int64_t virt_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
1654 return idx
% nb_numa_nodes
;
1657 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
1660 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
1662 if (ms
->possible_cpus
) {
1663 assert(ms
->possible_cpus
->len
== max_cpus
);
1664 return ms
->possible_cpus
;
1667 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
1668 sizeof(CPUArchId
) * max_cpus
);
1669 ms
->possible_cpus
->len
= max_cpus
;
1670 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
1671 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
1672 ms
->possible_cpus
->cpus
[n
].arch_id
=
1673 virt_cpu_mp_affinity(vms
, n
);
1674 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
1675 ms
->possible_cpus
->cpus
[n
].props
.thread_id
= n
;
1677 return ms
->possible_cpus
;
1680 static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
1681 DeviceState
*dev
, Error
**errp
)
1683 VirtMachineState
*vms
= VIRT_MACHINE(hotplug_dev
);
1685 if (vms
->platform_bus_dev
) {
1686 if (object_dynamic_cast(OBJECT(dev
), TYPE_SYS_BUS_DEVICE
)) {
1687 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms
->platform_bus_dev
),
1688 SYS_BUS_DEVICE(dev
));
1693 static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState
*machine
,
1696 if (object_dynamic_cast(OBJECT(dev
), TYPE_SYS_BUS_DEVICE
)) {
1697 return HOTPLUG_HANDLER(machine
);
1703 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1705 MachineClass
*mc
= MACHINE_CLASS(oc
);
1706 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
1708 mc
->init
= machvirt_init
;
1709 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
1710 * The value may be reduced later when we have more information about the
1711 * configuration of the particular instance.
1714 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_CALXEDA_XGMAC
);
1715 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_VFIO_AMD_XGBE
);
1716 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_RAMFB_DEVICE
);
1717 mc
->block_default_type
= IF_VIRTIO
;
1719 mc
->pci_allow_0_address
= true;
1720 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1721 mc
->minimum_page_bits
= 12;
1722 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
1723 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
1724 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-a15");
1725 mc
->get_default_cpu_node_id
= virt_get_default_cpu_node_id
;
1726 assert(!mc
->get_hotplug_handler
);
1727 mc
->get_hotplug_handler
= virt_machine_get_hotplug_handler
;
1728 hc
->plug
= virt_machine_device_plug_cb
;
1731 static const TypeInfo virt_machine_info
= {
1732 .name
= TYPE_VIRT_MACHINE
,
1733 .parent
= TYPE_MACHINE
,
1735 .instance_size
= sizeof(VirtMachineState
),
1736 .class_size
= sizeof(VirtMachineClass
),
1737 .class_init
= virt_machine_class_init
,
1738 .interfaces
= (InterfaceInfo
[]) {
1739 { TYPE_HOTPLUG_HANDLER
},
1744 static void machvirt_machine_init(void)
1746 type_register_static(&virt_machine_info
);
1748 type_init(machvirt_machine_init
);
1750 #define VIRT_COMPAT_2_12 \
1753 static void virt_3_0_instance_init(Object
*obj
)
1755 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1756 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1758 /* EL3 is disabled by default on virt: this makes us consistent
1759 * between KVM and TCG for this board, and it also allows us to
1760 * boot UEFI blobs which assume no TrustZone support.
1762 vms
->secure
= false;
1763 object_property_add_bool(obj
, "secure", virt_get_secure
,
1764 virt_set_secure
, NULL
);
1765 object_property_set_description(obj
, "secure",
1766 "Set on/off to enable/disable the ARM "
1767 "Security Extensions (TrustZone)",
1770 /* EL2 is also disabled by default, for similar reasons */
1772 object_property_add_bool(obj
, "virtualization", virt_get_virt
,
1773 virt_set_virt
, NULL
);
1774 object_property_set_description(obj
, "virtualization",
1775 "Set on/off to enable/disable emulating a "
1776 "guest CPU which implements the ARM "
1777 "Virtualization Extensions",
1780 /* High memory is enabled by default */
1781 vms
->highmem
= true;
1782 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1783 virt_set_highmem
, NULL
);
1784 object_property_set_description(obj
, "highmem",
1785 "Set on/off to enable/disable using "
1786 "physical address space above 32 bits",
1788 /* Default GIC type is v2 */
1789 vms
->gic_version
= 2;
1790 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1791 virt_set_gic_version
, NULL
);
1792 object_property_set_description(obj
, "gic-version",
1794 "Valid values are 2, 3 and host", NULL
);
1796 vms
->highmem_ecam
= !vmc
->no_highmem_ecam
;
1801 /* Default allows ITS instantiation */
1803 object_property_add_bool(obj
, "its", virt_get_its
,
1804 virt_set_its
, NULL
);
1805 object_property_set_description(obj
, "its",
1806 "Set on/off to enable/disable "
1807 "ITS instantiation",
1811 /* Default disallows iommu instantiation */
1812 vms
->iommu
= VIRT_IOMMU_NONE
;
1813 object_property_add_str(obj
, "iommu", virt_get_iommu
, virt_set_iommu
, NULL
);
1814 object_property_set_description(obj
, "iommu",
1815 "Set the IOMMU type. "
1816 "Valid values are none and smmuv3",
1819 vms
->memmap
= a15memmap
;
1820 vms
->irqmap
= a15irqmap
;
1823 static void virt_machine_3_0_options(MachineClass
*mc
)
1826 DEFINE_VIRT_MACHINE_AS_LATEST(3, 0)
1828 static void virt_2_12_instance_init(Object
*obj
)
1830 virt_3_0_instance_init(obj
);
1833 static void virt_machine_2_12_options(MachineClass
*mc
)
1835 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1837 virt_machine_3_0_options(mc
);
1838 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_12
);
1839 vmc
->no_highmem_ecam
= true;
1842 DEFINE_VIRT_MACHINE(2, 12)
1844 #define VIRT_COMPAT_2_11 \
1847 static void virt_2_11_instance_init(Object
*obj
)
1849 virt_2_12_instance_init(obj
);
1852 static void virt_machine_2_11_options(MachineClass
*mc
)
1854 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1856 virt_machine_2_12_options(mc
);
1857 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_11
);
1858 vmc
->smbios_old_sys_ver
= true;
1860 DEFINE_VIRT_MACHINE(2, 11)
1862 #define VIRT_COMPAT_2_10 \
1865 static void virt_2_10_instance_init(Object
*obj
)
1867 virt_2_11_instance_init(obj
);
1870 static void virt_machine_2_10_options(MachineClass
*mc
)
1872 virt_machine_2_11_options(mc
);
1873 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_10
);
1875 DEFINE_VIRT_MACHINE(2, 10)
1877 #define VIRT_COMPAT_2_9 \
1880 static void virt_2_9_instance_init(Object
*obj
)
1882 virt_2_10_instance_init(obj
);
1885 static void virt_machine_2_9_options(MachineClass
*mc
)
1887 virt_machine_2_10_options(mc
);
1888 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_9
);
1890 DEFINE_VIRT_MACHINE(2, 9)
1892 #define VIRT_COMPAT_2_8 \
1895 static void virt_2_8_instance_init(Object
*obj
)
1897 virt_2_9_instance_init(obj
);
1900 static void virt_machine_2_8_options(MachineClass
*mc
)
1902 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1904 virt_machine_2_9_options(mc
);
1905 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_8
);
1906 /* For 2.8 and earlier we falsely claimed in the DT that
1907 * our timers were edge-triggered, not level-triggered.
1909 vmc
->claim_edge_triggered_timers
= true;
1911 DEFINE_VIRT_MACHINE(2, 8)
1913 #define VIRT_COMPAT_2_7 \
1916 static void virt_2_7_instance_init(Object
*obj
)
1918 virt_2_8_instance_init(obj
);
1921 static void virt_machine_2_7_options(MachineClass
*mc
)
1923 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1925 virt_machine_2_8_options(mc
);
1926 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_7
);
1927 /* ITS was introduced with 2.8 */
1929 /* Stick with 1K pages for migration compatibility */
1930 mc
->minimum_page_bits
= 0;
1932 DEFINE_VIRT_MACHINE(2, 7)
1934 #define VIRT_COMPAT_2_6 \
1937 static void virt_2_6_instance_init(Object
*obj
)
1939 virt_2_7_instance_init(obj
);
1942 static void virt_machine_2_6_options(MachineClass
*mc
)
1944 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1946 virt_machine_2_7_options(mc
);
1947 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_6
);
1948 vmc
->disallow_affinity_adjustment
= true;
1949 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
1952 DEFINE_VIRT_MACHINE(2, 6)