1 #include "qemu/osdep.h"
3 #include "exec/exec-all.h"
4 #include "sysemu/kvm.h"
5 #include "sysemu/tcg.h"
6 #include "helper_regs.h"
7 #include "mmu-hash64.h"
8 #include "migration/cpu.h"
9 #include "qapi/error.h"
10 #include "qemu/main-loop.h"
12 #include "power8-pmu.h"
14 static void post_load_update_msr(CPUPPCState
*env
)
16 target_ulong msr
= env
->msr
;
19 * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB
20 * before restoring. Note that this recomputes hflags.
22 env
->msr
^= env
->msr_mask
& ~((1ULL << MSR_TGPR
) | MSR_HVB
);
23 ppc_store_msr(env
, msr
);
26 pmu_update_summaries(env
);
30 static int get_avr(QEMUFile
*f
, void *pv
, size_t size
,
31 const VMStateField
*field
)
35 v
->u64
[0] = qemu_get_be64(f
);
36 v
->u64
[1] = qemu_get_be64(f
);
41 static int put_avr(QEMUFile
*f
, void *pv
, size_t size
,
42 const VMStateField
*field
, JSONWriter
*vmdesc
)
46 qemu_put_be64(f
, v
->u64
[0]);
47 qemu_put_be64(f
, v
->u64
[1]);
51 static const VMStateInfo vmstate_info_avr
= {
57 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \
58 VMSTATE_SUB_ARRAY(_f, _s, 32, _n, _v, vmstate_info_avr, ppc_avr_t)
60 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \
61 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
63 static int get_fpr(QEMUFile
*f
, void *pv
, size_t size
,
64 const VMStateField
*field
)
68 v
->VsrD(0) = qemu_get_be64(f
);
73 static int put_fpr(QEMUFile
*f
, void *pv
, size_t size
,
74 const VMStateField
*field
, JSONWriter
*vmdesc
)
78 qemu_put_be64(f
, v
->VsrD(0));
82 static const VMStateInfo vmstate_info_fpr
= {
88 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \
89 VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_fpr, ppc_vsr_t)
91 #define VMSTATE_FPR_ARRAY(_f, _s, _n) \
92 VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
94 static int get_vsr(QEMUFile
*f
, void *pv
, size_t size
,
95 const VMStateField
*field
)
99 v
->VsrD(1) = qemu_get_be64(f
);
104 static int put_vsr(QEMUFile
*f
, void *pv
, size_t size
,
105 const VMStateField
*field
, JSONWriter
*vmdesc
)
109 qemu_put_be64(f
, v
->VsrD(1));
113 static const VMStateInfo vmstate_info_vsr
= {
119 #define VMSTATE_VSR_ARRAY_V(_f, _s, _n, _v) \
120 VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_vsr, ppc_vsr_t)
122 #define VMSTATE_VSR_ARRAY(_f, _s, _n) \
123 VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0)
125 static bool cpu_pre_2_8_migration(void *opaque
, int version_id
)
127 PowerPCCPU
*cpu
= opaque
;
129 return cpu
->pre_2_8_migration
;
132 #if defined(TARGET_PPC64)
133 static bool cpu_pre_3_0_migration(void *opaque
, int version_id
)
135 PowerPCCPU
*cpu
= opaque
;
137 return cpu
->pre_3_0_migration
;
141 static int cpu_pre_save(void *opaque
)
143 PowerPCCPU
*cpu
= opaque
;
144 CPUPPCState
*env
= &cpu
->env
;
146 uint64_t insns_compat_mask
=
147 PPC_INSNS_BASE
| PPC_ISEL
| PPC_STRING
| PPC_MFTB
148 | PPC_FLOAT
| PPC_FLOAT_FSEL
| PPC_FLOAT_FRES
149 | PPC_FLOAT_FSQRT
| PPC_FLOAT_FRSQRTE
| PPC_FLOAT_FRSQRTES
150 | PPC_FLOAT_STFIWX
| PPC_FLOAT_EXT
151 | PPC_CACHE
| PPC_CACHE_ICBI
| PPC_CACHE_DCBZ
152 | PPC_MEM_SYNC
| PPC_MEM_EIEIO
| PPC_MEM_TLBIE
| PPC_MEM_TLBSYNC
153 | PPC_64B
| PPC_64BX
| PPC_ALTIVEC
154 | PPC_SEGMENT_64B
| PPC_SLBI
| PPC_POPCNTB
| PPC_POPCNTWD
;
155 uint64_t insns_compat_mask2
= PPC2_VSX
| PPC2_VSX207
| PPC2_DFP
| PPC2_DBRX
156 | PPC2_PERM_ISA206
| PPC2_DIVE_ISA206
157 | PPC2_ATOMIC_ISA206
| PPC2_FP_CVT_ISA206
158 | PPC2_FP_TST_ISA206
| PPC2_BCTAR_ISA207
159 | PPC2_LSQ_ISA207
| PPC2_ALTIVEC_207
160 | PPC2_ISA205
| PPC2_ISA207S
| PPC2_FP_CVT_S64
| PPC2_TM
163 env
->spr
[SPR_LR
] = env
->lr
;
164 env
->spr
[SPR_CTR
] = env
->ctr
;
165 env
->spr
[SPR_XER
] = cpu_read_xer(env
);
166 #if defined(TARGET_PPC64)
167 env
->spr
[SPR_CFAR
] = env
->cfar
;
169 env
->spr
[SPR_BOOKE_SPEFSCR
] = env
->spe_fscr
;
171 for (i
= 0; (i
< 4) && (i
< env
->nb_BATs
); i
++) {
172 env
->spr
[SPR_DBAT0U
+ 2 * i
] = env
->DBAT
[0][i
];
173 env
->spr
[SPR_DBAT0U
+ 2 * i
+ 1] = env
->DBAT
[1][i
];
174 env
->spr
[SPR_IBAT0U
+ 2 * i
] = env
->IBAT
[0][i
];
175 env
->spr
[SPR_IBAT0U
+ 2 * i
+ 1] = env
->IBAT
[1][i
];
177 for (i
= 0; (i
< 4) && ((i
+ 4) < env
->nb_BATs
); i
++) {
178 env
->spr
[SPR_DBAT4U
+ 2 * i
] = env
->DBAT
[0][i
+ 4];
179 env
->spr
[SPR_DBAT4U
+ 2 * i
+ 1] = env
->DBAT
[1][i
+ 4];
180 env
->spr
[SPR_IBAT4U
+ 2 * i
] = env
->IBAT
[0][i
+ 4];
181 env
->spr
[SPR_IBAT4U
+ 2 * i
+ 1] = env
->IBAT
[1][i
+ 4];
184 /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
185 if (cpu
->pre_2_8_migration
) {
187 * Mask out bits that got added to msr_mask since the versions
188 * which stupidly included it in the migration stream.
190 target_ulong metamask
= 0
191 #if defined(TARGET_PPC64)
196 cpu
->mig_msr_mask
= env
->msr_mask
& ~metamask
;
197 cpu
->mig_insns_flags
= env
->insns_flags
& insns_compat_mask
;
199 * CPU models supported by old machines all have
200 * PPC_MEM_TLBIE, so we set it unconditionally to allow
201 * backward migration from a POWER9 host to a POWER8 host.
203 cpu
->mig_insns_flags
|= PPC_MEM_TLBIE
;
204 cpu
->mig_insns_flags2
= env
->insns_flags2
& insns_compat_mask2
;
205 cpu
->mig_nb_BATs
= env
->nb_BATs
;
207 if (cpu
->pre_3_0_migration
) {
208 if (cpu
->hash64_opts
) {
209 cpu
->mig_slb_nr
= cpu
->hash64_opts
->slb_size
;
213 /* Used to retain migration compatibility for pre 6.0 for 601 machines. */
214 env
->hflags_compat_nmsr
= 0;
220 * Determine if a given PVR is a "close enough" match to the CPU
221 * object. For TCG and KVM PR it would probably be sufficient to
222 * require an exact PVR match. However for KVM HV the user is
223 * restricted to a PVR exactly matching the host CPU. The correct way
224 * to handle this is to put the guest into an architected
225 * compatibility mode. However, to allow a more forgiving transition
226 * and migration from before this was widely done, we allow migration
227 * between sufficiently similar PVRs, as determined by the CPU class's
230 static bool pvr_match(PowerPCCPU
*cpu
, uint32_t pvr
)
232 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
234 if (pvr
== pcc
->pvr
) {
237 return pcc
->pvr_match(pcc
, pvr
, true);
240 static int cpu_post_load(void *opaque
, int version_id
)
242 PowerPCCPU
*cpu
= opaque
;
243 CPUPPCState
*env
= &cpu
->env
;
247 * If we're operating in compat mode, we should be ok as long as
248 * the destination supports the same compatibility mode.
250 * Otherwise, however, we require that the destination has exactly
251 * the same CPU model as the source.
254 #if defined(TARGET_PPC64)
255 if (cpu
->compat_pvr
) {
256 uint32_t compat_pvr
= cpu
->compat_pvr
;
257 Error
*local_err
= NULL
;
261 ret
= ppc_set_compat(cpu
, compat_pvr
, &local_err
);
263 error_report_err(local_err
);
269 if (!pvr_match(cpu
, env
->spr
[SPR_PVR
])) {
275 * If we're running with KVM HV, there is a chance that the guest
276 * is running with KVM HV and its kernel does not have the
277 * capability of dealing with a different PVR other than this
278 * exact host PVR in KVM_SET_SREGS. If that happens, the
279 * guest freezes after migration.
281 * The function kvmppc_pvr_workaround_required does this verification
282 * by first checking if the kernel has the cap, returning true immediately
283 * if that is the case. Otherwise, it checks if we're running in KVM PR.
284 * If the guest kernel does not have the cap and we're not running KVM-PR
285 * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will
286 * receive the PVR it expects as a workaround.
289 if (kvmppc_pvr_workaround_required(cpu
)) {
290 env
->spr
[SPR_PVR
] = env
->spr_cb
[SPR_PVR
].default_value
;
293 env
->lr
= env
->spr
[SPR_LR
];
294 env
->ctr
= env
->spr
[SPR_CTR
];
295 cpu_write_xer(env
, env
->spr
[SPR_XER
]);
296 #if defined(TARGET_PPC64)
297 env
->cfar
= env
->spr
[SPR_CFAR
];
299 env
->spe_fscr
= env
->spr
[SPR_BOOKE_SPEFSCR
];
301 for (i
= 0; (i
< 4) && (i
< env
->nb_BATs
); i
++) {
302 env
->DBAT
[0][i
] = env
->spr
[SPR_DBAT0U
+ 2 * i
];
303 env
->DBAT
[1][i
] = env
->spr
[SPR_DBAT0U
+ 2 * i
+ 1];
304 env
->IBAT
[0][i
] = env
->spr
[SPR_IBAT0U
+ 2 * i
];
305 env
->IBAT
[1][i
] = env
->spr
[SPR_IBAT0U
+ 2 * i
+ 1];
307 for (i
= 0; (i
< 4) && ((i
+ 4) < env
->nb_BATs
); i
++) {
308 env
->DBAT
[0][i
+ 4] = env
->spr
[SPR_DBAT4U
+ 2 * i
];
309 env
->DBAT
[1][i
+ 4] = env
->spr
[SPR_DBAT4U
+ 2 * i
+ 1];
310 env
->IBAT
[0][i
+ 4] = env
->spr
[SPR_IBAT4U
+ 2 * i
];
311 env
->IBAT
[1][i
+ 4] = env
->spr
[SPR_IBAT4U
+ 2 * i
+ 1];
315 ppc_store_sdr1(env
, env
->spr
[SPR_SDR1
]);
318 post_load_update_msr(env
);
323 static bool fpu_needed(void *opaque
)
325 PowerPCCPU
*cpu
= opaque
;
327 return cpu
->env
.insns_flags
& PPC_FLOAT
;
330 static const VMStateDescription vmstate_fpu
= {
333 .minimum_version_id
= 1,
334 .needed
= fpu_needed
,
335 .fields
= (VMStateField
[]) {
336 VMSTATE_FPR_ARRAY(env
.vsr
, PowerPCCPU
, 32),
337 VMSTATE_UINTTL(env
.fpscr
, PowerPCCPU
),
338 VMSTATE_END_OF_LIST()
342 static bool altivec_needed(void *opaque
)
344 PowerPCCPU
*cpu
= opaque
;
346 return cpu
->env
.insns_flags
& PPC_ALTIVEC
;
349 static int get_vscr(QEMUFile
*f
, void *opaque
, size_t size
,
350 const VMStateField
*field
)
352 PowerPCCPU
*cpu
= opaque
;
353 ppc_store_vscr(&cpu
->env
, qemu_get_be32(f
));
357 static int put_vscr(QEMUFile
*f
, void *opaque
, size_t size
,
358 const VMStateField
*field
, JSONWriter
*vmdesc
)
360 PowerPCCPU
*cpu
= opaque
;
361 qemu_put_be32(f
, ppc_get_vscr(&cpu
->env
));
365 static const VMStateInfo vmstate_vscr
= {
366 .name
= "cpu/altivec/vscr",
371 static const VMStateDescription vmstate_altivec
= {
372 .name
= "cpu/altivec",
374 .minimum_version_id
= 1,
375 .needed
= altivec_needed
,
376 .fields
= (VMStateField
[]) {
377 VMSTATE_AVR_ARRAY(env
.vsr
, PowerPCCPU
, 32),
379 * Save the architecture value of the vscr, not the internally
380 * expanded version. Since this architecture value does not
381 * exist in memory to be stored, this requires a but of hoop
382 * jumping. We want OFFSET=0 so that we effectively pass CPU
383 * to the helper functions.
388 .size
= sizeof(uint32_t),
389 .info
= &vmstate_vscr
,
393 VMSTATE_END_OF_LIST()
397 static bool vsx_needed(void *opaque
)
399 PowerPCCPU
*cpu
= opaque
;
401 return cpu
->env
.insns_flags2
& PPC2_VSX
;
404 static const VMStateDescription vmstate_vsx
= {
407 .minimum_version_id
= 1,
408 .needed
= vsx_needed
,
409 .fields
= (VMStateField
[]) {
410 VMSTATE_VSR_ARRAY(env
.vsr
, PowerPCCPU
, 32),
411 VMSTATE_END_OF_LIST()
416 /* Transactional memory state */
417 static bool tm_needed(void *opaque
)
419 PowerPCCPU
*cpu
= opaque
;
420 CPUPPCState
*env
= &cpu
->env
;
421 return FIELD_EX64(env
->msr
, MSR
, TS
);
424 static const VMStateDescription vmstate_tm
= {
427 .minimum_version_id
= 1,
429 .fields
= (VMStateField
[]) {
430 VMSTATE_UINTTL_ARRAY(env
.tm_gpr
, PowerPCCPU
, 32),
431 VMSTATE_AVR_ARRAY(env
.tm_vsr
, PowerPCCPU
, 64),
432 VMSTATE_UINT64(env
.tm_cr
, PowerPCCPU
),
433 VMSTATE_UINT64(env
.tm_lr
, PowerPCCPU
),
434 VMSTATE_UINT64(env
.tm_ctr
, PowerPCCPU
),
435 VMSTATE_UINT64(env
.tm_fpscr
, PowerPCCPU
),
436 VMSTATE_UINT64(env
.tm_amr
, PowerPCCPU
),
437 VMSTATE_UINT64(env
.tm_ppr
, PowerPCCPU
),
438 VMSTATE_UINT64(env
.tm_vrsave
, PowerPCCPU
),
439 VMSTATE_UINT32(env
.tm_vscr
, PowerPCCPU
),
440 VMSTATE_UINT64(env
.tm_dscr
, PowerPCCPU
),
441 VMSTATE_UINT64(env
.tm_tar
, PowerPCCPU
),
442 VMSTATE_END_OF_LIST()
447 static bool sr_needed(void *opaque
)
450 PowerPCCPU
*cpu
= opaque
;
452 return !mmu_is_64bit(cpu
->env
.mmu_model
);
458 static const VMStateDescription vmstate_sr
= {
461 .minimum_version_id
= 1,
463 .fields
= (VMStateField
[]) {
464 VMSTATE_UINTTL_ARRAY(env
.sr
, PowerPCCPU
, 32),
465 VMSTATE_END_OF_LIST()
470 static int get_slbe(QEMUFile
*f
, void *pv
, size_t size
,
471 const VMStateField
*field
)
475 v
->esid
= qemu_get_be64(f
);
476 v
->vsid
= qemu_get_be64(f
);
481 static int put_slbe(QEMUFile
*f
, void *pv
, size_t size
,
482 const VMStateField
*field
, JSONWriter
*vmdesc
)
486 qemu_put_be64(f
, v
->esid
);
487 qemu_put_be64(f
, v
->vsid
);
491 static const VMStateInfo vmstate_info_slbe
= {
497 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \
498 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
500 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \
501 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
503 static bool slb_needed(void *opaque
)
505 PowerPCCPU
*cpu
= opaque
;
507 /* We don't support any of the old segment table based 64-bit CPUs */
508 return mmu_is_64bit(cpu
->env
.mmu_model
);
511 static int slb_post_load(void *opaque
, int version_id
)
513 PowerPCCPU
*cpu
= opaque
;
514 CPUPPCState
*env
= &cpu
->env
;
518 * We've pulled in the raw esid and vsid values from the migration
519 * stream, but we need to recompute the page size pointers
521 for (i
= 0; i
< cpu
->hash64_opts
->slb_size
; i
++) {
522 if (ppc_store_slb(cpu
, i
, env
->slb
[i
].esid
, env
->slb
[i
].vsid
) < 0) {
523 /* Migration source had bad values in its SLB */
531 static const VMStateDescription vmstate_slb
= {
534 .minimum_version_id
= 1,
535 .needed
= slb_needed
,
536 .post_load
= slb_post_load
,
537 .fields
= (VMStateField
[]) {
538 VMSTATE_INT32_TEST(mig_slb_nr
, PowerPCCPU
, cpu_pre_3_0_migration
),
539 VMSTATE_SLB_ARRAY(env
.slb
, PowerPCCPU
, MAX_SLB_ENTRIES
),
540 VMSTATE_END_OF_LIST()
543 #endif /* TARGET_PPC64 */
545 static const VMStateDescription vmstate_tlb6xx_entry
= {
546 .name
= "cpu/tlb6xx_entry",
548 .minimum_version_id
= 1,
549 .fields
= (VMStateField
[]) {
550 VMSTATE_UINTTL(pte0
, ppc6xx_tlb_t
),
551 VMSTATE_UINTTL(pte1
, ppc6xx_tlb_t
),
552 VMSTATE_UINTTL(EPN
, ppc6xx_tlb_t
),
553 VMSTATE_END_OF_LIST()
557 static bool tlb6xx_needed(void *opaque
)
559 PowerPCCPU
*cpu
= opaque
;
560 CPUPPCState
*env
= &cpu
->env
;
562 return env
->nb_tlb
&& (env
->tlb_type
== TLB_6XX
);
565 static const VMStateDescription vmstate_tlb6xx
= {
566 .name
= "cpu/tlb6xx",
568 .minimum_version_id
= 1,
569 .needed
= tlb6xx_needed
,
570 .fields
= (VMStateField
[]) {
571 VMSTATE_INT32_EQUAL(env
.nb_tlb
, PowerPCCPU
, NULL
),
572 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env
.tlb
.tlb6
, PowerPCCPU
,
574 vmstate_tlb6xx_entry
,
576 VMSTATE_UINTTL_ARRAY(env
.tgpr
, PowerPCCPU
, 4),
577 VMSTATE_END_OF_LIST()
581 static const VMStateDescription vmstate_tlbemb_entry
= {
582 .name
= "cpu/tlbemb_entry",
584 .minimum_version_id
= 1,
585 .fields
= (VMStateField
[]) {
586 VMSTATE_UINT64(RPN
, ppcemb_tlb_t
),
587 VMSTATE_UINTTL(EPN
, ppcemb_tlb_t
),
588 VMSTATE_UINTTL(PID
, ppcemb_tlb_t
),
589 VMSTATE_UINTTL(size
, ppcemb_tlb_t
),
590 VMSTATE_UINT32(prot
, ppcemb_tlb_t
),
591 VMSTATE_UINT32(attr
, ppcemb_tlb_t
),
592 VMSTATE_END_OF_LIST()
596 static bool tlbemb_needed(void *opaque
)
598 PowerPCCPU
*cpu
= opaque
;
599 CPUPPCState
*env
= &cpu
->env
;
601 return env
->nb_tlb
&& (env
->tlb_type
== TLB_EMB
);
604 static const VMStateDescription vmstate_tlbemb
= {
605 .name
= "cpu/tlb6xx",
607 .minimum_version_id
= 1,
608 .needed
= tlbemb_needed
,
609 .fields
= (VMStateField
[]) {
610 VMSTATE_INT32_EQUAL(env
.nb_tlb
, PowerPCCPU
, NULL
),
611 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env
.tlb
.tlbe
, PowerPCCPU
,
613 vmstate_tlbemb_entry
,
615 VMSTATE_END_OF_LIST()
619 static const VMStateDescription vmstate_tlbmas_entry
= {
620 .name
= "cpu/tlbmas_entry",
622 .minimum_version_id
= 1,
623 .fields
= (VMStateField
[]) {
624 VMSTATE_UINT32(mas8
, ppcmas_tlb_t
),
625 VMSTATE_UINT32(mas1
, ppcmas_tlb_t
),
626 VMSTATE_UINT64(mas2
, ppcmas_tlb_t
),
627 VMSTATE_UINT64(mas7_3
, ppcmas_tlb_t
),
628 VMSTATE_END_OF_LIST()
632 static bool tlbmas_needed(void *opaque
)
634 PowerPCCPU
*cpu
= opaque
;
635 CPUPPCState
*env
= &cpu
->env
;
637 return env
->nb_tlb
&& (env
->tlb_type
== TLB_MAS
);
640 static const VMStateDescription vmstate_tlbmas
= {
641 .name
= "cpu/tlbmas",
643 .minimum_version_id
= 1,
644 .needed
= tlbmas_needed
,
645 .fields
= (VMStateField
[]) {
646 VMSTATE_INT32_EQUAL(env
.nb_tlb
, PowerPCCPU
, NULL
),
647 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env
.tlb
.tlbm
, PowerPCCPU
,
649 vmstate_tlbmas_entry
,
651 VMSTATE_END_OF_LIST()
655 static bool compat_needed(void *opaque
)
657 PowerPCCPU
*cpu
= opaque
;
659 assert(!(cpu
->compat_pvr
&& !cpu
->vhyp
));
660 return !cpu
->pre_2_10_migration
&& cpu
->compat_pvr
!= 0;
663 static const VMStateDescription vmstate_compat
= {
664 .name
= "cpu/compat",
666 .minimum_version_id
= 1,
667 .needed
= compat_needed
,
668 .fields
= (VMStateField
[]) {
669 VMSTATE_UINT32(compat_pvr
, PowerPCCPU
),
670 VMSTATE_END_OF_LIST()
674 const VMStateDescription vmstate_ppc_cpu
= {
677 .minimum_version_id
= 5,
678 .pre_save
= cpu_pre_save
,
679 .post_load
= cpu_post_load
,
680 .fields
= (VMStateField
[]) {
681 VMSTATE_UNUSED(sizeof(target_ulong
)), /* was _EQUAL(env.spr[SPR_PVR]) */
683 /* User mode architected state */
684 VMSTATE_UINTTL_ARRAY(env
.gpr
, PowerPCCPU
, 32),
685 #if !defined(TARGET_PPC64)
686 VMSTATE_UINTTL_ARRAY(env
.gprh
, PowerPCCPU
, 32),
688 VMSTATE_UINT32_ARRAY(env
.crf
, PowerPCCPU
, 8),
689 VMSTATE_UINTTL(env
.nip
, PowerPCCPU
),
692 VMSTATE_UINTTL_ARRAY(env
.spr
, PowerPCCPU
, 1024),
693 VMSTATE_UINT64(env
.spe_acc
, PowerPCCPU
),
696 VMSTATE_UINTTL(env
.reserve_addr
, PowerPCCPU
),
698 /* Supervisor mode architected state */
699 VMSTATE_UINTTL(env
.msr
, PowerPCCPU
),
701 /* Backward compatible internal state */
702 VMSTATE_UINTTL(env
.hflags_compat_nmsr
, PowerPCCPU
),
704 /* Sanity checking */
705 VMSTATE_UINTTL_TEST(mig_msr_mask
, PowerPCCPU
, cpu_pre_2_8_migration
),
706 VMSTATE_UINT64_TEST(mig_insns_flags
, PowerPCCPU
, cpu_pre_2_8_migration
),
707 VMSTATE_UINT64_TEST(mig_insns_flags2
, PowerPCCPU
,
708 cpu_pre_2_8_migration
),
709 VMSTATE_UINT32_TEST(mig_nb_BATs
, PowerPCCPU
, cpu_pre_2_8_migration
),
710 VMSTATE_END_OF_LIST()
712 .subsections
= (const VMStateDescription
*[]) {
720 #endif /* TARGET_PPC64 */