target/ppc/machine.c

   1 #include "qemu/osdep.h"
   2 #include "cpu.h"
   3 #include "exec/exec-all.h"
   4 #include "sysemu/kvm.h"
   5 #include "sysemu/tcg.h"
   6 #include "helper_regs.h"
   7 #include "mmu-hash64.h"
   8 #include "migration/cpu.h"
   9 #include "qapi/error.h"
  10 #include "kvm_ppc.h"
  11 #include "power8-pmu.h"
  12 #include "sysemu/replay.h"
  13
  14 static void post_load_update_msr(CPUPPCState *env)
  15 {
  16     target_ulong msr = env->msr;
  17
  18     /*
  19      * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB
  20      * before restoring.  Note that this recomputes hflags.
  21      */
  22     env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);
  23     ppc_store_msr(env, msr);
  24 }
  25
  26 static int get_avr(QEMUFile *f, void *pv, size_t size,
  27                    const VMStateField *field)
  28 {
  29     ppc_avr_t *v = pv;
  30
  31     v->u64[0] = qemu_get_be64(f);
  32     v->u64[1] = qemu_get_be64(f);
  33
  34     return 0;
  35 }
  36
  37 static int put_avr(QEMUFile *f, void *pv, size_t size,
  38                    const VMStateField *field, JSONWriter *vmdesc)
  39 {
  40     ppc_avr_t *v = pv;
  41
  42     qemu_put_be64(f, v->u64[0]);
  43     qemu_put_be64(f, v->u64[1]);
  44     return 0;
  45 }
  46
  47 static const VMStateInfo vmstate_info_avr = {
  48     .name = "avr",
  49     .get  = get_avr,
  50     .put  = put_avr,
  51 };
  52
  53 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
  54     VMSTATE_SUB_ARRAY(_f, _s, 32, _n, _v, vmstate_info_avr, ppc_avr_t)
  55
  56 #define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
  57     VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
  58
  59 static int get_fpr(QEMUFile *f, void *pv, size_t size,
  60                    const VMStateField *field)
  61 {
  62     ppc_vsr_t *v = pv;
  63
  64     v->VsrD(0) = qemu_get_be64(f);
  65
  66     return 0;
  67 }
  68
  69 static int put_fpr(QEMUFile *f, void *pv, size_t size,
  70                    const VMStateField *field, JSONWriter *vmdesc)
  71 {
  72     ppc_vsr_t *v = pv;
  73
  74     qemu_put_be64(f, v->VsrD(0));
  75     return 0;
  76 }
  77
  78 static const VMStateInfo vmstate_info_fpr = {
  79     .name = "fpr",
  80     .get  = get_fpr,
  81     .put  = put_fpr,
  82 };
  83
  84 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v)                       \
  85     VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_fpr, ppc_vsr_t)
  86
  87 #define VMSTATE_FPR_ARRAY(_f, _s, _n)                             \
  88     VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
  89
  90 static int get_vsr(QEMUFile *f, void *pv, size_t size,
  91                    const VMStateField *field)
  92 {
  93     ppc_vsr_t *v = pv;
  94
  95     v->VsrD(1) = qemu_get_be64(f);
  96
  97     return 0;
  98 }
  99
 100 static int put_vsr(QEMUFile *f, void *pv, size_t size,
 101                    const VMStateField *field, JSONWriter *vmdesc)
 102 {
 103     ppc_vsr_t *v = pv;
 104
 105     qemu_put_be64(f, v->VsrD(1));
 106     return 0;
 107 }
 108
 109 static const VMStateInfo vmstate_info_vsr = {
 110     .name = "vsr",
 111     .get  = get_vsr,
 112     .put  = put_vsr,
 113 };
 114
 115 #define VMSTATE_VSR_ARRAY_V(_f, _s, _n, _v)                       \
 116     VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_vsr, ppc_vsr_t)
 117
 118 #define VMSTATE_VSR_ARRAY(_f, _s, _n)                             \
 119     VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0)
 120
 121 static bool cpu_pre_2_8_migration(void *opaque, int version_id)
 122 {
 123     PowerPCCPU *cpu = opaque;
 124
 125     return cpu->pre_2_8_migration;
 126 }
 127
 128 #if defined(TARGET_PPC64)
 129 static bool cpu_pre_3_0_migration(void *opaque, int version_id)
 130 {
 131     PowerPCCPU *cpu = opaque;
 132
 133     return cpu->pre_3_0_migration;
 134 }
 135 #endif
 136
 137 static int cpu_pre_save(void *opaque)
 138 {
 139     PowerPCCPU *cpu = opaque;
 140     CPUPPCState *env = &cpu->env;
 141     int i;
 142     uint64_t insns_compat_mask =
 143         PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB
 144         | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES
 145         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES
 146         | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT
 147         | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ
 148         | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC
 149         | PPC_64B | PPC_64BX | PPC_ALTIVEC
 150         | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD;
 151     uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX
 152         | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206
 153         | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206
 154         | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207
 155         | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207
 156         | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM
 157         | PPC2_MEM_LWSYNC;
 158
 159     env->spr[SPR_LR] = env->lr;
 160     env->spr[SPR_CTR] = env->ctr;
 161     env->spr[SPR_XER] = cpu_read_xer(env);
 162 #if defined(TARGET_PPC64)
 163     env->spr[SPR_CFAR] = env->cfar;
 164 #endif
 165     env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
 166
 167     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 168         env->spr[SPR_DBAT0U + 2 * i] = env->DBAT[0][i];
 169         env->spr[SPR_DBAT0U + 2 * i + 1] = env->DBAT[1][i];
 170         env->spr[SPR_IBAT0U + 2 * i] = env->IBAT[0][i];
 171         env->spr[SPR_IBAT0U + 2 * i + 1] = env->IBAT[1][i];
 172     }
 173     for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) {
 174         env->spr[SPR_DBAT4U + 2 * i] = env->DBAT[0][i + 4];
 175         env->spr[SPR_DBAT4U + 2 * i + 1] = env->DBAT[1][i + 4];
 176         env->spr[SPR_IBAT4U + 2 * i] = env->IBAT[0][i + 4];
 177         env->spr[SPR_IBAT4U + 2 * i + 1] = env->IBAT[1][i + 4];
 178     }
 179
 180     /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
 181     if (cpu->pre_2_8_migration) {
 182         /*
 183          * Mask out bits that got added to msr_mask since the versions
 184          * which stupidly included it in the migration stream.
 185          */
 186         target_ulong metamask = 0
 187 #if defined(TARGET_PPC64)
 188             | (1ULL << MSR_TS0)
 189             | (1ULL << MSR_TS1)
 190 #endif
 191             ;
 192         cpu->mig_msr_mask = env->msr_mask & ~metamask;
 193         cpu->mig_insns_flags = env->insns_flags & insns_compat_mask;
 194         /*
 195          * CPU models supported by old machines all have
 196          * PPC_MEM_TLBIE, so we set it unconditionally to allow
 197          * backward migration from a POWER9 host to a POWER8 host.
 198          */
 199         cpu->mig_insns_flags |= PPC_MEM_TLBIE;
 200         cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2;
 201         cpu->mig_nb_BATs = env->nb_BATs;
 202     }
 203     if (cpu->pre_3_0_migration) {
 204         if (cpu->hash64_opts) {
 205             cpu->mig_slb_nr = cpu->hash64_opts->slb_size;
 206         }
 207     }
 208
 209     /* Used to retain migration compatibility for pre 6.0 for 601 machines. */
 210     env->hflags_compat_nmsr = 0;
 211
 212     if (tcg_enabled()) {
 213         /*
 214          * TCG does not maintain the DECR spr (unlike KVM) so have to save
 215          * it here.
 216          */
 217         env->spr[SPR_DECR] = cpu_ppc_load_decr(env);
 218     }
 219
 220     return 0;
 221 }
 222
 223 /*
 224  * Determine if a given PVR is a "close enough" match to the CPU
 225  * object.  For TCG and KVM PR it would probably be sufficient to
 226  * require an exact PVR match.  However for KVM HV the user is
 227  * restricted to a PVR exactly matching the host CPU.  The correct way
 228  * to handle this is to put the guest into an architected
 229  * compatibility mode.  However, to allow a more forgiving transition
 230  * and migration from before this was widely done, we allow migration
 231  * between sufficiently similar PVRs, as determined by the CPU class's
 232  * pvr_match() hook.
 233  */
 234 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr)
 235 {
 236     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 237
 238     if (pvr == pcc->pvr) {
 239         return true;
 240     }
 241     return pcc->pvr_match(pcc, pvr, true);
 242 }
 243
 244 static int cpu_post_load(void *opaque, int version_id)
 245 {
 246     PowerPCCPU *cpu = opaque;
 247     CPUPPCState *env = &cpu->env;
 248     int i;
 249
 250     /*
 251      * If we're operating in compat mode, we should be ok as long as
 252      * the destination supports the same compatibility mode.
 253      *
 254      * Otherwise, however, we require that the destination has exactly
 255      * the same CPU model as the source.
 256      */
 257
 258 #if defined(TARGET_PPC64)
 259     if (cpu->compat_pvr) {
 260         uint32_t compat_pvr = cpu->compat_pvr;
 261         Error *local_err = NULL;
 262         int ret;
 263
 264         cpu->compat_pvr = 0;
 265         ret = ppc_set_compat(cpu, compat_pvr, &local_err);
 266         if (ret < 0) {
 267             error_report_err(local_err);
 268             return ret;
 269         }
 270     } else
 271 #endif
 272     {
 273         if (!pvr_match(cpu, env->spr[SPR_PVR])) {
 274             return -EINVAL;
 275         }
 276     }
 277
 278     /*
 279      * If we're running with KVM HV, there is a chance that the guest
 280      * is running with KVM HV and its kernel does not have the
 281      * capability of dealing with a different PVR other than this
 282      * exact host PVR in KVM_SET_SREGS. If that happens, the
 283      * guest freezes after migration.
 284      *
 285      * The function kvmppc_pvr_workaround_required does this verification
 286      * by first checking if the kernel has the cap, returning true immediately
 287      * if that is the case. Otherwise, it checks if we're running in KVM PR.
 288      * If the guest kernel does not have the cap and we're not running KVM-PR
 289      * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will
 290      * receive the PVR it expects as a workaround.
 291      *
 292      */
 293     if (kvmppc_pvr_workaround_required(cpu)) {
 294         env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
 295     }
 296
 297     env->lr = env->spr[SPR_LR];
 298     env->ctr = env->spr[SPR_CTR];
 299     cpu_write_xer(env, env->spr[SPR_XER]);
 300 #if defined(TARGET_PPC64)
 301     env->cfar = env->spr[SPR_CFAR];
 302 #endif
 303     env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
 304
 305     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 306         env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2 * i];
 307         env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2 * i + 1];
 308         env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2 * i];
 309         env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2 * i + 1];
 310     }
 311     for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) {
 312         env->DBAT[0][i + 4] = env->spr[SPR_DBAT4U + 2 * i];
 313         env->DBAT[1][i + 4] = env->spr[SPR_DBAT4U + 2 * i + 1];
 314         env->IBAT[0][i + 4] = env->spr[SPR_IBAT4U + 2 * i];
 315         env->IBAT[1][i + 4] = env->spr[SPR_IBAT4U + 2 * i + 1];
 316     }
 317
 318     if (!cpu->vhyp) {
 319         ppc_store_sdr1(env, env->spr[SPR_SDR1]);
 320     }
 321
 322     post_load_update_msr(env);
 323
 324     if (tcg_enabled()) {
 325         /* Re-set breaks based on regs */
 326 #if defined(TARGET_PPC64)
 327         ppc_update_ciabr(env);
 328         ppc_update_daw0(env);
 329 #endif
 330         /*
 331          * TCG needs to re-start the decrementer timer and/or raise the
 332          * interrupt. This works for level-triggered decrementer. Edge
 333          * triggered types (including HDEC) would need to carry more state.
 334          */
 335         cpu_ppc_store_decr(env, env->spr[SPR_DECR]);
 336         pmu_mmcr01_updated(env);
 337     }
 338
 339     return 0;
 340 }
 341
 342 static bool fpu_needed(void *opaque)
 343 {
 344     PowerPCCPU *cpu = opaque;
 345
 346     return cpu->env.insns_flags & PPC_FLOAT;
 347 }
 348
 349 static const VMStateDescription vmstate_fpu = {
 350     .name = "cpu/fpu",
 351     .version_id = 1,
 352     .minimum_version_id = 1,
 353     .needed = fpu_needed,
 354     .fields = (const VMStateField[]) {
 355         VMSTATE_FPR_ARRAY(env.vsr, PowerPCCPU, 32),
 356         VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
 357         VMSTATE_END_OF_LIST()
 358     },
 359 };
 360
 361 static bool altivec_needed(void *opaque)
 362 {
 363     PowerPCCPU *cpu = opaque;
 364
 365     return cpu->env.insns_flags & PPC_ALTIVEC;
 366 }
 367
 368 static int get_vscr(QEMUFile *f, void *opaque, size_t size,
 369                     const VMStateField *field)
 370 {
 371     PowerPCCPU *cpu = opaque;
 372     ppc_store_vscr(&cpu->env, qemu_get_be32(f));
 373     return 0;
 374 }
 375
 376 static int put_vscr(QEMUFile *f, void *opaque, size_t size,
 377                     const VMStateField *field, JSONWriter *vmdesc)
 378 {
 379     PowerPCCPU *cpu = opaque;
 380     qemu_put_be32(f, ppc_get_vscr(&cpu->env));
 381     return 0;
 382 }
 383
 384 static const VMStateInfo vmstate_vscr = {
 385     .name = "cpu/altivec/vscr",
 386     .get = get_vscr,
 387     .put = put_vscr,
 388 };
 389
 390 static const VMStateDescription vmstate_altivec = {
 391     .name = "cpu/altivec",
 392     .version_id = 1,
 393     .minimum_version_id = 1,
 394     .needed = altivec_needed,
 395     .fields = (const VMStateField[]) {
 396         VMSTATE_AVR_ARRAY(env.vsr, PowerPCCPU, 32),
 397         /*
 398          * Save the architecture value of the vscr, not the internally
 399          * expanded version.  Since this architecture value does not
 400          * exist in memory to be stored, this requires a but of hoop
 401          * jumping.  We want OFFSET=0 so that we effectively pass CPU
 402          * to the helper functions.
 403          */
 404         {
 405             .name = "vscr",
 406             .version_id = 0,
 407             .size = sizeof(uint32_t),
 408             .info = &vmstate_vscr,
 409             .flags = VMS_SINGLE,
 410             .offset = 0
 411         },
 412         VMSTATE_END_OF_LIST()
 413     },
 414 };
 415
 416 static bool vsx_needed(void *opaque)
 417 {
 418     PowerPCCPU *cpu = opaque;
 419
 420     return cpu->env.insns_flags2 & PPC2_VSX;
 421 }
 422
 423 static const VMStateDescription vmstate_vsx = {
 424     .name = "cpu/vsx",
 425     .version_id = 1,
 426     .minimum_version_id = 1,
 427     .needed = vsx_needed,
 428     .fields = (const VMStateField[]) {
 429         VMSTATE_VSR_ARRAY(env.vsr, PowerPCCPU, 32),
 430         VMSTATE_END_OF_LIST()
 431     },
 432 };
 433
 434 #ifdef TARGET_PPC64
 435 /* Transactional memory state */
 436 static bool tm_needed(void *opaque)
 437 {
 438     PowerPCCPU *cpu = opaque;
 439     CPUPPCState *env = &cpu->env;
 440     return FIELD_EX64(env->msr, MSR, TS);
 441 }
 442
 443 static const VMStateDescription vmstate_tm = {
 444     .name = "cpu/tm",
 445     .version_id = 1,
 446     .minimum_version_id = 1,
 447     .needed = tm_needed,
 448     .fields = (const VMStateField []) {
 449         VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
 450         VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
 451         VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
 452         VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
 453         VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
 454         VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
 455         VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
 456         VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
 457         VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
 458         VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
 459         VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
 460         VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
 461         VMSTATE_END_OF_LIST()
 462     },
 463 };
 464 #endif
 465
 466 static bool sr_needed(void *opaque)
 467 {
 468 #ifdef TARGET_PPC64
 469     PowerPCCPU *cpu = opaque;
 470
 471     return !mmu_is_64bit(cpu->env.mmu_model);
 472 #else
 473     return true;
 474 #endif
 475 }
 476
 477 static const VMStateDescription vmstate_sr = {
 478     .name = "cpu/sr",
 479     .version_id = 1,
 480     .minimum_version_id = 1,
 481     .needed = sr_needed,
 482     .fields = (const VMStateField[]) {
 483         VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
 484         VMSTATE_END_OF_LIST()
 485     },
 486 };
 487
 488 #ifdef TARGET_PPC64
 489 static int get_slbe(QEMUFile *f, void *pv, size_t size,
 490                     const VMStateField *field)
 491 {
 492     ppc_slb_t *v = pv;
 493
 494     v->esid = qemu_get_be64(f);
 495     v->vsid = qemu_get_be64(f);
 496
 497     return 0;
 498 }
 499
 500 static int put_slbe(QEMUFile *f, void *pv, size_t size,
 501                     const VMStateField *field, JSONWriter *vmdesc)
 502 {
 503     ppc_slb_t *v = pv;
 504
 505     qemu_put_be64(f, v->esid);
 506     qemu_put_be64(f, v->vsid);
 507     return 0;
 508 }
 509
 510 static const VMStateInfo vmstate_info_slbe = {
 511     .name = "slbe",
 512     .get  = get_slbe,
 513     .put  = put_slbe,
 514 };
 515
 516 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
 517     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
 518
 519 #define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
 520     VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
 521
 522 static bool slb_needed(void *opaque)
 523 {
 524     PowerPCCPU *cpu = opaque;
 525
 526     /* We don't support any of the old segment table based 64-bit CPUs */
 527     return mmu_is_64bit(cpu->env.mmu_model);
 528 }
 529
 530 static int slb_post_load(void *opaque, int version_id)
 531 {
 532     PowerPCCPU *cpu = opaque;
 533     CPUPPCState *env = &cpu->env;
 534     int i;
 535
 536     /*
 537      * We've pulled in the raw esid and vsid values from the migration
 538      * stream, but we need to recompute the page size pointers
 539      */
 540     for (i = 0; i < cpu->hash64_opts->slb_size; i++) {
 541         if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
 542             /* Migration source had bad values in its SLB */
 543             return -1;
 544         }
 545     }
 546
 547     return 0;
 548 }
 549
 550 static const VMStateDescription vmstate_slb = {
 551     .name = "cpu/slb",
 552     .version_id = 1,
 553     .minimum_version_id = 1,
 554     .needed = slb_needed,
 555     .post_load = slb_post_load,
 556     .fields = (const VMStateField[]) {
 557         VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_3_0_migration),
 558         VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
 559         VMSTATE_END_OF_LIST()
 560     }
 561 };
 562 #endif /* TARGET_PPC64 */
 563
 564 static const VMStateDescription vmstate_tlb6xx_entry = {
 565     .name = "cpu/tlb6xx_entry",
 566     .version_id = 1,
 567     .minimum_version_id = 1,
 568     .fields = (const VMStateField[]) {
 569         VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
 570         VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
 571         VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
 572         VMSTATE_END_OF_LIST()
 573     },
 574 };
 575
 576 static bool tlb6xx_needed(void *opaque)
 577 {
 578     PowerPCCPU *cpu = opaque;
 579     CPUPPCState *env = &cpu->env;
 580
 581     return env->nb_tlb && (env->tlb_type == TLB_6XX);
 582 }
 583
 584 static const VMStateDescription vmstate_tlb6xx = {
 585     .name = "cpu/tlb6xx",
 586     .version_id = 1,
 587     .minimum_version_id = 1,
 588     .needed = tlb6xx_needed,
 589     .fields = (const VMStateField[]) {
 590         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 591         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
 592                                             env.nb_tlb,
 593                                             vmstate_tlb6xx_entry,
 594                                             ppc6xx_tlb_t),
 595         VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
 596         VMSTATE_END_OF_LIST()
 597     }
 598 };
 599
 600 static const VMStateDescription vmstate_tlbemb_entry = {
 601     .name = "cpu/tlbemb_entry",
 602     .version_id = 1,
 603     .minimum_version_id = 1,
 604     .fields = (const VMStateField[]) {
 605         VMSTATE_UINT64(RPN, ppcemb_tlb_t),
 606         VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
 607         VMSTATE_UINTTL(PID, ppcemb_tlb_t),
 608         VMSTATE_UINTTL(size, ppcemb_tlb_t),
 609         VMSTATE_UINT32(prot, ppcemb_tlb_t),
 610         VMSTATE_UINT32(attr, ppcemb_tlb_t),
 611         VMSTATE_END_OF_LIST()
 612     },
 613 };
 614
 615 static bool tlbemb_needed(void *opaque)
 616 {
 617     PowerPCCPU *cpu = opaque;
 618     CPUPPCState *env = &cpu->env;
 619
 620     return env->nb_tlb && (env->tlb_type == TLB_EMB);
 621 }
 622
 623 static const VMStateDescription vmstate_tlbemb = {
 624     .name = "cpu/tlb6xx",
 625     .version_id = 1,
 626     .minimum_version_id = 1,
 627     .needed = tlbemb_needed,
 628     .fields = (const VMStateField[]) {
 629         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 630         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
 631                                             env.nb_tlb,
 632                                             vmstate_tlbemb_entry,
 633                                             ppcemb_tlb_t),
 634         VMSTATE_END_OF_LIST()
 635     },
 636 };
 637
 638 static const VMStateDescription vmstate_tlbmas_entry = {
 639     .name = "cpu/tlbmas_entry",
 640     .version_id = 1,
 641     .minimum_version_id = 1,
 642     .fields = (const VMStateField[]) {
 643         VMSTATE_UINT32(mas8, ppcmas_tlb_t),
 644         VMSTATE_UINT32(mas1, ppcmas_tlb_t),
 645         VMSTATE_UINT64(mas2, ppcmas_tlb_t),
 646         VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
 647         VMSTATE_END_OF_LIST()
 648     },
 649 };
 650
 651 static bool tlbmas_needed(void *opaque)
 652 {
 653     PowerPCCPU *cpu = opaque;
 654     CPUPPCState *env = &cpu->env;
 655
 656     return env->nb_tlb && (env->tlb_type == TLB_MAS);
 657 }
 658
 659 static const VMStateDescription vmstate_tlbmas = {
 660     .name = "cpu/tlbmas",
 661     .version_id = 1,
 662     .minimum_version_id = 1,
 663     .needed = tlbmas_needed,
 664     .fields = (const VMStateField[]) {
 665         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 666         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
 667                                             env.nb_tlb,
 668                                             vmstate_tlbmas_entry,
 669                                             ppcmas_tlb_t),
 670         VMSTATE_END_OF_LIST()
 671     }
 672 };
 673
 674 static bool compat_needed(void *opaque)
 675 {
 676     PowerPCCPU *cpu = opaque;
 677
 678     assert(!(cpu->compat_pvr && !cpu->vhyp));
 679     return !cpu->pre_2_10_migration && cpu->compat_pvr != 0;
 680 }
 681
 682 static const VMStateDescription vmstate_compat = {
 683     .name = "cpu/compat",
 684     .version_id = 1,
 685     .minimum_version_id = 1,
 686     .needed = compat_needed,
 687     .fields = (const VMStateField[]) {
 688         VMSTATE_UINT32(compat_pvr, PowerPCCPU),
 689         VMSTATE_END_OF_LIST()
 690     }
 691 };
 692
 693 static bool reservation_needed(void *opaque)
 694 {
 695     return (replay_mode != REPLAY_MODE_NONE);
 696 }
 697
 698 static const VMStateDescription vmstate_reservation = {
 699     .name = "cpu/reservation",
 700     .version_id = 1,
 701     .minimum_version_id = 1,
 702     .needed = reservation_needed,
 703     .fields = (const VMStateField[]) {
 704         VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
 705         VMSTATE_UINTTL(env.reserve_length, PowerPCCPU),
 706         VMSTATE_UINTTL(env.reserve_val, PowerPCCPU),
 707 #if defined(TARGET_PPC64)
 708         VMSTATE_UINTTL(env.reserve_val2, PowerPCCPU),
 709 #endif
 710         VMSTATE_END_OF_LIST()
 711     }
 712 };
 713
 714 const VMStateDescription vmstate_ppc_cpu = {
 715     .name = "cpu",
 716     .version_id = 5,
 717     .minimum_version_id = 5,
 718     .pre_save = cpu_pre_save,
 719     .post_load = cpu_post_load,
 720     .fields = (const VMStateField[]) {
 721         VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
 722
 723         /* User mode architected state */
 724         VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
 725 #if !defined(TARGET_PPC64)
 726         VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
 727 #endif
 728         VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
 729         VMSTATE_UINTTL(env.nip, PowerPCCPU),
 730
 731         /* SPRs */
 732         VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
 733         VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
 734
 735         VMSTATE_UNUSED(sizeof(target_ulong)), /* was env.reserve_addr */
 736
 737         /* Supervisor mode architected state */
 738         VMSTATE_UINTTL(env.msr, PowerPCCPU),
 739
 740         /* Backward compatible internal state */
 741         VMSTATE_UINTTL(env.hflags_compat_nmsr, PowerPCCPU),
 742
 743         /* Sanity checking */
 744         VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration),
 745         VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration),
 746         VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU,
 747                             cpu_pre_2_8_migration),
 748         VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration),
 749         VMSTATE_END_OF_LIST()
 750     },
 751     .subsections = (const VMStateDescription * const []) {
 752         &vmstate_fpu,
 753         &vmstate_altivec,
 754         &vmstate_vsx,
 755         &vmstate_sr,
 756 #ifdef TARGET_PPC64
 757         &vmstate_tm,
 758         &vmstate_slb,
 759 #endif /* TARGET_PPC64 */
 760         &vmstate_tlb6xx,
 761         &vmstate_tlbemb,
 762         &vmstate_tlbmas,
 763         &vmstate_compat,
 764         &vmstate_reservation,
 765         NULL
 766     }
 767 };