2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "hw/sysbus.h"
34 #include "hw/arm/arm.h"
35 #include "hw/arm/primecell.h"
36 #include "hw/arm/virt.h"
37 #include "hw/devices.h"
39 #include "sysemu/block-backend.h"
40 #include "sysemu/device_tree.h"
41 #include "sysemu/numa.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/kvm.h"
44 #include "hw/compat.h"
45 #include "hw/loader.h"
46 #include "exec/address-spaces.h"
47 #include "qemu/bitops.h"
48 #include "qemu/error-report.h"
49 #include "hw/pci-host/gpex.h"
50 #include "hw/arm/sysbus-fdt.h"
51 #include "hw/platform-bus.h"
52 #include "hw/arm/fdt.h"
53 #include "hw/intc/arm_gic.h"
54 #include "hw/intc/arm_gicv3_common.h"
56 #include "hw/smbios/smbios.h"
57 #include "qapi/visitor.h"
58 #include "standard-headers/linux/input.h"
60 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
61 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
64 MachineClass *mc = MACHINE_CLASS(oc); \
65 virt_machine_##major##_##minor##_options(mc); \
66 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
71 static const TypeInfo machvirt_##major##_##minor##_info = { \
72 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
73 .parent = TYPE_VIRT_MACHINE, \
74 .instance_init = virt_##major##_##minor##_instance_init, \
75 .class_init = virt_##major##_##minor##_class_init, \
77 static void machvirt_machine_##major##_##minor##_init(void) \
79 type_register_static(&machvirt_##major##_##minor##_info); \
81 type_init(machvirt_machine_##major##_##minor##_init);
83 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
84 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
85 #define DEFINE_VIRT_MACHINE(major, minor) \
86 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
89 /* Number of external interrupt lines to configure the GIC with */
92 #define PLATFORM_BUS_NUM_IRQS 64
94 static ARMPlatformBusSystemParams platform_bus_params
;
96 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
97 * RAM can go up to the 256GB mark, leaving 256GB of the physical
98 * address space unallocated and free for future use between 256G and 512G.
99 * If we need to provide more RAM to VMs in the future then we need to:
100 * * allocate a second bank of RAM starting at 2TB and working up
101 * * fix the DT and ACPI table generation code in QEMU to correctly
102 * report two split lumps of RAM to the guest
103 * * fix KVM in the host kernel to allow guests with >40 bit address spaces
104 * (We don't want to fill all the way up to 512GB with RAM because
105 * we might want it for non-RAM purposes later. Conversely it seems
106 * reasonable to assume that anybody configuring a VM with a quarter
107 * of a terabyte of RAM will be doing it on a host with more than a
108 * terabyte of physical address space.)
110 #define RAMLIMIT_GB 255
111 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
113 /* Addresses and sizes of our components.
114 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
115 * 128MB..256MB is used for miscellaneous device I/O.
116 * 256MB..1GB is reserved for possible future PCI support (ie where the
117 * PCI memory window will go if we add a PCI host controller).
118 * 1GB and up is RAM (which may happily spill over into the
119 * high memory region beyond 4GB).
120 * This represents a compromise between how much RAM can be given to
121 * a 32 bit VM and leaving space for expansion and in particular for PCI.
122 * Note that devices should generally be placed at multiples of 0x10000,
123 * to accommodate guests using 64K pages.
125 static const MemMapEntry a15memmap
[] = {
126 /* Space up to 0x8000000 is reserved for a boot ROM */
127 [VIRT_FLASH
] = { 0, 0x08000000 },
128 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
129 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
130 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
131 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
132 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
133 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
134 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
135 /* This redistributor space allows up to 2*64kB*123 CPUs */
136 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
137 [VIRT_UART
] = { 0x09000000, 0x00001000 },
138 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
139 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
140 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
141 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
142 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
143 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
144 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
145 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
146 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
147 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
148 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
149 [VIRT_MEM
] = { 0x40000000, RAMLIMIT_BYTES
},
150 /* Second PCIe window, 512GB wide at the 512GB boundary */
151 [VIRT_PCIE_MMIO_HIGH
] = { 0x8000000000ULL
, 0x8000000000ULL
},
154 static const int a15irqmap
[] = {
157 [VIRT_PCIE
] = 3, /* ... to 6 */
159 [VIRT_SECURE_UART
] = 8,
160 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
161 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
162 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
165 static const char *valid_cpus
[] = {
172 static bool cpuname_valid(const char *cpu
)
176 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
177 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
184 static void create_fdt(VirtMachineState
*vms
)
186 void *fdt
= create_device_tree(&vms
->fdt_size
);
189 error_report("create_device_tree() failed");
196 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
197 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
198 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
201 * /chosen and /memory nodes must exist for load_dtb
202 * to fill in necessary properties later
204 qemu_fdt_add_subnode(fdt
, "/chosen");
205 qemu_fdt_add_subnode(fdt
, "/memory");
206 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
208 /* Clock node, for the benefit of the UART. The kernel device tree
209 * binding documentation claims the PL011 node clock properties are
210 * optional but in practice if you omit them the kernel refuses to
211 * probe for the device.
213 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
214 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
215 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
216 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
217 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
218 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
220 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
222 if (have_numa_distance
) {
223 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
224 uint32_t *matrix
= g_malloc0(size
);
227 for (i
= 0; i
< nb_numa_nodes
; i
++) {
228 for (j
= 0; j
< nb_numa_nodes
; j
++) {
229 idx
= (i
* nb_numa_nodes
+ j
) * 3;
230 matrix
[idx
+ 0] = cpu_to_be32(i
);
231 matrix
[idx
+ 1] = cpu_to_be32(j
);
232 matrix
[idx
+ 2] = cpu_to_be32(numa_info
[i
].distance
[j
]);
236 qemu_fdt_add_subnode(fdt
, "/distance-map");
237 qemu_fdt_setprop_string(fdt
, "/distance-map", "compatible",
238 "numa-distance-map-v1");
239 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
245 static void fdt_add_psci_node(const VirtMachineState
*vms
)
247 uint32_t cpu_suspend_fn
;
251 void *fdt
= vms
->fdt
;
252 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
253 const char *psci_method
;
255 switch (vms
->psci_conduit
) {
256 case QEMU_PSCI_CONDUIT_DISABLED
:
258 case QEMU_PSCI_CONDUIT_HVC
:
261 case QEMU_PSCI_CONDUIT_SMC
:
265 g_assert_not_reached();
268 qemu_fdt_add_subnode(fdt
, "/psci");
269 if (armcpu
->psci_version
== 2) {
270 const char comp
[] = "arm,psci-0.2\0arm,psci";
271 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
273 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
274 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
275 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
276 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
277 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
279 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
280 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
281 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
284 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
286 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
287 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
288 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
289 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
292 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
293 * to the instruction that should be used to invoke PSCI functions.
294 * However, the device tree binding uses 'method' instead, so that is
295 * what we should use here.
297 qemu_fdt_setprop_string(fdt
, "/psci", "method", psci_method
);
299 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
300 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
301 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
302 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
305 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
307 /* On real hardware these interrupts are level-triggered.
308 * On KVM they were edge-triggered before host kernel version 4.4,
309 * and level-triggered afterwards.
310 * On emulated QEMU they are level-triggered.
312 * Getting the DTB info about them wrong is awkward for some
314 * pre-4.8 ignore the DT and leave the interrupt configured
315 * with whatever the GIC reset value (or the bootloader) left it at
316 * 4.8 before rc6 honour the incorrect data by programming it back
317 * into the GIC, causing problems
318 * 4.8rc6 and later ignore the DT and always write "level triggered"
321 * For backwards-compatibility, virt-2.8 and earlier will continue
322 * to say these are edge-triggered, but later machines will report
323 * the correct information.
326 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
327 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
329 if (vmc
->claim_edge_triggered_timers
) {
330 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
333 if (vms
->gic_version
== 2) {
334 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
335 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
336 (1 << vms
->smp_cpus
) - 1);
339 qemu_fdt_add_subnode(vms
->fdt
, "/timer");
341 armcpu
= ARM_CPU(qemu_get_cpu(0));
342 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
343 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
344 qemu_fdt_setprop(vms
->fdt
, "/timer", "compatible",
345 compat
, sizeof(compat
));
347 qemu_fdt_setprop_string(vms
->fdt
, "/timer", "compatible",
350 qemu_fdt_setprop(vms
->fdt
, "/timer", "always-on", NULL
, 0);
351 qemu_fdt_setprop_cells(vms
->fdt
, "/timer", "interrupts",
352 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
353 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
354 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
355 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
358 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
362 const MachineState
*ms
= MACHINE(vms
);
365 * From Documentation/devicetree/bindings/arm/cpus.txt
366 * On ARM v8 64-bit systems value should be set to 2,
367 * that corresponds to the MPIDR_EL1 register size.
368 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
369 * in the system, #address-cells can be set to 1, since
370 * MPIDR_EL1[63:32] bits are not used for CPUs
373 * Here we actually don't know whether our system is 32- or 64-bit one.
374 * The simplest way to go is to examine affinity IDs of all our CPUs. If
375 * at least one of them has Aff3 populated, we set #address-cells to 2.
377 for (cpu
= 0; cpu
< vms
->smp_cpus
; cpu
++) {
378 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
380 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
386 qemu_fdt_add_subnode(vms
->fdt
, "/cpus");
387 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#address-cells", addr_cells
);
388 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#size-cells", 0x0);
390 for (cpu
= vms
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
391 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
392 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
393 CPUState
*cs
= CPU(armcpu
);
395 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
396 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "cpu");
397 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
398 armcpu
->dtb_compatible
);
400 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
401 && vms
->smp_cpus
> 1) {
402 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
403 "enable-method", "psci");
406 if (addr_cells
== 2) {
407 qemu_fdt_setprop_u64(vms
->fdt
, nodename
, "reg",
408 armcpu
->mp_affinity
);
410 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "reg",
411 armcpu
->mp_affinity
);
414 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
415 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "numa-node-id",
416 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
423 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
425 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
426 qemu_fdt_add_subnode(vms
->fdt
, "/intc/its");
427 qemu_fdt_setprop_string(vms
->fdt
, "/intc/its", "compatible",
429 qemu_fdt_setprop(vms
->fdt
, "/intc/its", "msi-controller", NULL
, 0);
430 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/its", "reg",
431 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
432 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
433 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/its", "phandle", vms
->msi_phandle
);
436 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
438 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
439 qemu_fdt_add_subnode(vms
->fdt
, "/intc/v2m");
440 qemu_fdt_setprop_string(vms
->fdt
, "/intc/v2m", "compatible",
441 "arm,gic-v2m-frame");
442 qemu_fdt_setprop(vms
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
443 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/v2m", "reg",
444 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
445 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
446 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/v2m", "phandle", vms
->msi_phandle
);
449 static void fdt_add_gic_node(VirtMachineState
*vms
)
451 vms
->gic_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
452 qemu_fdt_setprop_cell(vms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
454 qemu_fdt_add_subnode(vms
->fdt
, "/intc");
455 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#interrupt-cells", 3);
456 qemu_fdt_setprop(vms
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
457 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#address-cells", 0x2);
458 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#size-cells", 0x2);
459 qemu_fdt_setprop(vms
->fdt
, "/intc", "ranges", NULL
, 0);
460 if (vms
->gic_version
== 3) {
461 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
463 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
464 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
465 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
466 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
467 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
469 qemu_fdt_setprop_cells(vms
->fdt
, "/intc", "interrupts",
470 GIC_FDT_IRQ_TYPE_PPI
, ARCH_GICV3_MAINT_IRQ
,
471 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
474 /* 'cortex-a15-gic' means 'GIC v2' */
475 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
476 "arm,cortex-a15-gic");
477 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
478 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
479 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
480 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
481 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
484 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "phandle", vms
->gic_phandle
);
487 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
491 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
494 armcpu
= ARM_CPU(cpu
);
495 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
) ||
496 (kvm_enabled() && !kvm_arm_pmu_create(cpu
, PPI(VIRTUAL_PMU_IRQ
)))) {
501 if (vms
->gic_version
== 2) {
502 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
503 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
504 (1 << vms
->smp_cpus
) - 1);
507 armcpu
= ARM_CPU(qemu_get_cpu(0));
508 qemu_fdt_add_subnode(vms
->fdt
, "/pmu");
509 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
510 const char compat
[] = "arm,armv8-pmuv3";
511 qemu_fdt_setprop(vms
->fdt
, "/pmu", "compatible",
512 compat
, sizeof(compat
));
513 qemu_fdt_setprop_cells(vms
->fdt
, "/pmu", "interrupts",
514 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
518 static void create_its(VirtMachineState
*vms
, DeviceState
*gicdev
)
520 const char *itsclass
= its_class_name();
524 /* Do nothing if not supported */
528 dev
= qdev_create(NULL
, itsclass
);
530 object_property_set_link(OBJECT(dev
), OBJECT(gicdev
), "parent-gicv3",
532 qdev_init_nofail(dev
);
533 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
535 fdt_add_its_gic_node(vms
);
538 static void create_v2m(VirtMachineState
*vms
, qemu_irq
*pic
)
541 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
544 dev
= qdev_create(NULL
, "arm-gicv2m");
545 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
546 qdev_prop_set_uint32(dev
, "base-spi", irq
);
547 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
548 qdev_init_nofail(dev
);
550 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
551 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
554 fdt_add_v2m_gic_node(vms
);
557 static void create_gic(VirtMachineState
*vms
, qemu_irq
*pic
)
559 /* We create a standalone GIC */
561 SysBusDevice
*gicbusdev
;
563 int type
= vms
->gic_version
, i
;
565 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
567 gicdev
= qdev_create(NULL
, gictype
);
568 qdev_prop_set_uint32(gicdev
, "revision", type
);
569 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
570 /* Note that the num-irq property counts both internal and external
571 * interrupts; there are always 32 of the former (mandated by GIC spec).
573 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
574 if (!kvm_irqchip_in_kernel()) {
575 qdev_prop_set_bit(gicdev
, "has-security-extensions", vms
->secure
);
577 qdev_init_nofail(gicdev
);
578 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
579 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
581 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
583 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
586 /* Wire the outputs from each CPU's generic timer and the GICv3
587 * maintenance interrupt signal to the appropriate GIC PPI inputs,
588 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
590 for (i
= 0; i
< smp_cpus
; i
++) {
591 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
592 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
594 /* Mapping from the output timer irq lines from the CPU to the
595 * GIC PPI inputs we use for the virt board.
597 const int timer_irq
[] = {
598 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
599 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
600 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
601 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
604 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
605 qdev_connect_gpio_out(cpudev
, irq
,
606 qdev_get_gpio_in(gicdev
,
607 ppibase
+ timer_irq
[irq
]));
610 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt", 0,
611 qdev_get_gpio_in(gicdev
, ppibase
612 + ARCH_GICV3_MAINT_IRQ
));
613 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
614 qdev_get_gpio_in(gicdev
, ppibase
617 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
618 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
619 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
620 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
621 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
622 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
623 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
626 for (i
= 0; i
< NUM_IRQS
; i
++) {
627 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
630 fdt_add_gic_node(vms
);
632 if (type
== 3 && vms
->its
) {
633 create_its(vms
, gicdev
);
634 } else if (type
== 2) {
635 create_v2m(vms
, pic
);
639 static void create_uart(const VirtMachineState
*vms
, qemu_irq
*pic
, int uart
,
640 MemoryRegion
*mem
, Chardev
*chr
)
643 hwaddr base
= vms
->memmap
[uart
].base
;
644 hwaddr size
= vms
->memmap
[uart
].size
;
645 int irq
= vms
->irqmap
[uart
];
646 const char compat
[] = "arm,pl011\0arm,primecell";
647 const char clocknames
[] = "uartclk\0apb_pclk";
648 DeviceState
*dev
= qdev_create(NULL
, "pl011");
649 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
651 qdev_prop_set_chr(dev
, "chardev", chr
);
652 qdev_init_nofail(dev
);
653 memory_region_add_subregion(mem
, base
,
654 sysbus_mmio_get_region(s
, 0));
655 sysbus_connect_irq(s
, 0, pic
[irq
]);
657 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
658 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
659 /* Note that we can't use setprop_string because of the embedded NUL */
660 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible",
661 compat
, sizeof(compat
));
662 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
664 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
665 GIC_FDT_IRQ_TYPE_SPI
, irq
,
666 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
667 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "clocks",
668 vms
->clock_phandle
, vms
->clock_phandle
);
669 qemu_fdt_setprop(vms
->fdt
, nodename
, "clock-names",
670 clocknames
, sizeof(clocknames
));
672 if (uart
== VIRT_UART
) {
673 qemu_fdt_setprop_string(vms
->fdt
, "/chosen", "stdout-path", nodename
);
675 /* Mark as not usable by the normal world */
676 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
677 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
683 static void create_rtc(const VirtMachineState
*vms
, qemu_irq
*pic
)
686 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
687 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
688 int irq
= vms
->irqmap
[VIRT_RTC
];
689 const char compat
[] = "arm,pl031\0arm,primecell";
691 sysbus_create_simple("pl031", base
, pic
[irq
]);
693 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
694 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
695 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
696 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
698 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
699 GIC_FDT_IRQ_TYPE_SPI
, irq
,
700 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
701 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
702 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
706 static DeviceState
*gpio_key_dev
;
707 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
709 /* use gpio Pin 3 for power button event */
710 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
713 static Notifier virt_system_powerdown_notifier
= {
714 .notify
= virt_powerdown_req
717 static void create_gpio(const VirtMachineState
*vms
, qemu_irq
*pic
)
720 DeviceState
*pl061_dev
;
721 hwaddr base
= vms
->memmap
[VIRT_GPIO
].base
;
722 hwaddr size
= vms
->memmap
[VIRT_GPIO
].size
;
723 int irq
= vms
->irqmap
[VIRT_GPIO
];
724 const char compat
[] = "arm,pl061\0arm,primecell";
726 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
728 uint32_t phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
729 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
730 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
731 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
733 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
734 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#gpio-cells", 2);
735 qemu_fdt_setprop(vms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
736 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
737 GIC_FDT_IRQ_TYPE_SPI
, irq
,
738 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
739 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
740 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
741 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", phandle
);
743 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
744 qdev_get_gpio_in(pl061_dev
, 3));
745 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys");
746 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
747 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#size-cells", 0);
748 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#address-cells", 1);
750 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys/poweroff");
751 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys/poweroff",
752 "label", "GPIO Key Poweroff");
753 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys/poweroff", "linux,code",
755 qemu_fdt_setprop_cells(vms
->fdt
, "/gpio-keys/poweroff",
756 "gpios", phandle
, 3, 0);
758 /* connect powerdown request */
759 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
764 static void create_virtio_devices(const VirtMachineState
*vms
, qemu_irq
*pic
)
767 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
769 /* We create the transports in forwards order. Since qbus_realize()
770 * prepends (not appends) new child buses, the incrementing loop below will
771 * create a list of virtio-mmio buses with decreasing base addresses.
773 * When a -device option is processed from the command line,
774 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
775 * order. The upshot is that -device options in increasing command line
776 * order are mapped to virtio-mmio buses with decreasing base addresses.
778 * When this code was originally written, that arrangement ensured that the
779 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
780 * the first -device on the command line. (The end-to-end order is a
781 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
782 * guest kernel's name-to-address assignment strategy.)
784 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
785 * the message, if not necessarily the code, of commit 70161ff336.
786 * Therefore the loop now establishes the inverse of the original intent.
788 * Unfortunately, we can't counteract the kernel change by reversing the
789 * loop; it would break existing command lines.
791 * In any case, the kernel makes no guarantee about the stability of
792 * enumeration order of virtio devices (as demonstrated by it changing
793 * between kernel versions). For reliable and stable identification
794 * of disks users must use UUIDs or similar mechanisms.
796 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
797 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
798 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
800 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
803 /* We add dtb nodes in reverse order so that they appear in the finished
804 * device tree lowest address first.
806 * Note that this mapping is independent of the loop above. The previous
807 * loop influences virtio device to virtio transport assignment, whereas
808 * this loop controls how virtio transports are laid out in the dtb.
810 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
812 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
813 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
815 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
816 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
817 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
818 "compatible", "virtio,mmio");
819 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
821 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
822 GIC_FDT_IRQ_TYPE_SPI
, irq
,
823 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
824 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
829 static void create_one_flash(const char *name
, hwaddr flashbase
,
830 hwaddr flashsize
, const char *file
,
831 MemoryRegion
*sysmem
)
833 /* Create and map a single flash device. We use the same
834 * parameters as the flash devices on the Versatile Express board.
836 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
837 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
838 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
839 const uint64_t sectorlength
= 256 * 1024;
842 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
846 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
847 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
848 qdev_prop_set_uint8(dev
, "width", 4);
849 qdev_prop_set_uint8(dev
, "device-width", 2);
850 qdev_prop_set_bit(dev
, "big-endian", false);
851 qdev_prop_set_uint16(dev
, "id0", 0x89);
852 qdev_prop_set_uint16(dev
, "id1", 0x18);
853 qdev_prop_set_uint16(dev
, "id2", 0x00);
854 qdev_prop_set_uint16(dev
, "id3", 0x00);
855 qdev_prop_set_string(dev
, "name", name
);
856 qdev_init_nofail(dev
);
858 memory_region_add_subregion(sysmem
, flashbase
,
859 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0));
865 if (drive_get(IF_PFLASH
, 0, 0)) {
866 error_report("The contents of the first flash device may be "
867 "specified with -bios or with -drive if=pflash... "
868 "but you cannot use both options at once");
871 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, file
);
873 error_report("Could not find ROM image '%s'", file
);
876 image_size
= load_image_mr(fn
, sysbus_mmio_get_region(sbd
, 0));
878 if (image_size
< 0) {
879 error_report("Could not load ROM image '%s'", file
);
885 static void create_flash(const VirtMachineState
*vms
,
886 MemoryRegion
*sysmem
,
887 MemoryRegion
*secure_sysmem
)
889 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
890 * Any file passed via -bios goes in the first of these.
891 * sysmem is the system memory space. secure_sysmem is the secure view
892 * of the system, and the first flash device should be made visible only
893 * there. The second flash device is visible to both secure and nonsecure.
894 * If sysmem == secure_sysmem this means there is no separate Secure
895 * address space and both flash devices are generally visible.
897 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
898 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
901 create_one_flash("virt.flash0", flashbase
, flashsize
,
902 bios_name
, secure_sysmem
);
903 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
,
906 if (sysmem
== secure_sysmem
) {
907 /* Report both flash devices as a single node in the DT */
908 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
909 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
910 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
911 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
912 2, flashbase
, 2, flashsize
,
913 2, flashbase
+ flashsize
, 2, flashsize
);
914 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
917 /* Report the devices as separate nodes so we can mark one as
918 * only visible to the secure world.
920 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
921 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
922 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
923 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
924 2, flashbase
, 2, flashsize
);
925 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
926 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
927 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
930 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
931 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
932 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
933 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
934 2, flashbase
+ flashsize
, 2, flashsize
);
935 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
940 static FWCfgState
*create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
942 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
943 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
947 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
948 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)smp_cpus
);
950 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
951 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
952 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
953 "compatible", "qemu,fw-cfg-mmio");
954 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
956 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
961 static void create_pcie_irq_map(const VirtMachineState
*vms
,
962 uint32_t gic_phandle
,
963 int first_irq
, const char *nodename
)
966 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
967 uint32_t *irq_map
= full_irq_map
;
969 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
970 for (pin
= 0; pin
< 4; pin
++) {
971 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
972 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
973 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
977 devfn
<< 8, 0, 0, /* devfn */
978 pin
+ 1, /* PCI pin */
979 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
981 /* Convert map to big endian */
982 for (i
= 0; i
< 10; i
++) {
983 irq_map
[i
] = cpu_to_be32(map
[i
]);
989 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-map",
990 full_irq_map
, sizeof(full_irq_map
));
992 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupt-map-mask",
993 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
997 static void create_pcie(const VirtMachineState
*vms
, qemu_irq
*pic
)
999 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
1000 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
1001 hwaddr base_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
1002 hwaddr size_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
1003 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
1004 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
1005 hwaddr base_ecam
= vms
->memmap
[VIRT_PCIE_ECAM
].base
;
1006 hwaddr size_ecam
= vms
->memmap
[VIRT_PCIE_ECAM
].size
;
1007 hwaddr base
= base_mmio
;
1008 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
1009 int irq
= vms
->irqmap
[VIRT_PCIE
];
1010 MemoryRegion
*mmio_alias
;
1011 MemoryRegion
*mmio_reg
;
1012 MemoryRegion
*ecam_alias
;
1013 MemoryRegion
*ecam_reg
;
1019 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
1020 qdev_init_nofail(dev
);
1022 /* Map only the first size_ecam bytes of ECAM space */
1023 ecam_alias
= g_new0(MemoryRegion
, 1);
1024 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1025 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1026 ecam_reg
, 0, size_ecam
);
1027 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1029 /* Map the MMIO window into system address space so as to expose
1030 * the section of PCI MMIO space which starts at the same base address
1031 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1034 mmio_alias
= g_new0(MemoryRegion
, 1);
1035 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1036 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1037 mmio_reg
, base_mmio
, size_mmio
);
1038 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1041 /* Map high MMIO space */
1042 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1044 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1045 mmio_reg
, base_mmio_high
, size_mmio_high
);
1046 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1050 /* Map IO port space */
1051 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1053 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1054 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
1057 pci
= PCI_HOST_BRIDGE(dev
);
1059 for (i
= 0; i
< nb_nics
; i
++) {
1060 NICInfo
*nd
= &nd_table
[i
];
1063 nd
->model
= g_strdup("virtio");
1066 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1070 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1071 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1072 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1073 "compatible", "pci-host-ecam-generic");
1074 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "pci");
1075 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 3);
1076 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 2);
1077 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "bus-range", 0,
1079 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1081 if (vms
->msi_phandle
) {
1082 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "msi-parent",
1086 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1087 2, base_ecam
, 2, size_ecam
);
1090 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1091 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1092 2, base_pio
, 2, size_pio
,
1093 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1094 2, base_mmio
, 2, size_mmio
,
1095 1, FDT_PCI_RANGE_MMIO_64BIT
,
1097 2, base_mmio_high
, 2, size_mmio_high
);
1099 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1100 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1101 2, base_pio
, 2, size_pio
,
1102 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1103 2, base_mmio
, 2, size_mmio
);
1106 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 1);
1107 create_pcie_irq_map(vms
, vms
->gic_phandle
, irq
, nodename
);
1112 static void create_platform_bus(VirtMachineState
*vms
, qemu_irq
*pic
)
1117 ARMPlatformBusFDTParams
*fdt_params
= g_new(ARMPlatformBusFDTParams
, 1);
1118 MemoryRegion
*sysmem
= get_system_memory();
1120 platform_bus_params
.platform_bus_base
= vms
->memmap
[VIRT_PLATFORM_BUS
].base
;
1121 platform_bus_params
.platform_bus_size
= vms
->memmap
[VIRT_PLATFORM_BUS
].size
;
1122 platform_bus_params
.platform_bus_first_irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
];
1123 platform_bus_params
.platform_bus_num_irqs
= PLATFORM_BUS_NUM_IRQS
;
1125 fdt_params
->system_params
= &platform_bus_params
;
1126 fdt_params
->binfo
= &vms
->bootinfo
;
1127 fdt_params
->intc
= "/intc";
1129 * register a machine init done notifier that creates the device tree
1130 * nodes of the platform bus and its children dynamic sysbus devices
1132 arm_register_platform_bus_fdt_creator(fdt_params
);
1134 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1135 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1136 qdev_prop_set_uint32(dev
, "num_irqs",
1137 platform_bus_params
.platform_bus_num_irqs
);
1138 qdev_prop_set_uint32(dev
, "mmio_size",
1139 platform_bus_params
.platform_bus_size
);
1140 qdev_init_nofail(dev
);
1141 s
= SYS_BUS_DEVICE(dev
);
1143 for (i
= 0; i
< platform_bus_params
.platform_bus_num_irqs
; i
++) {
1144 int irqn
= platform_bus_params
.platform_bus_first_irq
+ i
;
1145 sysbus_connect_irq(s
, i
, pic
[irqn
]);
1148 memory_region_add_subregion(sysmem
,
1149 platform_bus_params
.platform_bus_base
,
1150 sysbus_mmio_get_region(s
, 0));
1153 static void create_secure_ram(VirtMachineState
*vms
,
1154 MemoryRegion
*secure_sysmem
)
1156 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1158 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1159 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1161 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
,
1163 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1165 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1166 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1167 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "memory");
1168 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1169 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
1170 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
1175 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1177 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1180 *fdt_size
= board
->fdt_size
;
1184 static void virt_build_smbios(VirtMachineState
*vms
)
1186 uint8_t *smbios_tables
, *smbios_anchor
;
1187 size_t smbios_tables_len
, smbios_anchor_len
;
1188 const char *product
= "QEMU Virtual Machine";
1194 if (kvm_enabled()) {
1195 product
= "KVM Virtual Machine";
1198 smbios_set_defaults("QEMU", product
,
1199 "1.0", false, true, SMBIOS_ENTRY_POINT_30
);
1201 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1202 &smbios_anchor
, &smbios_anchor_len
);
1204 if (smbios_anchor
) {
1205 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-tables",
1206 smbios_tables
, smbios_tables_len
);
1207 fw_cfg_add_file(vms
->fw_cfg
, "etc/smbios/smbios-anchor",
1208 smbios_anchor
, smbios_anchor_len
);
1213 void virt_machine_done(Notifier
*notifier
, void *data
)
1215 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1218 virt_acpi_setup(vms
);
1219 virt_build_smbios(vms
);
1222 static uint64_t virt_cpu_mp_affinity(VirtMachineState
*vms
, int idx
)
1224 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
1225 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1227 if (!vmc
->disallow_affinity_adjustment
) {
1228 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1229 * GIC's target-list limitations. 32-bit KVM hosts currently
1230 * always create clusters of 4 CPUs, but that is expected to
1231 * change when they gain support for gicv3. When KVM is enabled
1232 * it will override the changes we make here, therefore our
1233 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1234 * and to improve SGI efficiency.
1236 if (vms
->gic_version
== 3) {
1237 clustersz
= GICV3_TARGETLIST_BITS
;
1239 clustersz
= GIC_TARGETLIST_BITS
;
1242 return arm_cpu_mp_affinity(idx
, clustersz
);
1245 static void machvirt_init(MachineState
*machine
)
1247 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1248 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1249 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1250 const CPUArchIdList
*possible_cpus
;
1251 qemu_irq pic
[NUM_IRQS
];
1252 MemoryRegion
*sysmem
= get_system_memory();
1253 MemoryRegion
*secure_sysmem
= NULL
;
1254 int n
, virt_max_cpus
;
1255 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1256 const char *cpu_model
= machine
->cpu_model
;
1259 const char *typename
;
1262 bool firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1265 cpu_model
= "cortex-a15";
1268 /* We can probe only here because during property set
1269 * KVM is not available yet
1271 if (!vms
->gic_version
) {
1272 if (!kvm_enabled()) {
1273 error_report("gic-version=host requires KVM");
1277 vms
->gic_version
= kvm_arm_vgic_probe();
1278 if (!vms
->gic_version
) {
1279 error_report("Unable to determine GIC version supported by host");
1284 /* Separate the actual CPU model name from any appended features */
1285 cpustr
= g_strsplit(cpu_model
, ",", 2);
1287 if (!cpuname_valid(cpustr
[0])) {
1288 error_report("mach-virt: CPU %s not supported", cpustr
[0]);
1292 /* If we have an EL3 boot ROM then the assumption is that it will
1293 * implement PSCI itself, so disable QEMU's internal implementation
1294 * so it doesn't get in the way. Instead of starting secondary
1295 * CPUs in PSCI powerdown state we will start them all running and
1296 * let the boot ROM sort them out.
1297 * The usual case is that we do use QEMU's PSCI implementation;
1298 * if the guest has EL2 then we will use SMC as the conduit,
1299 * and otherwise we will use HVC (for backwards compatibility and
1300 * because if we're using KVM then we must use HVC).
1302 if (vms
->secure
&& firmware_loaded
) {
1303 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
1304 } else if (vms
->virt
) {
1305 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
1307 vms
->psci_conduit
= QEMU_PSCI_CONDUIT_HVC
;
1310 /* The maximum number of CPUs depends on the GIC version, or on how
1311 * many redistributors we can fit into the memory map.
1313 if (vms
->gic_version
== 3) {
1314 virt_max_cpus
= vms
->memmap
[VIRT_GIC_REDIST
].size
/ 0x20000;
1316 virt_max_cpus
= GIC_NCPU
;
1319 if (max_cpus
> virt_max_cpus
) {
1320 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1321 "supported by machine 'mach-virt' (%d)",
1322 max_cpus
, virt_max_cpus
);
1326 vms
->smp_cpus
= smp_cpus
;
1328 if (machine
->ram_size
> vms
->memmap
[VIRT_MEM
].size
) {
1329 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB
);
1333 if (vms
->virt
&& kvm_enabled()) {
1334 error_report("mach-virt: KVM does not support providing "
1335 "Virtualization extensions to the guest CPU");
1340 if (kvm_enabled()) {
1341 error_report("mach-virt: KVM does not support Security extensions");
1345 /* The Secure view of the world is the same as the NonSecure,
1346 * but with a few extra devices. Create it as a container region
1347 * containing the system memory at low priority; any secure-only
1348 * devices go in at higher priority and take precedence.
1350 secure_sysmem
= g_new(MemoryRegion
, 1);
1351 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1353 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1358 oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpustr
[0]);
1360 error_report("Unable to find CPU definition");
1363 typename
= object_class_get_name(oc
);
1365 /* convert -smp CPU options specified by the user into global props */
1367 cc
->parse_features(typename
, cpustr
[1], &err
);
1370 error_report_err(err
);
1374 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
1375 for (n
= 0; n
< possible_cpus
->len
; n
++) {
1379 if (n
>= smp_cpus
) {
1383 cpuobj
= object_new(typename
);
1384 object_property_set_int(cpuobj
, possible_cpus
->cpus
[n
].arch_id
,
1385 "mp-affinity", NULL
);
1390 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
1394 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1397 if (!vms
->virt
&& object_property_find(cpuobj
, "has_el2", NULL
)) {
1398 object_property_set_bool(cpuobj
, false, "has_el2", NULL
);
1401 if (vms
->psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
) {
1402 object_property_set_int(cpuobj
, vms
->psci_conduit
,
1403 "psci-conduit", NULL
);
1405 /* Secondary CPUs start in PSCI powered-down state */
1407 object_property_set_bool(cpuobj
, true,
1408 "start-powered-off", NULL
);
1412 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu", NULL
)) {
1413 object_property_set_bool(cpuobj
, false, "pmu", NULL
);
1416 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1417 object_property_set_int(cpuobj
, vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1418 "reset-cbar", &error_abort
);
1421 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1424 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1425 "secure-memory", &error_abort
);
1428 object_property_set_bool(cpuobj
, true, "realized", NULL
);
1429 object_unref(cpuobj
);
1431 fdt_add_timer_nodes(vms
);
1432 fdt_add_cpu_nodes(vms
);
1433 fdt_add_psci_node(vms
);
1435 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1437 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
, ram
);
1439 create_flash(vms
, sysmem
, secure_sysmem
? secure_sysmem
: sysmem
);
1441 create_gic(vms
, pic
);
1443 fdt_add_pmu_nodes(vms
);
1445 create_uart(vms
, pic
, VIRT_UART
, sysmem
, serial_hds
[0]);
1448 create_secure_ram(vms
, secure_sysmem
);
1449 create_uart(vms
, pic
, VIRT_SECURE_UART
, secure_sysmem
, serial_hds
[1]);
1452 create_rtc(vms
, pic
);
1454 create_pcie(vms
, pic
);
1456 create_gpio(vms
, pic
);
1458 /* Create mmio transports, so the user can create virtio backends
1459 * (which will be automatically plugged in to the transports). If
1460 * no backend is created the transport will just sit harmlessly idle.
1462 create_virtio_devices(vms
, pic
);
1464 vms
->fw_cfg
= create_fw_cfg(vms
, &address_space_memory
);
1465 rom_set_fw(vms
->fw_cfg
);
1467 vms
->machine_done
.notify
= virt_machine_done
;
1468 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
1470 vms
->bootinfo
.ram_size
= machine
->ram_size
;
1471 vms
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1472 vms
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1473 vms
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1474 vms
->bootinfo
.nb_cpus
= smp_cpus
;
1475 vms
->bootinfo
.board_id
= -1;
1476 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
1477 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
1478 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
1479 arm_load_kernel(ARM_CPU(first_cpu
), &vms
->bootinfo
);
1482 * arm_load_kernel machine init done notifier registration must
1483 * happen before the platform_bus_create call. In this latter,
1484 * another notifier is registered which adds platform bus nodes.
1485 * Notifiers are executed in registration reverse order.
1487 create_platform_bus(vms
, pic
);
1490 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1492 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1497 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1499 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1501 vms
->secure
= value
;
1504 static bool virt_get_virt(Object
*obj
, Error
**errp
)
1506 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1511 static void virt_set_virt(Object
*obj
, bool value
, Error
**errp
)
1513 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1518 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1520 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1522 return vms
->highmem
;
1525 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1527 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1529 vms
->highmem
= value
;
1532 static bool virt_get_its(Object
*obj
, Error
**errp
)
1534 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1539 static void virt_set_its(Object
*obj
, bool value
, Error
**errp
)
1541 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1546 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1548 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1549 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1551 return g_strdup(val
);
1554 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1556 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1558 if (!strcmp(value
, "3")) {
1559 vms
->gic_version
= 3;
1560 } else if (!strcmp(value
, "2")) {
1561 vms
->gic_version
= 2;
1562 } else if (!strcmp(value
, "host")) {
1563 vms
->gic_version
= 0; /* Will probe later */
1565 error_setg(errp
, "Invalid gic-version value");
1566 error_append_hint(errp
, "Valid values are 3, 2, host.\n");
1570 static CpuInstanceProperties
1571 virt_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
1573 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
1574 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
1576 assert(cpu_index
< possible_cpus
->len
);
1577 return possible_cpus
->cpus
[cpu_index
].props
;
1580 static const CPUArchIdList
*virt_possible_cpu_arch_ids(MachineState
*ms
)
1583 VirtMachineState
*vms
= VIRT_MACHINE(ms
);
1585 if (ms
->possible_cpus
) {
1586 assert(ms
->possible_cpus
->len
== max_cpus
);
1587 return ms
->possible_cpus
;
1590 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
1591 sizeof(CPUArchId
) * max_cpus
);
1592 ms
->possible_cpus
->len
= max_cpus
;
1593 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
1594 ms
->possible_cpus
->cpus
[n
].arch_id
=
1595 virt_cpu_mp_affinity(vms
, n
);
1596 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
1597 ms
->possible_cpus
->cpus
[n
].props
.thread_id
= n
;
1599 /* default distribution of CPUs over NUMA nodes */
1600 if (nb_numa_nodes
) {
1601 /* preset values but do not enable them i.e. 'has_node_id = false',
1602 * numa init code will enable them later if manual mapping wasn't
1604 ms
->possible_cpus
->cpus
[n
].props
.node_id
= n
% nb_numa_nodes
;
1607 return ms
->possible_cpus
;
1610 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1612 MachineClass
*mc
= MACHINE_CLASS(oc
);
1614 mc
->init
= machvirt_init
;
1615 /* Start max_cpus at the maximum QEMU supports. We'll further restrict
1616 * it later in machvirt_init, where we have more information about the
1617 * configuration of the particular instance.
1620 mc
->has_dynamic_sysbus
= true;
1621 mc
->block_default_type
= IF_VIRTIO
;
1623 mc
->pci_allow_0_address
= true;
1624 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1625 mc
->minimum_page_bits
= 12;
1626 mc
->possible_cpu_arch_ids
= virt_possible_cpu_arch_ids
;
1627 mc
->cpu_index_to_instance_props
= virt_cpu_index_to_props
;
1630 static const TypeInfo virt_machine_info
= {
1631 .name
= TYPE_VIRT_MACHINE
,
1632 .parent
= TYPE_MACHINE
,
1634 .instance_size
= sizeof(VirtMachineState
),
1635 .class_size
= sizeof(VirtMachineClass
),
1636 .class_init
= virt_machine_class_init
,
1639 static void machvirt_machine_init(void)
1641 type_register_static(&virt_machine_info
);
1643 type_init(machvirt_machine_init
);
1645 static void virt_2_10_instance_init(Object
*obj
)
1647 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1648 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
1650 /* EL3 is disabled by default on virt: this makes us consistent
1651 * between KVM and TCG for this board, and it also allows us to
1652 * boot UEFI blobs which assume no TrustZone support.
1654 vms
->secure
= false;
1655 object_property_add_bool(obj
, "secure", virt_get_secure
,
1656 virt_set_secure
, NULL
);
1657 object_property_set_description(obj
, "secure",
1658 "Set on/off to enable/disable the ARM "
1659 "Security Extensions (TrustZone)",
1662 /* EL2 is also disabled by default, for similar reasons */
1664 object_property_add_bool(obj
, "virtualization", virt_get_virt
,
1665 virt_set_virt
, NULL
);
1666 object_property_set_description(obj
, "virtualization",
1667 "Set on/off to enable/disable emulating a "
1668 "guest CPU which implements the ARM "
1669 "Virtualization Extensions",
1672 /* High memory is enabled by default */
1673 vms
->highmem
= true;
1674 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1675 virt_set_highmem
, NULL
);
1676 object_property_set_description(obj
, "highmem",
1677 "Set on/off to enable/disable using "
1678 "physical address space above 32 bits",
1680 /* Default GIC type is v2 */
1681 vms
->gic_version
= 2;
1682 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1683 virt_set_gic_version
, NULL
);
1684 object_property_set_description(obj
, "gic-version",
1686 "Valid values are 2, 3 and host", NULL
);
1691 /* Default allows ITS instantiation */
1693 object_property_add_bool(obj
, "its", virt_get_its
,
1694 virt_set_its
, NULL
);
1695 object_property_set_description(obj
, "its",
1696 "Set on/off to enable/disable "
1697 "ITS instantiation",
1701 vms
->memmap
= a15memmap
;
1702 vms
->irqmap
= a15irqmap
;
1705 static void virt_machine_2_10_options(MachineClass
*mc
)
1708 DEFINE_VIRT_MACHINE_AS_LATEST(2, 10)
1710 #define VIRT_COMPAT_2_9 \
1713 static void virt_2_9_instance_init(Object
*obj
)
1715 virt_2_10_instance_init(obj
);
1718 static void virt_machine_2_9_options(MachineClass
*mc
)
1720 virt_machine_2_10_options(mc
);
1721 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_9
);
1723 DEFINE_VIRT_MACHINE(2, 9)
1725 #define VIRT_COMPAT_2_8 \
1728 static void virt_2_8_instance_init(Object
*obj
)
1730 virt_2_9_instance_init(obj
);
1733 static void virt_machine_2_8_options(MachineClass
*mc
)
1735 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1737 virt_machine_2_9_options(mc
);
1738 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_8
);
1739 /* For 2.8 and earlier we falsely claimed in the DT that
1740 * our timers were edge-triggered, not level-triggered.
1742 vmc
->claim_edge_triggered_timers
= true;
1744 DEFINE_VIRT_MACHINE(2, 8)
1746 #define VIRT_COMPAT_2_7 \
1749 static void virt_2_7_instance_init(Object
*obj
)
1751 virt_2_8_instance_init(obj
);
1754 static void virt_machine_2_7_options(MachineClass
*mc
)
1756 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1758 virt_machine_2_8_options(mc
);
1759 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_7
);
1760 /* ITS was introduced with 2.8 */
1762 /* Stick with 1K pages for migration compatibility */
1763 mc
->minimum_page_bits
= 0;
1765 DEFINE_VIRT_MACHINE(2, 7)
1767 #define VIRT_COMPAT_2_6 \
1770 static void virt_2_6_instance_init(Object
*obj
)
1772 virt_2_7_instance_init(obj
);
1775 static void virt_machine_2_6_options(MachineClass
*mc
)
1777 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1779 virt_machine_2_7_options(mc
);
1780 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_6
);
1781 vmc
->disallow_affinity_adjustment
= true;
1782 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
1785 DEFINE_VIRT_MACHINE(2, 6)