2 * ARM Versatile Platform/Application Baseboard System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "hw/sysbus.h"
11 #include "hw/arm/arm.h"
12 #include "hw/devices.h"
14 #include "sysemu/sysemu.h"
15 #include "hw/pci/pci.h"
16 #include "hw/i2c/i2c.h"
17 #include "hw/boards.h"
18 #include "sysemu/block-backend.h"
19 #include "exec/address-spaces.h"
20 #include "hw/block/flash.h"
22 #define VERSATILE_FLASH_ADDR 0x34000000
23 #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
24 #define VERSATILE_FLASH_SECT_SIZE (256 * 1024)
26 /* Primary interrupt controller. */
28 #define TYPE_VERSATILE_PB_SIC "versatilepb_sic"
29 #define VERSATILE_PB_SIC(obj) \
30 OBJECT_CHECK(vpb_sic_state, (obj), TYPE_VERSATILE_PB_SIC)
32 typedef struct vpb_sic_state
{
33 SysBusDevice parent_obj
;
43 static const VMStateDescription vmstate_vpb_sic
= {
44 .name
= "versatilepb_sic",
46 .minimum_version_id
= 1,
47 .fields
= (VMStateField
[]) {
48 VMSTATE_UINT32(level
, vpb_sic_state
),
49 VMSTATE_UINT32(mask
, vpb_sic_state
),
50 VMSTATE_UINT32(pic_enable
, vpb_sic_state
),
55 static void vpb_sic_update(vpb_sic_state
*s
)
59 flags
= s
->level
& s
->mask
;
60 qemu_set_irq(s
->parent
[s
->irq
], flags
!= 0);
63 static void vpb_sic_update_pic(vpb_sic_state
*s
)
68 for (i
= 21; i
<= 30; i
++) {
70 if (!(s
->pic_enable
& mask
))
72 qemu_set_irq(s
->parent
[i
], (s
->level
& mask
) != 0);
76 static void vpb_sic_set_irq(void *opaque
, int irq
, int level
)
78 vpb_sic_state
*s
= (vpb_sic_state
*)opaque
;
80 s
->level
|= 1u << irq
;
82 s
->level
&= ~(1u << irq
);
83 if (s
->pic_enable
& (1u << irq
))
84 qemu_set_irq(s
->parent
[irq
], level
);
88 static uint64_t vpb_sic_read(void *opaque
, hwaddr offset
,
91 vpb_sic_state
*s
= (vpb_sic_state
*)opaque
;
93 switch (offset
>> 2) {
95 return s
->level
& s
->mask
;
100 case 4: /* SOFTINT */
102 case 8: /* PICENABLE */
103 return s
->pic_enable
;
105 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset
);
110 static void vpb_sic_write(void *opaque
, hwaddr offset
,
111 uint64_t value
, unsigned size
)
113 vpb_sic_state
*s
= (vpb_sic_state
*)opaque
;
115 switch (offset
>> 2) {
122 case 4: /* SOFTINTSET */
126 case 5: /* SOFTINTCLR */
130 case 8: /* PICENSET */
131 s
->pic_enable
|= (value
& 0x7fe00000);
132 vpb_sic_update_pic(s
);
134 case 9: /* PICENCLR */
135 s
->pic_enable
&= ~value
;
136 vpb_sic_update_pic(s
);
139 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset
);
145 static const MemoryRegionOps vpb_sic_ops
= {
146 .read
= vpb_sic_read
,
147 .write
= vpb_sic_write
,
148 .endianness
= DEVICE_NATIVE_ENDIAN
,
151 static int vpb_sic_init(SysBusDevice
*sbd
)
153 DeviceState
*dev
= DEVICE(sbd
);
154 vpb_sic_state
*s
= VERSATILE_PB_SIC(dev
);
157 qdev_init_gpio_in(dev
, vpb_sic_set_irq
, 32);
158 for (i
= 0; i
< 32; i
++) {
159 sysbus_init_irq(sbd
, &s
->parent
[i
]);
162 memory_region_init_io(&s
->iomem
, OBJECT(s
), &vpb_sic_ops
, s
,
164 sysbus_init_mmio(sbd
, &s
->iomem
);
170 /* The AB and PB boards both use the same core, just with different
171 peripherals and expansion busses. For now we emulate a subset of the
172 PB peripherals and just change the board ID. */
174 static struct arm_boot_info versatile_binfo
;
176 static void versatile_init(MachineState
*machine
, int board_id
)
179 MemoryRegion
*sysmem
= get_system_memory();
180 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
183 DeviceState
*dev
, *sysctl
;
184 SysBusDevice
*busdev
;
193 if (!machine
->cpu_model
) {
194 machine
->cpu_model
= "arm926";
196 cpu
= cpu_arm_init(machine
->cpu_model
);
198 fprintf(stderr
, "Unable to find CPU definition\n");
201 memory_region_init_ram(ram
, NULL
, "versatile.ram", machine
->ram_size
,
203 vmstate_register_ram_global(ram
);
204 /* ??? RAM should repeat to fill physical memory space. */
205 /* SDRAM at address zero. */
206 memory_region_add_subregion(sysmem
, 0, ram
);
208 sysctl
= qdev_create(NULL
, "realview_sysctl");
209 qdev_prop_set_uint32(sysctl
, "sys_id", 0x41007004);
210 qdev_prop_set_uint32(sysctl
, "proc_id", 0x02000000);
211 qdev_init_nofail(sysctl
);
212 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl
), 0, 0x10000000);
214 dev
= sysbus_create_varargs("pl190", 0x10140000,
215 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
),
216 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_FIQ
),
218 for (n
= 0; n
< 32; n
++) {
219 pic
[n
] = qdev_get_gpio_in(dev
, n
);
221 dev
= sysbus_create_simple(TYPE_VERSATILE_PB_SIC
, 0x10003000, NULL
);
222 for (n
= 0; n
< 32; n
++) {
223 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), n
, pic
[n
]);
224 sic
[n
] = qdev_get_gpio_in(dev
, n
);
227 sysbus_create_simple("pl050_keyboard", 0x10006000, sic
[3]);
228 sysbus_create_simple("pl050_mouse", 0x10007000, sic
[4]);
230 dev
= qdev_create(NULL
, "versatile_pci");
231 busdev
= SYS_BUS_DEVICE(dev
);
232 qdev_init_nofail(dev
);
233 sysbus_mmio_map(busdev
, 0, 0x10001000); /* PCI controller regs */
234 sysbus_mmio_map(busdev
, 1, 0x41000000); /* PCI self-config */
235 sysbus_mmio_map(busdev
, 2, 0x42000000); /* PCI config */
236 sysbus_mmio_map(busdev
, 3, 0x43000000); /* PCI I/O */
237 sysbus_mmio_map(busdev
, 4, 0x44000000); /* PCI memory window 1 */
238 sysbus_mmio_map(busdev
, 5, 0x50000000); /* PCI memory window 2 */
239 sysbus_mmio_map(busdev
, 6, 0x60000000); /* PCI memory window 3 */
240 sysbus_connect_irq(busdev
, 0, sic
[27]);
241 sysbus_connect_irq(busdev
, 1, sic
[28]);
242 sysbus_connect_irq(busdev
, 2, sic
[29]);
243 sysbus_connect_irq(busdev
, 3, sic
[30]);
244 pci_bus
= (PCIBus
*)qdev_get_child_bus(dev
, "pci");
246 for(n
= 0; n
< nb_nics
; n
++) {
249 if (!done_smc
&& (!nd
->model
|| strcmp(nd
->model
, "smc91c111") == 0)) {
250 smc91c111_init(nd
, 0x10010000, sic
[25]);
253 pci_nic_init_nofail(nd
, pci_bus
, "rtl8139", NULL
);
256 if (usb_enabled(false)) {
257 pci_create_simple(pci_bus
, -1, "pci-ohci");
259 n
= drive_get_max_bus(IF_SCSI
);
261 pci_create_simple(pci_bus
, -1, "lsi53c895a");
265 sysbus_create_simple("pl011", 0x101f1000, pic
[12]);
266 sysbus_create_simple("pl011", 0x101f2000, pic
[13]);
267 sysbus_create_simple("pl011", 0x101f3000, pic
[14]);
268 sysbus_create_simple("pl011", 0x10009000, sic
[6]);
270 sysbus_create_simple("pl080", 0x10130000, pic
[17]);
271 sysbus_create_simple("sp804", 0x101e2000, pic
[4]);
272 sysbus_create_simple("sp804", 0x101e3000, pic
[5]);
274 sysbus_create_simple("pl061", 0x101e4000, pic
[6]);
275 sysbus_create_simple("pl061", 0x101e5000, pic
[7]);
276 sysbus_create_simple("pl061", 0x101e6000, pic
[8]);
277 sysbus_create_simple("pl061", 0x101e7000, pic
[9]);
279 /* The versatile/PB actually has a modified Color LCD controller
280 that includes hardware cursor support from the PL111. */
281 dev
= sysbus_create_simple("pl110_versatile", 0x10120000, pic
[16]);
282 /* Wire up the mux control signals from the SYS_CLCD register */
283 qdev_connect_gpio_out(sysctl
, 0, qdev_get_gpio_in(dev
, 0));
285 sysbus_create_varargs("pl181", 0x10005000, sic
[22], sic
[1], NULL
);
286 sysbus_create_varargs("pl181", 0x1000b000, sic
[23], sic
[2], NULL
);
288 /* Add PL031 Real Time Clock. */
289 sysbus_create_simple("pl031", 0x101e8000, pic
[10]);
291 dev
= sysbus_create_simple("versatile_i2c", 0x10002000, NULL
);
292 i2c
= (I2CBus
*)qdev_get_child_bus(dev
, "i2c");
293 i2c_create_slave(i2c
, "ds1338", 0x68);
295 /* Add PL041 AACI Interface to the LM4549 codec */
296 pl041
= qdev_create(NULL
, "pl041");
297 qdev_prop_set_uint32(pl041
, "nc_fifo_depth", 512);
298 qdev_init_nofail(pl041
);
299 sysbus_mmio_map(SYS_BUS_DEVICE(pl041
), 0, 0x10004000);
300 sysbus_connect_irq(SYS_BUS_DEVICE(pl041
), 0, sic
[24]);
302 /* Memory map for Versatile/PB: */
303 /* 0x10000000 System registers. */
304 /* 0x10001000 PCI controller config registers. */
305 /* 0x10002000 Serial bus interface. */
306 /* 0x10003000 Secondary interrupt controller. */
307 /* 0x10004000 AACI (audio). */
308 /* 0x10005000 MMCI0. */
309 /* 0x10006000 KMI0 (keyboard). */
310 /* 0x10007000 KMI1 (mouse). */
311 /* 0x10008000 Character LCD Interface. */
312 /* 0x10009000 UART3. */
313 /* 0x1000a000 Smart card 1. */
314 /* 0x1000b000 MMCI1. */
315 /* 0x10010000 Ethernet. */
316 /* 0x10020000 USB. */
317 /* 0x10100000 SSMC. */
318 /* 0x10110000 MPMC. */
319 /* 0x10120000 CLCD Controller. */
320 /* 0x10130000 DMA Controller. */
321 /* 0x10140000 Vectored interrupt controller. */
322 /* 0x101d0000 AHB Monitor Interface. */
323 /* 0x101e0000 System Controller. */
324 /* 0x101e1000 Watchdog Interface. */
325 /* 0x101e2000 Timer 0/1. */
326 /* 0x101e3000 Timer 2/3. */
327 /* 0x101e4000 GPIO port 0. */
328 /* 0x101e5000 GPIO port 1. */
329 /* 0x101e6000 GPIO port 2. */
330 /* 0x101e7000 GPIO port 3. */
331 /* 0x101e8000 RTC. */
332 /* 0x101f0000 Smart card 0. */
333 /* 0x101f1000 UART0. */
334 /* 0x101f2000 UART1. */
335 /* 0x101f3000 UART2. */
336 /* 0x101f4000 SSPI. */
337 /* 0x34000000 NOR Flash */
339 dinfo
= drive_get(IF_PFLASH
, 0, 0);
340 if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR
, NULL
, "versatile.flash",
341 VERSATILE_FLASH_SIZE
,
342 dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
,
343 VERSATILE_FLASH_SECT_SIZE
,
344 VERSATILE_FLASH_SIZE
/ VERSATILE_FLASH_SECT_SIZE
,
345 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
346 fprintf(stderr
, "qemu: Error registering flash memory.\n");
349 versatile_binfo
.ram_size
= machine
->ram_size
;
350 versatile_binfo
.kernel_filename
= machine
->kernel_filename
;
351 versatile_binfo
.kernel_cmdline
= machine
->kernel_cmdline
;
352 versatile_binfo
.initrd_filename
= machine
->initrd_filename
;
353 versatile_binfo
.board_id
= board_id
;
354 arm_load_kernel(cpu
, &versatile_binfo
);
357 static void vpb_init(MachineState
*machine
)
359 versatile_init(machine
, 0x183);
362 static void vab_init(MachineState
*machine
)
364 versatile_init(machine
, 0x25e);
367 static QEMUMachine versatilepb_machine
= {
368 .name
= "versatilepb",
369 .desc
= "ARM Versatile/PB (ARM926EJ-S)",
371 .block_default_type
= IF_SCSI
,
374 static QEMUMachine versatileab_machine
= {
375 .name
= "versatileab",
376 .desc
= "ARM Versatile/AB (ARM926EJ-S)",
378 .block_default_type
= IF_SCSI
,
381 static void versatile_machine_init(void)
383 qemu_register_machine(&versatilepb_machine
);
384 qemu_register_machine(&versatileab_machine
);
387 machine_init(versatile_machine_init
);
389 static void vpb_sic_class_init(ObjectClass
*klass
, void *data
)
391 DeviceClass
*dc
= DEVICE_CLASS(klass
);
392 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
394 k
->init
= vpb_sic_init
;
395 dc
->vmsd
= &vmstate_vpb_sic
;
398 static const TypeInfo vpb_sic_info
= {
399 .name
= TYPE_VERSATILE_PB_SIC
,
400 .parent
= TYPE_SYS_BUS_DEVICE
,
401 .instance_size
= sizeof(vpb_sic_state
),
402 .class_init
= vpb_sic_class_init
,
405 static void versatilepb_register_types(void)
407 type_register_static(&vpb_sic_info
);
410 type_init(versatilepb_register_types
)