2 * Emulation of Linux signals
4 * Copyright (c) 2003 Fabrice Bellard
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "user-internals.h"
22 #include "signal-common.h"
23 #include "linux-user/trace.h"
24 #include "vdso-asmoffset.h"
26 /* See arch/powerpc/include/asm/ucontext.h. Only used for 32-bit PPC;
27 on 64-bit PPC, sigcontext and mcontext are one and the same. */
28 struct target_mcontext
{
29 target_ulong mc_gregs
[48];
31 uint64_t mc_fregs
[33];
33 #if defined(TARGET_PPC64)
34 /* Pointer to the vector regs */
37 * On ppc64, this mcontext structure is naturally *unaligned*,
38 * or rather it is aligned on a 8 bytes boundary but not on
39 * a 16 byte boundary. This pad fixes it up. This is why we
40 * cannot use ppc_avr_t, which would force alignment. This is
41 * also why the vector regs are referenced in the ABI by the
42 * v_regs pointer above so any amount of padding can be added here.
45 /* VSCR and VRSAVE are saved separately. Also reserve space for VSX. */
47 uint64_t altivec
[34 + 16][2];
50 target_ulong mc_pad
[2];
52 /* We need to handle Altivec and SPE at the same time, which no
53 kernel needs to do. Fortunately, the kernel defines this bit to
54 be Altivec-register-large all the time, rather than trying to
55 twiddle it based on the specific platform. */
57 /* SPE vector registers. One extra for SPEFSCR. */
60 * Altivec vector registers. One extra for VRSAVE.
61 * On ppc32, we are already aligned to 16 bytes. We could
62 * use ppc_avr_t, but choose to share the same type as ppc64.
64 uint64_t altivec
[33][2];
69 QEMU_BUILD_BUG_ON(offsetof(struct target_mcontext
, mc_fregs
)
70 != offsetof_mcontext_fregs
);
71 #if defined(TARGET_PPC64)
72 QEMU_BUILD_BUG_ON(offsetof(struct target_mcontext
, v_regs
)
73 != offsetof_mcontext_vregs_ptr
);
75 QEMU_BUILD_BUG_ON(offsetof(struct target_mcontext
, mc_vregs
)
76 != offsetof_mcontext_vregs
);
79 /* See arch/powerpc/include/asm/sigcontext.h. */
80 struct target_sigcontext
{
81 target_ulong _unused
[4];
83 #if defined(TARGET_PPC64)
88 target_ulong regs
; /* struct pt_regs __user * */
89 #if defined(TARGET_PPC64)
90 struct target_mcontext mcontext
;
94 /* Indices for target_mcontext.mc_gregs, below.
95 See arch/powerpc/include/asm/ptrace.h for details. */
131 TARGET_PT_ORIG_R3
= 34,
136 /* Yes, there are two registers with #39. One is 64-bit only. */
138 TARGET_PT_SOFTE
= 39,
141 TARGET_PT_DSISR
= 42,
142 TARGET_PT_RESULT
= 43,
143 TARGET_PT_REGS_COUNT
= 44
147 struct target_ucontext
{
148 target_ulong tuc_flags
;
149 target_ulong tuc_link
; /* ucontext_t __user * */
150 struct target_sigaltstack tuc_stack
;
151 #if !defined(TARGET_PPC64)
153 target_ulong tuc_regs
; /* struct mcontext __user *
154 points to uc_mcontext field */
156 target_sigset_t tuc_sigmask
;
157 #if defined(TARGET_PPC64)
158 target_sigset_t unused
[15]; /* Allow for uc_sigmask growth */
159 struct target_sigcontext tuc_sigcontext
;
161 int32_t tuc_maskext
[30];
163 struct target_mcontext tuc_mcontext
;
167 #if !defined(TARGET_PPC64)
168 /* See arch/powerpc/kernel/signal_32.c. */
169 struct target_sigframe
{
170 struct target_sigcontext sctx
;
171 struct target_mcontext mctx
;
175 QEMU_BUILD_BUG_ON(offsetof(struct target_sigframe
, mctx
)
176 != offsetof_sigframe_mcontext
);
179 #if defined(TARGET_PPC64)
181 #define TARGET_TRAMP_SIZE 6
183 struct target_rt_sigframe
{
184 /* sys_rt_sigreturn requires the ucontext be the first field */
185 struct target_ucontext uc
;
186 target_ulong _unused
[2];
187 uint32_t trampoline
[TARGET_TRAMP_SIZE
];
188 target_ulong pinfo
; /* struct siginfo __user * */
189 target_ulong puc
; /* void __user * */
190 struct target_siginfo info
;
191 /* 64 bit ABI allows for 288 bytes below sp before decrementing it. */
193 } __attribute__((aligned(16)));
195 QEMU_BUILD_BUG_ON(offsetof(struct target_rt_sigframe
,
196 uc
.tuc_sigcontext
.mcontext
)
197 != offsetof_rt_sigframe_mcontext
);
201 struct target_rt_sigframe
{
202 struct target_siginfo info
;
203 struct target_ucontext uc
;
207 QEMU_BUILD_BUG_ON(offsetof(struct target_rt_sigframe
, uc
.tuc_mcontext
)
208 != offsetof_rt_sigframe_mcontext
);
212 #if defined(TARGET_PPC64)
214 struct target_func_ptr
{
221 /* See arch/powerpc/kernel/signal.c. */
222 static target_ulong
get_sigframe(struct target_sigaction
*ka
,
228 oldsp
= target_sigsp(get_sp_from_cpustate(env
), ka
);
230 return (oldsp
- frame_size
) & ~0xFUL
;
233 #if TARGET_BIG_ENDIAN == HOST_BIG_ENDIAN
242 static void save_user_regs(CPUPPCState
*env
, struct target_mcontext
*frame
)
244 target_ulong msr
= env
->msr
;
248 /* In general, the kernel attempts to be intelligent about what it
249 needs to save for Altivec/FP/SPE registers. We don't care that
250 much, so we just go ahead and save everything. */
252 /* Save general registers. */
253 for (i
= 0; i
< ARRAY_SIZE(env
->gpr
); i
++) {
254 __put_user(env
->gpr
[i
], &frame
->mc_gregs
[i
]);
256 __put_user(env
->nip
, &frame
->mc_gregs
[TARGET_PT_NIP
]);
257 __put_user(env
->ctr
, &frame
->mc_gregs
[TARGET_PT_CTR
]);
258 __put_user(env
->lr
, &frame
->mc_gregs
[TARGET_PT_LNK
]);
259 __put_user(cpu_read_xer(env
), &frame
->mc_gregs
[TARGET_PT_XER
]);
261 ccr
= ppc_get_cr(env
);
262 __put_user(ccr
, &frame
->mc_gregs
[TARGET_PT_CCR
]);
264 /* Save Altivec registers if necessary. */
265 if (env
->insns_flags
& PPC_ALTIVEC
) {
267 for (i
= 0; i
< 32; i
++) {
268 ppc_avr_t
*avr
= cpu_avr_ptr(env
, i
);
269 ppc_avr_t
*vreg
= (ppc_avr_t
*)&frame
->mc_vregs
.altivec
[i
];
271 __put_user(avr
->u64
[PPC_VEC_HI
], &vreg
->u64
[0]);
272 __put_user(avr
->u64
[PPC_VEC_LO
], &vreg
->u64
[1]);
274 #if defined(TARGET_PPC64)
275 vrsave
= (uint32_t *)&frame
->mc_vregs
.altivec
[33];
276 /* 64-bit needs to put a pointer to the vectors in the frame */
277 __put_user(h2g(frame
->mc_vregs
.altivec
), &frame
->v_regs
);
279 vrsave
= (uint32_t *)&frame
->mc_vregs
.altivec
[32];
281 __put_user((uint32_t)env
->spr
[SPR_VRSAVE
], vrsave
);
284 #if defined(TARGET_PPC64)
285 /* Save VSX second halves */
286 if (env
->insns_flags2
& PPC2_VSX
) {
287 uint64_t *vsregs
= (uint64_t *)&frame
->mc_vregs
.altivec
[34];
288 for (i
= 0; i
< 32; i
++) {
289 uint64_t *vsrl
= cpu_vsrl_ptr(env
, i
);
290 __put_user(*vsrl
, &vsregs
[i
]);
295 /* Save floating point registers. */
296 if (env
->insns_flags
& PPC_FLOAT
) {
297 for (i
= 0; i
< 32; i
++) {
298 uint64_t *fpr
= cpu_fpr_ptr(env
, i
);
299 __put_user(*fpr
, &frame
->mc_fregs
[i
]);
301 __put_user((uint64_t) env
->fpscr
, &frame
->mc_fregs
[32]);
304 #if !defined(TARGET_PPC64)
305 /* Save SPE registers. The kernel only saves the high half. */
306 if (env
->insns_flags
& PPC_SPE
) {
307 for (i
= 0; i
< ARRAY_SIZE(env
->gprh
); i
++) {
308 __put_user(env
->gprh
[i
], &frame
->mc_vregs
.spe
[i
]);
310 __put_user(env
->spe_fscr
, &frame
->mc_vregs
.spe
[32]);
315 __put_user(msr
, &frame
->mc_gregs
[TARGET_PT_MSR
]);
318 static void encode_trampoline(int sigret
, uint32_t *tramp
)
320 /* Set up the sigreturn trampoline: li r0,sigret; sc. */
321 __put_user(0x38000000 | sigret
, &tramp
[0]);
322 __put_user(0x44000002, &tramp
[1]);
325 static void restore_user_regs(CPUPPCState
*env
,
326 struct target_mcontext
*frame
, int sig
)
328 target_ulong save_r2
= 0;
336 save_r2
= env
->gpr
[2];
339 /* Restore general registers. */
340 for (i
= 0; i
< ARRAY_SIZE(env
->gpr
); i
++) {
341 __get_user(env
->gpr
[i
], &frame
->mc_gregs
[i
]);
343 __get_user(env
->nip
, &frame
->mc_gregs
[TARGET_PT_NIP
]);
344 __get_user(env
->ctr
, &frame
->mc_gregs
[TARGET_PT_CTR
]);
345 __get_user(env
->lr
, &frame
->mc_gregs
[TARGET_PT_LNK
]);
347 __get_user(xer
, &frame
->mc_gregs
[TARGET_PT_XER
]);
348 cpu_write_xer(env
, xer
);
350 __get_user(ccr
, &frame
->mc_gregs
[TARGET_PT_CCR
]);
351 ppc_set_cr(env
, ccr
);
353 env
->gpr
[2] = save_r2
;
356 __get_user(msr
, &frame
->mc_gregs
[TARGET_PT_MSR
]);
358 /* If doing signal return, restore the previous little-endian mode. */
360 ppc_store_msr(env
, ((env
->msr
& ~(1ull << MSR_LE
)) |
361 (msr
& (1ull << MSR_LE
))));
364 /* Restore Altivec registers if necessary. */
365 if (env
->insns_flags
& PPC_ALTIVEC
) {
368 #if defined(TARGET_PPC64)
370 /* 64-bit needs to recover the pointer to the vectors from the frame */
371 __get_user(v_addr
, &frame
->v_regs
);
372 v_regs
= g2h(env_cpu(env
), v_addr
);
374 v_regs
= (ppc_avr_t
*)frame
->mc_vregs
.altivec
;
376 for (i
= 0; i
< 32; i
++) {
377 ppc_avr_t
*avr
= cpu_avr_ptr(env
, i
);
378 ppc_avr_t
*vreg
= &v_regs
[i
];
380 __get_user(avr
->u64
[PPC_VEC_HI
], &vreg
->u64
[0]);
381 __get_user(avr
->u64
[PPC_VEC_LO
], &vreg
->u64
[1]);
383 #if defined(TARGET_PPC64)
384 vrsave
= (uint32_t *)&v_regs
[33];
386 vrsave
= (uint32_t *)&v_regs
[32];
388 __get_user(env
->spr
[SPR_VRSAVE
], vrsave
);
391 #if defined(TARGET_PPC64)
392 /* Restore VSX second halves */
393 if (env
->insns_flags2
& PPC2_VSX
) {
394 uint64_t *vsregs
= (uint64_t *)&frame
->mc_vregs
.altivec
[34];
395 for (i
= 0; i
< 32; i
++) {
396 uint64_t *vsrl
= cpu_vsrl_ptr(env
, i
);
397 __get_user(*vsrl
, &vsregs
[i
]);
402 /* Restore floating point registers. */
403 if (env
->insns_flags
& PPC_FLOAT
) {
405 for (i
= 0; i
< 32; i
++) {
406 uint64_t *fpr
= cpu_fpr_ptr(env
, i
);
407 __get_user(*fpr
, &frame
->mc_fregs
[i
]);
409 __get_user(fpscr
, &frame
->mc_fregs
[32]);
410 env
->fpscr
= (uint32_t) fpscr
;
413 #if !defined(TARGET_PPC64)
414 /* Save SPE registers. The kernel only saves the high half. */
415 if (env
->insns_flags
& PPC_SPE
) {
416 for (i
= 0; i
< ARRAY_SIZE(env
->gprh
); i
++) {
417 __get_user(env
->gprh
[i
], &frame
->mc_vregs
.spe
[i
]);
419 __get_user(env
->spe_fscr
, &frame
->mc_vregs
.spe
[32]);
424 #if !defined(TARGET_PPC64)
425 void setup_frame(int sig
, struct target_sigaction
*ka
,
426 target_sigset_t
*set
, CPUPPCState
*env
)
428 struct target_sigframe
*frame
;
429 struct target_sigcontext
*sc
;
430 target_ulong frame_addr
, newsp
;
433 frame_addr
= get_sigframe(ka
, env
, sizeof(*frame
));
434 trace_user_setup_frame(env
, frame_addr
);
435 if (!lock_user_struct(VERIFY_WRITE
, frame
, frame_addr
, 1))
439 __put_user(ka
->_sa_handler
, &sc
->handler
);
440 __put_user(set
->sig
[0], &sc
->oldmask
);
441 __put_user(set
->sig
[1], &sc
->_unused
[3]);
442 __put_user(h2g(&frame
->mctx
), &sc
->regs
);
443 __put_user(sig
, &sc
->signal
);
445 /* Save user regs. */
446 save_user_regs(env
, &frame
->mctx
);
448 env
->lr
= default_sigreturn
;
450 /* Turn off all fp exceptions. */
453 /* Create a stack frame for the caller of the handler. */
454 newsp
= frame_addr
- SIGNAL_FRAMESIZE
;
455 err
|= put_user(env
->gpr
[1], newsp
, target_ulong
);
460 /* Set up registers for signal handler. */
463 env
->gpr
[4] = frame_addr
+ offsetof(struct target_sigframe
, sctx
);
465 env
->nip
= (target_ulong
) ka
->_sa_handler
;
467 /* Signal handlers are entered in big-endian mode. */
468 ppc_store_msr(env
, env
->msr
& ~(1ull << MSR_LE
));
470 unlock_user_struct(frame
, frame_addr
, 1);
474 unlock_user_struct(frame
, frame_addr
, 1);
477 #endif /* !defined(TARGET_PPC64) */
479 void setup_rt_frame(int sig
, struct target_sigaction
*ka
,
480 target_siginfo_t
*info
,
481 target_sigset_t
*set
, CPUPPCState
*env
)
483 struct target_rt_sigframe
*rt_sf
;
484 struct target_mcontext
*mctx
= 0;
485 target_ulong rt_sf_addr
, newsp
= 0;
487 #if defined(TARGET_PPC64)
488 struct target_sigcontext
*sc
= 0;
489 struct image_info
*image
= get_task_state(thread_cpu
)->info
;
492 rt_sf_addr
= get_sigframe(ka
, env
, sizeof(*rt_sf
));
493 if (!lock_user_struct(VERIFY_WRITE
, rt_sf
, rt_sf_addr
, 1))
496 tswap_siginfo(&rt_sf
->info
, info
);
498 __put_user(0, &rt_sf
->uc
.tuc_flags
);
499 __put_user(0, &rt_sf
->uc
.tuc_link
);
500 target_save_altstack(&rt_sf
->uc
.tuc_stack
, env
);
501 #if !defined(TARGET_PPC64)
502 __put_user(h2g (&rt_sf
->uc
.tuc_mcontext
),
503 &rt_sf
->uc
.tuc_regs
);
505 for(i
= 0; i
< TARGET_NSIG_WORDS
; i
++) {
506 __put_user(set
->sig
[i
], &rt_sf
->uc
.tuc_sigmask
.sig
[i
]);
509 #if defined(TARGET_PPC64)
510 mctx
= &rt_sf
->uc
.tuc_sigcontext
.mcontext
;
512 sc
= &rt_sf
->uc
.tuc_sigcontext
;
513 __put_user(h2g(mctx
), &sc
->regs
);
514 __put_user(sig
, &sc
->signal
);
516 mctx
= &rt_sf
->uc
.tuc_mcontext
;
519 save_user_regs(env
, mctx
);
521 env
->lr
= default_rt_sigreturn
;
523 /* Turn off all fp exceptions. */
526 /* Create a stack frame for the caller of the handler. */
527 newsp
= rt_sf_addr
- (SIGNAL_FRAMESIZE
+ 16);
528 err
|= put_user(env
->gpr
[1], newsp
, target_ulong
);
533 /* Set up registers for signal handler. */
535 env
->gpr
[3] = (target_ulong
) sig
;
536 env
->gpr
[4] = (target_ulong
) h2g(&rt_sf
->info
);
537 env
->gpr
[5] = (target_ulong
) h2g(&rt_sf
->uc
);
538 env
->gpr
[6] = (target_ulong
) h2g(rt_sf
);
540 #if defined(TARGET_PPC64)
541 if (get_ppc64_abi(image
) < 2) {
542 /* ELFv1 PPC64 function pointers are pointers to OPD entries. */
543 struct target_func_ptr
*handler
=
544 (struct target_func_ptr
*)g2h(env_cpu(env
), ka
->_sa_handler
);
545 env
->nip
= tswapl(handler
->entry
);
546 env
->gpr
[2] = tswapl(handler
->toc
);
548 /* ELFv2 PPC64 function pointers are entry points. R12 must also be set. */
549 env
->gpr
[12] = env
->nip
= ka
->_sa_handler
;
552 env
->nip
= (target_ulong
) ka
->_sa_handler
;
555 #if TARGET_BIG_ENDIAN
556 /* Signal handlers are entered in big-endian mode. */
557 ppc_store_msr(env
, env
->msr
& ~(1ull << MSR_LE
));
559 /* Signal handlers are entered in little-endian mode. */
560 ppc_store_msr(env
, env
->msr
| (1ull << MSR_LE
));
563 unlock_user_struct(rt_sf
, rt_sf_addr
, 1);
567 unlock_user_struct(rt_sf
, rt_sf_addr
, 1);
572 #if !defined(TARGET_PPC64)
573 long do_sigreturn(CPUPPCState
*env
)
575 struct target_sigcontext
*sc
= NULL
;
576 struct target_mcontext
*sr
= NULL
;
577 target_ulong sr_addr
= 0, sc_addr
;
581 sc_addr
= env
->gpr
[1] + SIGNAL_FRAMESIZE
;
582 if (!lock_user_struct(VERIFY_READ
, sc
, sc_addr
, 1))
585 __get_user(set
.sig
[0], &sc
->oldmask
);
586 __get_user(set
.sig
[1], &sc
->_unused
[3]);
588 target_to_host_sigset_internal(&blocked
, &set
);
589 set_sigmask(&blocked
);
591 __get_user(sr_addr
, &sc
->regs
);
592 if (!lock_user_struct(VERIFY_READ
, sr
, sr_addr
, 1))
594 restore_user_regs(env
, sr
, 1);
596 unlock_user_struct(sr
, sr_addr
, 1);
597 unlock_user_struct(sc
, sc_addr
, 1);
598 return -QEMU_ESIGRETURN
;
601 unlock_user_struct(sr
, sr_addr
, 1);
602 unlock_user_struct(sc
, sc_addr
, 1);
603 force_sig(TARGET_SIGSEGV
);
604 return -QEMU_ESIGRETURN
;
606 #endif /* !defined(TARGET_PPC64) */
608 /* See arch/powerpc/kernel/signal_32.c. */
609 static int do_setcontext(struct target_ucontext
*ucp
, CPUPPCState
*env
, int sig
)
611 struct target_mcontext
*mcp
;
612 target_ulong mcp_addr
;
616 if (copy_from_user(&set
, h2g(ucp
) + offsetof(struct target_ucontext
, tuc_sigmask
),
620 #if defined(TARGET_PPC64)
621 mcp_addr
= h2g(ucp
) +
622 offsetof(struct target_ucontext
, tuc_sigcontext
.mcontext
);
624 __get_user(mcp_addr
, &ucp
->tuc_regs
);
627 if (!lock_user_struct(VERIFY_READ
, mcp
, mcp_addr
, 1))
630 target_to_host_sigset_internal(&blocked
, &set
);
631 set_sigmask(&blocked
);
632 restore_user_regs(env
, mcp
, sig
);
634 unlock_user_struct(mcp
, mcp_addr
, 1);
638 long do_rt_sigreturn(CPUPPCState
*env
)
640 struct target_rt_sigframe
*rt_sf
= NULL
;
641 target_ulong rt_sf_addr
;
643 rt_sf_addr
= env
->gpr
[1] + SIGNAL_FRAMESIZE
+ 16;
644 if (!lock_user_struct(VERIFY_READ
, rt_sf
, rt_sf_addr
, 1))
647 if (do_setcontext(&rt_sf
->uc
, env
, 1))
650 target_restore_altstack(&rt_sf
->uc
.tuc_stack
, env
);
652 unlock_user_struct(rt_sf
, rt_sf_addr
, 1);
653 return -QEMU_ESIGRETURN
;
656 unlock_user_struct(rt_sf
, rt_sf_addr
, 1);
657 force_sig(TARGET_SIGSEGV
);
658 return -QEMU_ESIGRETURN
;
661 /* This syscall implements {get,set,swap}context for userland. */
662 abi_long
do_swapcontext(CPUArchState
*env
, abi_ulong uold_ctx
,
663 abi_ulong unew_ctx
, abi_long ctx_size
)
665 struct target_ucontext
*uctx
;
666 struct target_mcontext
*mctx
;
668 /* For ppc32, ctx_size is "reserved for future use".
669 * For ppc64, we do not yet support the VSX extension.
671 if (ctx_size
< sizeof(struct target_ucontext
)) {
672 return -TARGET_EINVAL
;
676 TaskState
*ts
= get_task_state(thread_cpu
);
678 if (!lock_user_struct(VERIFY_WRITE
, uctx
, uold_ctx
, 1)) {
679 return -TARGET_EFAULT
;
683 mctx
= &uctx
->tuc_sigcontext
.mcontext
;
685 /* ??? The kernel aligns the pointer down here into padding, but
686 * in setup_rt_frame we don't. Be self-compatible for now.
688 mctx
= &uctx
->tuc_mcontext
;
689 __put_user(h2g(mctx
), &uctx
->tuc_regs
);
692 save_user_regs(env
, mctx
);
693 host_to_target_sigset(&uctx
->tuc_sigmask
, &ts
->signal_mask
);
695 unlock_user_struct(uctx
, uold_ctx
, 1);
701 if (!lock_user_struct(VERIFY_READ
, uctx
, unew_ctx
, 1)) {
702 return -TARGET_EFAULT
;
704 err
= do_setcontext(uctx
, env
, 0);
705 unlock_user_struct(uctx
, unew_ctx
, 1);
708 /* We cannot return to a partially updated context. */
709 force_sig(TARGET_SIGSEGV
);
711 return -QEMU_ESIGRETURN
;
717 void setup_sigtramp(abi_ulong sigtramp_page
)
719 uint32_t *tramp
= lock_user(VERIFY_WRITE
, sigtramp_page
, 2 * 8, 0);
720 assert(tramp
!= NULL
);
722 #ifdef TARGET_ARCH_HAS_SETUP_FRAME
723 default_sigreturn
= sigtramp_page
;
724 encode_trampoline(TARGET_NR_sigreturn
, tramp
+ 0);
727 default_rt_sigreturn
= sigtramp_page
+ 8;
728 encode_trampoline(TARGET_NR_rt_sigreturn
, tramp
+ 2);
730 unlock_user(tramp
, sigtramp_page
, 2 * 8);