include/hw/ppc/xics.h

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #ifndef XICS_H
  29 #define XICS_H
  30
  31 #include "exec/memory.h"
  32 #include "hw/qdev-core.h"
  33
  34 #define XICS_IPI        0x2
  35 #define XICS_BUID       0x1
  36 #define XICS_IRQ_BASE   (XICS_BUID << 12)
  37
  38 /*
  39  * We currently only support one BUID which is our interrupt base
  40  * (the kernel implementation supports more but we don't exploit
  41  *  that yet)
  42  */
  43 typedef struct ICPStateClass ICPStateClass;
  44 typedef struct ICPState ICPState;
  45 typedef struct PnvICPState PnvICPState;
  46 typedef struct ICSStateClass ICSStateClass;
  47 typedef struct ICSState ICSState;
  48 typedef struct ICSIRQState ICSIRQState;
  49 typedef struct XICSFabric XICSFabric;
  50
  51 #define TYPE_ICP "icp"
  52 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
  53
  54 #define TYPE_PNV_ICP "pnv-icp"
  55 #define PNV_ICP(obj) OBJECT_CHECK(PnvICPState, (obj), TYPE_PNV_ICP)
  56
  57 #define ICP_CLASS(klass) \
  58      OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
  59 #define ICP_GET_CLASS(obj) \
  60      OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
  61
  62 struct ICPStateClass {
  63     DeviceClass parent_class;
  64
  65     DeviceRealize parent_realize;
  66 };
  67
  68 struct ICPState {
  69     /*< private >*/
  70     DeviceState parent_obj;
  71     /*< public >*/
  72     CPUState *cs;
  73     ICSState *xirr_owner;
  74     uint32_t xirr;
  75     uint8_t pending_priority;
  76     uint8_t mfrr;
  77     qemu_irq output;
  78
  79     XICSFabric *xics;
  80 };
  81
  82 #define ICP_PROP_XICS "xics"
  83 #define ICP_PROP_CPU "cpu"
  84
  85 struct PnvICPState {
  86     ICPState parent_obj;
  87
  88     MemoryRegion mmio;
  89     uint32_t links[3];
  90 };
  91
  92 #define TYPE_ICS_BASE "ics-base"
  93 #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE)
  94
  95 /* Retain ics for sPAPR for migration from existing sPAPR guests */
  96 #define TYPE_ICS_SIMPLE "ics"
  97 #define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE)
  98
  99 #define ICS_BASE_CLASS(klass) \
 100      OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE)
 101 #define ICS_BASE_GET_CLASS(obj) \
 102      OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE)
 103
 104 struct ICSStateClass {
 105     DeviceClass parent_class;
 106
 107     DeviceRealize parent_realize;
 108     DeviceReset parent_reset;
 109
 110     void (*reject)(ICSState *s, uint32_t irq);
 111     void (*resend)(ICSState *s);
 112     void (*eoi)(ICSState *s, uint32_t irq);
 113 };
 114
 115 struct ICSState {
 116     /*< private >*/
 117     DeviceState parent_obj;
 118     /*< public >*/
 119     uint32_t nr_irqs;
 120     uint32_t offset;
 121     ICSIRQState *irqs;
 122     XICSFabric *xics;
 123 };
 124
 125 #define ICS_PROP_XICS "xics"
 126
 127 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
 128 {
 129     return (nr >= ics->offset) && (nr < (ics->offset + ics->nr_irqs));
 130 }
 131
 132 struct ICSIRQState {
 133     uint32_t server;
 134     uint8_t priority;
 135     uint8_t saved_priority;
 136 #define XICS_STATUS_ASSERTED           0x1
 137 #define XICS_STATUS_SENT               0x2
 138 #define XICS_STATUS_REJECTED           0x4
 139 #define XICS_STATUS_MASKED_PENDING     0x8
 140 #define XICS_STATUS_PRESENTED          0x10
 141 #define XICS_STATUS_QUEUED             0x20
 142     uint8_t status;
 143 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
 144 #define XICS_FLAGS_IRQ_LSI             0x1
 145 #define XICS_FLAGS_IRQ_MSI             0x2
 146 #define XICS_FLAGS_IRQ_MASK            0x3
 147     uint8_t flags;
 148 };
 149
 150 #define TYPE_XICS_FABRIC "xics-fabric"
 151 #define XICS_FABRIC(obj)                                     \
 152     INTERFACE_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC)
 153 #define XICS_FABRIC_CLASS(klass)                                     \
 154     OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC)
 155 #define XICS_FABRIC_GET_CLASS(obj)                                   \
 156     OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC)
 157
 158 typedef struct XICSFabricClass {
 159     InterfaceClass parent;
 160     ICSState *(*ics_get)(XICSFabric *xi, int irq);
 161     void (*ics_resend)(XICSFabric *xi);
 162     ICPState *(*icp_get)(XICSFabric *xi, int server);
 163 } XICSFabricClass;
 164
 165 ICPState *xics_icp_get(XICSFabric *xi, int server);
 166
 167 /* Internal XICS interfaces */
 168 void icp_set_cppr(ICPState *icp, uint8_t cppr);
 169 void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
 170 uint32_t icp_accept(ICPState *ss);
 171 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
 172 void icp_eoi(ICPState *icp, uint32_t xirr);
 173
 174 void ics_simple_write_xive(ICSState *ics, int nr, int server,
 175                            uint8_t priority, uint8_t saved_priority);
 176 void ics_simple_set_irq(void *opaque, int srcno, int val);
 177
 178 static inline bool ics_irq_free(ICSState *ics, uint32_t srcno)
 179 {
 180     return !(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK);
 181 }
 182
 183 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
 184 void icp_pic_print_info(ICPState *icp, Monitor *mon);
 185 void ics_pic_print_info(ICSState *ics, Monitor *mon);
 186
 187 void ics_resend(ICSState *ics);
 188 void icp_resend(ICPState *ss);
 189
 190 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi,
 191                    Error **errp);
 192
 193 /* KVM */
 194 void icp_get_kvm_state(ICPState *icp);
 195 int icp_set_kvm_state(ICPState *icp, Error **errp);
 196 void icp_synchronize_state(ICPState *icp);
 197 void icp_kvm_realize(DeviceState *dev, Error **errp);
 198
 199 void ics_get_kvm_state(ICSState *ics);
 200 int ics_set_kvm_state_one(ICSState *ics, int srcno, Error **errp);
 201 int ics_set_kvm_state(ICSState *ics, Error **errp);
 202 void ics_synchronize_state(ICSState *ics);
 203 void ics_kvm_set_irq(ICSState *ics, int srcno, int val);
 204
 205 #endif /* XICS_H */