Public Git Hosting - qemu.git/search

2022-05-24	Frank Chang	target/riscv: Fix typo of mimpid cpu option Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-04-29	Frank Chang	target/riscv: Support configuarable marchid, mvendorid... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-04-22	Frank Chang	hw/intc: Make RISC-V ACLINT mtime MMIO register writable Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-04-22	Frank Chang	hw/intc: Support 32/64-bit mtimecmp and mtime accesses... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-04-22	Frank Chang	hw/intc: Add .impl.[min\|max]_access_size declaration... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Allow Zve32f extension to be... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve32f support for narrowing... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve32f support for widening... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve32f support for single... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve32f support for scalar... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve32f support for configuration... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve32f extension into RISC-V Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Allow Zve64f extension to be... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve64f support for narrowing... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve64f support for widening... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve64f support for single... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve64f support for scalar... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve64f support for vsmul... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve64f support for vmulh... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve64f support for load... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve64f support for configuration... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-21	Frank Chang	target/riscv: rvv-1.0: Add Zve64f extension into RISC-V Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-08	Frank Chang	target/riscv: rvv-1.0: Call the correct RVF/RVD check... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-08	Frank Chang	target/riscv: rvv-1.0: Call the correct RVF/RVD check... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-08	Frank Chang	target/riscv: rvv-1.0: Call the correct RVF/RVD check... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2022-01-04	Frank Chang	hw/sd: Add SDHC support for SD card SPI-mode Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: Add ELEN checks for widening... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: update opivv_vadc_check() comment Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: rename vmandnot.mm and vmornot... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: add vector unit-stride mask... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: add vsetivli instruction Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: floating-point reciprocal estimate... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: floating-point reciprocal square... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: trigger illegal instruction... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: implement vstart CSR Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: narrowing floating-point/integer... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: add "set round to odd" rounding mode... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: widening floating-point/integer... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: floating-point/integer type... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: introduce floating-point rounding mode... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: floating-point min/max instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: remove integer extract instruction Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: remove vmford.vv and vmford.vf Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: remove widening saturating scaled... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: single-width scaling shift instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: widening floating-point reduction... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: single-width floating-point... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: narrowing fixed-point clip instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: floating-point slide instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: slide instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: mask-register logical instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: floating-point compare instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: integer comparison instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: single-width saturating add... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: widening integer multiply-add... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: narrowing integer right shift... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: integer add-with-carry/subtract... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: single-width bit shift instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: single-width averaging add and... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: integer extension instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: whole register move instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: floating-point scalar move instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: floating-point move instruction Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: integer scalar move instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: register gather instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: allow load element with sign... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: element index instruction Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: iota instruction Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: set-X-first mask bit instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: find-first-set mask bit instruction Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: count population in mask instruction Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: floating-point classify instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: floating-point square-root instruction Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: take fractional LMUL into vector... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: update vext_max_elems() for... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: load/store whole register instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: fault-only-first unit stride... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: fix address index overflow bug... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: index load and store instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: stride load and store instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: configure instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: remove amo operations instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv:1.0: add translation-time nan-box... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: introduce more imm value modes in translator... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: update check functions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: add VMA and VTA Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: add fractional LMUL Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: remove MLEN calculations Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: check MSTATUS_VS when accessing... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: remove rvv related codes from... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: add translation-time vector... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: introduce writable misa.v field Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: rvv-1.0: set mstatus.SD bit if mstatus... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: Use FIELD_EX32() to extract wd field Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: drop vector 0.7.1 and add 1.0 support Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: zfh: add Zfhmin cpu property Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-12-20	Frank Chang	target/riscv: zfh: implement zfhmin extension Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
next

QEmu

RSS Atom