| commit | 5160bacc0638088a7cb0180d2be3d8c2c8a21831 | |
| author | Hongren (Zenithal) Zheng <i@zenithal.me> | |
| Wed, 18 May 2022 12:46:58 +0000 (18 20:46 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Tue, 24 May 2022 00:38:50 +0000 (24 10:38 +1000) | ||
| tree | f4ba73b24ec68d81f9fb05bbedca7b15d39352c2 | treesnapshot (tar.gz zip) |
| parent | d644e5e44ff627d6b4da73a65795f60335ba4cb9 | commitdiff |
target/riscv: add zicsr/zifencei to isa_string
Zicsr/Zifencei is not in 'I' since ISA version 20190608,
thus to fully express the capability of the CPU,
they should be exposed in isa_string.
Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <YoTqwpfrodveJ7CR@Sun>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Zicsr/Zifencei is not in 'I' since ISA version 20190608,
thus to fully express the capability of the CPU,
they should be exposed in isa_string.
Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <YoTqwpfrodveJ7CR@Sun>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.c | diffblobblamehistory |