spapr: Add "slb-size" property to CPU device tree nodes
[qemu.git] / hw / ppc / spapr.c
blob3ba1e90aee207b206879d878ca07ac69a513c5a5
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
27 #include "sysemu/sysemu.h"
28 #include "sysemu/numa.h"
29 #include "hw/hw.h"
30 #include "hw/fw-path-provider.h"
31 #include "elf.h"
32 #include "net/net.h"
33 #include "sysemu/device_tree.h"
34 #include "sysemu/block-backend.h"
35 #include "sysemu/cpus.h"
36 #include "sysemu/kvm.h"
37 #include "sysemu/device_tree.h"
38 #include "kvm_ppc.h"
39 #include "migration/migration.h"
40 #include "mmu-hash64.h"
41 #include "qom/cpu.h"
43 #include "hw/boards.h"
44 #include "hw/ppc/ppc.h"
45 #include "hw/loader.h"
47 #include "hw/ppc/spapr.h"
48 #include "hw/ppc/spapr_vio.h"
49 #include "hw/pci-host/spapr.h"
50 #include "hw/ppc/xics.h"
51 #include "hw/pci/msi.h"
53 #include "hw/pci/pci.h"
54 #include "hw/scsi/scsi.h"
55 #include "hw/virtio/virtio-scsi.h"
57 #include "exec/address-spaces.h"
58 #include "hw/usb.h"
59 #include "qemu/config-file.h"
60 #include "qemu/error-report.h"
61 #include "trace.h"
62 #include "hw/nmi.h"
64 #include "hw/compat.h"
65 #include "qemu-common.h"
67 #include <libfdt.h>
69 /* SLOF memory layout:
71 * SLOF raw image loaded at 0, copies its romfs right below the flat
72 * device-tree, then position SLOF itself 31M below that
74 * So we set FW_OVERHEAD to 40MB which should account for all of that
75 * and more
77 * We load our kernel at 4M, leaving space for SLOF initial image
79 #define FDT_MAX_SIZE 0x100000
80 #define RTAS_MAX_SIZE 0x10000
81 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
82 #define FW_MAX_SIZE 0x400000
83 #define FW_FILE_NAME "slof.bin"
84 #define FW_OVERHEAD 0x2800000
85 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
87 #define MIN_RMA_SLOF 128UL
89 #define TIMEBASE_FREQ 512000000ULL
91 #define PHANDLE_XICP 0x00001111
93 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
95 static XICSState *try_create_xics(const char *type, int nr_servers,
96 int nr_irqs, Error **errp)
98 Error *err = NULL;
99 DeviceState *dev;
101 dev = qdev_create(NULL, type);
102 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
103 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
104 object_property_set_bool(OBJECT(dev), true, "realized", &err);
105 if (err) {
106 error_propagate(errp, err);
107 object_unparent(OBJECT(dev));
108 return NULL;
110 return XICS_COMMON(dev);
113 static XICSState *xics_system_init(MachineState *machine,
114 int nr_servers, int nr_irqs)
116 XICSState *icp = NULL;
118 if (kvm_enabled()) {
119 Error *err = NULL;
121 if (machine_kernel_irqchip_allowed(machine)) {
122 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err);
124 if (machine_kernel_irqchip_required(machine) && !icp) {
125 error_report("kernel_irqchip requested but unavailable: %s",
126 error_get_pretty(err));
130 if (!icp) {
131 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, &error_abort);
134 return icp;
137 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
138 int smt_threads)
140 int i, ret = 0;
141 uint32_t servers_prop[smt_threads];
142 uint32_t gservers_prop[smt_threads * 2];
143 int index = ppc_get_vcpu_dt_id(cpu);
145 if (cpu->cpu_version) {
146 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
147 if (ret < 0) {
148 return ret;
152 /* Build interrupt servers and gservers properties */
153 for (i = 0; i < smt_threads; i++) {
154 servers_prop[i] = cpu_to_be32(index + i);
155 /* Hack, direct the group queues back to cpu 0 */
156 gservers_prop[i*2] = cpu_to_be32(index + i);
157 gservers_prop[i*2 + 1] = 0;
159 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
160 servers_prop, sizeof(servers_prop));
161 if (ret < 0) {
162 return ret;
164 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
165 gservers_prop, sizeof(gservers_prop));
167 return ret;
170 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
172 int ret = 0;
173 PowerPCCPU *cpu = POWERPC_CPU(cs);
174 int index = ppc_get_vcpu_dt_id(cpu);
175 uint32_t associativity[] = {cpu_to_be32(0x5),
176 cpu_to_be32(0x0),
177 cpu_to_be32(0x0),
178 cpu_to_be32(0x0),
179 cpu_to_be32(cs->numa_node),
180 cpu_to_be32(index)};
182 /* Advertise NUMA via ibm,associativity */
183 if (nb_numa_nodes > 1) {
184 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
185 sizeof(associativity));
188 return ret;
191 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
193 int ret = 0, offset, cpus_offset;
194 CPUState *cs;
195 char cpu_model[32];
196 int smt = kvmppc_smt_threads();
197 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
199 CPU_FOREACH(cs) {
200 PowerPCCPU *cpu = POWERPC_CPU(cs);
201 DeviceClass *dc = DEVICE_GET_CLASS(cs);
202 int index = ppc_get_vcpu_dt_id(cpu);
204 if ((index % smt) != 0) {
205 continue;
208 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
210 cpus_offset = fdt_path_offset(fdt, "/cpus");
211 if (cpus_offset < 0) {
212 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
213 "cpus");
214 if (cpus_offset < 0) {
215 return cpus_offset;
218 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
219 if (offset < 0) {
220 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
221 if (offset < 0) {
222 return offset;
226 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
227 pft_size_prop, sizeof(pft_size_prop));
228 if (ret < 0) {
229 return ret;
232 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
233 if (ret < 0) {
234 return ret;
237 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
238 ppc_get_compat_smt_threads(cpu));
239 if (ret < 0) {
240 return ret;
243 return ret;
247 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
248 size_t maxsize)
250 size_t maxcells = maxsize / sizeof(uint32_t);
251 int i, j, count;
252 uint32_t *p = prop;
254 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
255 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
257 if (!sps->page_shift) {
258 break;
260 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
261 if (sps->enc[count].page_shift == 0) {
262 break;
265 if ((p - prop) >= (maxcells - 3 - count * 2)) {
266 break;
268 *(p++) = cpu_to_be32(sps->page_shift);
269 *(p++) = cpu_to_be32(sps->slb_enc);
270 *(p++) = cpu_to_be32(count);
271 for (j = 0; j < count; j++) {
272 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
273 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
277 return (p - prop) * sizeof(uint32_t);
280 static hwaddr spapr_node0_size(void)
282 MachineState *machine = MACHINE(qdev_get_machine());
284 if (nb_numa_nodes) {
285 int i;
286 for (i = 0; i < nb_numa_nodes; ++i) {
287 if (numa_info[i].node_mem) {
288 return MIN(pow2floor(numa_info[i].node_mem),
289 machine->ram_size);
293 return machine->ram_size;
296 #define _FDT(exp) \
297 do { \
298 int ret = (exp); \
299 if (ret < 0) { \
300 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
301 #exp, fdt_strerror(ret)); \
302 exit(1); \
304 } while (0)
306 static void add_str(GString *s, const gchar *s1)
308 g_string_append_len(s, s1, strlen(s1) + 1);
311 static void *spapr_create_fdt_skel(hwaddr initrd_base,
312 hwaddr initrd_size,
313 hwaddr kernel_size,
314 bool little_endian,
315 const char *kernel_cmdline,
316 uint32_t epow_irq)
318 void *fdt;
319 uint32_t start_prop = cpu_to_be32(initrd_base);
320 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
321 GString *hypertas = g_string_sized_new(256);
322 GString *qemu_hypertas = g_string_sized_new(256);
323 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
324 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
325 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
326 char *buf;
328 add_str(hypertas, "hcall-pft");
329 add_str(hypertas, "hcall-term");
330 add_str(hypertas, "hcall-dabr");
331 add_str(hypertas, "hcall-interrupt");
332 add_str(hypertas, "hcall-tce");
333 add_str(hypertas, "hcall-vio");
334 add_str(hypertas, "hcall-splpar");
335 add_str(hypertas, "hcall-bulk");
336 add_str(hypertas, "hcall-set-mode");
337 add_str(qemu_hypertas, "hcall-memop1");
339 fdt = g_malloc0(FDT_MAX_SIZE);
340 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
342 if (kernel_size) {
343 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
345 if (initrd_size) {
346 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
348 _FDT((fdt_finish_reservemap(fdt)));
350 /* Root node */
351 _FDT((fdt_begin_node(fdt, "")));
352 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
353 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
354 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
357 * Add info to guest to indentify which host is it being run on
358 * and what is the uuid of the guest
360 if (kvmppc_get_host_model(&buf)) {
361 _FDT((fdt_property_string(fdt, "host-model", buf)));
362 g_free(buf);
364 if (kvmppc_get_host_serial(&buf)) {
365 _FDT((fdt_property_string(fdt, "host-serial", buf)));
366 g_free(buf);
369 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1],
370 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4],
371 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7],
372 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10],
373 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13],
374 qemu_uuid[14], qemu_uuid[15]);
376 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
377 g_free(buf);
379 if (qemu_get_vm_name()) {
380 _FDT((fdt_property_string(fdt, "ibm,partition-name",
381 qemu_get_vm_name())));
384 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
385 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
387 /* /chosen */
388 _FDT((fdt_begin_node(fdt, "chosen")));
390 /* Set Form1_affinity */
391 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
393 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
394 _FDT((fdt_property(fdt, "linux,initrd-start",
395 &start_prop, sizeof(start_prop))));
396 _FDT((fdt_property(fdt, "linux,initrd-end",
397 &end_prop, sizeof(end_prop))));
398 if (kernel_size) {
399 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
400 cpu_to_be64(kernel_size) };
402 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
403 if (little_endian) {
404 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
407 if (boot_menu) {
408 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
410 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
411 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
412 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
414 _FDT((fdt_end_node(fdt)));
416 /* RTAS */
417 _FDT((fdt_begin_node(fdt, "rtas")));
419 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
420 add_str(hypertas, "hcall-multi-tce");
422 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
423 hypertas->len)));
424 g_string_free(hypertas, TRUE);
425 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
426 qemu_hypertas->len)));
427 g_string_free(qemu_hypertas, TRUE);
429 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
430 refpoints, sizeof(refpoints))));
432 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
433 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
434 RTAS_EVENT_SCAN_RATE)));
436 if (msi_supported) {
437 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
441 * According to PAPR, rtas ibm,os-term does not guarantee a return
442 * back to the guest cpu.
444 * While an additional ibm,extended-os-term property indicates that
445 * rtas call return will always occur. Set this property.
447 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
449 _FDT((fdt_end_node(fdt)));
451 /* interrupt controller */
452 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
454 _FDT((fdt_property_string(fdt, "device_type",
455 "PowerPC-External-Interrupt-Presentation")));
456 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
457 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
458 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
459 interrupt_server_ranges_prop,
460 sizeof(interrupt_server_ranges_prop))));
461 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
462 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
463 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
465 _FDT((fdt_end_node(fdt)));
467 /* vdevice */
468 _FDT((fdt_begin_node(fdt, "vdevice")));
470 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
471 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
472 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
473 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
474 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
475 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
477 _FDT((fdt_end_node(fdt)));
479 /* event-sources */
480 spapr_events_fdt_skel(fdt, epow_irq);
482 /* /hypervisor node */
483 if (kvm_enabled()) {
484 uint8_t hypercall[16];
486 /* indicate KVM hypercall interface */
487 _FDT((fdt_begin_node(fdt, "hypervisor")));
488 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
489 if (kvmppc_has_cap_fixup_hcalls()) {
491 * Older KVM versions with older guest kernels were broken with the
492 * magic page, don't allow the guest to map it.
494 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
495 sizeof(hypercall));
496 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
497 sizeof(hypercall))));
499 _FDT((fdt_end_node(fdt)));
502 _FDT((fdt_end_node(fdt))); /* close root node */
503 _FDT((fdt_finish(fdt)));
505 return fdt;
508 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
509 hwaddr size)
511 uint32_t associativity[] = {
512 cpu_to_be32(0x4), /* length */
513 cpu_to_be32(0x0), cpu_to_be32(0x0),
514 cpu_to_be32(0x0), cpu_to_be32(nodeid)
516 char mem_name[32];
517 uint64_t mem_reg_property[2];
518 int off;
520 mem_reg_property[0] = cpu_to_be64(start);
521 mem_reg_property[1] = cpu_to_be64(size);
523 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
524 off = fdt_add_subnode(fdt, 0, mem_name);
525 _FDT(off);
526 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
527 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
528 sizeof(mem_reg_property))));
529 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
530 sizeof(associativity))));
531 return off;
534 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
536 MachineState *machine = MACHINE(spapr);
537 hwaddr mem_start, node_size;
538 int i, nb_nodes = nb_numa_nodes;
539 NodeInfo *nodes = numa_info;
540 NodeInfo ramnode;
542 /* No NUMA nodes, assume there is just one node with whole RAM */
543 if (!nb_numa_nodes) {
544 nb_nodes = 1;
545 ramnode.node_mem = machine->ram_size;
546 nodes = &ramnode;
549 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
550 if (!nodes[i].node_mem) {
551 continue;
553 if (mem_start >= machine->ram_size) {
554 node_size = 0;
555 } else {
556 node_size = nodes[i].node_mem;
557 if (node_size > machine->ram_size - mem_start) {
558 node_size = machine->ram_size - mem_start;
561 if (!mem_start) {
562 /* ppc_spapr_init() checks for rma_size <= node0_size already */
563 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
564 mem_start += spapr->rma_size;
565 node_size -= spapr->rma_size;
567 for ( ; node_size; ) {
568 hwaddr sizetmp = pow2floor(node_size);
570 /* mem_start != 0 here */
571 if (ctzl(mem_start) < ctzl(sizetmp)) {
572 sizetmp = 1ULL << ctzl(mem_start);
575 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
576 node_size -= sizetmp;
577 mem_start += sizetmp;
581 return 0;
584 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
585 sPAPRMachineState *spapr)
587 PowerPCCPU *cpu = POWERPC_CPU(cs);
588 CPUPPCState *env = &cpu->env;
589 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
590 int index = ppc_get_vcpu_dt_id(cpu);
591 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
592 0xffffffff, 0xffffffff};
593 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
594 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
595 uint32_t page_sizes_prop[64];
596 size_t page_sizes_prop_size;
597 uint32_t vcpus_per_socket = smp_threads * smp_cores;
598 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
600 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
601 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
603 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
604 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
605 env->dcache_line_size)));
606 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
607 env->dcache_line_size)));
608 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
609 env->icache_line_size)));
610 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
611 env->icache_line_size)));
613 if (pcc->l1_dcache_size) {
614 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
615 pcc->l1_dcache_size)));
616 } else {
617 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
619 if (pcc->l1_icache_size) {
620 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
621 pcc->l1_icache_size)));
622 } else {
623 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
626 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
627 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
628 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
629 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
630 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
631 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
633 if (env->spr_cb[SPR_PURR].oea_read) {
634 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
637 if (env->mmu_model & POWERPC_MMU_1TSEG) {
638 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
639 segs, sizeof(segs))));
642 /* Advertise VMX/VSX (vector extensions) if available
643 * 0 / no property == no vector extensions
644 * 1 == VMX / Altivec available
645 * 2 == VSX available */
646 if (env->insns_flags & PPC_ALTIVEC) {
647 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
649 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
652 /* Advertise DFP (Decimal Floating Point) if available
653 * 0 / no property == no DFP
654 * 1 == DFP available */
655 if (env->insns_flags2 & PPC2_DFP) {
656 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
659 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
660 sizeof(page_sizes_prop));
661 if (page_sizes_prop_size) {
662 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
663 page_sizes_prop, page_sizes_prop_size)));
666 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
667 cs->cpu_index / vcpus_per_socket)));
669 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
670 pft_size_prop, sizeof(pft_size_prop))));
672 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
674 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
675 ppc_get_compat_smt_threads(cpu)));
678 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
680 CPUState *cs;
681 int cpus_offset;
682 char *nodename;
683 int smt = kvmppc_smt_threads();
685 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
686 _FDT(cpus_offset);
687 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
688 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
691 * We walk the CPUs in reverse order to ensure that CPU DT nodes
692 * created by fdt_add_subnode() end up in the right order in FDT
693 * for the guest kernel the enumerate the CPUs correctly.
695 CPU_FOREACH_REVERSE(cs) {
696 PowerPCCPU *cpu = POWERPC_CPU(cs);
697 int index = ppc_get_vcpu_dt_id(cpu);
698 DeviceClass *dc = DEVICE_GET_CLASS(cs);
699 int offset;
701 if ((index % smt) != 0) {
702 continue;
705 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
706 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
707 g_free(nodename);
708 _FDT(offset);
709 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
715 * Adds ibm,dynamic-reconfiguration-memory node.
716 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
717 * of this device tree node.
719 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
721 MachineState *machine = MACHINE(spapr);
722 int ret, i, offset;
723 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
724 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
725 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
726 uint32_t *int_buf, *cur_index, buf_len;
727 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
730 * Allocate enough buffer size to fit in ibm,dynamic-memory
731 * or ibm,associativity-lookup-arrays
733 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
734 * sizeof(uint32_t);
735 cur_index = int_buf = g_malloc0(buf_len);
737 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
739 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
740 sizeof(prop_lmb_size));
741 if (ret < 0) {
742 goto out;
745 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
746 if (ret < 0) {
747 goto out;
750 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
751 if (ret < 0) {
752 goto out;
755 /* ibm,dynamic-memory */
756 int_buf[0] = cpu_to_be32(nr_lmbs);
757 cur_index++;
758 for (i = 0; i < nr_lmbs; i++) {
759 sPAPRDRConnector *drc;
760 sPAPRDRConnectorClass *drck;
761 uint64_t addr = i * lmb_size + spapr->hotplug_memory.base;;
762 uint32_t *dynamic_memory = cur_index;
764 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
765 addr/lmb_size);
766 g_assert(drc);
767 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
769 dynamic_memory[0] = cpu_to_be32(addr >> 32);
770 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
771 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
772 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
773 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
774 if (addr < machine->ram_size ||
775 memory_region_present(get_system_memory(), addr)) {
776 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
777 } else {
778 dynamic_memory[5] = cpu_to_be32(0);
781 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
783 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
784 if (ret < 0) {
785 goto out;
788 /* ibm,associativity-lookup-arrays */
789 cur_index = int_buf;
790 int_buf[0] = cpu_to_be32(nr_nodes);
791 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
792 cur_index += 2;
793 for (i = 0; i < nr_nodes; i++) {
794 uint32_t associativity[] = {
795 cpu_to_be32(0x0),
796 cpu_to_be32(0x0),
797 cpu_to_be32(0x0),
798 cpu_to_be32(i)
800 memcpy(cur_index, associativity, sizeof(associativity));
801 cur_index += 4;
803 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
804 (cur_index - int_buf) * sizeof(uint32_t));
805 out:
806 g_free(int_buf);
807 return ret;
810 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
811 target_ulong addr, target_ulong size,
812 bool cpu_update, bool memory_update)
814 void *fdt, *fdt_skel;
815 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
816 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
818 size -= sizeof(hdr);
820 /* Create sceleton */
821 fdt_skel = g_malloc0(size);
822 _FDT((fdt_create(fdt_skel, size)));
823 _FDT((fdt_begin_node(fdt_skel, "")));
824 _FDT((fdt_end_node(fdt_skel)));
825 _FDT((fdt_finish(fdt_skel)));
826 fdt = g_malloc0(size);
827 _FDT((fdt_open_into(fdt_skel, fdt, size)));
828 g_free(fdt_skel);
830 /* Fixup cpu nodes */
831 if (cpu_update) {
832 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
835 /* Generate memory nodes or ibm,dynamic-reconfiguration-memory node */
836 if (memory_update && smc->dr_lmb_enabled) {
837 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
840 /* Pack resulting tree */
841 _FDT((fdt_pack(fdt)));
843 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
844 trace_spapr_cas_failed(size);
845 return -1;
848 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
849 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
850 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
851 g_free(fdt);
853 return 0;
856 static void spapr_finalize_fdt(sPAPRMachineState *spapr,
857 hwaddr fdt_addr,
858 hwaddr rtas_addr,
859 hwaddr rtas_size)
861 MachineState *machine = MACHINE(qdev_get_machine());
862 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
863 const char *boot_device = machine->boot_order;
864 int ret, i;
865 size_t cb = 0;
866 char *bootlist;
867 void *fdt;
868 sPAPRPHBState *phb;
870 fdt = g_malloc(FDT_MAX_SIZE);
872 /* open out the base tree into a temp buffer for the final tweaks */
873 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
875 ret = spapr_populate_memory(spapr, fdt);
876 if (ret < 0) {
877 fprintf(stderr, "couldn't setup memory nodes in fdt\n");
878 exit(1);
881 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
882 if (ret < 0) {
883 fprintf(stderr, "couldn't setup vio devices in fdt\n");
884 exit(1);
887 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
888 ret = spapr_rng_populate_dt(fdt);
889 if (ret < 0) {
890 fprintf(stderr, "could not set up rng device in the fdt\n");
891 exit(1);
895 QLIST_FOREACH(phb, &spapr->phbs, list) {
896 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
899 if (ret < 0) {
900 fprintf(stderr, "couldn't setup PCI devices in fdt\n");
901 exit(1);
904 /* RTAS */
905 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
906 if (ret < 0) {
907 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
910 /* cpus */
911 spapr_populate_cpus_dt_node(fdt, spapr);
913 bootlist = get_boot_devices_list(&cb, true);
914 if (cb && bootlist) {
915 int offset = fdt_path_offset(fdt, "/chosen");
916 if (offset < 0) {
917 exit(1);
919 for (i = 0; i < cb; i++) {
920 if (bootlist[i] == '\n') {
921 bootlist[i] = ' ';
925 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
928 if (boot_device && strlen(boot_device)) {
929 int offset = fdt_path_offset(fdt, "/chosen");
931 if (offset < 0) {
932 exit(1);
934 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
937 if (!spapr->has_graphics) {
938 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
941 if (smc->dr_lmb_enabled) {
942 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
945 _FDT((fdt_pack(fdt)));
947 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
948 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
949 fdt_totalsize(fdt), FDT_MAX_SIZE);
950 exit(1);
953 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
954 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
956 g_free(bootlist);
957 g_free(fdt);
960 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
962 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
965 static void emulate_spapr_hypercall(PowerPCCPU *cpu)
967 CPUPPCState *env = &cpu->env;
969 if (msr_pr) {
970 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
971 env->gpr[3] = H_PRIVILEGE;
972 } else {
973 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
977 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
978 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
979 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
980 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
981 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
983 static void spapr_alloc_htab(sPAPRMachineState *spapr)
985 long shift;
986 int index;
988 /* allocate hash page table. For now we always make this 16mb,
989 * later we should probably make it scale to the size of guest
990 * RAM */
992 shift = kvmppc_reset_htab(spapr->htab_shift);
994 if (shift > 0) {
995 /* Kernel handles htab, we don't need to allocate one */
996 if (shift != spapr->htab_shift) {
997 error_setg(&error_abort, "Failed to allocate HTAB of requested size, try with smaller maxmem");
1000 spapr->htab_shift = shift;
1001 kvmppc_kern_htab = true;
1002 } else {
1003 /* Allocate htab */
1004 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr));
1006 /* And clear it */
1007 memset(spapr->htab, 0, HTAB_SIZE(spapr));
1009 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) {
1010 DIRTY_HPTE(HPTE(spapr->htab, index));
1016 * Clear HTAB entries during reset.
1018 * If host kernel has allocated HTAB, KVM_PPC_ALLOCATE_HTAB ioctl is
1019 * used to clear HTAB. Otherwise QEMU-allocated HTAB is cleared manually.
1021 static void spapr_reset_htab(sPAPRMachineState *spapr)
1023 long shift;
1024 int index;
1026 shift = kvmppc_reset_htab(spapr->htab_shift);
1027 if (shift > 0) {
1028 if (shift != spapr->htab_shift) {
1029 error_setg(&error_abort, "Requested HTAB allocation failed during reset");
1032 /* Tell readers to update their file descriptor */
1033 if (spapr->htab_fd >= 0) {
1034 spapr->htab_fd_stale = true;
1036 } else {
1037 memset(spapr->htab, 0, HTAB_SIZE(spapr));
1039 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) {
1040 DIRTY_HPTE(HPTE(spapr->htab, index));
1044 /* Update the RMA size if necessary */
1045 if (spapr->vrma_adjust) {
1046 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1047 spapr->htab_shift);
1051 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1053 bool matched = false;
1055 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1056 matched = true;
1059 if (!matched) {
1060 error_report("Device %s is not supported by this machine yet.",
1061 qdev_fw_name(DEVICE(sbdev)));
1062 exit(1);
1065 return 0;
1069 * A guest reset will cause spapr->htab_fd to become stale if being used.
1070 * Reopen the file descriptor to make sure the whole HTAB is properly read.
1072 static int spapr_check_htab_fd(sPAPRMachineState *spapr)
1074 int rc = 0;
1076 if (spapr->htab_fd_stale) {
1077 close(spapr->htab_fd);
1078 spapr->htab_fd = kvmppc_get_htab_fd(false);
1079 if (spapr->htab_fd < 0) {
1080 error_report("Unable to open fd for reading hash table from KVM: "
1081 "%s", strerror(errno));
1082 rc = -1;
1084 spapr->htab_fd_stale = false;
1087 return rc;
1090 static void ppc_spapr_reset(void)
1092 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1093 PowerPCCPU *first_ppc_cpu;
1094 uint32_t rtas_limit;
1096 /* Check for unknown sysbus devices */
1097 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1099 /* Reset the hash table & recalc the RMA */
1100 spapr_reset_htab(spapr);
1102 qemu_devices_reset();
1105 * We place the device tree and RTAS just below either the top of the RMA,
1106 * or just below 2GB, whichever is lowere, so that it can be
1107 * processed with 32-bit real mode code if necessary
1109 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1110 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1111 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1113 /* Load the fdt */
1114 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1115 spapr->rtas_size);
1117 /* Copy RTAS over */
1118 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1119 spapr->rtas_size);
1121 /* Set up the entry state */
1122 first_ppc_cpu = POWERPC_CPU(first_cpu);
1123 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1124 first_ppc_cpu->env.gpr[5] = 0;
1125 first_cpu->halted = 0;
1126 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1130 static void spapr_cpu_reset(void *opaque)
1132 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1133 PowerPCCPU *cpu = opaque;
1134 CPUState *cs = CPU(cpu);
1135 CPUPPCState *env = &cpu->env;
1137 cpu_reset(cs);
1139 /* All CPUs start halted. CPU0 is unhalted from the machine level
1140 * reset code and the rest are explicitly started up by the guest
1141 * using an RTAS call */
1142 cs->halted = 1;
1144 env->spr[SPR_HIOR] = 0;
1146 env->external_htab = (uint8_t *)spapr->htab;
1147 if (kvm_enabled() && !env->external_htab) {
1149 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte*
1150 * functions do the right thing.
1152 env->external_htab = (void *)1;
1154 env->htab_base = -1;
1156 * htab_mask is the mask used to normalize hash value to PTEG index.
1157 * htab_shift is log2 of hash table size.
1158 * We have 8 hpte per group, and each hpte is 16 bytes.
1159 * ie have 128 bytes per hpte entry.
1161 env->htab_mask = (1ULL << (spapr->htab_shift - 7)) - 1;
1162 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab |
1163 (spapr->htab_shift - 18);
1166 static void spapr_create_nvram(sPAPRMachineState *spapr)
1168 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1169 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1171 if (dinfo) {
1172 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(dinfo));
1175 qdev_init_nofail(dev);
1177 spapr->nvram = (struct sPAPRNVRAM *)dev;
1180 static void spapr_rtc_create(sPAPRMachineState *spapr)
1182 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1184 qdev_init_nofail(dev);
1185 spapr->rtc = dev;
1187 object_property_add_alias(qdev_get_machine(), "rtc-time",
1188 OBJECT(spapr->rtc), "date", NULL);
1191 /* Returns whether we want to use VGA or not */
1192 static int spapr_vga_init(PCIBus *pci_bus)
1194 switch (vga_interface_type) {
1195 case VGA_NONE:
1196 return false;
1197 case VGA_DEVICE:
1198 return true;
1199 case VGA_STD:
1200 case VGA_VIRTIO:
1201 return pci_vga_init(pci_bus) != NULL;
1202 default:
1203 fprintf(stderr, "This vga model is not supported,"
1204 "currently it only supports -vga std\n");
1205 exit(0);
1209 static int spapr_post_load(void *opaque, int version_id)
1211 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1212 int err = 0;
1214 /* In earlier versions, there was no separate qdev for the PAPR
1215 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1216 * So when migrating from those versions, poke the incoming offset
1217 * value into the RTC device */
1218 if (version_id < 3) {
1219 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1222 return err;
1225 static bool version_before_3(void *opaque, int version_id)
1227 return version_id < 3;
1230 static const VMStateDescription vmstate_spapr = {
1231 .name = "spapr",
1232 .version_id = 3,
1233 .minimum_version_id = 1,
1234 .post_load = spapr_post_load,
1235 .fields = (VMStateField[]) {
1236 /* used to be @next_irq */
1237 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1239 /* RTC offset */
1240 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1242 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1243 VMSTATE_END_OF_LIST()
1247 static int htab_save_setup(QEMUFile *f, void *opaque)
1249 sPAPRMachineState *spapr = opaque;
1251 /* "Iteration" header */
1252 qemu_put_be32(f, spapr->htab_shift);
1254 if (spapr->htab) {
1255 spapr->htab_save_index = 0;
1256 spapr->htab_first_pass = true;
1257 } else {
1258 assert(kvm_enabled());
1260 spapr->htab_fd = kvmppc_get_htab_fd(false);
1261 spapr->htab_fd_stale = false;
1262 if (spapr->htab_fd < 0) {
1263 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n",
1264 strerror(errno));
1265 return -1;
1270 return 0;
1273 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1274 int64_t max_ns)
1276 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1277 int index = spapr->htab_save_index;
1278 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1280 assert(spapr->htab_first_pass);
1282 do {
1283 int chunkstart;
1285 /* Consume invalid HPTEs */
1286 while ((index < htabslots)
1287 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1288 index++;
1289 CLEAN_HPTE(HPTE(spapr->htab, index));
1292 /* Consume valid HPTEs */
1293 chunkstart = index;
1294 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1295 && HPTE_VALID(HPTE(spapr->htab, index))) {
1296 index++;
1297 CLEAN_HPTE(HPTE(spapr->htab, index));
1300 if (index > chunkstart) {
1301 int n_valid = index - chunkstart;
1303 qemu_put_be32(f, chunkstart);
1304 qemu_put_be16(f, n_valid);
1305 qemu_put_be16(f, 0);
1306 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1307 HASH_PTE_SIZE_64 * n_valid);
1309 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1310 break;
1313 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1315 if (index >= htabslots) {
1316 assert(index == htabslots);
1317 index = 0;
1318 spapr->htab_first_pass = false;
1320 spapr->htab_save_index = index;
1323 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1324 int64_t max_ns)
1326 bool final = max_ns < 0;
1327 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1328 int examined = 0, sent = 0;
1329 int index = spapr->htab_save_index;
1330 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1332 assert(!spapr->htab_first_pass);
1334 do {
1335 int chunkstart, invalidstart;
1337 /* Consume non-dirty HPTEs */
1338 while ((index < htabslots)
1339 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1340 index++;
1341 examined++;
1344 chunkstart = index;
1345 /* Consume valid dirty HPTEs */
1346 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1347 && HPTE_DIRTY(HPTE(spapr->htab, index))
1348 && HPTE_VALID(HPTE(spapr->htab, index))) {
1349 CLEAN_HPTE(HPTE(spapr->htab, index));
1350 index++;
1351 examined++;
1354 invalidstart = index;
1355 /* Consume invalid dirty HPTEs */
1356 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1357 && HPTE_DIRTY(HPTE(spapr->htab, index))
1358 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1359 CLEAN_HPTE(HPTE(spapr->htab, index));
1360 index++;
1361 examined++;
1364 if (index > chunkstart) {
1365 int n_valid = invalidstart - chunkstart;
1366 int n_invalid = index - invalidstart;
1368 qemu_put_be32(f, chunkstart);
1369 qemu_put_be16(f, n_valid);
1370 qemu_put_be16(f, n_invalid);
1371 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1372 HASH_PTE_SIZE_64 * n_valid);
1373 sent += index - chunkstart;
1375 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1376 break;
1380 if (examined >= htabslots) {
1381 break;
1384 if (index >= htabslots) {
1385 assert(index == htabslots);
1386 index = 0;
1388 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1390 if (index >= htabslots) {
1391 assert(index == htabslots);
1392 index = 0;
1395 spapr->htab_save_index = index;
1397 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1400 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1401 #define MAX_KVM_BUF_SIZE 2048
1403 static int htab_save_iterate(QEMUFile *f, void *opaque)
1405 sPAPRMachineState *spapr = opaque;
1406 int rc = 0;
1408 /* Iteration header */
1409 qemu_put_be32(f, 0);
1411 if (!spapr->htab) {
1412 assert(kvm_enabled());
1414 rc = spapr_check_htab_fd(spapr);
1415 if (rc < 0) {
1416 return rc;
1419 rc = kvmppc_save_htab(f, spapr->htab_fd,
1420 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1421 if (rc < 0) {
1422 return rc;
1424 } else if (spapr->htab_first_pass) {
1425 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1426 } else {
1427 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1430 /* End marker */
1431 qemu_put_be32(f, 0);
1432 qemu_put_be16(f, 0);
1433 qemu_put_be16(f, 0);
1435 return rc;
1438 static int htab_save_complete(QEMUFile *f, void *opaque)
1440 sPAPRMachineState *spapr = opaque;
1442 /* Iteration header */
1443 qemu_put_be32(f, 0);
1445 if (!spapr->htab) {
1446 int rc;
1448 assert(kvm_enabled());
1450 rc = spapr_check_htab_fd(spapr);
1451 if (rc < 0) {
1452 return rc;
1455 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1);
1456 if (rc < 0) {
1457 return rc;
1459 close(spapr->htab_fd);
1460 spapr->htab_fd = -1;
1461 } else {
1462 htab_save_later_pass(f, spapr, -1);
1465 /* End marker */
1466 qemu_put_be32(f, 0);
1467 qemu_put_be16(f, 0);
1468 qemu_put_be16(f, 0);
1470 return 0;
1473 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1475 sPAPRMachineState *spapr = opaque;
1476 uint32_t section_hdr;
1477 int fd = -1;
1479 if (version_id < 1 || version_id > 1) {
1480 fprintf(stderr, "htab_load() bad version\n");
1481 return -EINVAL;
1484 section_hdr = qemu_get_be32(f);
1486 if (section_hdr) {
1487 /* First section, just the hash shift */
1488 if (spapr->htab_shift != section_hdr) {
1489 error_report("htab_shift mismatch: source %d target %d",
1490 section_hdr, spapr->htab_shift);
1491 return -EINVAL;
1493 return 0;
1496 if (!spapr->htab) {
1497 assert(kvm_enabled());
1499 fd = kvmppc_get_htab_fd(true);
1500 if (fd < 0) {
1501 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n",
1502 strerror(errno));
1506 while (true) {
1507 uint32_t index;
1508 uint16_t n_valid, n_invalid;
1510 index = qemu_get_be32(f);
1511 n_valid = qemu_get_be16(f);
1512 n_invalid = qemu_get_be16(f);
1514 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1515 /* End of Stream */
1516 break;
1519 if ((index + n_valid + n_invalid) >
1520 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1521 /* Bad index in stream */
1522 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) "
1523 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid,
1524 spapr->htab_shift);
1525 return -EINVAL;
1528 if (spapr->htab) {
1529 if (n_valid) {
1530 qemu_get_buffer(f, HPTE(spapr->htab, index),
1531 HASH_PTE_SIZE_64 * n_valid);
1533 if (n_invalid) {
1534 memset(HPTE(spapr->htab, index + n_valid), 0,
1535 HASH_PTE_SIZE_64 * n_invalid);
1537 } else {
1538 int rc;
1540 assert(fd >= 0);
1542 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1543 if (rc < 0) {
1544 return rc;
1549 if (!spapr->htab) {
1550 assert(fd >= 0);
1551 close(fd);
1554 return 0;
1557 static SaveVMHandlers savevm_htab_handlers = {
1558 .save_live_setup = htab_save_setup,
1559 .save_live_iterate = htab_save_iterate,
1560 .save_live_complete = htab_save_complete,
1561 .load_state = htab_load,
1564 static void spapr_boot_set(void *opaque, const char *boot_device,
1565 Error **errp)
1567 MachineState *machine = MACHINE(qdev_get_machine());
1568 machine->boot_order = g_strdup(boot_device);
1571 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu)
1573 CPUPPCState *env = &cpu->env;
1575 /* Set time-base frequency to 512 MHz */
1576 cpu_ppc_tb_init(env, TIMEBASE_FREQ);
1578 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
1579 * MSR[IP] should never be set.
1581 env->msr_mask &= ~(1 << 6);
1583 /* Tell KVM that we're in PAPR mode */
1584 if (kvm_enabled()) {
1585 kvmppc_set_papr(cpu);
1588 if (cpu->max_compat) {
1589 if (ppc_set_compat(cpu, cpu->max_compat) < 0) {
1590 exit(1);
1594 xics_cpu_setup(spapr->icp, cpu);
1596 qemu_register_reset(spapr_cpu_reset, cpu);
1600 * Reset routine for LMB DR devices.
1602 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1603 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1604 * when it walks all its children devices. LMB devices reset occurs
1605 * as part of spapr_ppc_reset().
1607 static void spapr_drc_reset(void *opaque)
1609 sPAPRDRConnector *drc = opaque;
1610 DeviceState *d = DEVICE(drc);
1612 if (d) {
1613 device_reset(d);
1617 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1619 MachineState *machine = MACHINE(spapr);
1620 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1621 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1622 int i;
1624 for (i = 0; i < nr_lmbs; i++) {
1625 sPAPRDRConnector *drc;
1626 uint64_t addr;
1628 addr = i * lmb_size + spapr->hotplug_memory.base;
1629 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1630 addr/lmb_size);
1631 qemu_register_reset(spapr_drc_reset, drc);
1636 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1637 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1638 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1640 static void spapr_validate_node_memory(MachineState *machine)
1642 int i;
1644 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE ||
1645 machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1646 error_report("Can't support memory configuration where RAM size "
1647 "0x" RAM_ADDR_FMT " or maxmem size "
1648 "0x" RAM_ADDR_FMT " isn't aligned to %llu MB",
1649 machine->ram_size, machine->maxram_size,
1650 SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
1651 exit(EXIT_FAILURE);
1654 for (i = 0; i < nb_numa_nodes; i++) {
1655 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1656 error_report("Can't support memory configuration where memory size"
1657 " %" PRIx64 " of node %d isn't aligned to %llu MB",
1658 numa_info[i].node_mem, i,
1659 SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
1660 exit(EXIT_FAILURE);
1665 /* pSeries LPAR / sPAPR hardware init */
1666 static void ppc_spapr_init(MachineState *machine)
1668 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1669 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1670 const char *kernel_filename = machine->kernel_filename;
1671 const char *kernel_cmdline = machine->kernel_cmdline;
1672 const char *initrd_filename = machine->initrd_filename;
1673 PowerPCCPU *cpu;
1674 PCIHostState *phb;
1675 int i;
1676 MemoryRegion *sysmem = get_system_memory();
1677 MemoryRegion *ram = g_new(MemoryRegion, 1);
1678 MemoryRegion *rma_region;
1679 void *rma = NULL;
1680 hwaddr rma_alloc_size;
1681 hwaddr node0_size = spapr_node0_size();
1682 uint32_t initrd_base = 0;
1683 long kernel_size = 0, initrd_size = 0;
1684 long load_limit, fw_size;
1685 bool kernel_le = false;
1686 char *filename;
1688 msi_supported = true;
1690 QLIST_INIT(&spapr->phbs);
1692 cpu_ppc_hypercall = emulate_spapr_hypercall;
1694 /* Allocate RMA if necessary */
1695 rma_alloc_size = kvmppc_alloc_rma(&rma);
1697 if (rma_alloc_size == -1) {
1698 error_report("Unable to create RMA");
1699 exit(1);
1702 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1703 spapr->rma_size = rma_alloc_size;
1704 } else {
1705 spapr->rma_size = node0_size;
1707 /* With KVM, we don't actually know whether KVM supports an
1708 * unbounded RMA (PR KVM) or is limited by the hash table size
1709 * (HV KVM using VRMA), so we always assume the latter
1711 * In that case, we also limit the initial allocations for RTAS
1712 * etc... to 256M since we have no way to know what the VRMA size
1713 * is going to be as it depends on the size of the hash table
1714 * isn't determined yet.
1716 if (kvm_enabled()) {
1717 spapr->vrma_adjust = 1;
1718 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1722 if (spapr->rma_size > node0_size) {
1723 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n",
1724 spapr->rma_size);
1725 exit(1);
1728 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1729 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1731 /* We aim for a hash table of size 1/128 the size of RAM. The
1732 * normal rule of thumb is 1/64 the size of RAM, but that's much
1733 * more than needed for the Linux guests we support. */
1734 spapr->htab_shift = 18; /* Minimum architected size */
1735 while (spapr->htab_shift <= 46) {
1736 if ((1ULL << (spapr->htab_shift + 7)) >= machine->maxram_size) {
1737 break;
1739 spapr->htab_shift++;
1741 spapr_alloc_htab(spapr);
1743 /* Set up Interrupt Controller before we create the VCPUs */
1744 spapr->icp = xics_system_init(machine,
1745 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(),
1746 smp_threads),
1747 XICS_IRQS);
1749 if (smc->dr_lmb_enabled) {
1750 spapr_validate_node_memory(machine);
1753 /* init CPUs */
1754 if (machine->cpu_model == NULL) {
1755 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
1757 for (i = 0; i < smp_cpus; i++) {
1758 cpu = cpu_ppc_init(machine->cpu_model);
1759 if (cpu == NULL) {
1760 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
1761 exit(1);
1763 spapr_cpu_init(spapr, cpu);
1766 if (kvm_enabled()) {
1767 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1768 kvmppc_enable_logical_ci_hcalls();
1769 kvmppc_enable_set_mode_hcall();
1772 /* allocate RAM */
1773 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
1774 machine->ram_size);
1775 memory_region_add_subregion(sysmem, 0, ram);
1777 if (rma_alloc_size && rma) {
1778 rma_region = g_new(MemoryRegion, 1);
1779 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1780 rma_alloc_size, rma);
1781 vmstate_register_ram_global(rma_region);
1782 memory_region_add_subregion(sysmem, 0, rma_region);
1785 /* initialize hotplug memory address space */
1786 if (machine->ram_size < machine->maxram_size) {
1787 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1789 if (machine->ram_slots > SPAPR_MAX_RAM_SLOTS) {
1790 error_report("Specified number of memory slots %"PRIu64" exceeds max supported %d\n",
1791 machine->ram_slots, SPAPR_MAX_RAM_SLOTS);
1792 exit(EXIT_FAILURE);
1795 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1796 SPAPR_HOTPLUG_MEM_ALIGN);
1797 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1798 "hotplug-memory", hotplug_mem_size);
1799 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1800 &spapr->hotplug_memory.mr);
1803 if (smc->dr_lmb_enabled) {
1804 spapr_create_lmb_dr_connectors(spapr);
1807 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1808 if (!filename) {
1809 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1810 exit(1);
1812 spapr->rtas_size = get_image_size(filename);
1813 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1814 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
1815 error_report("Could not load LPAR rtas '%s'", filename);
1816 exit(1);
1818 if (spapr->rtas_size > RTAS_MAX_SIZE) {
1819 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1820 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
1821 exit(1);
1823 g_free(filename);
1825 /* Set up EPOW events infrastructure */
1826 spapr_events_init(spapr);
1828 /* Set up the RTC RTAS interfaces */
1829 spapr_rtc_create(spapr);
1831 /* Set up VIO bus */
1832 spapr->vio_bus = spapr_vio_bus_init();
1834 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1835 if (serial_hds[i]) {
1836 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1840 /* We always have at least the nvram device on VIO */
1841 spapr_create_nvram(spapr);
1843 /* Set up PCI */
1844 spapr_pci_rtas_init();
1846 phb = spapr_create_phb(spapr, 0);
1848 for (i = 0; i < nb_nics; i++) {
1849 NICInfo *nd = &nd_table[i];
1851 if (!nd->model) {
1852 nd->model = g_strdup("ibmveth");
1855 if (strcmp(nd->model, "ibmveth") == 0) {
1856 spapr_vlan_create(spapr->vio_bus, nd);
1857 } else {
1858 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1862 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1863 spapr_vscsi_create(spapr->vio_bus);
1866 /* Graphics */
1867 if (spapr_vga_init(phb->bus)) {
1868 spapr->has_graphics = true;
1869 machine->usb |= defaults_enabled() && !machine->usb_disabled;
1872 if (machine->usb) {
1873 pci_create_simple(phb->bus, -1, "pci-ohci");
1875 if (spapr->has_graphics) {
1876 USBBus *usb_bus = usb_bus_find(-1);
1878 usb_create_simple(usb_bus, "usb-kbd");
1879 usb_create_simple(usb_bus, "usb-mouse");
1883 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
1884 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
1885 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
1886 exit(1);
1889 if (kernel_filename) {
1890 uint64_t lowaddr = 0;
1892 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
1893 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 0);
1894 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
1895 kernel_size = load_elf(kernel_filename,
1896 translate_kernel_address, NULL,
1897 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE, 0);
1898 kernel_le = kernel_size > 0;
1900 if (kernel_size < 0) {
1901 fprintf(stderr, "qemu: error loading %s: %s\n",
1902 kernel_filename, load_elf_strerror(kernel_size));
1903 exit(1);
1906 /* load initrd */
1907 if (initrd_filename) {
1908 /* Try to locate the initrd in the gap between the kernel
1909 * and the firmware. Add a bit of space just in case
1911 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
1912 initrd_size = load_image_targphys(initrd_filename, initrd_base,
1913 load_limit - initrd_base);
1914 if (initrd_size < 0) {
1915 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
1916 initrd_filename);
1917 exit(1);
1919 } else {
1920 initrd_base = 0;
1921 initrd_size = 0;
1925 if (bios_name == NULL) {
1926 bios_name = FW_FILE_NAME;
1928 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1929 if (!filename) {
1930 error_report("Could not find LPAR firmware '%s'", bios_name);
1931 exit(1);
1933 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
1934 if (fw_size <= 0) {
1935 error_report("Could not load LPAR firmware '%s'", filename);
1936 exit(1);
1938 g_free(filename);
1940 /* FIXME: Should register things through the MachineState's qdev
1941 * interface, this is a legacy from the sPAPREnvironment structure
1942 * which predated MachineState but had a similar function */
1943 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
1944 register_savevm_live(NULL, "spapr/htab", -1, 1,
1945 &savevm_htab_handlers, spapr);
1947 /* Prepare the device tree */
1948 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
1949 kernel_size, kernel_le,
1950 kernel_cmdline,
1951 spapr->check_exception_irq);
1952 assert(spapr->fdt_skel != NULL);
1954 /* used by RTAS */
1955 QTAILQ_INIT(&spapr->ccs_list);
1956 qemu_register_reset(spapr_ccs_reset_hook, spapr);
1958 qemu_register_boot_set(spapr_boot_set, spapr);
1961 static int spapr_kvm_type(const char *vm_type)
1963 if (!vm_type) {
1964 return 0;
1967 if (!strcmp(vm_type, "HV")) {
1968 return 1;
1971 if (!strcmp(vm_type, "PR")) {
1972 return 2;
1975 error_report("Unknown kvm-type specified '%s'", vm_type);
1976 exit(1);
1980 * Implementation of an interface to adjust firmware path
1981 * for the bootindex property handling.
1983 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
1984 DeviceState *dev)
1986 #define CAST(type, obj, name) \
1987 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
1988 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
1989 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
1991 if (d) {
1992 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
1993 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
1994 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
1996 if (spapr) {
1998 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
1999 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2000 * in the top 16 bits of the 64-bit LUN
2002 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2003 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2004 (uint64_t)id << 48);
2005 } else if (virtio) {
2007 * We use SRP luns of the form 01000000 | (target << 8) | lun
2008 * in the top 32 bits of the 64-bit LUN
2009 * Note: the quote above is from SLOF and it is wrong,
2010 * the actual binding is:
2011 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2013 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2014 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2015 (uint64_t)id << 32);
2016 } else if (usb) {
2018 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2019 * in the top 32 bits of the 64-bit LUN
2021 unsigned usb_port = atoi(usb->port->path);
2022 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2023 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2024 (uint64_t)id << 32);
2028 if (phb) {
2029 /* Replace "pci" with "pci@800000020000000" */
2030 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2033 return NULL;
2036 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2038 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2040 return g_strdup(spapr->kvm_type);
2043 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2045 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2047 g_free(spapr->kvm_type);
2048 spapr->kvm_type = g_strdup(value);
2051 static void spapr_machine_initfn(Object *obj)
2053 object_property_add_str(obj, "kvm-type",
2054 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2055 object_property_set_description(obj, "kvm-type",
2056 "Specifies the KVM virtualization mode (HV, PR)",
2057 NULL);
2060 static void ppc_cpu_do_nmi_on_cpu(void *arg)
2062 CPUState *cs = arg;
2064 cpu_synchronize_state(cs);
2065 ppc_cpu_do_system_reset(cs);
2068 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2070 CPUState *cs;
2072 CPU_FOREACH(cs) {
2073 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs);
2077 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2078 uint32_t node, Error **errp)
2080 sPAPRDRConnector *drc;
2081 sPAPRDRConnectorClass *drck;
2082 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2083 int i, fdt_offset, fdt_size;
2084 void *fdt;
2087 * Check for DRC connectors and send hotplug notification to the
2088 * guest only in case of hotplugged memory. This allows cold plugged
2089 * memory to be specified at boot time.
2091 if (!dev->hotplugged) {
2092 return;
2095 for (i = 0; i < nr_lmbs; i++) {
2096 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2097 addr/SPAPR_MEMORY_BLOCK_SIZE);
2098 g_assert(drc);
2100 fdt = create_device_tree(&fdt_size);
2101 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2102 SPAPR_MEMORY_BLOCK_SIZE);
2104 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2105 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2106 addr += SPAPR_MEMORY_BLOCK_SIZE;
2108 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2111 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2112 uint32_t node, Error **errp)
2114 Error *local_err = NULL;
2115 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2116 PCDIMMDevice *dimm = PC_DIMM(dev);
2117 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2118 MemoryRegion *mr = ddc->get_memory_region(dimm);
2119 uint64_t align = memory_region_get_alignment(mr);
2120 uint64_t size = memory_region_size(mr);
2121 uint64_t addr;
2123 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2124 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2125 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2126 goto out;
2129 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, false, &local_err);
2130 if (local_err) {
2131 goto out;
2134 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2135 if (local_err) {
2136 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2137 goto out;
2140 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2142 out:
2143 error_propagate(errp, local_err);
2146 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2147 DeviceState *dev, Error **errp)
2149 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2151 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2152 int node;
2154 if (!smc->dr_lmb_enabled) {
2155 error_setg(errp, "Memory hotplug not supported for this machine");
2156 return;
2158 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2159 if (*errp) {
2160 return;
2164 * Currently PowerPC kernel doesn't allow hot-adding memory to
2165 * memory-less node, but instead will silently add the memory
2166 * to the first node that has some memory. This causes two
2167 * unexpected behaviours for the user.
2169 * - Memory gets hotplugged to a different node than what the user
2170 * specified.
2171 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2172 * to memory-less node, a reboot will set things accordingly
2173 * and the previously hotplugged memory now ends in the right node.
2174 * This appears as if some memory moved from one node to another.
2176 * So until kernel starts supporting memory hotplug to memory-less
2177 * nodes, just prevent such attempts upfront in QEMU.
2179 if (nb_numa_nodes && !numa_info[node].node_mem) {
2180 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2181 node);
2182 return;
2185 spapr_memory_plug(hotplug_dev, dev, node, errp);
2189 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2190 DeviceState *dev, Error **errp)
2192 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2193 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2197 static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine,
2198 DeviceState *dev)
2200 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2201 return HOTPLUG_HANDLER(machine);
2203 return NULL;
2206 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2208 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2209 * socket means much for the paravirtualized PAPR platform) */
2210 return cpu_index / smp_threads / smp_cores;
2213 static void spapr_machine_class_init(ObjectClass *oc, void *data)
2215 MachineClass *mc = MACHINE_CLASS(oc);
2216 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2217 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2218 NMIClass *nc = NMI_CLASS(oc);
2219 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2221 mc->init = ppc_spapr_init;
2222 mc->reset = ppc_spapr_reset;
2223 mc->block_default_type = IF_SCSI;
2224 mc->max_cpus = MAX_CPUMASK_BITS;
2225 mc->no_parallel = 1;
2226 mc->default_boot_order = "";
2227 mc->default_ram_size = 512 * M_BYTE;
2228 mc->kvm_type = spapr_kvm_type;
2229 mc->has_dynamic_sysbus = true;
2230 mc->pci_allow_0_address = true;
2231 mc->get_hotplug_handler = spapr_get_hotpug_handler;
2232 hc->plug = spapr_machine_device_plug;
2233 hc->unplug = spapr_machine_device_unplug;
2234 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2236 smc->dr_lmb_enabled = false;
2237 fwc->get_dev_path = spapr_get_fw_dev_path;
2238 nc->nmi_monitor_handler = spapr_nmi;
2241 static const TypeInfo spapr_machine_info = {
2242 .name = TYPE_SPAPR_MACHINE,
2243 .parent = TYPE_MACHINE,
2244 .abstract = true,
2245 .instance_size = sizeof(sPAPRMachineState),
2246 .instance_init = spapr_machine_initfn,
2247 .class_size = sizeof(sPAPRMachineClass),
2248 .class_init = spapr_machine_class_init,
2249 .interfaces = (InterfaceInfo[]) {
2250 { TYPE_FW_PATH_PROVIDER },
2251 { TYPE_NMI },
2252 { TYPE_HOTPLUG_HANDLER },
2257 #define SPAPR_COMPAT_2_3 \
2258 HW_COMPAT_2_3 \
2260 .driver = "spapr-pci-host-bridge",\
2261 .property = "dynamic-reconfiguration",\
2262 .value = "off",\
2265 #define SPAPR_COMPAT_2_2 \
2266 SPAPR_COMPAT_2_3 \
2267 HW_COMPAT_2_2 \
2269 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2270 .property = "mem_win_size",\
2271 .value = "0x20000000",\
2274 #define SPAPR_COMPAT_2_1 \
2275 SPAPR_COMPAT_2_2 \
2276 HW_COMPAT_2_1
2278 static void spapr_compat_2_3(Object *obj)
2280 savevm_skip_section_footers();
2281 global_state_set_optional();
2284 static void spapr_compat_2_2(Object *obj)
2286 spapr_compat_2_3(obj);
2289 static void spapr_compat_2_1(Object *obj)
2291 spapr_compat_2_2(obj);
2294 static void spapr_machine_2_3_instance_init(Object *obj)
2296 spapr_compat_2_3(obj);
2297 spapr_machine_initfn(obj);
2300 static void spapr_machine_2_2_instance_init(Object *obj)
2302 spapr_compat_2_2(obj);
2303 spapr_machine_initfn(obj);
2306 static void spapr_machine_2_1_instance_init(Object *obj)
2308 spapr_compat_2_1(obj);
2309 spapr_machine_initfn(obj);
2312 static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data)
2314 MachineClass *mc = MACHINE_CLASS(oc);
2315 static GlobalProperty compat_props[] = {
2316 SPAPR_COMPAT_2_1
2317 { /* end of list */ }
2320 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1";
2321 mc->compat_props = compat_props;
2324 static const TypeInfo spapr_machine_2_1_info = {
2325 .name = MACHINE_TYPE_NAME("pseries-2.1"),
2326 .parent = TYPE_SPAPR_MACHINE,
2327 .class_init = spapr_machine_2_1_class_init,
2328 .instance_init = spapr_machine_2_1_instance_init,
2331 static void spapr_machine_2_2_class_init(ObjectClass *oc, void *data)
2333 static GlobalProperty compat_props[] = {
2334 SPAPR_COMPAT_2_2
2335 { /* end of list */ }
2337 MachineClass *mc = MACHINE_CLASS(oc);
2339 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.2";
2340 mc->compat_props = compat_props;
2343 static const TypeInfo spapr_machine_2_2_info = {
2344 .name = MACHINE_TYPE_NAME("pseries-2.2"),
2345 .parent = TYPE_SPAPR_MACHINE,
2346 .class_init = spapr_machine_2_2_class_init,
2347 .instance_init = spapr_machine_2_2_instance_init,
2350 static void spapr_machine_2_3_class_init(ObjectClass *oc, void *data)
2352 static GlobalProperty compat_props[] = {
2353 SPAPR_COMPAT_2_3
2354 { /* end of list */ }
2356 MachineClass *mc = MACHINE_CLASS(oc);
2358 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.3";
2359 mc->compat_props = compat_props;
2362 static const TypeInfo spapr_machine_2_3_info = {
2363 .name = MACHINE_TYPE_NAME("pseries-2.3"),
2364 .parent = TYPE_SPAPR_MACHINE,
2365 .class_init = spapr_machine_2_3_class_init,
2366 .instance_init = spapr_machine_2_3_instance_init,
2369 static void spapr_machine_2_4_class_init(ObjectClass *oc, void *data)
2371 MachineClass *mc = MACHINE_CLASS(oc);
2373 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.4";
2374 mc->alias = "pseries";
2375 mc->is_default = 0;
2378 static const TypeInfo spapr_machine_2_4_info = {
2379 .name = MACHINE_TYPE_NAME("pseries-2.4"),
2380 .parent = TYPE_SPAPR_MACHINE,
2381 .class_init = spapr_machine_2_4_class_init,
2384 static void spapr_machine_2_5_class_init(ObjectClass *oc, void *data)
2386 MachineClass *mc = MACHINE_CLASS(oc);
2387 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2389 mc->name = "pseries-2.5";
2390 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.5";
2391 mc->alias = "pseries";
2392 mc->is_default = 1;
2393 smc->dr_lmb_enabled = true;
2396 static const TypeInfo spapr_machine_2_5_info = {
2397 .name = MACHINE_TYPE_NAME("pseries-2.5"),
2398 .parent = TYPE_SPAPR_MACHINE,
2399 .class_init = spapr_machine_2_5_class_init,
2402 static void spapr_machine_register_types(void)
2404 type_register_static(&spapr_machine_info);
2405 type_register_static(&spapr_machine_2_1_info);
2406 type_register_static(&spapr_machine_2_2_info);
2407 type_register_static(&spapr_machine_2_3_info);
2408 type_register_static(&spapr_machine_2_4_info);
2409 type_register_static(&spapr_machine_2_5_info);
2412 type_init(spapr_machine_register_types)