2 * Copyright (c) 2018, Impinj, Inc.
4 * i.MX7 SoC definitions
6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
8 * Based on hw/arm/fsl-imx6.c
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu-common.h"
24 #include "hw/arm/fsl-imx7.h"
25 #include "hw/misc/unimp.h"
26 #include "sysemu/sysemu.h"
27 #include "qemu/error-report.h"
31 static void fsl_imx7_init(Object
*obj
)
33 FslIMX7State
*s
= FSL_IMX7(obj
);
38 for (i
= 0; i
< MIN(smp_cpus
, FSL_IMX7_NUM_CPUS
); i
++) {
39 snprintf(name
, NAME_SIZE
, "cpu%d", i
);
40 object_initialize_child(obj
, name
, &s
->cpu
[i
], sizeof(s
->cpu
[i
]),
41 ARM_CPU_TYPE_NAME("cortex-a7"), &error_abort
,
48 sysbus_init_child_obj(obj
, "a7mpcore", &s
->a7mpcore
, sizeof(s
->a7mpcore
),
54 for (i
= 0; i
< FSL_IMX7_NUM_GPIOS
; i
++) {
55 snprintf(name
, NAME_SIZE
, "gpio%d", i
);
56 sysbus_init_child_obj(obj
, name
, &s
->gpio
[i
], sizeof(s
->gpio
[i
]),
63 for (i
= 0; i
< FSL_IMX7_NUM_GPTS
; i
++) {
64 snprintf(name
, NAME_SIZE
, "gpt%d", i
);
65 sysbus_init_child_obj(obj
, name
, &s
->gpt
[i
], sizeof(s
->gpt
[i
]),
72 sysbus_init_child_obj(obj
, "ccm", &s
->ccm
, sizeof(s
->ccm
), TYPE_IMX7_CCM
);
77 sysbus_init_child_obj(obj
, "analog", &s
->analog
, sizeof(s
->analog
),
83 sysbus_init_child_obj(obj
, "gpcv2", &s
->gpcv2
, sizeof(s
->gpcv2
),
86 for (i
= 0; i
< FSL_IMX7_NUM_ECSPIS
; i
++) {
87 snprintf(name
, NAME_SIZE
, "spi%d", i
+ 1);
88 sysbus_init_child_obj(obj
, name
, &s
->spi
[i
], sizeof(s
->spi
[i
]),
93 for (i
= 0; i
< FSL_IMX7_NUM_I2CS
; i
++) {
94 snprintf(name
, NAME_SIZE
, "i2c%d", i
+ 1);
95 sysbus_init_child_obj(obj
, name
, &s
->i2c
[i
], sizeof(s
->i2c
[i
]),
102 for (i
= 0; i
< FSL_IMX7_NUM_UARTS
; i
++) {
103 snprintf(name
, NAME_SIZE
, "uart%d", i
);
104 sysbus_init_child_obj(obj
, name
, &s
->uart
[i
], sizeof(s
->uart
[i
]),
111 for (i
= 0; i
< FSL_IMX7_NUM_ETHS
; i
++) {
112 snprintf(name
, NAME_SIZE
, "eth%d", i
);
113 sysbus_init_child_obj(obj
, name
, &s
->eth
[i
], sizeof(s
->eth
[i
]),
120 for (i
= 0; i
< FSL_IMX7_NUM_USDHCS
; i
++) {
121 snprintf(name
, NAME_SIZE
, "usdhc%d", i
);
122 sysbus_init_child_obj(obj
, name
, &s
->usdhc
[i
], sizeof(s
->usdhc
[i
]),
129 sysbus_init_child_obj(obj
, "snvs", &s
->snvs
, sizeof(s
->snvs
),
135 for (i
= 0; i
< FSL_IMX7_NUM_WDTS
; i
++) {
136 snprintf(name
, NAME_SIZE
, "wdt%d", i
);
137 sysbus_init_child_obj(obj
, name
, &s
->wdt
[i
], sizeof(s
->wdt
[i
]),
144 sysbus_init_child_obj(obj
, "gpr", &s
->gpr
, sizeof(s
->gpr
), TYPE_IMX7_GPR
);
146 sysbus_init_child_obj(obj
, "pcie", &s
->pcie
, sizeof(s
->pcie
),
147 TYPE_DESIGNWARE_PCIE_HOST
);
149 for (i
= 0; i
< FSL_IMX7_NUM_USBS
; i
++) {
150 snprintf(name
, NAME_SIZE
, "usb%d", i
);
151 sysbus_init_child_obj(obj
, name
, &s
->usb
[i
], sizeof(s
->usb
[i
]),
156 static void fsl_imx7_realize(DeviceState
*dev
, Error
**errp
)
158 FslIMX7State
*s
= FSL_IMX7(dev
);
162 char name
[NAME_SIZE
];
164 if (smp_cpus
> FSL_IMX7_NUM_CPUS
) {
165 error_setg(errp
, "%s: Only %d CPUs are supported (%d requested)",
166 TYPE_FSL_IMX7
, FSL_IMX7_NUM_CPUS
, smp_cpus
);
170 for (i
= 0; i
< smp_cpus
; i
++) {
171 o
= OBJECT(&s
->cpu
[i
]);
173 object_property_set_int(o
, QEMU_PSCI_CONDUIT_SMC
,
174 "psci-conduit", &error_abort
);
176 /* On uniprocessor, the CBAR is set to 0 */
178 object_property_set_int(o
, FSL_IMX7_A7MPCORE_ADDR
,
179 "reset-cbar", &error_abort
);
183 /* Secondary CPUs start in PSCI powered-down state */
184 object_property_set_bool(o
, true,
185 "start-powered-off", &error_abort
);
188 object_property_set_bool(o
, true, "realized", &error_abort
);
194 object_property_set_int(OBJECT(&s
->a7mpcore
), smp_cpus
, "num-cpu",
196 object_property_set_int(OBJECT(&s
->a7mpcore
),
197 FSL_IMX7_MAX_IRQ
+ GIC_INTERNAL
,
198 "num-irq", &error_abort
);
200 object_property_set_bool(OBJECT(&s
->a7mpcore
), true, "realized",
202 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->a7mpcore
), 0, FSL_IMX7_A7MPCORE_ADDR
);
204 for (i
= 0; i
< smp_cpus
; i
++) {
205 SysBusDevice
*sbd
= SYS_BUS_DEVICE(&s
->a7mpcore
);
206 DeviceState
*d
= DEVICE(qemu_get_cpu(i
));
208 irq
= qdev_get_gpio_in(d
, ARM_CPU_IRQ
);
209 sysbus_connect_irq(sbd
, i
, irq
);
210 irq
= qdev_get_gpio_in(d
, ARM_CPU_FIQ
);
211 sysbus_connect_irq(sbd
, i
+ smp_cpus
, irq
);
217 create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR
,
223 for (i
= 0; i
< FSL_IMX7_NUM_GPTS
; i
++) {
224 static const hwaddr FSL_IMX7_GPTn_ADDR
[FSL_IMX7_NUM_GPTS
] = {
231 s
->gpt
[i
].ccm
= IMX_CCM(&s
->ccm
);
232 object_property_set_bool(OBJECT(&s
->gpt
[i
]), true, "realized",
234 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpt
[i
]), 0, FSL_IMX7_GPTn_ADDR
[i
]);
237 for (i
= 0; i
< FSL_IMX7_NUM_GPIOS
; i
++) {
238 static const hwaddr FSL_IMX7_GPIOn_ADDR
[FSL_IMX7_NUM_GPIOS
] = {
248 object_property_set_bool(OBJECT(&s
->gpio
[i
]), true, "realized",
250 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0, FSL_IMX7_GPIOn_ADDR
[i
]);
254 * IOMUXC and IOMUXC_LPSR
256 for (i
= 0; i
< FSL_IMX7_NUM_IOMUXCS
; i
++) {
257 static const hwaddr FSL_IMX7_IOMUXCn_ADDR
[FSL_IMX7_NUM_IOMUXCS
] = {
258 FSL_IMX7_IOMUXC_ADDR
,
259 FSL_IMX7_IOMUXC_LPSR_ADDR
,
262 snprintf(name
, NAME_SIZE
, "iomuxc%d", i
);
263 create_unimplemented_device(name
, FSL_IMX7_IOMUXCn_ADDR
[i
],
264 FSL_IMX7_IOMUXCn_SIZE
);
270 object_property_set_bool(OBJECT(&s
->ccm
), true, "realized", &error_abort
);
271 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ccm
), 0, FSL_IMX7_CCM_ADDR
);
276 object_property_set_bool(OBJECT(&s
->analog
), true, "realized",
278 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->analog
), 0, FSL_IMX7_ANALOG_ADDR
);
283 object_property_set_bool(OBJECT(&s
->gpcv2
), true,
284 "realized", &error_abort
);
285 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpcv2
), 0, FSL_IMX7_GPC_ADDR
);
287 /* Initialize all ECSPI */
288 for (i
= 0; i
< FSL_IMX7_NUM_ECSPIS
; i
++) {
289 static const hwaddr FSL_IMX7_SPIn_ADDR
[FSL_IMX7_NUM_ECSPIS
] = {
290 FSL_IMX7_ECSPI1_ADDR
,
291 FSL_IMX7_ECSPI2_ADDR
,
292 FSL_IMX7_ECSPI3_ADDR
,
293 FSL_IMX7_ECSPI4_ADDR
,
296 static const int FSL_IMX7_SPIn_IRQ
[FSL_IMX7_NUM_ECSPIS
] = {
303 /* Initialize the SPI */
304 object_property_set_bool(OBJECT(&s
->spi
[i
]), true, "realized",
306 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
307 FSL_IMX7_SPIn_ADDR
[i
]);
308 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
309 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
310 FSL_IMX7_SPIn_IRQ
[i
]));
313 for (i
= 0; i
< FSL_IMX7_NUM_I2CS
; i
++) {
314 static const hwaddr FSL_IMX7_I2Cn_ADDR
[FSL_IMX7_NUM_I2CS
] = {
321 static const int FSL_IMX7_I2Cn_IRQ
[FSL_IMX7_NUM_I2CS
] = {
328 object_property_set_bool(OBJECT(&s
->i2c
[i
]), true, "realized",
330 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0, FSL_IMX7_I2Cn_ADDR
[i
]);
332 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0,
333 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
334 FSL_IMX7_I2Cn_IRQ
[i
]));
340 for (i
= 0; i
< FSL_IMX7_NUM_UARTS
; i
++) {
341 static const hwaddr FSL_IMX7_UARTn_ADDR
[FSL_IMX7_NUM_UARTS
] = {
351 static const int FSL_IMX7_UARTn_IRQ
[FSL_IMX7_NUM_UARTS
] = {
362 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", serial_hd(i
));
364 object_property_set_bool(OBJECT(&s
->uart
[i
]), true, "realized",
367 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, FSL_IMX7_UARTn_ADDR
[i
]);
369 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_UARTn_IRQ
[i
]);
370 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, irq
);
376 for (i
= 0; i
< FSL_IMX7_NUM_ETHS
; i
++) {
377 static const hwaddr FSL_IMX7_ENETn_ADDR
[FSL_IMX7_NUM_ETHS
] = {
382 object_property_set_uint(OBJECT(&s
->eth
[i
]), FSL_IMX7_ETH_NUM_TX_RINGS
,
383 "tx-ring-num", &error_abort
);
384 qdev_set_nic_properties(DEVICE(&s
->eth
[i
]), &nd_table
[i
]);
385 object_property_set_bool(OBJECT(&s
->eth
[i
]), true, "realized",
388 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->eth
[i
]), 0, FSL_IMX7_ENETn_ADDR
[i
]);
390 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_ENET_IRQ(i
, 0));
391 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->eth
[i
]), 0, irq
);
392 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_ENET_IRQ(i
, 3));
393 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->eth
[i
]), 1, irq
);
399 for (i
= 0; i
< FSL_IMX7_NUM_USDHCS
; i
++) {
400 static const hwaddr FSL_IMX7_USDHCn_ADDR
[FSL_IMX7_NUM_USDHCS
] = {
401 FSL_IMX7_USDHC1_ADDR
,
402 FSL_IMX7_USDHC2_ADDR
,
403 FSL_IMX7_USDHC3_ADDR
,
406 static const int FSL_IMX7_USDHCn_IRQ
[FSL_IMX7_NUM_USDHCS
] = {
412 object_property_set_bool(OBJECT(&s
->usdhc
[i
]), true, "realized",
415 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->usdhc
[i
]), 0,
416 FSL_IMX7_USDHCn_ADDR
[i
]);
418 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_USDHCn_IRQ
[i
]);
419 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->usdhc
[i
]), 0, irq
);
425 object_property_set_bool(OBJECT(&s
->snvs
), true, "realized", &error_abort
);
426 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->snvs
), 0, FSL_IMX7_SNVS_ADDR
);
431 create_unimplemented_device("src", FSL_IMX7_SRC_ADDR
, FSL_IMX7_SRC_SIZE
);
436 for (i
= 0; i
< FSL_IMX7_NUM_WDTS
; i
++) {
437 static const hwaddr FSL_IMX7_WDOGn_ADDR
[FSL_IMX7_NUM_WDTS
] = {
444 object_property_set_bool(OBJECT(&s
->wdt
[i
]), true, "realized",
447 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0, FSL_IMX7_WDOGn_ADDR
[i
]);
453 create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR
, FSL_IMX7_SDMA_SIZE
);
456 object_property_set_bool(OBJECT(&s
->gpr
), true, "realized",
458 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpr
), 0, FSL_IMX7_GPR_ADDR
);
460 object_property_set_bool(OBJECT(&s
->pcie
), true,
461 "realized", &error_abort
);
462 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->pcie
), 0, FSL_IMX7_PCIE_REG_ADDR
);
464 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_PCI_INTA_IRQ
);
465 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->pcie
), 0, irq
);
466 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_PCI_INTB_IRQ
);
467 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->pcie
), 1, irq
);
468 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_PCI_INTC_IRQ
);
469 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->pcie
), 2, irq
);
470 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_PCI_INTD_IRQ
);
471 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->pcie
), 3, irq
);
474 for (i
= 0; i
< FSL_IMX7_NUM_USBS
; i
++) {
475 static const hwaddr FSL_IMX7_USBMISCn_ADDR
[FSL_IMX7_NUM_USBS
] = {
476 FSL_IMX7_USBMISC1_ADDR
,
477 FSL_IMX7_USBMISC2_ADDR
,
478 FSL_IMX7_USBMISC3_ADDR
,
481 static const hwaddr FSL_IMX7_USBn_ADDR
[FSL_IMX7_NUM_USBS
] = {
487 static const int FSL_IMX7_USBn_IRQ
[FSL_IMX7_NUM_USBS
] = {
493 object_property_set_bool(OBJECT(&s
->usb
[i
]), true, "realized",
495 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->usb
[i
]), 0,
496 FSL_IMX7_USBn_ADDR
[i
]);
498 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_USBn_IRQ
[i
]);
499 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->usb
[i
]), 0, irq
);
501 snprintf(name
, NAME_SIZE
, "usbmisc%d", i
);
502 create_unimplemented_device(name
, FSL_IMX7_USBMISCn_ADDR
[i
],
503 FSL_IMX7_USBMISCn_SIZE
);
509 for (i
= 0; i
< FSL_IMX7_NUM_ADCS
; i
++) {
510 static const hwaddr FSL_IMX7_ADCn_ADDR
[FSL_IMX7_NUM_ADCS
] = {
515 snprintf(name
, NAME_SIZE
, "adc%d", i
);
516 create_unimplemented_device(name
, FSL_IMX7_ADCn_ADDR
[i
],
523 create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR
,
524 FSL_IMX7_LCDIF_SIZE
);
527 static void fsl_imx7_class_init(ObjectClass
*oc
, void *data
)
529 DeviceClass
*dc
= DEVICE_CLASS(oc
);
531 dc
->realize
= fsl_imx7_realize
;
533 /* Reason: Uses serial_hds and nd_table in realize() directly */
534 dc
->user_creatable
= false;
535 dc
->desc
= "i.MX7 SOC";
538 static const TypeInfo fsl_imx7_type_info
= {
539 .name
= TYPE_FSL_IMX7
,
540 .parent
= TYPE_DEVICE
,
541 .instance_size
= sizeof(FslIMX7State
),
542 .instance_init
= fsl_imx7_init
,
543 .class_init
= fsl_imx7_class_init
,
546 static void fsl_imx7_register_types(void)
548 type_register_static(&fsl_imx7_type_info
);
550 type_init(fsl_imx7_register_types
)