hw/arm/fsl-imx7.c

   1 /*
   2  * Copyright (c) 2018, Impinj, Inc.
   3  *
   4  * i.MX7 SoC definitions
   5  *
   6  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
   7  *
   8  * Based on hw/arm/fsl-imx6.c
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "hw/arm/fsl-imx7.h"
  24 #include "hw/misc/unimp.h"
  25 #include "hw/boards.h"
  26 #include "sysemu/sysemu.h"
  27 #include "qemu/error-report.h"
  28 #include "qemu/module.h"
  29
  30 #define NAME_SIZE 20
  31
  32 static void fsl_imx7_init(Object *obj)
  33 {
  34     MachineState *ms = MACHINE(qdev_get_machine());
  35     FslIMX7State *s = FSL_IMX7(obj);
  36     char name[NAME_SIZE];
  37     int i;
  38
  39     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
  40         snprintf(name, NAME_SIZE, "cpu%d", i);
  41         object_initialize_child(obj, name, &s->cpu[i],
  42                                 ARM_CPU_TYPE_NAME("cortex-a7"));
  43     }
  44
  45     /*
  46      * A7MPCORE
  47      */
  48     object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
  49                             TYPE_A15MPCORE_PRIV);
  50
  51     /*
  52      * GPIOs 1 to 7
  53      */
  54     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
  55         snprintf(name, NAME_SIZE, "gpio%d", i);
  56         object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
  57     }
  58
  59     /*
  60      * GPT1, 2, 3, 4
  61      */
  62     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
  63         snprintf(name, NAME_SIZE, "gpt%d", i);
  64         object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
  65     }
  66
  67     /*
  68      * CCM
  69      */
  70     object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX7_CCM);
  71
  72     /*
  73      * Analog
  74      */
  75     object_initialize_child(obj, "analog", &s->analog, TYPE_IMX7_ANALOG);
  76
  77     /*
  78      * GPCv2
  79      */
  80     object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
  81
  82     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
  83         snprintf(name, NAME_SIZE, "spi%d", i + 1);
  84         object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
  85     }
  86
  87
  88     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
  89         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
  90         object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
  91     }
  92
  93     /*
  94      * UART
  95      */
  96     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
  97             snprintf(name, NAME_SIZE, "uart%d", i);
  98             object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
  99     }
 100
 101     /*
 102      * Ethernet
 103      */
 104     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
 105             snprintf(name, NAME_SIZE, "eth%d", i);
 106             object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
 107     }
 108
 109     /*
 110      * SDHCI
 111      */
 112     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
 113             snprintf(name, NAME_SIZE, "usdhc%d", i);
 114             object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
 115     }
 116
 117     /*
 118      * SNVS
 119      */
 120     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 121
 122     /*
 123      * Watchdog
 124      */
 125     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
 126             snprintf(name, NAME_SIZE, "wdt%d", i);
 127             object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
 128     }
 129
 130     /*
 131      * GPR
 132      */
 133     object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
 134
 135     object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
 136
 137     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
 138         snprintf(name, NAME_SIZE, "usb%d", i);
 139         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
 140     }
 141 }
 142
 143 static void fsl_imx7_realize(DeviceState *dev, Error **errp)
 144 {
 145     MachineState *ms = MACHINE(qdev_get_machine());
 146     FslIMX7State *s = FSL_IMX7(dev);
 147     Object *o;
 148     int i;
 149     qemu_irq irq;
 150     char name[NAME_SIZE];
 151     unsigned int smp_cpus = ms->smp.cpus;
 152
 153     if (smp_cpus > FSL_IMX7_NUM_CPUS) {
 154         error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
 155                    TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus);
 156         return;
 157     }
 158
 159     for (i = 0; i < smp_cpus; i++) {
 160         o = OBJECT(&s->cpu[i]);
 161
 162         /* On uniprocessor, the CBAR is set to 0 */
 163         if (smp_cpus > 1) {
 164             object_property_set_int(o, "reset-cbar", FSL_IMX7_A7MPCORE_ADDR,
 165                                     &error_abort);
 166         }
 167
 168         if (i) {
 169             /*
 170              * Secondary CPUs start in powered-down state (and can be
 171              * powered up via the SRC system reset controller)
 172              */
 173             object_property_set_bool(o, "start-powered-off", true,
 174                                      &error_abort);
 175         }
 176
 177         qdev_realize(DEVICE(o), NULL, &error_abort);
 178     }
 179
 180     /*
 181      * A7MPCORE
 182      */
 183     object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", smp_cpus,
 184                             &error_abort);
 185     object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
 186                             FSL_IMX7_MAX_IRQ + GIC_INTERNAL, &error_abort);
 187
 188     sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
 189     sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
 190
 191     for (i = 0; i < smp_cpus; i++) {
 192         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
 193         DeviceState  *d   = DEVICE(qemu_get_cpu(i));
 194
 195         irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
 196         sysbus_connect_irq(sbd, i, irq);
 197         irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
 198         sysbus_connect_irq(sbd, i + smp_cpus, irq);
 199         irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
 200         sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq);
 201         irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
 202         sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq);
 203     }
 204
 205     /*
 206      * A7MPCORE DAP
 207      */
 208     create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
 209                                 0x100000);
 210
 211     /*
 212      * GPT1, 2, 3, 4
 213      */
 214     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
 215         static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
 216             FSL_IMX7_GPT1_ADDR,
 217             FSL_IMX7_GPT2_ADDR,
 218             FSL_IMX7_GPT3_ADDR,
 219             FSL_IMX7_GPT4_ADDR,
 220         };
 221
 222         static const int FSL_IMX7_GPTn_IRQ[FSL_IMX7_NUM_GPTS] = {
 223             FSL_IMX7_GPT1_IRQ,
 224             FSL_IMX7_GPT2_IRQ,
 225             FSL_IMX7_GPT3_IRQ,
 226             FSL_IMX7_GPT4_IRQ,
 227         };
 228
 229         s->gpt[i].ccm = IMX_CCM(&s->ccm);
 230         sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
 231         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
 232         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
 233                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 234                                             FSL_IMX7_GPTn_IRQ[i]));
 235     }
 236
 237     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
 238         static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
 239             FSL_IMX7_GPIO1_ADDR,
 240             FSL_IMX7_GPIO2_ADDR,
 241             FSL_IMX7_GPIO3_ADDR,
 242             FSL_IMX7_GPIO4_ADDR,
 243             FSL_IMX7_GPIO5_ADDR,
 244             FSL_IMX7_GPIO6_ADDR,
 245             FSL_IMX7_GPIO7_ADDR,
 246         };
 247
 248         static const int FSL_IMX7_GPIOn_LOW_IRQ[FSL_IMX7_NUM_GPIOS] = {
 249             FSL_IMX7_GPIO1_LOW_IRQ,
 250             FSL_IMX7_GPIO2_LOW_IRQ,
 251             FSL_IMX7_GPIO3_LOW_IRQ,
 252             FSL_IMX7_GPIO4_LOW_IRQ,
 253             FSL_IMX7_GPIO5_LOW_IRQ,
 254             FSL_IMX7_GPIO6_LOW_IRQ,
 255             FSL_IMX7_GPIO7_LOW_IRQ,
 256         };
 257
 258         static const int FSL_IMX7_GPIOn_HIGH_IRQ[FSL_IMX7_NUM_GPIOS] = {
 259             FSL_IMX7_GPIO1_HIGH_IRQ,
 260             FSL_IMX7_GPIO2_HIGH_IRQ,
 261             FSL_IMX7_GPIO3_HIGH_IRQ,
 262             FSL_IMX7_GPIO4_HIGH_IRQ,
 263             FSL_IMX7_GPIO5_HIGH_IRQ,
 264             FSL_IMX7_GPIO6_HIGH_IRQ,
 265             FSL_IMX7_GPIO7_HIGH_IRQ,
 266         };
 267
 268         sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
 269         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 270                         FSL_IMX7_GPIOn_ADDR[i]);
 271
 272         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 273                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 274                                             FSL_IMX7_GPIOn_LOW_IRQ[i]));
 275
 276         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
 277                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 278                                             FSL_IMX7_GPIOn_HIGH_IRQ[i]));
 279     }
 280
 281     /*
 282      * IOMUXC and IOMUXC_LPSR
 283      */
 284     for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
 285         static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
 286             FSL_IMX7_IOMUXC_ADDR,
 287             FSL_IMX7_IOMUXC_LPSR_ADDR,
 288         };
 289
 290         snprintf(name, NAME_SIZE, "iomuxc%d", i);
 291         create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
 292                                     FSL_IMX7_IOMUXCn_SIZE);
 293     }
 294
 295     /*
 296      * CCM
 297      */
 298     sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort);
 299     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR);
 300
 301     /*
 302      * Analog
 303      */
 304     sysbus_realize(SYS_BUS_DEVICE(&s->analog), &error_abort);
 305     sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR);
 306
 307     /*
 308      * GPCv2
 309      */
 310     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
 311     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
 312
 313     /* Initialize all ECSPI */
 314     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
 315         static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
 316             FSL_IMX7_ECSPI1_ADDR,
 317             FSL_IMX7_ECSPI2_ADDR,
 318             FSL_IMX7_ECSPI3_ADDR,
 319             FSL_IMX7_ECSPI4_ADDR,
 320         };
 321
 322         static const int FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = {
 323             FSL_IMX7_ECSPI1_IRQ,
 324             FSL_IMX7_ECSPI2_IRQ,
 325             FSL_IMX7_ECSPI3_IRQ,
 326             FSL_IMX7_ECSPI4_IRQ,
 327         };
 328
 329         /* Initialize the SPI */
 330         sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort);
 331         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
 332                         FSL_IMX7_SPIn_ADDR[i]);
 333         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 334                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 335                                             FSL_IMX7_SPIn_IRQ[i]));
 336     }
 337
 338     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
 339         static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
 340             FSL_IMX7_I2C1_ADDR,
 341             FSL_IMX7_I2C2_ADDR,
 342             FSL_IMX7_I2C3_ADDR,
 343             FSL_IMX7_I2C4_ADDR,
 344         };
 345
 346         static const int FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = {
 347             FSL_IMX7_I2C1_IRQ,
 348             FSL_IMX7_I2C2_IRQ,
 349             FSL_IMX7_I2C3_IRQ,
 350             FSL_IMX7_I2C4_IRQ,
 351         };
 352
 353         sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort);
 354         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
 355
 356         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 357                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 358                                             FSL_IMX7_I2Cn_IRQ[i]));
 359     }
 360
 361     /*
 362      * UART
 363      */
 364     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
 365         static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
 366             FSL_IMX7_UART1_ADDR,
 367             FSL_IMX7_UART2_ADDR,
 368             FSL_IMX7_UART3_ADDR,
 369             FSL_IMX7_UART4_ADDR,
 370             FSL_IMX7_UART5_ADDR,
 371             FSL_IMX7_UART6_ADDR,
 372             FSL_IMX7_UART7_ADDR,
 373         };
 374
 375         static const int FSL_IMX7_UARTn_IRQ[FSL_IMX7_NUM_UARTS] = {
 376             FSL_IMX7_UART1_IRQ,
 377             FSL_IMX7_UART2_IRQ,
 378             FSL_IMX7_UART3_IRQ,
 379             FSL_IMX7_UART4_IRQ,
 380             FSL_IMX7_UART5_IRQ,
 381             FSL_IMX7_UART6_IRQ,
 382             FSL_IMX7_UART7_IRQ,
 383         };
 384
 385
 386         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 387
 388         sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort);
 389
 390         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
 391
 392         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]);
 393         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq);
 394     }
 395
 396     /*
 397      * Ethernet
 398      */
 399     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
 400         static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = {
 401             FSL_IMX7_ENET1_ADDR,
 402             FSL_IMX7_ENET2_ADDR,
 403         };
 404
 405         object_property_set_uint(OBJECT(&s->eth[i]), "phy-num",
 406                                  s->phy_num[i], &error_abort);
 407         object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num",
 408                                  FSL_IMX7_ETH_NUM_TX_RINGS, &error_abort);
 409         qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
 410         sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort);
 411
 412         sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
 413
 414         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0));
 415         sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq);
 416         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3));
 417         sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq);
 418     }
 419
 420     /*
 421      * USDHC
 422      */
 423     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
 424         static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
 425             FSL_IMX7_USDHC1_ADDR,
 426             FSL_IMX7_USDHC2_ADDR,
 427             FSL_IMX7_USDHC3_ADDR,
 428         };
 429
 430         static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = {
 431             FSL_IMX7_USDHC1_IRQ,
 432             FSL_IMX7_USDHC2_IRQ,
 433             FSL_IMX7_USDHC3_IRQ,
 434         };
 435
 436         object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor",
 437                                  SDHCI_VENDOR_IMX, &error_abort);
 438         sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
 439
 440         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
 441                         FSL_IMX7_USDHCn_ADDR[i]);
 442
 443         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]);
 444         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq);
 445     }
 446
 447     /*
 448      * SNVS
 449      */
 450     sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
 451     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
 452
 453     /*
 454      * SRC
 455      */
 456     create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
 457
 458     /*
 459      * Watchdog
 460      */
 461     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
 462         static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
 463             FSL_IMX7_WDOG1_ADDR,
 464             FSL_IMX7_WDOG2_ADDR,
 465             FSL_IMX7_WDOG3_ADDR,
 466             FSL_IMX7_WDOG4_ADDR,
 467         };
 468         static const int FSL_IMX7_WDOGn_IRQ[FSL_IMX7_NUM_WDTS] = {
 469             FSL_IMX7_WDOG1_IRQ,
 470             FSL_IMX7_WDOG2_IRQ,
 471             FSL_IMX7_WDOG3_IRQ,
 472             FSL_IMX7_WDOG4_IRQ,
 473         };
 474
 475         object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
 476                                  true, &error_abort);
 477         sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
 478
 479         sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
 480         sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
 481                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 482                                             FSL_IMX7_WDOGn_IRQ[i]));
 483     }
 484
 485     /*
 486      * SDMA
 487      */
 488     create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE);
 489
 490     /*
 491      * CAAM
 492      */
 493     create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
 494
 495     /*
 496      * PWM
 497      */
 498     create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
 499     create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
 500     create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
 501     create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
 502
 503     /*
 504      * CAN
 505      */
 506     create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
 507     create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
 508
 509     /*
 510      * SAI (Audio SSI (Synchronous Serial Interface))
 511      */
 512     create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
 513     create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
 514     create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
 515
 516     /*
 517      * OCOTP
 518      */
 519     create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
 520                                 FSL_IMX7_OCOTP_SIZE);
 521
 522     sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
 523     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
 524
 525     sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
 526     sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
 527
 528     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ);
 529     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
 530     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ);
 531     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
 532     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ);
 533     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
 534     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
 535     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
 536
 537
 538     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
 539         static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
 540             FSL_IMX7_USBMISC1_ADDR,
 541             FSL_IMX7_USBMISC2_ADDR,
 542             FSL_IMX7_USBMISC3_ADDR,
 543         };
 544
 545         static const hwaddr FSL_IMX7_USBn_ADDR[FSL_IMX7_NUM_USBS] = {
 546             FSL_IMX7_USB1_ADDR,
 547             FSL_IMX7_USB2_ADDR,
 548             FSL_IMX7_USB3_ADDR,
 549         };
 550
 551         static const int FSL_IMX7_USBn_IRQ[FSL_IMX7_NUM_USBS] = {
 552             FSL_IMX7_USB1_IRQ,
 553             FSL_IMX7_USB2_IRQ,
 554             FSL_IMX7_USB3_IRQ,
 555         };
 556
 557         sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
 558         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
 559                         FSL_IMX7_USBn_ADDR[i]);
 560
 561         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]);
 562         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq);
 563
 564         snprintf(name, NAME_SIZE, "usbmisc%d", i);
 565         create_unimplemented_device(name, FSL_IMX7_USBMISCn_ADDR[i],
 566                                     FSL_IMX7_USBMISCn_SIZE);
 567     }
 568
 569     /*
 570      * ADCs
 571      */
 572     for (i = 0; i < FSL_IMX7_NUM_ADCS; i++) {
 573         static const hwaddr FSL_IMX7_ADCn_ADDR[FSL_IMX7_NUM_ADCS] = {
 574             FSL_IMX7_ADC1_ADDR,
 575             FSL_IMX7_ADC2_ADDR,
 576         };
 577
 578         snprintf(name, NAME_SIZE, "adc%d", i);
 579         create_unimplemented_device(name, FSL_IMX7_ADCn_ADDR[i],
 580                                     FSL_IMX7_ADCn_SIZE);
 581     }
 582
 583     /*
 584      * LCD
 585      */
 586     create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR,
 587                                 FSL_IMX7_LCDIF_SIZE);
 588
 589     /*
 590      * DMA APBH
 591      */
 592     create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
 593                                 FSL_IMX7_DMA_APBH_SIZE);
 594     /*
 595      * PCIe PHY
 596      */
 597     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
 598                                 FSL_IMX7_PCIE_PHY_SIZE);
 599 }
 600
 601 static Property fsl_imx7_properties[] = {
 602     DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State, phy_num[0], 0),
 603     DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State, phy_num[1], 1),
 604     DEFINE_PROP_END_OF_LIST(),
 605 };
 606
 607 static void fsl_imx7_class_init(ObjectClass *oc, void *data)
 608 {
 609     DeviceClass *dc = DEVICE_CLASS(oc);
 610
 611     device_class_set_props(dc, fsl_imx7_properties);
 612     dc->realize = fsl_imx7_realize;
 613
 614     /* Reason: Uses serial_hds and nd_table in realize() directly */
 615     dc->user_creatable = false;
 616     dc->desc = "i.MX7 SOC";
 617 }
 618
 619 static const TypeInfo fsl_imx7_type_info = {
 620     .name = TYPE_FSL_IMX7,
 621     .parent = TYPE_DEVICE,
 622     .instance_size = sizeof(FslIMX7State),
 623     .instance_init = fsl_imx7_init,
 624     .class_init = fsl_imx7_class_init,
 625 };
 626
 627 static void fsl_imx7_register_types(void)
 628 {
 629     type_register_static(&fsl_imx7_type_info);
 630 }
 631 type_init(fsl_imx7_register_types)