2 * Copyright (c) 2018, Impinj, Inc.
4 * i.MX7 SoC definitions
6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
8 * Based on hw/arm/fsl-imx6.c
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "hw/arm/fsl-imx7.h"
24 #include "hw/misc/unimp.h"
25 #include "hw/boards.h"
26 #include "sysemu/sysemu.h"
27 #include "qemu/error-report.h"
28 #include "qemu/module.h"
32 static void fsl_imx7_init(Object
*obj
)
34 MachineState
*ms
= MACHINE(qdev_get_machine());
35 FslIMX7State
*s
= FSL_IMX7(obj
);
39 for (i
= 0; i
< MIN(ms
->smp
.cpus
, FSL_IMX7_NUM_CPUS
); i
++) {
40 snprintf(name
, NAME_SIZE
, "cpu%d", i
);
41 object_initialize_child(obj
, name
, &s
->cpu
[i
],
42 ARM_CPU_TYPE_NAME("cortex-a7"));
48 object_initialize_child(obj
, "a7mpcore", &s
->a7mpcore
,
54 for (i
= 0; i
< FSL_IMX7_NUM_GPIOS
; i
++) {
55 snprintf(name
, NAME_SIZE
, "gpio%d", i
);
56 object_initialize_child(obj
, name
, &s
->gpio
[i
], TYPE_IMX_GPIO
);
62 for (i
= 0; i
< FSL_IMX7_NUM_GPTS
; i
++) {
63 snprintf(name
, NAME_SIZE
, "gpt%d", i
);
64 object_initialize_child(obj
, name
, &s
->gpt
[i
], TYPE_IMX7_GPT
);
70 object_initialize_child(obj
, "ccm", &s
->ccm
, TYPE_IMX7_CCM
);
75 object_initialize_child(obj
, "analog", &s
->analog
, TYPE_IMX7_ANALOG
);
80 object_initialize_child(obj
, "gpcv2", &s
->gpcv2
, TYPE_IMX_GPCV2
);
82 for (i
= 0; i
< FSL_IMX7_NUM_ECSPIS
; i
++) {
83 snprintf(name
, NAME_SIZE
, "spi%d", i
+ 1);
84 object_initialize_child(obj
, name
, &s
->spi
[i
], TYPE_IMX_SPI
);
88 for (i
= 0; i
< FSL_IMX7_NUM_I2CS
; i
++) {
89 snprintf(name
, NAME_SIZE
, "i2c%d", i
+ 1);
90 object_initialize_child(obj
, name
, &s
->i2c
[i
], TYPE_IMX_I2C
);
96 for (i
= 0; i
< FSL_IMX7_NUM_UARTS
; i
++) {
97 snprintf(name
, NAME_SIZE
, "uart%d", i
);
98 object_initialize_child(obj
, name
, &s
->uart
[i
], TYPE_IMX_SERIAL
);
104 for (i
= 0; i
< FSL_IMX7_NUM_ETHS
; i
++) {
105 snprintf(name
, NAME_SIZE
, "eth%d", i
);
106 object_initialize_child(obj
, name
, &s
->eth
[i
], TYPE_IMX_ENET
);
112 for (i
= 0; i
< FSL_IMX7_NUM_USDHCS
; i
++) {
113 snprintf(name
, NAME_SIZE
, "usdhc%d", i
);
114 object_initialize_child(obj
, name
, &s
->usdhc
[i
], TYPE_IMX_USDHC
);
120 object_initialize_child(obj
, "snvs", &s
->snvs
, TYPE_IMX7_SNVS
);
125 for (i
= 0; i
< FSL_IMX7_NUM_WDTS
; i
++) {
126 snprintf(name
, NAME_SIZE
, "wdt%d", i
);
127 object_initialize_child(obj
, name
, &s
->wdt
[i
], TYPE_IMX2_WDT
);
133 object_initialize_child(obj
, "gpr", &s
->gpr
, TYPE_IMX7_GPR
);
135 object_initialize_child(obj
, "pcie", &s
->pcie
, TYPE_DESIGNWARE_PCIE_HOST
);
137 for (i
= 0; i
< FSL_IMX7_NUM_USBS
; i
++) {
138 snprintf(name
, NAME_SIZE
, "usb%d", i
);
139 object_initialize_child(obj
, name
, &s
->usb
[i
], TYPE_CHIPIDEA
);
143 static void fsl_imx7_realize(DeviceState
*dev
, Error
**errp
)
145 MachineState
*ms
= MACHINE(qdev_get_machine());
146 FslIMX7State
*s
= FSL_IMX7(dev
);
150 char name
[NAME_SIZE
];
151 unsigned int smp_cpus
= ms
->smp
.cpus
;
153 if (smp_cpus
> FSL_IMX7_NUM_CPUS
) {
154 error_setg(errp
, "%s: Only %d CPUs are supported (%d requested)",
155 TYPE_FSL_IMX7
, FSL_IMX7_NUM_CPUS
, smp_cpus
);
159 for (i
= 0; i
< smp_cpus
; i
++) {
160 o
= OBJECT(&s
->cpu
[i
]);
162 /* On uniprocessor, the CBAR is set to 0 */
164 object_property_set_int(o
, "reset-cbar", FSL_IMX7_A7MPCORE_ADDR
,
170 * Secondary CPUs start in powered-down state (and can be
171 * powered up via the SRC system reset controller)
173 object_property_set_bool(o
, "start-powered-off", true,
177 qdev_realize(DEVICE(o
), NULL
, &error_abort
);
183 object_property_set_int(OBJECT(&s
->a7mpcore
), "num-cpu", smp_cpus
,
185 object_property_set_int(OBJECT(&s
->a7mpcore
), "num-irq",
186 FSL_IMX7_MAX_IRQ
+ GIC_INTERNAL
, &error_abort
);
188 sysbus_realize(SYS_BUS_DEVICE(&s
->a7mpcore
), &error_abort
);
189 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->a7mpcore
), 0, FSL_IMX7_A7MPCORE_ADDR
);
191 for (i
= 0; i
< smp_cpus
; i
++) {
192 SysBusDevice
*sbd
= SYS_BUS_DEVICE(&s
->a7mpcore
);
193 DeviceState
*d
= DEVICE(qemu_get_cpu(i
));
195 irq
= qdev_get_gpio_in(d
, ARM_CPU_IRQ
);
196 sysbus_connect_irq(sbd
, i
, irq
);
197 irq
= qdev_get_gpio_in(d
, ARM_CPU_FIQ
);
198 sysbus_connect_irq(sbd
, i
+ smp_cpus
, irq
);
199 irq
= qdev_get_gpio_in(d
, ARM_CPU_VIRQ
);
200 sysbus_connect_irq(sbd
, i
+ 2 * smp_cpus
, irq
);
201 irq
= qdev_get_gpio_in(d
, ARM_CPU_VFIQ
);
202 sysbus_connect_irq(sbd
, i
+ 3 * smp_cpus
, irq
);
208 create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR
,
214 for (i
= 0; i
< FSL_IMX7_NUM_GPTS
; i
++) {
215 static const hwaddr FSL_IMX7_GPTn_ADDR
[FSL_IMX7_NUM_GPTS
] = {
222 static const int FSL_IMX7_GPTn_IRQ
[FSL_IMX7_NUM_GPTS
] = {
229 s
->gpt
[i
].ccm
= IMX_CCM(&s
->ccm
);
230 sysbus_realize(SYS_BUS_DEVICE(&s
->gpt
[i
]), &error_abort
);
231 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpt
[i
]), 0, FSL_IMX7_GPTn_ADDR
[i
]);
232 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpt
[i
]), 0,
233 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
234 FSL_IMX7_GPTn_IRQ
[i
]));
237 for (i
= 0; i
< FSL_IMX7_NUM_GPIOS
; i
++) {
238 static const hwaddr FSL_IMX7_GPIOn_ADDR
[FSL_IMX7_NUM_GPIOS
] = {
248 static const int FSL_IMX7_GPIOn_LOW_IRQ
[FSL_IMX7_NUM_GPIOS
] = {
249 FSL_IMX7_GPIO1_LOW_IRQ
,
250 FSL_IMX7_GPIO2_LOW_IRQ
,
251 FSL_IMX7_GPIO3_LOW_IRQ
,
252 FSL_IMX7_GPIO4_LOW_IRQ
,
253 FSL_IMX7_GPIO5_LOW_IRQ
,
254 FSL_IMX7_GPIO6_LOW_IRQ
,
255 FSL_IMX7_GPIO7_LOW_IRQ
,
258 static const int FSL_IMX7_GPIOn_HIGH_IRQ
[FSL_IMX7_NUM_GPIOS
] = {
259 FSL_IMX7_GPIO1_HIGH_IRQ
,
260 FSL_IMX7_GPIO2_HIGH_IRQ
,
261 FSL_IMX7_GPIO3_HIGH_IRQ
,
262 FSL_IMX7_GPIO4_HIGH_IRQ
,
263 FSL_IMX7_GPIO5_HIGH_IRQ
,
264 FSL_IMX7_GPIO6_HIGH_IRQ
,
265 FSL_IMX7_GPIO7_HIGH_IRQ
,
268 sysbus_realize(SYS_BUS_DEVICE(&s
->gpio
[i
]), &error_abort
);
269 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0,
270 FSL_IMX7_GPIOn_ADDR
[i
]);
272 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0,
273 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
274 FSL_IMX7_GPIOn_LOW_IRQ
[i
]));
276 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
[i
]), 1,
277 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
278 FSL_IMX7_GPIOn_HIGH_IRQ
[i
]));
282 * IOMUXC and IOMUXC_LPSR
284 for (i
= 0; i
< FSL_IMX7_NUM_IOMUXCS
; i
++) {
285 static const hwaddr FSL_IMX7_IOMUXCn_ADDR
[FSL_IMX7_NUM_IOMUXCS
] = {
286 FSL_IMX7_IOMUXC_ADDR
,
287 FSL_IMX7_IOMUXC_LPSR_ADDR
,
290 snprintf(name
, NAME_SIZE
, "iomuxc%d", i
);
291 create_unimplemented_device(name
, FSL_IMX7_IOMUXCn_ADDR
[i
],
292 FSL_IMX7_IOMUXCn_SIZE
);
298 sysbus_realize(SYS_BUS_DEVICE(&s
->ccm
), &error_abort
);
299 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ccm
), 0, FSL_IMX7_CCM_ADDR
);
304 sysbus_realize(SYS_BUS_DEVICE(&s
->analog
), &error_abort
);
305 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->analog
), 0, FSL_IMX7_ANALOG_ADDR
);
310 sysbus_realize(SYS_BUS_DEVICE(&s
->gpcv2
), &error_abort
);
311 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpcv2
), 0, FSL_IMX7_GPC_ADDR
);
313 /* Initialize all ECSPI */
314 for (i
= 0; i
< FSL_IMX7_NUM_ECSPIS
; i
++) {
315 static const hwaddr FSL_IMX7_SPIn_ADDR
[FSL_IMX7_NUM_ECSPIS
] = {
316 FSL_IMX7_ECSPI1_ADDR
,
317 FSL_IMX7_ECSPI2_ADDR
,
318 FSL_IMX7_ECSPI3_ADDR
,
319 FSL_IMX7_ECSPI4_ADDR
,
322 static const int FSL_IMX7_SPIn_IRQ
[FSL_IMX7_NUM_ECSPIS
] = {
329 /* Initialize the SPI */
330 sysbus_realize(SYS_BUS_DEVICE(&s
->spi
[i
]), &error_abort
);
331 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
332 FSL_IMX7_SPIn_ADDR
[i
]);
333 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
334 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
335 FSL_IMX7_SPIn_IRQ
[i
]));
338 for (i
= 0; i
< FSL_IMX7_NUM_I2CS
; i
++) {
339 static const hwaddr FSL_IMX7_I2Cn_ADDR
[FSL_IMX7_NUM_I2CS
] = {
346 static const int FSL_IMX7_I2Cn_IRQ
[FSL_IMX7_NUM_I2CS
] = {
353 sysbus_realize(SYS_BUS_DEVICE(&s
->i2c
[i
]), &error_abort
);
354 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0, FSL_IMX7_I2Cn_ADDR
[i
]);
356 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0,
357 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
358 FSL_IMX7_I2Cn_IRQ
[i
]));
364 for (i
= 0; i
< FSL_IMX7_NUM_UARTS
; i
++) {
365 static const hwaddr FSL_IMX7_UARTn_ADDR
[FSL_IMX7_NUM_UARTS
] = {
375 static const int FSL_IMX7_UARTn_IRQ
[FSL_IMX7_NUM_UARTS
] = {
386 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", serial_hd(i
));
388 sysbus_realize(SYS_BUS_DEVICE(&s
->uart
[i
]), &error_abort
);
390 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, FSL_IMX7_UARTn_ADDR
[i
]);
392 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_UARTn_IRQ
[i
]);
393 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, irq
);
399 for (i
= 0; i
< FSL_IMX7_NUM_ETHS
; i
++) {
400 static const hwaddr FSL_IMX7_ENETn_ADDR
[FSL_IMX7_NUM_ETHS
] = {
405 object_property_set_uint(OBJECT(&s
->eth
[i
]), "phy-num",
406 s
->phy_num
[i
], &error_abort
);
407 object_property_set_uint(OBJECT(&s
->eth
[i
]), "tx-ring-num",
408 FSL_IMX7_ETH_NUM_TX_RINGS
, &error_abort
);
409 qdev_set_nic_properties(DEVICE(&s
->eth
[i
]), &nd_table
[i
]);
410 sysbus_realize(SYS_BUS_DEVICE(&s
->eth
[i
]), &error_abort
);
412 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->eth
[i
]), 0, FSL_IMX7_ENETn_ADDR
[i
]);
414 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_ENET_IRQ(i
, 0));
415 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->eth
[i
]), 0, irq
);
416 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_ENET_IRQ(i
, 3));
417 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->eth
[i
]), 1, irq
);
423 for (i
= 0; i
< FSL_IMX7_NUM_USDHCS
; i
++) {
424 static const hwaddr FSL_IMX7_USDHCn_ADDR
[FSL_IMX7_NUM_USDHCS
] = {
425 FSL_IMX7_USDHC1_ADDR
,
426 FSL_IMX7_USDHC2_ADDR
,
427 FSL_IMX7_USDHC3_ADDR
,
430 static const int FSL_IMX7_USDHCn_IRQ
[FSL_IMX7_NUM_USDHCS
] = {
436 object_property_set_uint(OBJECT(&s
->usdhc
[i
]), "vendor",
437 SDHCI_VENDOR_IMX
, &error_abort
);
438 sysbus_realize(SYS_BUS_DEVICE(&s
->usdhc
[i
]), &error_abort
);
440 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->usdhc
[i
]), 0,
441 FSL_IMX7_USDHCn_ADDR
[i
]);
443 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_USDHCn_IRQ
[i
]);
444 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->usdhc
[i
]), 0, irq
);
450 sysbus_realize(SYS_BUS_DEVICE(&s
->snvs
), &error_abort
);
451 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->snvs
), 0, FSL_IMX7_SNVS_ADDR
);
456 create_unimplemented_device("src", FSL_IMX7_SRC_ADDR
, FSL_IMX7_SRC_SIZE
);
461 for (i
= 0; i
< FSL_IMX7_NUM_WDTS
; i
++) {
462 static const hwaddr FSL_IMX7_WDOGn_ADDR
[FSL_IMX7_NUM_WDTS
] = {
468 static const int FSL_IMX7_WDOGn_IRQ
[FSL_IMX7_NUM_WDTS
] = {
475 object_property_set_bool(OBJECT(&s
->wdt
[i
]), "pretimeout-support",
477 sysbus_realize(SYS_BUS_DEVICE(&s
->wdt
[i
]), &error_abort
);
479 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0, FSL_IMX7_WDOGn_ADDR
[i
]);
480 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0,
481 qdev_get_gpio_in(DEVICE(&s
->a7mpcore
),
482 FSL_IMX7_WDOGn_IRQ
[i
]));
488 create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR
, FSL_IMX7_SDMA_SIZE
);
493 create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR
, FSL_IMX7_CAAM_SIZE
);
498 create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR
, FSL_IMX7_PWMn_SIZE
);
499 create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR
, FSL_IMX7_PWMn_SIZE
);
500 create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR
, FSL_IMX7_PWMn_SIZE
);
501 create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR
, FSL_IMX7_PWMn_SIZE
);
506 create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR
, FSL_IMX7_CANn_SIZE
);
507 create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR
, FSL_IMX7_CANn_SIZE
);
510 * SAI (Audio SSI (Synchronous Serial Interface))
512 create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR
, FSL_IMX7_SAIn_SIZE
);
513 create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR
, FSL_IMX7_SAIn_SIZE
);
514 create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR
, FSL_IMX7_SAIn_SIZE
);
519 create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR
,
520 FSL_IMX7_OCOTP_SIZE
);
522 sysbus_realize(SYS_BUS_DEVICE(&s
->gpr
), &error_abort
);
523 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpr
), 0, FSL_IMX7_GPR_ADDR
);
525 sysbus_realize(SYS_BUS_DEVICE(&s
->pcie
), &error_abort
);
526 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->pcie
), 0, FSL_IMX7_PCIE_REG_ADDR
);
528 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_PCI_INTA_IRQ
);
529 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->pcie
), 0, irq
);
530 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_PCI_INTB_IRQ
);
531 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->pcie
), 1, irq
);
532 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_PCI_INTC_IRQ
);
533 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->pcie
), 2, irq
);
534 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_PCI_INTD_IRQ
);
535 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->pcie
), 3, irq
);
538 for (i
= 0; i
< FSL_IMX7_NUM_USBS
; i
++) {
539 static const hwaddr FSL_IMX7_USBMISCn_ADDR
[FSL_IMX7_NUM_USBS
] = {
540 FSL_IMX7_USBMISC1_ADDR
,
541 FSL_IMX7_USBMISC2_ADDR
,
542 FSL_IMX7_USBMISC3_ADDR
,
545 static const hwaddr FSL_IMX7_USBn_ADDR
[FSL_IMX7_NUM_USBS
] = {
551 static const int FSL_IMX7_USBn_IRQ
[FSL_IMX7_NUM_USBS
] = {
557 sysbus_realize(SYS_BUS_DEVICE(&s
->usb
[i
]), &error_abort
);
558 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->usb
[i
]), 0,
559 FSL_IMX7_USBn_ADDR
[i
]);
561 irq
= qdev_get_gpio_in(DEVICE(&s
->a7mpcore
), FSL_IMX7_USBn_IRQ
[i
]);
562 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->usb
[i
]), 0, irq
);
564 snprintf(name
, NAME_SIZE
, "usbmisc%d", i
);
565 create_unimplemented_device(name
, FSL_IMX7_USBMISCn_ADDR
[i
],
566 FSL_IMX7_USBMISCn_SIZE
);
572 for (i
= 0; i
< FSL_IMX7_NUM_ADCS
; i
++) {
573 static const hwaddr FSL_IMX7_ADCn_ADDR
[FSL_IMX7_NUM_ADCS
] = {
578 snprintf(name
, NAME_SIZE
, "adc%d", i
);
579 create_unimplemented_device(name
, FSL_IMX7_ADCn_ADDR
[i
],
586 create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR
,
587 FSL_IMX7_LCDIF_SIZE
);
592 create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR
,
593 FSL_IMX7_DMA_APBH_SIZE
);
597 create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR
,
598 FSL_IMX7_PCIE_PHY_SIZE
);
601 static Property fsl_imx7_properties
[] = {
602 DEFINE_PROP_UINT32("fec1-phy-num", FslIMX7State
, phy_num
[0], 0),
603 DEFINE_PROP_UINT32("fec2-phy-num", FslIMX7State
, phy_num
[1], 1),
604 DEFINE_PROP_END_OF_LIST(),
607 static void fsl_imx7_class_init(ObjectClass
*oc
, void *data
)
609 DeviceClass
*dc
= DEVICE_CLASS(oc
);
611 device_class_set_props(dc
, fsl_imx7_properties
);
612 dc
->realize
= fsl_imx7_realize
;
614 /* Reason: Uses serial_hds and nd_table in realize() directly */
615 dc
->user_creatable
= false;
616 dc
->desc
= "i.MX7 SOC";
619 static const TypeInfo fsl_imx7_type_info
= {
620 .name
= TYPE_FSL_IMX7
,
621 .parent
= TYPE_DEVICE
,
622 .instance_size
= sizeof(FslIMX7State
),
623 .instance_init
= fsl_imx7_init
,
624 .class_init
= fsl_imx7_class_init
,
627 static void fsl_imx7_register_types(void)
629 type_register_static(&fsl_imx7_type_info
);
631 type_init(fsl_imx7_register_types
)