4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
23 #include "exec/helper-proto.h"
24 #include "internals.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
28 #define SIGNBIT (uint32_t)0x80000000
29 #define SIGNBIT64 ((uint64_t)1 << 63)
31 static void raise_exception(CPUARMState
*env
, uint32_t excp
,
32 uint32_t syndrome
, uint32_t target_el
)
34 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
36 if ((env
->cp15
.hcr_el2
& HCR_TGE
) &&
37 target_el
== 1 && !arm_is_secure(env
)) {
39 * Redirect NS EL1 exceptions to NS EL2. These are reported with
40 * their original syndrome register value, with the exception of
41 * SIMD/FP access traps, which are reported as uncategorized
42 * (see DDI0478C.a D1.10.4)
45 if (syndrome
>> ARM_EL_EC_SHIFT
== EC_ADVSIMDFPACCESSTRAP
) {
46 syndrome
= syn_uncategorized();
50 assert(!excp_is_internal(excp
));
51 cs
->exception_index
= excp
;
52 env
->exception
.syndrome
= syndrome
;
53 env
->exception
.target_el
= target_el
;
57 static int exception_target_el(CPUARMState
*env
)
59 int target_el
= MAX(1, arm_current_el(env
));
61 /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL
62 * to EL3 in this case.
64 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3) && target_el
== 1) {
71 uint32_t HELPER(neon_tbl
)(uint32_t ireg
, uint32_t def
, void *vn
,
78 for (shift
= 0; shift
< 32; shift
+= 8) {
79 uint32_t index
= (ireg
>> shift
) & 0xff;
80 if (index
< maxindex
) {
81 uint32_t tmp
= (table
[index
>> 3] >> ((index
& 7) << 3)) & 0xff;
84 val
|= def
& (0xff << shift
);
90 #if !defined(CONFIG_USER_ONLY)
92 static inline uint32_t merge_syn_data_abort(uint32_t template_syn
,
93 unsigned int target_el
,
94 bool same_el
, bool ea
,
95 bool s1ptw
, bool is_write
,
100 /* ISV is only set for data aborts routed to EL2 and
101 * never for stage-1 page table walks faulting on stage 2.
103 * Furthermore, ISV is only set for certain kinds of load/stores.
104 * If the template syndrome does not have ISV set, we should leave
107 * See ARMv8 specs, D7-1974:
108 * ISS encoding for an exception from a Data Abort, the
111 if (!(template_syn
& ARM_EL_ISV
) || target_el
!= 2 || s1ptw
) {
112 syn
= syn_data_abort_no_iss(same_el
,
113 ea
, 0, s1ptw
, is_write
, fsc
);
115 /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
116 * syndrome created at translation time.
117 * Now we create the runtime syndrome with the remaining fields.
119 syn
= syn_data_abort_with_iss(same_el
,
121 ea
, 0, s1ptw
, is_write
, fsc
,
123 /* Merge the runtime syndrome with the template syndrome. */
129 static void deliver_fault(ARMCPU
*cpu
, vaddr addr
, MMUAccessType access_type
,
130 int mmu_idx
, ARMMMUFaultInfo
*fi
)
132 CPUARMState
*env
= &cpu
->env
;
135 uint32_t syn
, exc
, fsr
, fsc
;
136 ARMMMUIdx arm_mmu_idx
= core_to_arm_mmu_idx(env
, mmu_idx
);
138 target_el
= exception_target_el(env
);
141 env
->cp15
.hpfar_el2
= extract64(fi
->s2addr
, 12, 47) << 4;
143 same_el
= (arm_current_el(env
) == target_el
);
145 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
146 arm_s1_regime_using_lpae_format(env
, arm_mmu_idx
)) {
147 /* LPAE format fault status register : bottom 6 bits are
148 * status code in the same form as needed for syndrome
150 fsr
= arm_fi_to_lfsc(fi
);
151 fsc
= extract32(fsr
, 0, 6);
153 fsr
= arm_fi_to_sfsc(fi
);
154 /* Short format FSR : this fault will never actually be reported
155 * to an EL that uses a syndrome register. Use a (currently)
156 * reserved FSR code in case the constructed syndrome does leak
157 * into the guest somehow.
162 if (access_type
== MMU_INST_FETCH
) {
163 syn
= syn_insn_abort(same_el
, fi
->ea
, fi
->s1ptw
, fsc
);
164 exc
= EXCP_PREFETCH_ABORT
;
166 syn
= merge_syn_data_abort(env
->exception
.syndrome
, target_el
,
167 same_el
, fi
->ea
, fi
->s1ptw
,
168 access_type
== MMU_DATA_STORE
,
170 if (access_type
== MMU_DATA_STORE
171 && arm_feature(env
, ARM_FEATURE_V6
)) {
174 exc
= EXCP_DATA_ABORT
;
177 env
->exception
.vaddress
= addr
;
178 env
->exception
.fsr
= fsr
;
179 raise_exception(env
, exc
, syn
, target_el
);
182 /* try to fill the TLB and return an exception if error. If retaddr is
183 * NULL, it means that the function was called in C code (i.e. not
184 * from generated code or from helper.c)
186 void tlb_fill(CPUState
*cs
, target_ulong addr
, int size
,
187 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
190 ARMMMUFaultInfo fi
= {};
192 ret
= arm_tlb_fill(cs
, addr
, access_type
, mmu_idx
, &fi
);
194 ARMCPU
*cpu
= ARM_CPU(cs
);
196 /* now we have a real cpu fault */
197 cpu_restore_state(cs
, retaddr
, true);
199 deliver_fault(cpu
, addr
, access_type
, mmu_idx
, &fi
);
203 /* Raise a data fault alignment exception for the specified virtual address */
204 void arm_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
205 MMUAccessType access_type
,
206 int mmu_idx
, uintptr_t retaddr
)
208 ARMCPU
*cpu
= ARM_CPU(cs
);
209 ARMMMUFaultInfo fi
= {};
211 /* now we have a real cpu fault */
212 cpu_restore_state(cs
, retaddr
, true);
214 fi
.type
= ARMFault_Alignment
;
215 deliver_fault(cpu
, vaddr
, access_type
, mmu_idx
, &fi
);
218 /* arm_cpu_do_transaction_failed: handle a memory system error response
219 * (eg "no device/memory present at address") by raising an external abort
222 void arm_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
223 vaddr addr
, unsigned size
,
224 MMUAccessType access_type
,
225 int mmu_idx
, MemTxAttrs attrs
,
226 MemTxResult response
, uintptr_t retaddr
)
228 ARMCPU
*cpu
= ARM_CPU(cs
);
229 ARMMMUFaultInfo fi
= {};
231 /* now we have a real cpu fault */
232 cpu_restore_state(cs
, retaddr
, true);
234 fi
.ea
= arm_extabort_type(response
);
235 fi
.type
= ARMFault_SyncExternal
;
236 deliver_fault(cpu
, addr
, access_type
, mmu_idx
, &fi
);
239 #endif /* !defined(CONFIG_USER_ONLY) */
241 uint32_t HELPER(add_setq
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
243 uint32_t res
= a
+ b
;
244 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
))
249 uint32_t HELPER(add_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
251 uint32_t res
= a
+ b
;
252 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
)) {
254 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
259 uint32_t HELPER(sub_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
261 uint32_t res
= a
- b
;
262 if (((res
^ a
) & SIGNBIT
) && ((a
^ b
) & SIGNBIT
)) {
264 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
269 uint32_t HELPER(double_saturate
)(CPUARMState
*env
, int32_t val
)
272 if (val
>= 0x40000000) {
275 } else if (val
<= (int32_t)0xc0000000) {
284 uint32_t HELPER(add_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
286 uint32_t res
= a
+ b
;
294 uint32_t HELPER(sub_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
296 uint32_t res
= a
- b
;
304 /* Signed saturation. */
305 static inline uint32_t do_ssat(CPUARMState
*env
, int32_t val
, int shift
)
311 mask
= (1u << shift
) - 1;
315 } else if (top
< -1) {
322 /* Unsigned saturation. */
323 static inline uint32_t do_usat(CPUARMState
*env
, int32_t val
, int shift
)
327 max
= (1u << shift
) - 1;
331 } else if (val
> max
) {
338 /* Signed saturate. */
339 uint32_t HELPER(ssat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
341 return do_ssat(env
, x
, shift
);
344 /* Dual halfword signed saturate. */
345 uint32_t HELPER(ssat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
349 res
= (uint16_t)do_ssat(env
, (int16_t)x
, shift
);
350 res
|= do_ssat(env
, ((int32_t)x
) >> 16, shift
) << 16;
354 /* Unsigned saturate. */
355 uint32_t HELPER(usat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
357 return do_usat(env
, x
, shift
);
360 /* Dual halfword unsigned saturate. */
361 uint32_t HELPER(usat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
365 res
= (uint16_t)do_usat(env
, (int16_t)x
, shift
);
366 res
|= do_usat(env
, ((int32_t)x
) >> 16, shift
) << 16;
370 void HELPER(setend
)(CPUARMState
*env
)
372 env
->uncached_cpsr
^= CPSR_E
;
375 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
376 * The function returns the target EL (1-3) if the instruction is to be trapped;
377 * otherwise it returns 0 indicating it is not trapped.
379 static inline int check_wfx_trap(CPUARMState
*env
, bool is_wfe
)
381 int cur_el
= arm_current_el(env
);
384 if (arm_feature(env
, ARM_FEATURE_M
)) {
385 /* M profile cores can never trap WFI/WFE. */
389 /* If we are currently in EL0 then we need to check if SCTLR is set up for
390 * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
392 if (cur_el
< 1 && arm_feature(env
, ARM_FEATURE_V8
)) {
395 mask
= is_wfe
? SCTLR_nTWE
: SCTLR_nTWI
;
396 if (arm_is_secure_below_el3(env
) && !arm_el_is_aa64(env
, 3)) {
397 /* Secure EL0 and Secure PL1 is at EL3 */
403 if (!(env
->cp15
.sctlr_el
[target_el
] & mask
)) {
408 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
409 * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
410 * bits will be zero indicating no trap.
412 if (cur_el
< 2 && !arm_is_secure(env
)) {
413 mask
= (is_wfe
) ? HCR_TWE
: HCR_TWI
;
414 if (env
->cp15
.hcr_el2
& mask
) {
419 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
421 mask
= (is_wfe
) ? SCR_TWE
: SCR_TWI
;
422 if (env
->cp15
.scr_el3
& mask
) {
430 void HELPER(wfi
)(CPUARMState
*env
, uint32_t insn_len
)
432 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
433 int target_el
= check_wfx_trap(env
, false);
435 if (cpu_has_work(cs
)) {
436 /* Don't bother to go into our "low power state" if
437 * we would just wake up immediately.
444 raise_exception(env
, EXCP_UDEF
, syn_wfx(1, 0xe, 0, insn_len
== 2),
448 cs
->exception_index
= EXCP_HLT
;
453 void HELPER(wfe
)(CPUARMState
*env
)
455 /* This is a hint instruction that is semantically different
456 * from YIELD even though we currently implement it identically.
457 * Don't actually halt the CPU, just yield back to top
458 * level loop. This is not going into a "low power state"
459 * (ie halting until some event occurs), so we never take
460 * a configurable trap to a different exception level.
465 void HELPER(yield
)(CPUARMState
*env
)
467 ARMCPU
*cpu
= arm_env_get_cpu(env
);
468 CPUState
*cs
= CPU(cpu
);
470 /* This is a non-trappable hint instruction that generally indicates
471 * that the guest is currently busy-looping. Yield control back to the
472 * top level loop so that a more deserving VCPU has a chance to run.
474 cs
->exception_index
= EXCP_YIELD
;
478 /* Raise an internal-to-QEMU exception. This is limited to only
479 * those EXCP values which are special cases for QEMU to interrupt
480 * execution and not to be used for exceptions which are passed to
481 * the guest (those must all have syndrome information and thus should
482 * use exception_with_syndrome).
484 void HELPER(exception_internal
)(CPUARMState
*env
, uint32_t excp
)
486 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
488 assert(excp_is_internal(excp
));
489 cs
->exception_index
= excp
;
493 /* Raise an exception with the specified syndrome register value */
494 void HELPER(exception_with_syndrome
)(CPUARMState
*env
, uint32_t excp
,
495 uint32_t syndrome
, uint32_t target_el
)
497 raise_exception(env
, excp
, syndrome
, target_el
);
500 /* Raise an EXCP_BKPT with the specified syndrome register value,
501 * targeting the correct exception level for debug exceptions.
503 void HELPER(exception_bkpt_insn
)(CPUARMState
*env
, uint32_t syndrome
)
505 /* FSR will only be used if the debug target EL is AArch32. */
506 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
507 /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
508 * values to the guest that it shouldn't be able to see at its
509 * exception/security level.
511 env
->exception
.vaddress
= 0;
512 raise_exception(env
, EXCP_BKPT
, syndrome
, arm_debug_target_el(env
));
515 uint32_t HELPER(cpsr_read
)(CPUARMState
*env
)
517 return cpsr_read(env
) & ~(CPSR_EXEC
| CPSR_RESERVED
);
520 void HELPER(cpsr_write
)(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
522 cpsr_write(env
, val
, mask
, CPSRWriteByInstr
);
525 /* Write the CPSR for a 32-bit exception return */
526 void HELPER(cpsr_write_eret
)(CPUARMState
*env
, uint32_t val
)
528 qemu_mutex_lock_iothread();
529 arm_call_pre_el_change_hook(arm_env_get_cpu(env
));
530 qemu_mutex_unlock_iothread();
532 cpsr_write(env
, val
, CPSR_ERET_MASK
, CPSRWriteExceptionReturn
);
534 /* Generated code has already stored the new PC value, but
535 * without masking out its low bits, because which bits need
536 * masking depends on whether we're returning to Thumb or ARM
537 * state. Do the masking now.
539 env
->regs
[15] &= (env
->thumb
? ~1 : ~3);
541 qemu_mutex_lock_iothread();
542 arm_call_el_change_hook(arm_env_get_cpu(env
));
543 qemu_mutex_unlock_iothread();
546 /* Access to user mode registers from privileged modes. */
547 uint32_t HELPER(get_user_reg
)(CPUARMState
*env
, uint32_t regno
)
552 val
= env
->banked_r13
[BANK_USRSYS
];
553 } else if (regno
== 14) {
554 val
= env
->banked_r14
[BANK_USRSYS
];
555 } else if (regno
>= 8
556 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
557 val
= env
->usr_regs
[regno
- 8];
559 val
= env
->regs
[regno
];
564 void HELPER(set_user_reg
)(CPUARMState
*env
, uint32_t regno
, uint32_t val
)
567 env
->banked_r13
[BANK_USRSYS
] = val
;
568 } else if (regno
== 14) {
569 env
->banked_r14
[BANK_USRSYS
] = val
;
570 } else if (regno
>= 8
571 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
572 env
->usr_regs
[regno
- 8] = val
;
574 env
->regs
[regno
] = val
;
578 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
580 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
583 env
->banked_r13
[bank_number(mode
)] = val
;
587 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
589 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_SYS
) {
590 /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
591 * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
593 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
594 exception_target_el(env
));
597 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
598 return env
->regs
[13];
600 return env
->banked_r13
[bank_number(mode
)];
604 static void msr_mrs_banked_exc_checks(CPUARMState
*env
, uint32_t tgtmode
,
607 /* Raise an exception if the requested access is one of the UNPREDICTABLE
608 * cases; otherwise return. This broadly corresponds to the pseudocode
609 * BankedRegisterAccessValid() and SPSRAccessValid(),
610 * except that we have already handled some cases at translate time.
612 int curmode
= env
->uncached_cpsr
& CPSR_M
;
615 /* ELR_Hyp: a special case because access from tgtmode is OK */
616 if (curmode
!= ARM_CPU_MODE_HYP
&& curmode
!= ARM_CPU_MODE_MON
) {
622 if (curmode
== tgtmode
) {
626 if (tgtmode
== ARM_CPU_MODE_USR
) {
629 if (curmode
!= ARM_CPU_MODE_FIQ
) {
634 if (curmode
== ARM_CPU_MODE_SYS
) {
639 if (curmode
== ARM_CPU_MODE_HYP
|| curmode
== ARM_CPU_MODE_SYS
) {
648 if (tgtmode
== ARM_CPU_MODE_HYP
) {
649 /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
650 if (curmode
!= ARM_CPU_MODE_MON
) {
658 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
659 exception_target_el(env
));
662 void HELPER(msr_banked
)(CPUARMState
*env
, uint32_t value
, uint32_t tgtmode
,
665 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
669 env
->banked_spsr
[bank_number(tgtmode
)] = value
;
671 case 17: /* ELR_Hyp */
672 env
->elr_el
[2] = value
;
675 env
->banked_r13
[bank_number(tgtmode
)] = value
;
678 env
->banked_r14
[bank_number(tgtmode
)] = value
;
682 case ARM_CPU_MODE_USR
:
683 env
->usr_regs
[regno
- 8] = value
;
685 case ARM_CPU_MODE_FIQ
:
686 env
->fiq_regs
[regno
- 8] = value
;
689 g_assert_not_reached();
693 g_assert_not_reached();
697 uint32_t HELPER(mrs_banked
)(CPUARMState
*env
, uint32_t tgtmode
, uint32_t regno
)
699 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
703 return env
->banked_spsr
[bank_number(tgtmode
)];
704 case 17: /* ELR_Hyp */
705 return env
->elr_el
[2];
707 return env
->banked_r13
[bank_number(tgtmode
)];
709 return env
->banked_r14
[bank_number(tgtmode
)];
712 case ARM_CPU_MODE_USR
:
713 return env
->usr_regs
[regno
- 8];
714 case ARM_CPU_MODE_FIQ
:
715 return env
->fiq_regs
[regno
- 8];
717 g_assert_not_reached();
720 g_assert_not_reached();
724 void HELPER(access_check_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t syndrome
,
727 const ARMCPRegInfo
*ri
= rip
;
730 if (arm_feature(env
, ARM_FEATURE_XSCALE
) && ri
->cp
< 14
731 && extract32(env
->cp15
.c15_cpar
, ri
->cp
, 1) == 0) {
732 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
739 switch (ri
->accessfn(env
, ri
, isread
)) {
743 target_el
= exception_target_el(env
);
745 case CP_ACCESS_TRAP_EL2
:
746 /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
747 * a bug in the access function.
749 assert(!arm_is_secure(env
) && arm_current_el(env
) != 3);
752 case CP_ACCESS_TRAP_EL3
:
755 case CP_ACCESS_TRAP_UNCATEGORIZED
:
756 target_el
= exception_target_el(env
);
757 syndrome
= syn_uncategorized();
759 case CP_ACCESS_TRAP_UNCATEGORIZED_EL2
:
761 syndrome
= syn_uncategorized();
763 case CP_ACCESS_TRAP_UNCATEGORIZED_EL3
:
765 syndrome
= syn_uncategorized();
767 case CP_ACCESS_TRAP_FP_EL2
:
769 /* Since we are an implementation that takes exceptions on a trapped
770 * conditional insn only if the insn has passed its condition code
771 * check, we take the IMPDEF choice to always report CV=1 COND=0xe
772 * (which is also the required value for AArch64 traps).
774 syndrome
= syn_fp_access_trap(1, 0xe, false);
776 case CP_ACCESS_TRAP_FP_EL3
:
778 syndrome
= syn_fp_access_trap(1, 0xe, false);
781 g_assert_not_reached();
784 raise_exception(env
, EXCP_UDEF
, syndrome
, target_el
);
787 void HELPER(set_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t value
)
789 const ARMCPRegInfo
*ri
= rip
;
791 if (ri
->type
& ARM_CP_IO
) {
792 qemu_mutex_lock_iothread();
793 ri
->writefn(env
, ri
, value
);
794 qemu_mutex_unlock_iothread();
796 ri
->writefn(env
, ri
, value
);
800 uint32_t HELPER(get_cp_reg
)(CPUARMState
*env
, void *rip
)
802 const ARMCPRegInfo
*ri
= rip
;
805 if (ri
->type
& ARM_CP_IO
) {
806 qemu_mutex_lock_iothread();
807 res
= ri
->readfn(env
, ri
);
808 qemu_mutex_unlock_iothread();
810 res
= ri
->readfn(env
, ri
);
816 void HELPER(set_cp_reg64
)(CPUARMState
*env
, void *rip
, uint64_t value
)
818 const ARMCPRegInfo
*ri
= rip
;
820 if (ri
->type
& ARM_CP_IO
) {
821 qemu_mutex_lock_iothread();
822 ri
->writefn(env
, ri
, value
);
823 qemu_mutex_unlock_iothread();
825 ri
->writefn(env
, ri
, value
);
829 uint64_t HELPER(get_cp_reg64
)(CPUARMState
*env
, void *rip
)
831 const ARMCPRegInfo
*ri
= rip
;
834 if (ri
->type
& ARM_CP_IO
) {
835 qemu_mutex_lock_iothread();
836 res
= ri
->readfn(env
, ri
);
837 qemu_mutex_unlock_iothread();
839 res
= ri
->readfn(env
, ri
);
845 void HELPER(msr_i_pstate
)(CPUARMState
*env
, uint32_t op
, uint32_t imm
)
847 /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
848 * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
849 * to catch that case at translate time.
851 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
852 uint32_t syndrome
= syn_aa64_sysregtrap(0, extract32(op
, 0, 3),
853 extract32(op
, 3, 3), 4,
855 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
859 case 0x05: /* SPSel */
860 update_spsel(env
, imm
);
862 case 0x1e: /* DAIFSet */
863 env
->daif
|= (imm
<< 6) & PSTATE_DAIF
;
865 case 0x1f: /* DAIFClear */
866 env
->daif
&= ~((imm
<< 6) & PSTATE_DAIF
);
869 g_assert_not_reached();
873 void HELPER(clear_pstate_ss
)(CPUARMState
*env
)
875 env
->pstate
&= ~PSTATE_SS
;
878 void HELPER(pre_hvc
)(CPUARMState
*env
)
880 ARMCPU
*cpu
= arm_env_get_cpu(env
);
881 int cur_el
= arm_current_el(env
);
882 /* FIXME: Use actual secure state. */
886 if (arm_is_psci_call(cpu
, EXCP_HVC
)) {
887 /* If PSCI is enabled and this looks like a valid PSCI call then
888 * that overrides the architecturally mandated HVC behaviour.
893 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
894 /* If EL2 doesn't exist, HVC always UNDEFs */
896 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
897 /* EL3.HCE has priority over EL2.HCD. */
898 undef
= !(env
->cp15
.scr_el3
& SCR_HCE
);
900 undef
= env
->cp15
.hcr_el2
& HCR_HCD
;
903 /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
904 * For ARMv8/AArch64, HVC is allowed in EL3.
905 * Note that we've already trapped HVC from EL0 at translation
908 if (secure
&& (!is_a64(env
) || cur_el
== 1)) {
913 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
914 exception_target_el(env
));
918 void HELPER(pre_smc
)(CPUARMState
*env
, uint32_t syndrome
)
920 ARMCPU
*cpu
= arm_env_get_cpu(env
);
921 int cur_el
= arm_current_el(env
);
922 bool secure
= arm_is_secure(env
);
923 bool smd
= env
->cp15
.scr_el3
& SCR_SMD
;
924 /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
925 * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
926 * extensions, SMD only applies to NS state.
927 * On ARMv7 without the Virtualization extensions, the SMD bit
928 * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
929 * so we need not special case this here.
931 bool undef
= arm_feature(env
, ARM_FEATURE_AARCH64
) ? smd
: smd
&& !secure
;
933 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
934 cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
935 /* If we have no EL3 then SMC always UNDEFs and can't be
936 * trapped to EL2. PSCI-via-SMC is a sort of ersatz EL3
937 * firmware within QEMU, and we want an EL2 guest to be able
938 * to forbid its EL1 from making PSCI calls into QEMU's
939 * "firmware" via HCR.TSC, so for these purposes treat
940 * PSCI-via-SMC as implying an EL3.
943 } else if (!secure
&& cur_el
== 1 && (env
->cp15
.hcr_el2
& HCR_TSC
)) {
944 /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
945 * We also want an EL2 guest to be able to forbid its EL1 from
946 * making PSCI calls into QEMU's "firmware" via HCR.TSC.
948 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);
951 /* If PSCI is enabled and this looks like a valid PSCI call then
952 * suppress the UNDEF -- we'll catch the SMC exception and
953 * implement the PSCI call behaviour there.
955 if (undef
&& !arm_is_psci_call(cpu
, EXCP_SMC
)) {
956 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
957 exception_target_el(env
));
961 static int el_from_spsr(uint32_t spsr
)
963 /* Return the exception level that this SPSR is requesting a return to,
964 * or -1 if it is invalid (an illegal return)
966 if (spsr
& PSTATE_nRW
) {
967 switch (spsr
& CPSR_M
) {
968 case ARM_CPU_MODE_USR
:
970 case ARM_CPU_MODE_HYP
:
972 case ARM_CPU_MODE_FIQ
:
973 case ARM_CPU_MODE_IRQ
:
974 case ARM_CPU_MODE_SVC
:
975 case ARM_CPU_MODE_ABT
:
976 case ARM_CPU_MODE_UND
:
977 case ARM_CPU_MODE_SYS
:
979 case ARM_CPU_MODE_MON
:
980 /* Returning to Mon from AArch64 is never possible,
981 * so this is an illegal return.
987 if (extract32(spsr
, 1, 1)) {
988 /* Return with reserved M[1] bit set */
991 if (extract32(spsr
, 0, 4) == 1) {
992 /* return to EL0 with M[0] bit set */
995 return extract32(spsr
, 2, 2);
999 void HELPER(exception_return
)(CPUARMState
*env
)
1001 int cur_el
= arm_current_el(env
);
1002 unsigned int spsr_idx
= aarch64_banked_spsr_index(cur_el
);
1003 uint32_t spsr
= env
->banked_spsr
[spsr_idx
];
1005 bool return_to_aa64
= (spsr
& PSTATE_nRW
) == 0;
1007 aarch64_save_sp(env
, cur_el
);
1009 arm_clear_exclusive(env
);
1011 /* We must squash the PSTATE.SS bit to zero unless both of the
1013 * 1. debug exceptions are currently disabled
1014 * 2. singlestep will be active in the EL we return to
1015 * We check 1 here and 2 after we've done the pstate/cpsr write() to
1016 * transition to the EL we're going to.
1018 if (arm_generate_debug_exceptions(env
)) {
1022 new_el
= el_from_spsr(spsr
);
1024 goto illegal_return
;
1027 || (new_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
))) {
1028 /* Disallow return to an EL which is unimplemented or higher
1029 * than the current one.
1031 goto illegal_return
;
1034 if (new_el
!= 0 && arm_el_is_aa64(env
, new_el
) != return_to_aa64
) {
1035 /* Return to an EL which is configured for a different register width */
1036 goto illegal_return
;
1039 if (new_el
== 2 && arm_is_secure_below_el3(env
)) {
1040 /* Return to the non-existent secure-EL2 */
1041 goto illegal_return
;
1044 if (new_el
== 1 && (env
->cp15
.hcr_el2
& HCR_TGE
)
1045 && !arm_is_secure_below_el3(env
)) {
1046 goto illegal_return
;
1049 qemu_mutex_lock_iothread();
1050 arm_call_pre_el_change_hook(arm_env_get_cpu(env
));
1051 qemu_mutex_unlock_iothread();
1053 if (!return_to_aa64
) {
1055 /* We do a raw CPSR write because aarch64_sync_64_to_32()
1056 * will sort the register banks out for us, and we've already
1057 * caught all the bad-mode cases in el_from_spsr().
1059 cpsr_write(env
, spsr
, ~0, CPSRWriteRaw
);
1060 if (!arm_singlestep_active(env
)) {
1061 env
->uncached_cpsr
&= ~PSTATE_SS
;
1063 aarch64_sync_64_to_32(env
);
1065 if (spsr
& CPSR_T
) {
1066 env
->regs
[15] = env
->elr_el
[cur_el
] & ~0x1;
1068 env
->regs
[15] = env
->elr_el
[cur_el
] & ~0x3;
1070 qemu_log_mask(CPU_LOG_INT
, "Exception return from AArch64 EL%d to "
1071 "AArch32 EL%d PC 0x%" PRIx32
"\n",
1072 cur_el
, new_el
, env
->regs
[15]);
1075 pstate_write(env
, spsr
);
1076 if (!arm_singlestep_active(env
)) {
1077 env
->pstate
&= ~PSTATE_SS
;
1079 aarch64_restore_sp(env
, new_el
);
1080 env
->pc
= env
->elr_el
[cur_el
];
1081 qemu_log_mask(CPU_LOG_INT
, "Exception return from AArch64 EL%d to "
1082 "AArch64 EL%d PC 0x%" PRIx64
"\n",
1083 cur_el
, new_el
, env
->pc
);
1086 qemu_mutex_lock_iothread();
1087 arm_call_el_change_hook(arm_env_get_cpu(env
));
1088 qemu_mutex_unlock_iothread();
1093 /* Illegal return events of various kinds have architecturally
1094 * mandated behaviour:
1095 * restore NZCV and DAIF from SPSR_ELx
1097 * restore PC from ELR_ELx
1098 * no change to exception level, execution state or stack pointer
1100 env
->pstate
|= PSTATE_IL
;
1101 env
->pc
= env
->elr_el
[cur_el
];
1102 spsr
&= PSTATE_NZCV
| PSTATE_DAIF
;
1103 spsr
|= pstate_read(env
) & ~(PSTATE_NZCV
| PSTATE_DAIF
);
1104 pstate_write(env
, spsr
);
1105 if (!arm_singlestep_active(env
)) {
1106 env
->pstate
&= ~PSTATE_SS
;
1108 qemu_log_mask(LOG_GUEST_ERROR
, "Illegal exception return at EL%d: "
1109 "resuming execution at 0x%" PRIx64
"\n", cur_el
, env
->pc
);
1112 /* Return true if the linked breakpoint entry lbn passes its checks */
1113 static bool linked_bp_matches(ARMCPU
*cpu
, int lbn
)
1115 CPUARMState
*env
= &cpu
->env
;
1116 uint64_t bcr
= env
->cp15
.dbgbcr
[lbn
];
1117 int brps
= extract32(cpu
->dbgdidr
, 24, 4);
1118 int ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
1120 uint32_t contextidr
;
1122 /* Links to unimplemented or non-context aware breakpoints are
1123 * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
1124 * as if linked to an UNKNOWN context-aware breakpoint (in which
1125 * case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
1126 * We choose the former.
1128 if (lbn
> brps
|| lbn
< (brps
- ctx_cmps
)) {
1132 bcr
= env
->cp15
.dbgbcr
[lbn
];
1134 if (extract64(bcr
, 0, 1) == 0) {
1135 /* Linked breakpoint disabled : generate no events */
1139 bt
= extract64(bcr
, 20, 4);
1141 /* We match the whole register even if this is AArch32 using the
1142 * short descriptor format (in which case it holds both PROCID and ASID),
1143 * since we don't implement the optional v7 context ID masking.
1145 contextidr
= extract64(env
->cp15
.contextidr_el
[1], 0, 32);
1148 case 3: /* linked context ID match */
1149 if (arm_current_el(env
) > 1) {
1150 /* Context matches never fire in EL2 or (AArch64) EL3 */
1153 return (contextidr
== extract64(env
->cp15
.dbgbvr
[lbn
], 0, 32));
1154 case 5: /* linked address mismatch (reserved in AArch64) */
1155 case 9: /* linked VMID match (reserved if no EL2) */
1156 case 11: /* linked context ID and VMID match (reserved if no EL2) */
1158 /* Links to Unlinked context breakpoints must generate no
1159 * events; we choose to do the same for reserved values too.
1167 static bool bp_wp_matches(ARMCPU
*cpu
, int n
, bool is_wp
)
1169 CPUARMState
*env
= &cpu
->env
;
1171 int pac
, hmc
, ssc
, wt
, lbn
;
1172 /* Note that for watchpoints the check is against the CPU security
1173 * state, not the S/NS attribute on the offending data access.
1175 bool is_secure
= arm_is_secure(env
);
1176 int access_el
= arm_current_el(env
);
1179 CPUWatchpoint
*wp
= env
->cpu_watchpoint
[n
];
1181 if (!wp
|| !(wp
->flags
& BP_WATCHPOINT_HIT
)) {
1184 cr
= env
->cp15
.dbgwcr
[n
];
1185 if (wp
->hitattrs
.user
) {
1186 /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
1187 * match watchpoints as if they were accesses done at EL0, even if
1188 * the CPU is at EL1 or higher.
1193 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1195 if (!env
->cpu_breakpoint
[n
] || env
->cpu_breakpoint
[n
]->pc
!= pc
) {
1198 cr
= env
->cp15
.dbgbcr
[n
];
1200 /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
1201 * enabled and that the address and access type match; for breakpoints
1202 * we know the address matched; check the remaining fields, including
1203 * linked breakpoints. We rely on WCR and BCR having the same layout
1204 * for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
1205 * Note that some combinations of {PAC, HMC, SSC} are reserved and
1206 * must act either like some valid combination or as if the watchpoint
1207 * were disabled. We choose the former, and use this together with
1208 * the fact that EL3 must always be Secure and EL2 must always be
1209 * Non-Secure to simplify the code slightly compared to the full
1210 * table in the ARM ARM.
1212 pac
= extract64(cr
, 1, 2);
1213 hmc
= extract64(cr
, 13, 1);
1214 ssc
= extract64(cr
, 14, 2);
1232 switch (access_el
) {
1240 if (extract32(pac
, 0, 1) == 0) {
1245 if (extract32(pac
, 1, 1) == 0) {
1250 g_assert_not_reached();
1253 wt
= extract64(cr
, 20, 1);
1254 lbn
= extract64(cr
, 16, 4);
1256 if (wt
&& !linked_bp_matches(cpu
, lbn
)) {
1263 static bool check_watchpoints(ARMCPU
*cpu
)
1265 CPUARMState
*env
= &cpu
->env
;
1268 /* If watchpoints are disabled globally or we can't take debug
1269 * exceptions here then watchpoint firings are ignored.
1271 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1272 || !arm_generate_debug_exceptions(env
)) {
1276 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_watchpoint
); n
++) {
1277 if (bp_wp_matches(cpu
, n
, true)) {
1284 static bool check_breakpoints(ARMCPU
*cpu
)
1286 CPUARMState
*env
= &cpu
->env
;
1289 /* If breakpoints are disabled globally or we can't take debug
1290 * exceptions here then breakpoint firings are ignored.
1292 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1293 || !arm_generate_debug_exceptions(env
)) {
1297 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_breakpoint
); n
++) {
1298 if (bp_wp_matches(cpu
, n
, false)) {
1305 void HELPER(check_breakpoints
)(CPUARMState
*env
)
1307 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1309 if (check_breakpoints(cpu
)) {
1310 HELPER(exception_internal(env
, EXCP_DEBUG
));
1314 bool arm_debug_check_watchpoint(CPUState
*cs
, CPUWatchpoint
*wp
)
1316 /* Called by core code when a CPU watchpoint fires; need to check if this
1317 * is also an architectural watchpoint match.
1319 ARMCPU
*cpu
= ARM_CPU(cs
);
1321 return check_watchpoints(cpu
);
1324 vaddr
arm_adjust_watchpoint_address(CPUState
*cs
, vaddr addr
, int len
)
1326 ARMCPU
*cpu
= ARM_CPU(cs
);
1327 CPUARMState
*env
= &cpu
->env
;
1329 /* In BE32 system mode, target memory is stored byteswapped (on a
1330 * little-endian host system), and by the time we reach here (via an
1331 * opcode helper) the addresses of subword accesses have been adjusted
1332 * to account for that, which means that watchpoints will not match.
1333 * Undo the adjustment here.
1335 if (arm_sctlr_b(env
)) {
1338 } else if (len
== 2) {
1346 void arm_debug_excp_handler(CPUState
*cs
)
1348 /* Called by core code when a watchpoint or breakpoint fires;
1349 * need to check which one and raise the appropriate exception.
1351 ARMCPU
*cpu
= ARM_CPU(cs
);
1352 CPUARMState
*env
= &cpu
->env
;
1353 CPUWatchpoint
*wp_hit
= cs
->watchpoint_hit
;
1356 if (wp_hit
->flags
& BP_CPU
) {
1357 bool wnr
= (wp_hit
->flags
& BP_WATCHPOINT_HIT_WRITE
) != 0;
1358 bool same_el
= arm_debug_target_el(env
) == arm_current_el(env
);
1360 cs
->watchpoint_hit
= NULL
;
1362 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
1363 env
->exception
.vaddress
= wp_hit
->hitaddr
;
1364 raise_exception(env
, EXCP_DATA_ABORT
,
1365 syn_watchpoint(same_el
, 0, wnr
),
1366 arm_debug_target_el(env
));
1369 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1370 bool same_el
= (arm_debug_target_el(env
) == arm_current_el(env
));
1372 /* (1) GDB breakpoints should be handled first.
1373 * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
1374 * since singlestep is also done by generating a debug internal
1377 if (cpu_breakpoint_test(cs
, pc
, BP_GDB
)
1378 || !cpu_breakpoint_test(cs
, pc
, BP_CPU
)) {
1382 env
->exception
.fsr
= arm_debug_exception_fsr(env
);
1383 /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
1384 * values to the guest that it shouldn't be able to see at its
1385 * exception/security level.
1387 env
->exception
.vaddress
= 0;
1388 raise_exception(env
, EXCP_PREFETCH_ABORT
,
1389 syn_breakpoint(same_el
),
1390 arm_debug_target_el(env
));
1394 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
1395 The only way to do that in TCG is a conditional branch, which clobbers
1396 all our temporaries. For now implement these as helper functions. */
1398 /* Similarly for variable shift instructions. */
1400 uint32_t HELPER(shl_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1402 int shift
= i
& 0xff;
1409 } else if (shift
!= 0) {
1410 env
->CF
= (x
>> (32 - shift
)) & 1;
1416 uint32_t HELPER(shr_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1418 int shift
= i
& 0xff;
1421 env
->CF
= (x
>> 31) & 1;
1425 } else if (shift
!= 0) {
1426 env
->CF
= (x
>> (shift
- 1)) & 1;
1432 uint32_t HELPER(sar_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1434 int shift
= i
& 0xff;
1436 env
->CF
= (x
>> 31) & 1;
1437 return (int32_t)x
>> 31;
1438 } else if (shift
!= 0) {
1439 env
->CF
= (x
>> (shift
- 1)) & 1;
1440 return (int32_t)x
>> shift
;
1445 uint32_t HELPER(ror_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1449 shift
= shift1
& 0x1f;
1452 env
->CF
= (x
>> 31) & 1;
1455 env
->CF
= (x
>> (shift
- 1)) & 1;
1456 return ((uint32_t)x
>> shift
) | (x
<< (32 - shift
));