4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
22 #include "exec/helper-proto.h"
23 #include "internals.h"
24 #include "exec/exec-all.h"
25 #include "exec/cpu_ldst.h"
28 #define SIGNBIT (uint32_t)0x80000000
29 #define SIGNBIT64 ((uint64_t)1 << 63)
31 int exception_target_el(CPUARMState
*env
)
33 int target_el
= MAX(1, arm_current_el(env
));
36 * No such thing as secure EL1 if EL3 is aarch32,
37 * so update the target EL to EL3 in this case.
39 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3) && target_el
== 1) {
46 void raise_exception(CPUARMState
*env
, uint32_t excp
,
47 uint32_t syndrome
, uint32_t target_el
)
49 CPUState
*cs
= env_cpu(env
);
51 if (target_el
== 1 && (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
53 * Redirect NS EL1 exceptions to NS EL2. These are reported with
54 * their original syndrome register value, with the exception of
55 * SIMD/FP access traps, which are reported as uncategorized
56 * (see DDI0478C.a D1.10.4)
59 if (syn_get_ec(syndrome
) == EC_ADVSIMDFPACCESSTRAP
) {
60 syndrome
= syn_uncategorized();
64 assert(!excp_is_internal(excp
));
65 cs
->exception_index
= excp
;
66 env
->exception
.syndrome
= syndrome
;
67 env
->exception
.target_el
= target_el
;
71 void raise_exception_ra(CPUARMState
*env
, uint32_t excp
, uint32_t syndrome
,
72 uint32_t target_el
, uintptr_t ra
)
74 CPUState
*cs
= env_cpu(env
);
77 * restore_state_to_opc() will set env->exception.syndrome, so
78 * we must restore CPU state here before setting the syndrome
79 * the caller passed us, and cannot use cpu_loop_exit_restore().
81 cpu_restore_state(cs
, ra
, true);
82 raise_exception(env
, excp
, syndrome
, target_el
);
85 uint64_t HELPER(neon_tbl
)(CPUARMState
*env
, uint32_t desc
,
86 uint64_t ireg
, uint64_t def
)
88 uint64_t tmp
, val
= 0;
89 uint32_t maxindex
= ((desc
& 3) + 1) * 8;
90 uint32_t base_reg
= desc
>> 2;
91 uint32_t shift
, index
, reg
;
93 for (shift
= 0; shift
< 64; shift
+= 8) {
94 index
= (ireg
>> shift
) & 0xff;
95 if (index
< maxindex
) {
96 reg
= base_reg
+ (index
>> 3);
97 tmp
= *aa32_vfp_dreg(env
, reg
);
98 tmp
= ((tmp
>> ((index
& 7) << 3)) & 0xff) << shift
;
100 tmp
= def
& (0xffull
<< shift
);
107 void HELPER(v8m_stackcheck
)(CPUARMState
*env
, uint32_t newvalue
)
110 * Perform the v8M stack limit check for SP updates from translated code,
111 * raising an exception if the limit is breached.
113 if (newvalue
< v7m_sp_limit(env
)) {
115 * Stack limit exceptions are a rare case, so rather than syncing
116 * PC/condbits before the call, we use raise_exception_ra() so
117 * that cpu_restore_state() will sort them out.
119 raise_exception_ra(env
, EXCP_STKOF
, 0, 1, GETPC());
123 uint32_t HELPER(add_setq
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
125 uint32_t res
= a
+ b
;
126 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
))
131 uint32_t HELPER(add_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
133 uint32_t res
= a
+ b
;
134 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
)) {
136 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
141 uint32_t HELPER(sub_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
143 uint32_t res
= a
- b
;
144 if (((res
^ a
) & SIGNBIT
) && ((a
^ b
) & SIGNBIT
)) {
146 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
151 uint32_t HELPER(add_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
153 uint32_t res
= a
+ b
;
161 uint32_t HELPER(sub_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
163 uint32_t res
= a
- b
;
171 /* Signed saturation. */
172 static inline uint32_t do_ssat(CPUARMState
*env
, int32_t val
, int shift
)
178 mask
= (1u << shift
) - 1;
182 } else if (top
< -1) {
189 /* Unsigned saturation. */
190 static inline uint32_t do_usat(CPUARMState
*env
, int32_t val
, int shift
)
194 max
= (1u << shift
) - 1;
198 } else if (val
> max
) {
205 /* Signed saturate. */
206 uint32_t HELPER(ssat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
208 return do_ssat(env
, x
, shift
);
211 /* Dual halfword signed saturate. */
212 uint32_t HELPER(ssat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
216 res
= (uint16_t)do_ssat(env
, (int16_t)x
, shift
);
217 res
|= do_ssat(env
, ((int32_t)x
) >> 16, shift
) << 16;
221 /* Unsigned saturate. */
222 uint32_t HELPER(usat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
224 return do_usat(env
, x
, shift
);
227 /* Dual halfword unsigned saturate. */
228 uint32_t HELPER(usat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
232 res
= (uint16_t)do_usat(env
, (int16_t)x
, shift
);
233 res
|= do_usat(env
, ((int32_t)x
) >> 16, shift
) << 16;
237 void HELPER(setend
)(CPUARMState
*env
)
239 env
->uncached_cpsr
^= CPSR_E
;
240 arm_rebuild_hflags(env
);
243 void HELPER(check_bxj_trap
)(CPUARMState
*env
, uint32_t rm
)
246 * Only called if in NS EL0 or EL1 for a BXJ for a v7A CPU;
247 * check if HSTR.TJDBX means we need to trap to EL2.
249 if (env
->cp15
.hstr_el2
& HSTR_TJDBX
) {
251 * We know the condition code check passed, so take the IMPDEF
252 * choice to always report CV=1 COND 0xe
254 uint32_t syn
= syn_bxjtrap(1, 0xe, rm
);
255 raise_exception_ra(env
, EXCP_HYP_TRAP
, syn
, 2, GETPC());
259 #ifndef CONFIG_USER_ONLY
260 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
261 * The function returns the target EL (1-3) if the instruction is to be trapped;
262 * otherwise it returns 0 indicating it is not trapped.
264 static inline int check_wfx_trap(CPUARMState
*env
, bool is_wfe
)
266 int cur_el
= arm_current_el(env
);
269 if (arm_feature(env
, ARM_FEATURE_M
)) {
270 /* M profile cores can never trap WFI/WFE. */
274 /* If we are currently in EL0 then we need to check if SCTLR is set up for
275 * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
277 if (cur_el
< 1 && arm_feature(env
, ARM_FEATURE_V8
)) {
280 mask
= is_wfe
? SCTLR_nTWE
: SCTLR_nTWI
;
281 if (arm_is_secure_below_el3(env
) && !arm_el_is_aa64(env
, 3)) {
282 /* Secure EL0 and Secure PL1 is at EL3 */
288 if (!(env
->cp15
.sctlr_el
[target_el
] & mask
)) {
293 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
294 * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
295 * bits will be zero indicating no trap.
298 mask
= is_wfe
? HCR_TWE
: HCR_TWI
;
299 if (arm_hcr_el2_eff(env
) & mask
) {
304 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
306 mask
= (is_wfe
) ? SCR_TWE
: SCR_TWI
;
307 if (env
->cp15
.scr_el3
& mask
) {
316 void HELPER(wfi
)(CPUARMState
*env
, uint32_t insn_len
)
318 #ifdef CONFIG_USER_ONLY
320 * WFI in the user-mode emulator is technically permitted but not
321 * something any real-world code would do. AArch64 Linux kernels
322 * trap it via SCTRL_EL1.nTWI and make it an (expensive) NOP;
323 * AArch32 kernels don't trap it so it will delay a bit.
324 * For QEMU, make it NOP here, because trying to raise EXCP_HLT
325 * would trigger an abort.
329 CPUState
*cs
= env_cpu(env
);
330 int target_el
= check_wfx_trap(env
, false);
332 if (cpu_has_work(cs
)) {
333 /* Don't bother to go into our "low power state" if
334 * we would just wake up immediately.
343 env
->regs
[15] -= insn_len
;
346 raise_exception(env
, EXCP_UDEF
, syn_wfx(1, 0xe, 0, insn_len
== 2),
350 cs
->exception_index
= EXCP_HLT
;
356 void HELPER(wfe
)(CPUARMState
*env
)
358 /* This is a hint instruction that is semantically different
359 * from YIELD even though we currently implement it identically.
360 * Don't actually halt the CPU, just yield back to top
361 * level loop. This is not going into a "low power state"
362 * (ie halting until some event occurs), so we never take
363 * a configurable trap to a different exception level.
368 void HELPER(yield
)(CPUARMState
*env
)
370 CPUState
*cs
= env_cpu(env
);
372 /* This is a non-trappable hint instruction that generally indicates
373 * that the guest is currently busy-looping. Yield control back to the
374 * top level loop so that a more deserving VCPU has a chance to run.
376 cs
->exception_index
= EXCP_YIELD
;
380 /* Raise an internal-to-QEMU exception. This is limited to only
381 * those EXCP values which are special cases for QEMU to interrupt
382 * execution and not to be used for exceptions which are passed to
383 * the guest (those must all have syndrome information and thus should
384 * use exception_with_syndrome*).
386 void HELPER(exception_internal
)(CPUARMState
*env
, uint32_t excp
)
388 CPUState
*cs
= env_cpu(env
);
390 assert(excp_is_internal(excp
));
391 cs
->exception_index
= excp
;
395 /* Raise an exception with the specified syndrome register value */
396 void HELPER(exception_with_syndrome_el
)(CPUARMState
*env
, uint32_t excp
,
397 uint32_t syndrome
, uint32_t target_el
)
399 raise_exception(env
, excp
, syndrome
, target_el
);
402 uint32_t HELPER(cpsr_read
)(CPUARMState
*env
)
404 return cpsr_read(env
) & ~CPSR_EXEC
;
407 void HELPER(cpsr_write
)(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
409 cpsr_write(env
, val
, mask
, CPSRWriteByInstr
);
410 /* TODO: Not all cpsr bits are relevant to hflags. */
411 arm_rebuild_hflags(env
);
414 /* Write the CPSR for a 32-bit exception return */
415 void HELPER(cpsr_write_eret
)(CPUARMState
*env
, uint32_t val
)
419 qemu_mutex_lock_iothread();
420 arm_call_pre_el_change_hook(env_archcpu(env
));
421 qemu_mutex_unlock_iothread();
423 mask
= aarch32_cpsr_valid_mask(env
->features
, &env_archcpu(env
)->isar
);
424 cpsr_write(env
, val
, mask
, CPSRWriteExceptionReturn
);
426 /* Generated code has already stored the new PC value, but
427 * without masking out its low bits, because which bits need
428 * masking depends on whether we're returning to Thumb or ARM
429 * state. Do the masking now.
431 env
->regs
[15] &= (env
->thumb
? ~1 : ~3);
432 arm_rebuild_hflags(env
);
434 qemu_mutex_lock_iothread();
435 arm_call_el_change_hook(env_archcpu(env
));
436 qemu_mutex_unlock_iothread();
439 /* Access to user mode registers from privileged modes. */
440 uint32_t HELPER(get_user_reg
)(CPUARMState
*env
, uint32_t regno
)
445 val
= env
->banked_r13
[BANK_USRSYS
];
446 } else if (regno
== 14) {
447 val
= env
->banked_r14
[BANK_USRSYS
];
448 } else if (regno
>= 8
449 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
450 val
= env
->usr_regs
[regno
- 8];
452 val
= env
->regs
[regno
];
457 void HELPER(set_user_reg
)(CPUARMState
*env
, uint32_t regno
, uint32_t val
)
460 env
->banked_r13
[BANK_USRSYS
] = val
;
461 } else if (regno
== 14) {
462 env
->banked_r14
[BANK_USRSYS
] = val
;
463 } else if (regno
>= 8
464 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
465 env
->usr_regs
[regno
- 8] = val
;
467 env
->regs
[regno
] = val
;
471 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
473 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
476 env
->banked_r13
[bank_number(mode
)] = val
;
480 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
482 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_SYS
) {
483 /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
484 * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
486 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
487 exception_target_el(env
));
490 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
491 return env
->regs
[13];
493 return env
->banked_r13
[bank_number(mode
)];
497 static void msr_mrs_banked_exc_checks(CPUARMState
*env
, uint32_t tgtmode
,
500 /* Raise an exception if the requested access is one of the UNPREDICTABLE
501 * cases; otherwise return. This broadly corresponds to the pseudocode
502 * BankedRegisterAccessValid() and SPSRAccessValid(),
503 * except that we have already handled some cases at translate time.
505 int curmode
= env
->uncached_cpsr
& CPSR_M
;
508 /* ELR_Hyp: a special case because access from tgtmode is OK */
509 if (curmode
!= ARM_CPU_MODE_HYP
&& curmode
!= ARM_CPU_MODE_MON
) {
515 if (curmode
== tgtmode
) {
519 if (tgtmode
== ARM_CPU_MODE_USR
) {
522 if (curmode
!= ARM_CPU_MODE_FIQ
) {
527 if (curmode
== ARM_CPU_MODE_SYS
) {
532 if (curmode
== ARM_CPU_MODE_HYP
|| curmode
== ARM_CPU_MODE_SYS
) {
541 if (tgtmode
== ARM_CPU_MODE_HYP
) {
542 /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
543 if (curmode
!= ARM_CPU_MODE_MON
) {
551 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
552 exception_target_el(env
));
555 void HELPER(msr_banked
)(CPUARMState
*env
, uint32_t value
, uint32_t tgtmode
,
558 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
562 env
->banked_spsr
[bank_number(tgtmode
)] = value
;
564 case 17: /* ELR_Hyp */
565 env
->elr_el
[2] = value
;
568 env
->banked_r13
[bank_number(tgtmode
)] = value
;
571 env
->banked_r14
[r14_bank_number(tgtmode
)] = value
;
575 case ARM_CPU_MODE_USR
:
576 env
->usr_regs
[regno
- 8] = value
;
578 case ARM_CPU_MODE_FIQ
:
579 env
->fiq_regs
[regno
- 8] = value
;
582 g_assert_not_reached();
586 g_assert_not_reached();
590 uint32_t HELPER(mrs_banked
)(CPUARMState
*env
, uint32_t tgtmode
, uint32_t regno
)
592 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
596 return env
->banked_spsr
[bank_number(tgtmode
)];
597 case 17: /* ELR_Hyp */
598 return env
->elr_el
[2];
600 return env
->banked_r13
[bank_number(tgtmode
)];
602 return env
->banked_r14
[r14_bank_number(tgtmode
)];
605 case ARM_CPU_MODE_USR
:
606 return env
->usr_regs
[regno
- 8];
607 case ARM_CPU_MODE_FIQ
:
608 return env
->fiq_regs
[regno
- 8];
610 g_assert_not_reached();
613 g_assert_not_reached();
617 void HELPER(access_check_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t syndrome
,
620 ARMCPU
*cpu
= env_archcpu(env
);
621 const ARMCPRegInfo
*ri
= rip
;
622 CPAccessResult res
= CP_ACCESS_OK
;
625 if (arm_feature(env
, ARM_FEATURE_XSCALE
) && ri
->cp
< 14
626 && extract32(env
->cp15
.c15_cpar
, ri
->cp
, 1) == 0) {
627 res
= CP_ACCESS_TRAP
;
632 * Check for an EL2 trap due to HSTR_EL2. We expect EL0 accesses
633 * to sysregs non accessible at EL0 to have UNDEF-ed already.
635 if (!is_a64(env
) && arm_current_el(env
) < 2 && ri
->cp
== 15 &&
636 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
637 uint32_t mask
= 1 << ri
->crn
;
639 if (ri
->type
& ARM_CP_64BIT
) {
643 /* T4 and T14 are RES0 */
644 mask
&= ~((1 << 4) | (1 << 14));
646 if (env
->cp15
.hstr_el2
& mask
) {
647 res
= CP_ACCESS_TRAP_EL2
;
653 res
= ri
->accessfn(env
, ri
, isread
);
655 if (likely(res
== CP_ACCESS_OK
)) {
660 switch (res
& ~CP_ACCESS_EL_MASK
) {
663 case CP_ACCESS_TRAP_UNCATEGORIZED
:
664 if (cpu_isar_feature(aa64_ids
, cpu
) && isread
&&
665 arm_cpreg_in_idspace(ri
)) {
667 * FEAT_IDST says this should be reported as EC_SYSTEMREGISTERTRAP,
668 * not EC_UNCATEGORIZED
672 syndrome
= syn_uncategorized();
675 g_assert_not_reached();
678 target_el
= res
& CP_ACCESS_EL_MASK
;
681 target_el
= exception_target_el(env
);
684 assert(arm_current_el(env
) != 3);
685 assert(arm_is_el2_enabled(env
));
688 assert(arm_feature(env
, ARM_FEATURE_EL3
));
691 /* No "direct" traps to EL1 */
692 g_assert_not_reached();
695 raise_exception(env
, EXCP_UDEF
, syndrome
, target_el
);
698 void HELPER(set_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t value
)
700 const ARMCPRegInfo
*ri
= rip
;
702 if (ri
->type
& ARM_CP_IO
) {
703 qemu_mutex_lock_iothread();
704 ri
->writefn(env
, ri
, value
);
705 qemu_mutex_unlock_iothread();
707 ri
->writefn(env
, ri
, value
);
711 uint32_t HELPER(get_cp_reg
)(CPUARMState
*env
, void *rip
)
713 const ARMCPRegInfo
*ri
= rip
;
716 if (ri
->type
& ARM_CP_IO
) {
717 qemu_mutex_lock_iothread();
718 res
= ri
->readfn(env
, ri
);
719 qemu_mutex_unlock_iothread();
721 res
= ri
->readfn(env
, ri
);
727 void HELPER(set_cp_reg64
)(CPUARMState
*env
, void *rip
, uint64_t value
)
729 const ARMCPRegInfo
*ri
= rip
;
731 if (ri
->type
& ARM_CP_IO
) {
732 qemu_mutex_lock_iothread();
733 ri
->writefn(env
, ri
, value
);
734 qemu_mutex_unlock_iothread();
736 ri
->writefn(env
, ri
, value
);
740 uint64_t HELPER(get_cp_reg64
)(CPUARMState
*env
, void *rip
)
742 const ARMCPRegInfo
*ri
= rip
;
745 if (ri
->type
& ARM_CP_IO
) {
746 qemu_mutex_lock_iothread();
747 res
= ri
->readfn(env
, ri
);
748 qemu_mutex_unlock_iothread();
750 res
= ri
->readfn(env
, ri
);
756 void HELPER(pre_hvc
)(CPUARMState
*env
)
758 ARMCPU
*cpu
= env_archcpu(env
);
759 int cur_el
= arm_current_el(env
);
760 /* FIXME: Use actual secure state. */
764 if (arm_is_psci_call(cpu
, EXCP_HVC
)) {
765 /* If PSCI is enabled and this looks like a valid PSCI call then
766 * that overrides the architecturally mandated HVC behaviour.
771 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
772 /* If EL2 doesn't exist, HVC always UNDEFs */
774 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
775 /* EL3.HCE has priority over EL2.HCD. */
776 undef
= !(env
->cp15
.scr_el3
& SCR_HCE
);
778 undef
= env
->cp15
.hcr_el2
& HCR_HCD
;
781 /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
782 * For ARMv8/AArch64, HVC is allowed in EL3.
783 * Note that we've already trapped HVC from EL0 at translation
786 if (secure
&& (!is_a64(env
) || cur_el
== 1)) {
791 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
792 exception_target_el(env
));
796 void HELPER(pre_smc
)(CPUARMState
*env
, uint32_t syndrome
)
798 ARMCPU
*cpu
= env_archcpu(env
);
799 int cur_el
= arm_current_el(env
);
800 bool secure
= arm_is_secure(env
);
801 bool smd_flag
= env
->cp15
.scr_el3
& SCR_SMD
;
804 * SMC behaviour is summarized in the following table.
805 * This helper handles the "Trap to EL2" and "Undef insn" cases.
806 * The "Trap to EL3" and "PSCI call" cases are handled in the exception
809 * -> ARM_FEATURE_EL3 and !SMD
810 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
812 * Conduit SMC, valid call Trap to EL2 PSCI Call
813 * Conduit SMC, inval call Trap to EL2 Trap to EL3
814 * Conduit not SMC Trap to EL2 Trap to EL3
817 * -> ARM_FEATURE_EL3 and SMD
818 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
820 * Conduit SMC, valid call Trap to EL2 PSCI Call
821 * Conduit SMC, inval call Trap to EL2 Undef insn
822 * Conduit not SMC Trap to EL2 Undef insn
825 * -> !ARM_FEATURE_EL3
826 * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
828 * Conduit SMC, valid call Trap to EL2 PSCI Call
829 * Conduit SMC, inval call Trap to EL2 Undef insn
830 * Conduit not SMC Undef insn Undef insn
833 /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
834 * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
835 * extensions, SMD only applies to NS state.
836 * On ARMv7 without the Virtualization extensions, the SMD bit
837 * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
838 * so we need not special case this here.
840 bool smd
= arm_feature(env
, ARM_FEATURE_AARCH64
) ? smd_flag
841 : smd_flag
&& !secure
;
843 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
844 cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
845 /* If we have no EL3 then SMC always UNDEFs and can't be
846 * trapped to EL2. PSCI-via-SMC is a sort of ersatz EL3
847 * firmware within QEMU, and we want an EL2 guest to be able
848 * to forbid its EL1 from making PSCI calls into QEMU's
849 * "firmware" via HCR.TSC, so for these purposes treat
850 * PSCI-via-SMC as implying an EL3.
851 * This handles the very last line of the previous table.
853 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
854 exception_target_el(env
));
857 if (cur_el
== 1 && (arm_hcr_el2_eff(env
) & HCR_TSC
)) {
858 /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
859 * We also want an EL2 guest to be able to forbid its EL1 from
860 * making PSCI calls into QEMU's "firmware" via HCR.TSC.
861 * This handles all the "Trap to EL2" cases of the previous table.
863 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);
866 /* Catch the two remaining "Undef insn" cases of the previous table:
867 * - PSCI conduit is SMC but we don't have a valid PCSI call,
868 * - We don't have EL3 or SMD is set.
870 if (!arm_is_psci_call(cpu
, EXCP_SMC
) &&
871 (smd
|| !arm_feature(env
, ARM_FEATURE_EL3
))) {
872 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
873 exception_target_el(env
));
877 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
878 The only way to do that in TCG is a conditional branch, which clobbers
879 all our temporaries. For now implement these as helper functions. */
881 /* Similarly for variable shift instructions. */
883 uint32_t HELPER(shl_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
885 int shift
= i
& 0xff;
892 } else if (shift
!= 0) {
893 env
->CF
= (x
>> (32 - shift
)) & 1;
899 uint32_t HELPER(shr_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
901 int shift
= i
& 0xff;
904 env
->CF
= (x
>> 31) & 1;
908 } else if (shift
!= 0) {
909 env
->CF
= (x
>> (shift
- 1)) & 1;
915 uint32_t HELPER(sar_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
917 int shift
= i
& 0xff;
919 env
->CF
= (x
>> 31) & 1;
920 return (int32_t)x
>> 31;
921 } else if (shift
!= 0) {
922 env
->CF
= (x
>> (shift
- 1)) & 1;
923 return (int32_t)x
>> shift
;
928 uint32_t HELPER(ror_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
932 shift
= shift1
& 0x1f;
935 env
->CF
= (x
>> 31) & 1;
938 env
->CF
= (x
>> (shift
- 1)) & 1;
939 return ((uint32_t)x
>> shift
) | (x
<< (32 - shift
));
943 void HELPER(probe_access
)(CPUARMState
*env
, target_ulong ptr
,
944 uint32_t access_type
, uint32_t mmu_idx
,
947 uint32_t in_page
= -((uint32_t)ptr
| TARGET_PAGE_SIZE
);
948 uintptr_t ra
= GETPC();
950 if (likely(size
<= in_page
)) {
951 probe_access(env
, ptr
, size
, access_type
, mmu_idx
, ra
);
953 probe_access(env
, ptr
, in_page
, access_type
, mmu_idx
, ra
);
954 probe_access(env
, ptr
+ in_page
, size
- in_page
,
955 access_type
, mmu_idx
, ra
);
960 * This function corresponds to AArch64.vESBOperation().
961 * Note that the AArch32 version is not functionally different.
963 void HELPER(vesb
)(CPUARMState
*env
)
966 * The EL2Enabled() check is done inside arm_hcr_el2_eff,
967 * and will return HCR_EL2.VSE == 0, so nothing happens.
969 uint64_t hcr
= arm_hcr_el2_eff(env
);
970 bool enabled
= !(hcr
& HCR_TGE
) && (hcr
& HCR_AMO
);
971 bool pending
= enabled
&& (hcr
& HCR_VSE
);
972 bool masked
= (env
->daif
& PSTATE_A
);
974 /* If VSE pending and masked, defer the exception. */
975 if (pending
&& masked
) {
978 if (arm_el_is_aa64(env
, 1)) {
979 /* Copy across IDS and ISS from VSESR. */
980 syndrome
= env
->cp15
.vsesr_el2
& 0x1ffffff;
982 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
};
984 if (extended_addresses_enabled(env
)) {
985 syndrome
= arm_fi_to_lfsc(&fi
);
987 syndrome
= arm_fi_to_sfsc(&fi
);
989 /* Copy across AET and ExT from VSESR. */
990 syndrome
|= env
->cp15
.vsesr_el2
& 0xd000;
993 /* Set VDISR_EL2.A along with the syndrome. */
994 env
->cp15
.vdisr_el2
= syndrome
| (1u << 31);
996 /* Clear pending virtual SError */
997 env
->cp15
.hcr_el2
&= ~HCR_VSE
;
998 cpu_reset_interrupt(env_cpu(env
), CPU_INTERRUPT_VSERR
);