2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
33 #include "qemu-common.h"
39 //#define MIPS_DEBUG_DISAS
40 //#define MIPS_DEBUG_SIGN_EXTENSIONS
42 /* MIPS major opcodes */
43 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
46 /* indirect opcode tables */
47 OPC_SPECIAL
= (0x00 << 26),
48 OPC_REGIMM
= (0x01 << 26),
49 OPC_CP0
= (0x10 << 26),
50 OPC_CP1
= (0x11 << 26),
51 OPC_CP2
= (0x12 << 26),
52 OPC_CP3
= (0x13 << 26),
53 OPC_SPECIAL2
= (0x1C << 26),
54 OPC_SPECIAL3
= (0x1F << 26),
55 /* arithmetic with immediate */
56 OPC_ADDI
= (0x08 << 26),
57 OPC_ADDIU
= (0x09 << 26),
58 OPC_SLTI
= (0x0A << 26),
59 OPC_SLTIU
= (0x0B << 26),
60 /* logic with immediate */
61 OPC_ANDI
= (0x0C << 26),
62 OPC_ORI
= (0x0D << 26),
63 OPC_XORI
= (0x0E << 26),
64 OPC_LUI
= (0x0F << 26),
65 /* arithmetic with immediate */
66 OPC_DADDI
= (0x18 << 26),
67 OPC_DADDIU
= (0x19 << 26),
68 /* Jump and branches */
70 OPC_JAL
= (0x03 << 26),
71 OPC_JALS
= OPC_JAL
| 0x5,
72 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
73 OPC_BEQL
= (0x14 << 26),
74 OPC_BNE
= (0x05 << 26),
75 OPC_BNEL
= (0x15 << 26),
76 OPC_BLEZ
= (0x06 << 26),
77 OPC_BLEZL
= (0x16 << 26),
78 OPC_BGTZ
= (0x07 << 26),
79 OPC_BGTZL
= (0x17 << 26),
80 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
81 OPC_JALXS
= OPC_JALX
| 0x5,
83 OPC_LDL
= (0x1A << 26),
84 OPC_LDR
= (0x1B << 26),
85 OPC_LB
= (0x20 << 26),
86 OPC_LH
= (0x21 << 26),
87 OPC_LWL
= (0x22 << 26),
88 OPC_LW
= (0x23 << 26),
89 OPC_LWPC
= OPC_LW
| 0x5,
90 OPC_LBU
= (0x24 << 26),
91 OPC_LHU
= (0x25 << 26),
92 OPC_LWR
= (0x26 << 26),
93 OPC_LWU
= (0x27 << 26),
94 OPC_SB
= (0x28 << 26),
95 OPC_SH
= (0x29 << 26),
96 OPC_SWL
= (0x2A << 26),
97 OPC_SW
= (0x2B << 26),
98 OPC_SDL
= (0x2C << 26),
99 OPC_SDR
= (0x2D << 26),
100 OPC_SWR
= (0x2E << 26),
101 OPC_LL
= (0x30 << 26),
102 OPC_LLD
= (0x34 << 26),
103 OPC_LD
= (0x37 << 26),
104 OPC_LDPC
= OPC_LD
| 0x5,
105 OPC_SC
= (0x38 << 26),
106 OPC_SCD
= (0x3C << 26),
107 OPC_SD
= (0x3F << 26),
108 /* Floating point load/store */
109 OPC_LWC1
= (0x31 << 26),
110 OPC_LWC2
= (0x32 << 26),
111 OPC_LDC1
= (0x35 << 26),
112 OPC_LDC2
= (0x36 << 26),
113 OPC_SWC1
= (0x39 << 26),
114 OPC_SWC2
= (0x3A << 26),
115 OPC_SDC1
= (0x3D << 26),
116 OPC_SDC2
= (0x3E << 26),
117 /* MDMX ASE specific */
118 OPC_MDMX
= (0x1E << 26),
119 /* Cache and prefetch */
120 OPC_CACHE
= (0x2F << 26),
121 OPC_PREF
= (0x33 << 26),
122 /* Reserved major opcode */
123 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
126 /* MIPS special opcodes */
127 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
131 OPC_SLL
= 0x00 | OPC_SPECIAL
,
132 /* NOP is SLL r0, r0, 0 */
133 /* SSNOP is SLL r0, r0, 1 */
134 /* EHB is SLL r0, r0, 3 */
135 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
136 OPC_ROTR
= OPC_SRL
| (1 << 21),
137 OPC_SRA
= 0x03 | OPC_SPECIAL
,
138 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
139 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
140 OPC_ROTRV
= OPC_SRLV
| (1 << 6),
141 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
142 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
143 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
144 OPC_DROTRV
= OPC_DSRLV
| (1 << 6),
145 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
146 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
147 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
148 OPC_DROTR
= OPC_DSRL
| (1 << 21),
149 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
150 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
151 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
152 OPC_DROTR32
= OPC_DSRL32
| (1 << 21),
153 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
154 /* Multiplication / division */
155 OPC_MULT
= 0x18 | OPC_SPECIAL
,
156 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
157 OPC_DIV
= 0x1A | OPC_SPECIAL
,
158 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
159 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
160 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
161 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
162 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
163 /* 2 registers arithmetic / logic */
164 OPC_ADD
= 0x20 | OPC_SPECIAL
,
165 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
166 OPC_SUB
= 0x22 | OPC_SPECIAL
,
167 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
168 OPC_AND
= 0x24 | OPC_SPECIAL
,
169 OPC_OR
= 0x25 | OPC_SPECIAL
,
170 OPC_XOR
= 0x26 | OPC_SPECIAL
,
171 OPC_NOR
= 0x27 | OPC_SPECIAL
,
172 OPC_SLT
= 0x2A | OPC_SPECIAL
,
173 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
174 OPC_DADD
= 0x2C | OPC_SPECIAL
,
175 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
176 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
177 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
179 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
180 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
181 OPC_JALRC
= OPC_JALR
| (0x5 << 6),
182 OPC_JALRS
= 0x10 | OPC_SPECIAL
| (0x5 << 6),
184 OPC_TGE
= 0x30 | OPC_SPECIAL
,
185 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
186 OPC_TLT
= 0x32 | OPC_SPECIAL
,
187 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
188 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
189 OPC_TNE
= 0x36 | OPC_SPECIAL
,
190 /* HI / LO registers load & stores */
191 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
192 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
193 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
194 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
195 /* Conditional moves */
196 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
197 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
199 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
202 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* unofficial */
203 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
204 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
205 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* unofficial */
206 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
208 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
209 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
210 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
211 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
212 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
213 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
214 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
217 /* Multiplication variants of the vr54xx. */
218 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
221 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
222 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
223 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
224 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
225 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
226 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
227 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
228 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
229 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
230 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
231 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
232 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
233 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
234 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
237 /* REGIMM (rt field) opcodes */
238 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
241 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
242 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
243 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
244 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
245 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
246 OPC_BLTZALS
= OPC_BLTZAL
| 0x5, /* microMIPS */
247 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
248 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
249 OPC_BGEZALS
= OPC_BGEZAL
| 0x5, /* microMIPS */
250 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
251 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
252 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
253 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
254 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
255 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
256 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
257 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
260 /* Special2 opcodes */
261 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
264 /* Multiply & xxx operations */
265 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
266 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
267 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
268 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
269 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
271 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
272 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
273 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
274 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
276 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
279 /* Special3 opcodes */
280 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
283 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
284 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
285 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
286 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
287 OPC_INS
= 0x04 | OPC_SPECIAL3
,
288 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
289 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
290 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
291 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
292 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
293 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
294 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
295 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
299 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
302 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
303 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
304 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
308 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
311 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
312 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
315 /* Coprocessor 0 (rs field) */
316 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
319 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
320 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
321 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
322 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
323 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
324 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
325 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
326 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
327 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
328 OPC_C0
= (0x10 << 21) | OPC_CP0
,
329 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
330 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
334 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
337 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
338 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
339 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
340 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
341 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
342 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
345 /* Coprocessor 0 (with rs == C0) */
346 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
349 OPC_TLBR
= 0x01 | OPC_C0
,
350 OPC_TLBWI
= 0x02 | OPC_C0
,
351 OPC_TLBWR
= 0x06 | OPC_C0
,
352 OPC_TLBP
= 0x08 | OPC_C0
,
353 OPC_RFE
= 0x10 | OPC_C0
,
354 OPC_ERET
= 0x18 | OPC_C0
,
355 OPC_DERET
= 0x1F | OPC_C0
,
356 OPC_WAIT
= 0x20 | OPC_C0
,
359 /* Coprocessor 1 (rs field) */
360 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
362 /* Values for the fmt field in FP instructions */
364 /* 0 - 15 are reserved */
365 FMT_S
= 16, /* single fp */
366 FMT_D
= 17, /* double fp */
367 FMT_E
= 18, /* extended fp */
368 FMT_Q
= 19, /* quad fp */
369 FMT_W
= 20, /* 32-bit fixed */
370 FMT_L
= 21, /* 64-bit fixed */
371 FMT_PS
= 22, /* paired single fp */
372 /* 23 - 31 are reserved */
376 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
377 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
378 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
379 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
380 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
381 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
382 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
383 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
384 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
385 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
386 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
387 OPC_S_FMT
= (FMT_S
<< 21) | OPC_CP1
,
388 OPC_D_FMT
= (FMT_D
<< 21) | OPC_CP1
,
389 OPC_E_FMT
= (FMT_E
<< 21) | OPC_CP1
,
390 OPC_Q_FMT
= (FMT_Q
<< 21) | OPC_CP1
,
391 OPC_W_FMT
= (FMT_W
<< 21) | OPC_CP1
,
392 OPC_L_FMT
= (FMT_L
<< 21) | OPC_CP1
,
393 OPC_PS_FMT
= (FMT_PS
<< 21) | OPC_CP1
,
396 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
397 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
400 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
401 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
402 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
403 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
407 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
408 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
412 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
413 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
416 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
419 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
420 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
421 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
422 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
423 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
424 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
425 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
426 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
427 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
430 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
433 OPC_LWXC1
= 0x00 | OPC_CP3
,
434 OPC_LDXC1
= 0x01 | OPC_CP3
,
435 OPC_LUXC1
= 0x05 | OPC_CP3
,
436 OPC_SWXC1
= 0x08 | OPC_CP3
,
437 OPC_SDXC1
= 0x09 | OPC_CP3
,
438 OPC_SUXC1
= 0x0D | OPC_CP3
,
439 OPC_PREFX
= 0x0F | OPC_CP3
,
440 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
441 OPC_MADD_S
= 0x20 | OPC_CP3
,
442 OPC_MADD_D
= 0x21 | OPC_CP3
,
443 OPC_MADD_PS
= 0x26 | OPC_CP3
,
444 OPC_MSUB_S
= 0x28 | OPC_CP3
,
445 OPC_MSUB_D
= 0x29 | OPC_CP3
,
446 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
447 OPC_NMADD_S
= 0x30 | OPC_CP3
,
448 OPC_NMADD_D
= 0x31 | OPC_CP3
,
449 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
450 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
451 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
452 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
455 /* global register indices */
456 static TCGv_ptr cpu_env
;
457 static TCGv cpu_gpr
[32], cpu_PC
;
458 static TCGv cpu_HI
[MIPS_DSP_ACC
], cpu_LO
[MIPS_DSP_ACC
], cpu_ACX
[MIPS_DSP_ACC
];
459 static TCGv cpu_dspctrl
, btarget
, bcond
;
460 static TCGv_i32 hflags
;
461 static TCGv_i32 fpu_fcr0
, fpu_fcr31
;
463 static uint32_t gen_opc_hflags
[OPC_BUF_SIZE
];
465 #include "gen-icount.h"
467 #define gen_helper_0i(name, arg) do { \
468 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
469 gen_helper_##name(helper_tmp); \
470 tcg_temp_free_i32(helper_tmp); \
473 #define gen_helper_1i(name, arg1, arg2) do { \
474 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
475 gen_helper_##name(arg1, helper_tmp); \
476 tcg_temp_free_i32(helper_tmp); \
479 #define gen_helper_2i(name, arg1, arg2, arg3) do { \
480 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
481 gen_helper_##name(arg1, arg2, helper_tmp); \
482 tcg_temp_free_i32(helper_tmp); \
485 #define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
486 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
487 gen_helper_##name(arg1, arg2, arg3, helper_tmp); \
488 tcg_temp_free_i32(helper_tmp); \
491 typedef struct DisasContext
{
492 struct TranslationBlock
*tb
;
493 target_ulong pc
, saved_pc
;
495 int singlestep_enabled
;
496 /* Routine used to access memory */
498 uint32_t hflags
, saved_hflags
;
500 target_ulong btarget
;
504 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
505 * exception condition */
506 BS_STOP
= 1, /* We want to stop translation for any reason */
507 BS_BRANCH
= 2, /* We reached a branch condition */
508 BS_EXCP
= 3, /* We reached an exception condition */
511 static const char *regnames
[] =
512 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
513 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
514 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
515 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
517 static const char *regnames_HI
[] =
518 { "HI0", "HI1", "HI2", "HI3", };
520 static const char *regnames_LO
[] =
521 { "LO0", "LO1", "LO2", "LO3", };
523 static const char *regnames_ACX
[] =
524 { "ACX0", "ACX1", "ACX2", "ACX3", };
526 static const char *fregnames
[] =
527 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
528 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
529 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
530 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
532 #ifdef MIPS_DEBUG_DISAS
533 #define MIPS_DEBUG(fmt, ...) \
534 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
535 TARGET_FMT_lx ": %08x " fmt "\n", \
536 ctx->pc, ctx->opcode , ## __VA_ARGS__)
537 #define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
539 #define MIPS_DEBUG(fmt, ...) do { } while(0)
540 #define LOG_DISAS(...) do { } while (0)
543 #define MIPS_INVAL(op) \
545 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
546 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
549 /* General purpose registers moves. */
550 static inline void gen_load_gpr (TCGv t
, int reg
)
553 tcg_gen_movi_tl(t
, 0);
555 tcg_gen_mov_tl(t
, cpu_gpr
[reg
]);
558 static inline void gen_store_gpr (TCGv t
, int reg
)
561 tcg_gen_mov_tl(cpu_gpr
[reg
], t
);
564 /* Moves to/from ACX register. */
565 static inline void gen_load_ACX (TCGv t
, int reg
)
567 tcg_gen_mov_tl(t
, cpu_ACX
[reg
]);
570 static inline void gen_store_ACX (TCGv t
, int reg
)
572 tcg_gen_mov_tl(cpu_ACX
[reg
], t
);
575 /* Moves to/from shadow registers. */
576 static inline void gen_load_srsgpr (int from
, int to
)
578 TCGv t0
= tcg_temp_new();
581 tcg_gen_movi_tl(t0
, 0);
583 TCGv_i32 t2
= tcg_temp_new_i32();
584 TCGv_ptr addr
= tcg_temp_new_ptr();
586 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
587 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
588 tcg_gen_andi_i32(t2
, t2
, 0xf);
589 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
590 tcg_gen_ext_i32_ptr(addr
, t2
);
591 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
593 tcg_gen_ld_tl(t0
, addr
, sizeof(target_ulong
) * from
);
594 tcg_temp_free_ptr(addr
);
595 tcg_temp_free_i32(t2
);
597 gen_store_gpr(t0
, to
);
601 static inline void gen_store_srsgpr (int from
, int to
)
604 TCGv t0
= tcg_temp_new();
605 TCGv_i32 t2
= tcg_temp_new_i32();
606 TCGv_ptr addr
= tcg_temp_new_ptr();
608 gen_load_gpr(t0
, from
);
609 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
610 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
611 tcg_gen_andi_i32(t2
, t2
, 0xf);
612 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
613 tcg_gen_ext_i32_ptr(addr
, t2
);
614 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
616 tcg_gen_st_tl(t0
, addr
, sizeof(target_ulong
) * to
);
617 tcg_temp_free_ptr(addr
);
618 tcg_temp_free_i32(t2
);
623 /* Floating point register moves. */
624 static inline void gen_load_fpr32 (TCGv_i32 t
, int reg
)
626 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
629 static inline void gen_store_fpr32 (TCGv_i32 t
, int reg
)
631 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
634 static inline void gen_load_fpr32h (TCGv_i32 t
, int reg
)
636 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
639 static inline void gen_store_fpr32h (TCGv_i32 t
, int reg
)
641 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
644 static inline void gen_load_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
646 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
647 tcg_gen_ld_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
649 TCGv_i32 t0
= tcg_temp_new_i32();
650 TCGv_i32 t1
= tcg_temp_new_i32();
651 gen_load_fpr32(t0
, reg
& ~1);
652 gen_load_fpr32(t1
, reg
| 1);
653 tcg_gen_concat_i32_i64(t
, t0
, t1
);
654 tcg_temp_free_i32(t0
);
655 tcg_temp_free_i32(t1
);
659 static inline void gen_store_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
661 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
662 tcg_gen_st_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
664 TCGv_i64 t0
= tcg_temp_new_i64();
665 TCGv_i32 t1
= tcg_temp_new_i32();
666 tcg_gen_trunc_i64_i32(t1
, t
);
667 gen_store_fpr32(t1
, reg
& ~1);
668 tcg_gen_shri_i64(t0
, t
, 32);
669 tcg_gen_trunc_i64_i32(t1
, t0
);
670 gen_store_fpr32(t1
, reg
| 1);
671 tcg_temp_free_i32(t1
);
672 tcg_temp_free_i64(t0
);
676 static inline int get_fp_bit (int cc
)
685 static inline void gen_save_pc(target_ulong pc
)
687 tcg_gen_movi_tl(cpu_PC
, pc
);
690 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
692 LOG_DISAS("hflags %08x saved %08x\n", ctx
->hflags
, ctx
->saved_hflags
);
693 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
694 gen_save_pc(ctx
->pc
);
695 ctx
->saved_pc
= ctx
->pc
;
697 if (ctx
->hflags
!= ctx
->saved_hflags
) {
698 tcg_gen_movi_i32(hflags
, ctx
->hflags
);
699 ctx
->saved_hflags
= ctx
->hflags
;
700 switch (ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) {
706 tcg_gen_movi_tl(btarget
, ctx
->btarget
);
712 static inline void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
714 ctx
->saved_hflags
= ctx
->hflags
;
715 switch (ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) {
721 ctx
->btarget
= env
->btarget
;
727 generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
729 TCGv_i32 texcp
= tcg_const_i32(excp
);
730 TCGv_i32 terr
= tcg_const_i32(err
);
731 save_cpu_state(ctx
, 1);
732 gen_helper_raise_exception_err(texcp
, terr
);
733 tcg_temp_free_i32(terr
);
734 tcg_temp_free_i32(texcp
);
738 generate_exception (DisasContext
*ctx
, int excp
)
740 save_cpu_state(ctx
, 1);
741 gen_helper_0i(raise_exception
, excp
);
744 /* Addresses computation */
745 static inline void gen_op_addr_add (DisasContext
*ctx
, TCGv ret
, TCGv arg0
, TCGv arg1
)
747 tcg_gen_add_tl(ret
, arg0
, arg1
);
749 #if defined(TARGET_MIPS64)
750 /* For compatibility with 32-bit code, data reference in user mode
751 with Status_UX = 0 should be casted to 32-bit and sign extended.
752 See the MIPS64 PRA manual, section 4.10. */
753 if (((ctx
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
754 !(ctx
->hflags
& MIPS_HFLAG_UX
)) {
755 tcg_gen_ext32s_i64(ret
, ret
);
760 static inline void check_cp0_enabled(DisasContext
*ctx
)
762 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
763 generate_exception_err(ctx
, EXCP_CpU
, 0);
766 static inline void check_cp1_enabled(DisasContext
*ctx
)
768 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
769 generate_exception_err(ctx
, EXCP_CpU
, 1);
772 /* Verify that the processor is running with COP1X instructions enabled.
773 This is associated with the nabla symbol in the MIPS32 and MIPS64
776 static inline void check_cop1x(DisasContext
*ctx
)
778 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
779 generate_exception(ctx
, EXCP_RI
);
782 /* Verify that the processor is running with 64-bit floating-point
783 operations enabled. */
785 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
787 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
788 generate_exception(ctx
, EXCP_RI
);
792 * Verify if floating point register is valid; an operation is not defined
793 * if bit 0 of any register specification is set and the FR bit in the
794 * Status register equals zero, since the register numbers specify an
795 * even-odd pair of adjacent coprocessor general registers. When the FR bit
796 * in the Status register equals one, both even and odd register numbers
797 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
799 * Multiple 64 bit wide registers can be checked by calling
800 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
802 static inline void check_cp1_registers(DisasContext
*ctx
, int regs
)
804 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
805 generate_exception(ctx
, EXCP_RI
);
808 /* This code generates a "reserved instruction" exception if the
809 CPU does not support the instruction set corresponding to flags. */
810 static inline void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
812 if (unlikely(!(env
->insn_flags
& flags
)))
813 generate_exception(ctx
, EXCP_RI
);
816 /* This code generates a "reserved instruction" exception if 64-bit
817 instructions are not enabled. */
818 static inline void check_mips_64(DisasContext
*ctx
)
820 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
821 generate_exception(ctx
, EXCP_RI
);
824 /* Define small wrappers for gen_load_fpr* so that we have a uniform
825 calling interface for 32 and 64-bit FPRs. No sense in changing
826 all callers for gen_load_fpr32 when we need the CTX parameter for
828 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(x, y)
829 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
830 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \
831 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
832 int ft, int fs, int cc) \
834 TCGv_i##bits fp0 = tcg_temp_new_i##bits (); \
835 TCGv_i##bits fp1 = tcg_temp_new_i##bits (); \
838 check_cp1_64bitmode(ctx); \
844 check_cp1_registers(ctx, fs | ft); \
852 gen_ldcmp_fpr##bits (ctx, fp0, fs); \
853 gen_ldcmp_fpr##bits (ctx, fp1, ft); \
855 case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\
856 case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\
857 case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\
858 case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\
859 case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\
860 case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\
861 case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\
862 case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\
863 case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\
864 case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\
865 case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\
866 case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\
867 case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\
868 case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\
869 case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\
870 case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\
873 tcg_temp_free_i##bits (fp0); \
874 tcg_temp_free_i##bits (fp1); \
877 FOP_CONDS(, 0, d
, FMT_D
, 64)
878 FOP_CONDS(abs
, 1, d
, FMT_D
, 64)
879 FOP_CONDS(, 0, s
, FMT_S
, 32)
880 FOP_CONDS(abs
, 1, s
, FMT_S
, 32)
881 FOP_CONDS(, 0, ps
, FMT_PS
, 64)
882 FOP_CONDS(abs
, 1, ps
, FMT_PS
, 64)
884 #undef gen_ldcmp_fpr32
885 #undef gen_ldcmp_fpr64
887 /* load/store instructions. */
888 #define OP_LD(insn,fname) \
889 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
891 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
898 #if defined(TARGET_MIPS64)
904 #define OP_ST(insn,fname) \
905 static inline void op_st_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
907 tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
912 #if defined(TARGET_MIPS64)
917 #ifdef CONFIG_USER_ONLY
918 #define OP_LD_ATOMIC(insn,fname) \
919 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
921 TCGv t0 = tcg_temp_new(); \
922 tcg_gen_mov_tl(t0, arg1); \
923 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
924 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
925 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
929 #define OP_LD_ATOMIC(insn,fname) \
930 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
932 gen_helper_2i(insn, ret, arg1, ctx->mem_idx); \
935 OP_LD_ATOMIC(ll
,ld32s
);
936 #if defined(TARGET_MIPS64)
937 OP_LD_ATOMIC(lld
,ld64
);
941 #ifdef CONFIG_USER_ONLY
942 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
943 static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
945 TCGv t0 = tcg_temp_new(); \
946 int l1 = gen_new_label(); \
947 int l2 = gen_new_label(); \
949 tcg_gen_andi_tl(t0, arg2, almask); \
950 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
951 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
952 generate_exception(ctx, EXCP_AdES); \
954 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
955 tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
956 tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
957 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
958 tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \
959 gen_helper_0i(raise_exception, EXCP_SC); \
961 tcg_gen_movi_tl(t0, 0); \
962 gen_store_gpr(t0, rt); \
966 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
967 static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
969 TCGv t0 = tcg_temp_new(); \
970 gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx); \
971 gen_store_gpr(t0, rt); \
975 OP_ST_ATOMIC(sc
,st32
,ld32s
,0x3);
976 #if defined(TARGET_MIPS64)
977 OP_ST_ATOMIC(scd
,st64
,ld64
,0x7);
981 static void gen_base_offset_addr (DisasContext
*ctx
, TCGv addr
,
982 int base
, int16_t offset
)
985 tcg_gen_movi_tl(addr
, offset
);
986 } else if (offset
== 0) {
987 gen_load_gpr(addr
, base
);
989 tcg_gen_movi_tl(addr
, offset
);
990 gen_op_addr_add(ctx
, addr
, cpu_gpr
[base
], addr
);
994 static target_ulong
pc_relative_pc (DisasContext
*ctx
)
996 target_ulong pc
= ctx
->pc
;
998 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
999 int branch_bytes
= ctx
->hflags
& MIPS_HFLAG_BDS16
? 2 : 4;
1004 pc
&= ~(target_ulong
)3;
1009 static void gen_ld (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1010 int rt
, int base
, int16_t offset
)
1012 const char *opn
= "ld";
1015 if (rt
== 0 && env
->insn_flags
& (INSN_LOONGSON2E
| INSN_LOONGSON2F
)) {
1016 /* Loongson CPU uses a load to zero register for prefetch.
1017 We emulate it as a NOP. On other CPU we must perform the
1018 actual memory access. */
1023 t0
= tcg_temp_new();
1024 t1
= tcg_temp_new();
1025 gen_base_offset_addr(ctx
, t0
, base
, offset
);
1028 #if defined(TARGET_MIPS64)
1030 save_cpu_state(ctx
, 0);
1031 op_ld_lwu(t0
, t0
, ctx
);
1032 gen_store_gpr(t0
, rt
);
1036 save_cpu_state(ctx
, 0);
1037 op_ld_ld(t0
, t0
, ctx
);
1038 gen_store_gpr(t0
, rt
);
1042 save_cpu_state(ctx
, 0);
1043 op_ld_lld(t0
, t0
, ctx
);
1044 gen_store_gpr(t0
, rt
);
1048 save_cpu_state(ctx
, 1);
1049 gen_load_gpr(t1
, rt
);
1050 gen_helper_3i(ldl
, t1
, t1
, t0
, ctx
->mem_idx
);
1051 gen_store_gpr(t1
, rt
);
1055 save_cpu_state(ctx
, 1);
1056 gen_load_gpr(t1
, rt
);
1057 gen_helper_3i(ldr
, t1
, t1
, t0
, ctx
->mem_idx
);
1058 gen_store_gpr(t1
, rt
);
1062 save_cpu_state(ctx
, 1);
1063 tcg_gen_movi_tl(t1
, pc_relative_pc(ctx
));
1064 gen_op_addr_add(ctx
, t0
, t0
, t1
);
1065 op_ld_ld(t0
, t0
, ctx
);
1066 gen_store_gpr(t0
, rt
);
1071 save_cpu_state(ctx
, 1);
1072 tcg_gen_movi_tl(t1
, pc_relative_pc(ctx
));
1073 gen_op_addr_add(ctx
, t0
, t0
, t1
);
1074 op_ld_lw(t0
, t0
, ctx
);
1075 gen_store_gpr(t0
, rt
);
1079 save_cpu_state(ctx
, 0);
1080 op_ld_lw(t0
, t0
, ctx
);
1081 gen_store_gpr(t0
, rt
);
1085 save_cpu_state(ctx
, 0);
1086 op_ld_lh(t0
, t0
, ctx
);
1087 gen_store_gpr(t0
, rt
);
1091 save_cpu_state(ctx
, 0);
1092 op_ld_lhu(t0
, t0
, ctx
);
1093 gen_store_gpr(t0
, rt
);
1097 save_cpu_state(ctx
, 0);
1098 op_ld_lb(t0
, t0
, ctx
);
1099 gen_store_gpr(t0
, rt
);
1103 save_cpu_state(ctx
, 0);
1104 op_ld_lbu(t0
, t0
, ctx
);
1105 gen_store_gpr(t0
, rt
);
1109 save_cpu_state(ctx
, 1);
1110 gen_load_gpr(t1
, rt
);
1111 gen_helper_3i(lwl
, t1
, t1
, t0
, ctx
->mem_idx
);
1112 gen_store_gpr(t1
, rt
);
1116 save_cpu_state(ctx
, 1);
1117 gen_load_gpr(t1
, rt
);
1118 gen_helper_3i(lwr
, t1
, t1
, t0
, ctx
->mem_idx
);
1119 gen_store_gpr(t1
, rt
);
1123 save_cpu_state(ctx
, 1);
1124 op_ld_ll(t0
, t0
, ctx
);
1125 gen_store_gpr(t0
, rt
);
1129 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1135 static void gen_st (DisasContext
*ctx
, uint32_t opc
, int rt
,
1136 int base
, int16_t offset
)
1138 const char *opn
= "st";
1139 TCGv t0
= tcg_temp_new();
1140 TCGv t1
= tcg_temp_new();
1142 gen_base_offset_addr(ctx
, t0
, base
, offset
);
1143 gen_load_gpr(t1
, rt
);
1145 #if defined(TARGET_MIPS64)
1147 save_cpu_state(ctx
, 0);
1148 op_st_sd(t1
, t0
, ctx
);
1152 save_cpu_state(ctx
, 1);
1153 gen_helper_2i(sdl
, t1
, t0
, ctx
->mem_idx
);
1157 save_cpu_state(ctx
, 1);
1158 gen_helper_2i(sdr
, t1
, t0
, ctx
->mem_idx
);
1163 save_cpu_state(ctx
, 0);
1164 op_st_sw(t1
, t0
, ctx
);
1168 save_cpu_state(ctx
, 0);
1169 op_st_sh(t1
, t0
, ctx
);
1173 save_cpu_state(ctx
, 0);
1174 op_st_sb(t1
, t0
, ctx
);
1178 save_cpu_state(ctx
, 1);
1179 gen_helper_2i(swl
, t1
, t0
, ctx
->mem_idx
);
1183 save_cpu_state(ctx
, 1);
1184 gen_helper_2i(swr
, t1
, t0
, ctx
->mem_idx
);
1188 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1194 /* Store conditional */
1195 static void gen_st_cond (DisasContext
*ctx
, uint32_t opc
, int rt
,
1196 int base
, int16_t offset
)
1198 const char *opn
= "st_cond";
1201 t0
= tcg_temp_local_new();
1203 gen_base_offset_addr(ctx
, t0
, base
, offset
);
1204 /* Don't do NOP if destination is zero: we must perform the actual
1207 t1
= tcg_temp_local_new();
1208 gen_load_gpr(t1
, rt
);
1210 #if defined(TARGET_MIPS64)
1212 save_cpu_state(ctx
, 0);
1213 op_st_scd(t1
, t0
, rt
, ctx
);
1218 save_cpu_state(ctx
, 1);
1219 op_st_sc(t1
, t0
, rt
, ctx
);
1223 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1228 /* Load and store */
1229 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1230 int base
, int16_t offset
)
1232 const char *opn
= "flt_ldst";
1233 TCGv t0
= tcg_temp_new();
1235 gen_base_offset_addr(ctx
, t0
, base
, offset
);
1236 /* Don't do NOP if destination is zero: we must perform the actual
1241 TCGv_i32 fp0
= tcg_temp_new_i32();
1243 tcg_gen_qemu_ld32s(t0
, t0
, ctx
->mem_idx
);
1244 tcg_gen_trunc_tl_i32(fp0
, t0
);
1245 gen_store_fpr32(fp0
, ft
);
1246 tcg_temp_free_i32(fp0
);
1252 TCGv_i32 fp0
= tcg_temp_new_i32();
1253 TCGv t1
= tcg_temp_new();
1255 gen_load_fpr32(fp0
, ft
);
1256 tcg_gen_extu_i32_tl(t1
, fp0
);
1257 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
1259 tcg_temp_free_i32(fp0
);
1265 TCGv_i64 fp0
= tcg_temp_new_i64();
1267 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
1268 gen_store_fpr64(ctx
, fp0
, ft
);
1269 tcg_temp_free_i64(fp0
);
1275 TCGv_i64 fp0
= tcg_temp_new_i64();
1277 gen_load_fpr64(ctx
, fp0
, ft
);
1278 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
1279 tcg_temp_free_i64(fp0
);
1285 generate_exception(ctx
, EXCP_RI
);
1288 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1293 static void gen_cop1_ldst(CPUState
*env
, DisasContext
*ctx
,
1294 uint32_t op
, int rt
, int rs
, int16_t imm
)
1296 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
1297 check_cp1_enabled(ctx
);
1298 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
1300 generate_exception_err(ctx
, EXCP_CpU
, 1);
1304 /* Arithmetic with immediate operand */
1305 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1306 int rt
, int rs
, int16_t imm
)
1308 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1309 const char *opn
= "imm arith";
1311 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1312 /* If no destination, treat it as a NOP.
1313 For addi, we must generate the overflow exception when needed. */
1320 TCGv t0
= tcg_temp_local_new();
1321 TCGv t1
= tcg_temp_new();
1322 TCGv t2
= tcg_temp_new();
1323 int l1
= gen_new_label();
1325 gen_load_gpr(t1
, rs
);
1326 tcg_gen_addi_tl(t0
, t1
, uimm
);
1327 tcg_gen_ext32s_tl(t0
, t0
);
1329 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
1330 tcg_gen_xori_tl(t2
, t0
, uimm
);
1331 tcg_gen_and_tl(t1
, t1
, t2
);
1333 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1335 /* operands of same sign, result different sign */
1336 generate_exception(ctx
, EXCP_OVERFLOW
);
1338 tcg_gen_ext32s_tl(t0
, t0
);
1339 gen_store_gpr(t0
, rt
);
1346 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1347 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
1349 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1353 #if defined(TARGET_MIPS64)
1356 TCGv t0
= tcg_temp_local_new();
1357 TCGv t1
= tcg_temp_new();
1358 TCGv t2
= tcg_temp_new();
1359 int l1
= gen_new_label();
1361 gen_load_gpr(t1
, rs
);
1362 tcg_gen_addi_tl(t0
, t1
, uimm
);
1364 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
1365 tcg_gen_xori_tl(t2
, t0
, uimm
);
1366 tcg_gen_and_tl(t1
, t1
, t2
);
1368 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1370 /* operands of same sign, result different sign */
1371 generate_exception(ctx
, EXCP_OVERFLOW
);
1373 gen_store_gpr(t0
, rt
);
1380 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1382 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1388 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1391 /* Logic with immediate operand */
1392 static void gen_logic_imm (CPUState
*env
, uint32_t opc
, int rt
, int rs
, int16_t imm
)
1395 const char *opn
= "imm logic";
1398 /* If no destination, treat it as a NOP. */
1402 uimm
= (uint16_t)imm
;
1405 if (likely(rs
!= 0))
1406 tcg_gen_andi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1408 tcg_gen_movi_tl(cpu_gpr
[rt
], 0);
1413 tcg_gen_ori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1415 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1419 if (likely(rs
!= 0))
1420 tcg_gen_xori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1422 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1426 tcg_gen_movi_tl(cpu_gpr
[rt
], imm
<< 16);
1430 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1433 /* Set on less than with immediate operand */
1434 static void gen_slt_imm (CPUState
*env
, uint32_t opc
, int rt
, int rs
, int16_t imm
)
1436 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1437 const char *opn
= "imm arith";
1441 /* If no destination, treat it as a NOP. */
1445 t0
= tcg_temp_new();
1446 gen_load_gpr(t0
, rs
);
1449 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_gpr
[rt
], t0
, uimm
);
1453 tcg_gen_setcondi_tl(TCG_COND_LTU
, cpu_gpr
[rt
], t0
, uimm
);
1457 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1461 /* Shifts with immediate operand */
1462 static void gen_shift_imm(CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1463 int rt
, int rs
, int16_t imm
)
1465 target_ulong uimm
= ((uint16_t)imm
) & 0x1f;
1466 const char *opn
= "imm shift";
1470 /* If no destination, treat it as a NOP. */
1475 t0
= tcg_temp_new();
1476 gen_load_gpr(t0
, rs
);
1479 tcg_gen_shli_tl(t0
, t0
, uimm
);
1480 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1484 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
1489 tcg_gen_ext32u_tl(t0
, t0
);
1490 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1492 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1498 TCGv_i32 t1
= tcg_temp_new_i32();
1500 tcg_gen_trunc_tl_i32(t1
, t0
);
1501 tcg_gen_rotri_i32(t1
, t1
, uimm
);
1502 tcg_gen_ext_i32_tl(cpu_gpr
[rt
], t1
);
1503 tcg_temp_free_i32(t1
);
1505 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1509 #if defined(TARGET_MIPS64)
1511 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
);
1515 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
1519 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1524 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
);
1526 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
1531 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1535 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1539 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1543 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1548 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1553 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1554 int rd
, int rs
, int rt
)
1556 const char *opn
= "arith";
1558 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1559 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1560 /* If no destination, treat it as a NOP.
1561 For add & sub, we must generate the overflow exception when needed. */
1569 TCGv t0
= tcg_temp_local_new();
1570 TCGv t1
= tcg_temp_new();
1571 TCGv t2
= tcg_temp_new();
1572 int l1
= gen_new_label();
1574 gen_load_gpr(t1
, rs
);
1575 gen_load_gpr(t2
, rt
);
1576 tcg_gen_add_tl(t0
, t1
, t2
);
1577 tcg_gen_ext32s_tl(t0
, t0
);
1578 tcg_gen_xor_tl(t1
, t1
, t2
);
1579 tcg_gen_xor_tl(t2
, t0
, t2
);
1580 tcg_gen_andc_tl(t1
, t2
, t1
);
1582 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1584 /* operands of same sign, result different sign */
1585 generate_exception(ctx
, EXCP_OVERFLOW
);
1587 gen_store_gpr(t0
, rd
);
1593 if (rs
!= 0 && rt
!= 0) {
1594 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1595 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1596 } else if (rs
== 0 && rt
!= 0) {
1597 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1598 } else if (rs
!= 0 && rt
== 0) {
1599 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1601 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1607 TCGv t0
= tcg_temp_local_new();
1608 TCGv t1
= tcg_temp_new();
1609 TCGv t2
= tcg_temp_new();
1610 int l1
= gen_new_label();
1612 gen_load_gpr(t1
, rs
);
1613 gen_load_gpr(t2
, rt
);
1614 tcg_gen_sub_tl(t0
, t1
, t2
);
1615 tcg_gen_ext32s_tl(t0
, t0
);
1616 tcg_gen_xor_tl(t2
, t1
, t2
);
1617 tcg_gen_xor_tl(t1
, t0
, t1
);
1618 tcg_gen_and_tl(t1
, t1
, t2
);
1620 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1622 /* operands of different sign, first operand and result different sign */
1623 generate_exception(ctx
, EXCP_OVERFLOW
);
1625 gen_store_gpr(t0
, rd
);
1631 if (rs
!= 0 && rt
!= 0) {
1632 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1633 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1634 } else if (rs
== 0 && rt
!= 0) {
1635 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1636 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1637 } else if (rs
!= 0 && rt
== 0) {
1638 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1640 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1644 #if defined(TARGET_MIPS64)
1647 TCGv t0
= tcg_temp_local_new();
1648 TCGv t1
= tcg_temp_new();
1649 TCGv t2
= tcg_temp_new();
1650 int l1
= gen_new_label();
1652 gen_load_gpr(t1
, rs
);
1653 gen_load_gpr(t2
, rt
);
1654 tcg_gen_add_tl(t0
, t1
, t2
);
1655 tcg_gen_xor_tl(t1
, t1
, t2
);
1656 tcg_gen_xor_tl(t2
, t0
, t2
);
1657 tcg_gen_andc_tl(t1
, t2
, t1
);
1659 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1661 /* operands of same sign, result different sign */
1662 generate_exception(ctx
, EXCP_OVERFLOW
);
1664 gen_store_gpr(t0
, rd
);
1670 if (rs
!= 0 && rt
!= 0) {
1671 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1672 } else if (rs
== 0 && rt
!= 0) {
1673 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1674 } else if (rs
!= 0 && rt
== 0) {
1675 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1677 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1683 TCGv t0
= tcg_temp_local_new();
1684 TCGv t1
= tcg_temp_new();
1685 TCGv t2
= tcg_temp_new();
1686 int l1
= gen_new_label();
1688 gen_load_gpr(t1
, rs
);
1689 gen_load_gpr(t2
, rt
);
1690 tcg_gen_sub_tl(t0
, t1
, t2
);
1691 tcg_gen_xor_tl(t2
, t1
, t2
);
1692 tcg_gen_xor_tl(t1
, t0
, t1
);
1693 tcg_gen_and_tl(t1
, t1
, t2
);
1695 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1697 /* operands of different sign, first operand and result different sign */
1698 generate_exception(ctx
, EXCP_OVERFLOW
);
1700 gen_store_gpr(t0
, rd
);
1706 if (rs
!= 0 && rt
!= 0) {
1707 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1708 } else if (rs
== 0 && rt
!= 0) {
1709 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1710 } else if (rs
!= 0 && rt
== 0) {
1711 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1713 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1719 if (likely(rs
!= 0 && rt
!= 0)) {
1720 tcg_gen_mul_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1721 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1723 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1728 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1731 /* Conditional move */
1732 static void gen_cond_move (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1734 const char *opn
= "cond move";
1738 /* If no destination, treat it as a NOP.
1739 For add & sub, we must generate the overflow exception when needed. */
1744 l1
= gen_new_label();
1747 if (likely(rt
!= 0))
1748 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rt
], 0, l1
);
1754 if (likely(rt
!= 0))
1755 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rt
], 0, l1
);
1760 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1762 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1765 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1769 static void gen_logic (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1771 const char *opn
= "logic";
1774 /* If no destination, treat it as a NOP. */
1781 if (likely(rs
!= 0 && rt
!= 0)) {
1782 tcg_gen_and_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1784 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1789 if (rs
!= 0 && rt
!= 0) {
1790 tcg_gen_nor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1791 } else if (rs
== 0 && rt
!= 0) {
1792 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1793 } else if (rs
!= 0 && rt
== 0) {
1794 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1796 tcg_gen_movi_tl(cpu_gpr
[rd
], ~((target_ulong
)0));
1801 if (likely(rs
!= 0 && rt
!= 0)) {
1802 tcg_gen_or_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1803 } else if (rs
== 0 && rt
!= 0) {
1804 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1805 } else if (rs
!= 0 && rt
== 0) {
1806 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1808 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1813 if (likely(rs
!= 0 && rt
!= 0)) {
1814 tcg_gen_xor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1815 } else if (rs
== 0 && rt
!= 0) {
1816 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1817 } else if (rs
!= 0 && rt
== 0) {
1818 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1820 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1825 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1828 /* Set on lower than */
1829 static void gen_slt (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1831 const char *opn
= "slt";
1835 /* If no destination, treat it as a NOP. */
1840 t0
= tcg_temp_new();
1841 t1
= tcg_temp_new();
1842 gen_load_gpr(t0
, rs
);
1843 gen_load_gpr(t1
, rt
);
1846 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_gpr
[rd
], t0
, t1
);
1850 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_gpr
[rd
], t0
, t1
);
1854 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1860 static void gen_shift (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1861 int rd
, int rs
, int rt
)
1863 const char *opn
= "shifts";
1867 /* If no destination, treat it as a NOP.
1868 For add & sub, we must generate the overflow exception when needed. */
1873 t0
= tcg_temp_new();
1874 t1
= tcg_temp_new();
1875 gen_load_gpr(t0
, rs
);
1876 gen_load_gpr(t1
, rt
);
1879 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1880 tcg_gen_shl_tl(t0
, t1
, t0
);
1881 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1885 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1886 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
1890 tcg_gen_ext32u_tl(t1
, t1
);
1891 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1892 tcg_gen_shr_tl(t0
, t1
, t0
);
1893 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1898 TCGv_i32 t2
= tcg_temp_new_i32();
1899 TCGv_i32 t3
= tcg_temp_new_i32();
1901 tcg_gen_trunc_tl_i32(t2
, t0
);
1902 tcg_gen_trunc_tl_i32(t3
, t1
);
1903 tcg_gen_andi_i32(t2
, t2
, 0x1f);
1904 tcg_gen_rotr_i32(t2
, t3
, t2
);
1905 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
1906 tcg_temp_free_i32(t2
);
1907 tcg_temp_free_i32(t3
);
1911 #if defined(TARGET_MIPS64)
1913 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1914 tcg_gen_shl_tl(cpu_gpr
[rd
], t1
, t0
);
1918 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1919 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
1923 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1924 tcg_gen_shr_tl(cpu_gpr
[rd
], t1
, t0
);
1928 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1929 tcg_gen_rotr_tl(cpu_gpr
[rd
], t1
, t0
);
1934 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1939 /* Arithmetic on HI/LO registers */
1940 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1942 const char *opn
= "hilo";
1944 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1951 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_HI
[0]);
1955 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_LO
[0]);
1960 tcg_gen_mov_tl(cpu_HI
[0], cpu_gpr
[reg
]);
1962 tcg_gen_movi_tl(cpu_HI
[0], 0);
1967 tcg_gen_mov_tl(cpu_LO
[0], cpu_gpr
[reg
]);
1969 tcg_gen_movi_tl(cpu_LO
[0], 0);
1973 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1976 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
1979 const char *opn
= "mul/div";
1985 #if defined(TARGET_MIPS64)
1989 t0
= tcg_temp_local_new();
1990 t1
= tcg_temp_local_new();
1993 t0
= tcg_temp_new();
1994 t1
= tcg_temp_new();
1998 gen_load_gpr(t0
, rs
);
1999 gen_load_gpr(t1
, rt
);
2003 int l1
= gen_new_label();
2004 int l2
= gen_new_label();
2006 tcg_gen_ext32s_tl(t0
, t0
);
2007 tcg_gen_ext32s_tl(t1
, t1
);
2008 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2009 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, INT_MIN
, l2
);
2010 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1, l2
);
2012 tcg_gen_mov_tl(cpu_LO
[0], t0
);
2013 tcg_gen_movi_tl(cpu_HI
[0], 0);
2016 tcg_gen_div_tl(cpu_LO
[0], t0
, t1
);
2017 tcg_gen_rem_tl(cpu_HI
[0], t0
, t1
);
2018 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
2019 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
2026 int l1
= gen_new_label();
2028 tcg_gen_ext32u_tl(t0
, t0
);
2029 tcg_gen_ext32u_tl(t1
, t1
);
2030 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2031 tcg_gen_divu_tl(cpu_LO
[0], t0
, t1
);
2032 tcg_gen_remu_tl(cpu_HI
[0], t0
, t1
);
2033 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
2034 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
2041 TCGv_i64 t2
= tcg_temp_new_i64();
2042 TCGv_i64 t3
= tcg_temp_new_i64();
2044 tcg_gen_ext_tl_i64(t2
, t0
);
2045 tcg_gen_ext_tl_i64(t3
, t1
);
2046 tcg_gen_mul_i64(t2
, t2
, t3
);
2047 tcg_temp_free_i64(t3
);
2048 tcg_gen_trunc_i64_tl(t0
, t2
);
2049 tcg_gen_shri_i64(t2
, t2
, 32);
2050 tcg_gen_trunc_i64_tl(t1
, t2
);
2051 tcg_temp_free_i64(t2
);
2052 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2053 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2059 TCGv_i64 t2
= tcg_temp_new_i64();
2060 TCGv_i64 t3
= tcg_temp_new_i64();
2062 tcg_gen_ext32u_tl(t0
, t0
);
2063 tcg_gen_ext32u_tl(t1
, t1
);
2064 tcg_gen_extu_tl_i64(t2
, t0
);
2065 tcg_gen_extu_tl_i64(t3
, t1
);
2066 tcg_gen_mul_i64(t2
, t2
, t3
);
2067 tcg_temp_free_i64(t3
);
2068 tcg_gen_trunc_i64_tl(t0
, t2
);
2069 tcg_gen_shri_i64(t2
, t2
, 32);
2070 tcg_gen_trunc_i64_tl(t1
, t2
);
2071 tcg_temp_free_i64(t2
);
2072 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2073 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2077 #if defined(TARGET_MIPS64)
2080 int l1
= gen_new_label();
2081 int l2
= gen_new_label();
2083 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2084 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
2085 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
2086 tcg_gen_mov_tl(cpu_LO
[0], t0
);
2087 tcg_gen_movi_tl(cpu_HI
[0], 0);
2090 tcg_gen_div_i64(cpu_LO
[0], t0
, t1
);
2091 tcg_gen_rem_i64(cpu_HI
[0], t0
, t1
);
2098 int l1
= gen_new_label();
2100 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2101 tcg_gen_divu_i64(cpu_LO
[0], t0
, t1
);
2102 tcg_gen_remu_i64(cpu_HI
[0], t0
, t1
);
2108 gen_helper_dmult(t0
, t1
);
2112 gen_helper_dmultu(t0
, t1
);
2118 TCGv_i64 t2
= tcg_temp_new_i64();
2119 TCGv_i64 t3
= tcg_temp_new_i64();
2121 tcg_gen_ext_tl_i64(t2
, t0
);
2122 tcg_gen_ext_tl_i64(t3
, t1
);
2123 tcg_gen_mul_i64(t2
, t2
, t3
);
2124 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2125 tcg_gen_add_i64(t2
, t2
, t3
);
2126 tcg_temp_free_i64(t3
);
2127 tcg_gen_trunc_i64_tl(t0
, t2
);
2128 tcg_gen_shri_i64(t2
, t2
, 32);
2129 tcg_gen_trunc_i64_tl(t1
, t2
);
2130 tcg_temp_free_i64(t2
);
2131 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2132 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2138 TCGv_i64 t2
= tcg_temp_new_i64();
2139 TCGv_i64 t3
= tcg_temp_new_i64();
2141 tcg_gen_ext32u_tl(t0
, t0
);
2142 tcg_gen_ext32u_tl(t1
, t1
);
2143 tcg_gen_extu_tl_i64(t2
, t0
);
2144 tcg_gen_extu_tl_i64(t3
, t1
);
2145 tcg_gen_mul_i64(t2
, t2
, t3
);
2146 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2147 tcg_gen_add_i64(t2
, t2
, t3
);
2148 tcg_temp_free_i64(t3
);
2149 tcg_gen_trunc_i64_tl(t0
, t2
);
2150 tcg_gen_shri_i64(t2
, t2
, 32);
2151 tcg_gen_trunc_i64_tl(t1
, t2
);
2152 tcg_temp_free_i64(t2
);
2153 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2154 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2160 TCGv_i64 t2
= tcg_temp_new_i64();
2161 TCGv_i64 t3
= tcg_temp_new_i64();
2163 tcg_gen_ext_tl_i64(t2
, t0
);
2164 tcg_gen_ext_tl_i64(t3
, t1
);
2165 tcg_gen_mul_i64(t2
, t2
, t3
);
2166 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2167 tcg_gen_sub_i64(t2
, t3
, t2
);
2168 tcg_temp_free_i64(t3
);
2169 tcg_gen_trunc_i64_tl(t0
, t2
);
2170 tcg_gen_shri_i64(t2
, t2
, 32);
2171 tcg_gen_trunc_i64_tl(t1
, t2
);
2172 tcg_temp_free_i64(t2
);
2173 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2174 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2180 TCGv_i64 t2
= tcg_temp_new_i64();
2181 TCGv_i64 t3
= tcg_temp_new_i64();
2183 tcg_gen_ext32u_tl(t0
, t0
);
2184 tcg_gen_ext32u_tl(t1
, t1
);
2185 tcg_gen_extu_tl_i64(t2
, t0
);
2186 tcg_gen_extu_tl_i64(t3
, t1
);
2187 tcg_gen_mul_i64(t2
, t2
, t3
);
2188 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2189 tcg_gen_sub_i64(t2
, t3
, t2
);
2190 tcg_temp_free_i64(t3
);
2191 tcg_gen_trunc_i64_tl(t0
, t2
);
2192 tcg_gen_shri_i64(t2
, t2
, 32);
2193 tcg_gen_trunc_i64_tl(t1
, t2
);
2194 tcg_temp_free_i64(t2
);
2195 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2196 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2202 generate_exception(ctx
, EXCP_RI
);
2205 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
2211 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
2212 int rd
, int rs
, int rt
)
2214 const char *opn
= "mul vr54xx";
2215 TCGv t0
= tcg_temp_new();
2216 TCGv t1
= tcg_temp_new();
2218 gen_load_gpr(t0
, rs
);
2219 gen_load_gpr(t1
, rt
);
2222 case OPC_VR54XX_MULS
:
2223 gen_helper_muls(t0
, t0
, t1
);
2226 case OPC_VR54XX_MULSU
:
2227 gen_helper_mulsu(t0
, t0
, t1
);
2230 case OPC_VR54XX_MACC
:
2231 gen_helper_macc(t0
, t0
, t1
);
2234 case OPC_VR54XX_MACCU
:
2235 gen_helper_maccu(t0
, t0
, t1
);
2238 case OPC_VR54XX_MSAC
:
2239 gen_helper_msac(t0
, t0
, t1
);
2242 case OPC_VR54XX_MSACU
:
2243 gen_helper_msacu(t0
, t0
, t1
);
2246 case OPC_VR54XX_MULHI
:
2247 gen_helper_mulhi(t0
, t0
, t1
);
2250 case OPC_VR54XX_MULHIU
:
2251 gen_helper_mulhiu(t0
, t0
, t1
);
2254 case OPC_VR54XX_MULSHI
:
2255 gen_helper_mulshi(t0
, t0
, t1
);
2258 case OPC_VR54XX_MULSHIU
:
2259 gen_helper_mulshiu(t0
, t0
, t1
);
2262 case OPC_VR54XX_MACCHI
:
2263 gen_helper_macchi(t0
, t0
, t1
);
2266 case OPC_VR54XX_MACCHIU
:
2267 gen_helper_macchiu(t0
, t0
, t1
);
2270 case OPC_VR54XX_MSACHI
:
2271 gen_helper_msachi(t0
, t0
, t1
);
2274 case OPC_VR54XX_MSACHIU
:
2275 gen_helper_msachiu(t0
, t0
, t1
);
2279 MIPS_INVAL("mul vr54xx");
2280 generate_exception(ctx
, EXCP_RI
);
2283 gen_store_gpr(t0
, rd
);
2284 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2291 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
2294 const char *opn
= "CLx";
2302 t0
= tcg_temp_new();
2303 gen_load_gpr(t0
, rs
);
2306 gen_helper_clo(cpu_gpr
[rd
], t0
);
2310 gen_helper_clz(cpu_gpr
[rd
], t0
);
2313 #if defined(TARGET_MIPS64)
2315 gen_helper_dclo(cpu_gpr
[rd
], t0
);
2319 gen_helper_dclz(cpu_gpr
[rd
], t0
);
2324 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
2329 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
2330 int rs
, int rt
, int16_t imm
)
2333 TCGv t0
= tcg_temp_new();
2334 TCGv t1
= tcg_temp_new();
2337 /* Load needed operands */
2345 /* Compare two registers */
2347 gen_load_gpr(t0
, rs
);
2348 gen_load_gpr(t1
, rt
);
2358 /* Compare register to immediate */
2359 if (rs
!= 0 || imm
!= 0) {
2360 gen_load_gpr(t0
, rs
);
2361 tcg_gen_movi_tl(t1
, (int32_t)imm
);
2368 case OPC_TEQ
: /* rs == rs */
2369 case OPC_TEQI
: /* r0 == 0 */
2370 case OPC_TGE
: /* rs >= rs */
2371 case OPC_TGEI
: /* r0 >= 0 */
2372 case OPC_TGEU
: /* rs >= rs unsigned */
2373 case OPC_TGEIU
: /* r0 >= 0 unsigned */
2375 generate_exception(ctx
, EXCP_TRAP
);
2377 case OPC_TLT
: /* rs < rs */
2378 case OPC_TLTI
: /* r0 < 0 */
2379 case OPC_TLTU
: /* rs < rs unsigned */
2380 case OPC_TLTIU
: /* r0 < 0 unsigned */
2381 case OPC_TNE
: /* rs != rs */
2382 case OPC_TNEI
: /* r0 != 0 */
2383 /* Never trap: treat as NOP. */
2387 int l1
= gen_new_label();
2392 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, t1
, l1
);
2396 tcg_gen_brcond_tl(TCG_COND_LT
, t0
, t1
, l1
);
2400 tcg_gen_brcond_tl(TCG_COND_LTU
, t0
, t1
, l1
);
2404 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
2408 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
2412 tcg_gen_brcond_tl(TCG_COND_EQ
, t0
, t1
, l1
);
2415 generate_exception(ctx
, EXCP_TRAP
);
2422 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
2424 TranslationBlock
*tb
;
2426 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
2427 likely(!ctx
->singlestep_enabled
)) {
2430 tcg_gen_exit_tb((long)tb
+ n
);
2433 if (ctx
->singlestep_enabled
) {
2434 save_cpu_state(ctx
, 0);
2435 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
2441 /* Branches (before delay slot) */
2442 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
2444 int rs
, int rt
, int32_t offset
)
2446 target_ulong btgt
= -1;
2448 int bcond_compute
= 0;
2449 TCGv t0
= tcg_temp_new();
2450 TCGv t1
= tcg_temp_new();
2452 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
2453 #ifdef MIPS_DEBUG_DISAS
2454 LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n", ctx
->pc
);
2456 generate_exception(ctx
, EXCP_RI
);
2460 /* Load needed operands */
2466 /* Compare two registers */
2468 gen_load_gpr(t0
, rs
);
2469 gen_load_gpr(t1
, rt
);
2472 btgt
= ctx
->pc
+ insn_bytes
+ offset
;
2488 /* Compare to zero */
2490 gen_load_gpr(t0
, rs
);
2493 btgt
= ctx
->pc
+ insn_bytes
+ offset
;
2500 /* Jump to immediate */
2501 btgt
= ((ctx
->pc
+ insn_bytes
) & (int32_t)0xF0000000) | (uint32_t)offset
;
2507 /* Jump to register */
2508 if (offset
!= 0 && offset
!= 16) {
2509 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2510 others are reserved. */
2511 MIPS_INVAL("jump hint");
2512 generate_exception(ctx
, EXCP_RI
);
2515 gen_load_gpr(btarget
, rs
);
2518 MIPS_INVAL("branch/jump");
2519 generate_exception(ctx
, EXCP_RI
);
2522 if (bcond_compute
== 0) {
2523 /* No condition to be computed */
2525 case OPC_BEQ
: /* rx == rx */
2526 case OPC_BEQL
: /* rx == rx likely */
2527 case OPC_BGEZ
: /* 0 >= 0 */
2528 case OPC_BGEZL
: /* 0 >= 0 likely */
2529 case OPC_BLEZ
: /* 0 <= 0 */
2530 case OPC_BLEZL
: /* 0 <= 0 likely */
2532 ctx
->hflags
|= MIPS_HFLAG_B
;
2533 MIPS_DEBUG("balways");
2536 case OPC_BGEZAL
: /* 0 >= 0 */
2537 case OPC_BGEZALL
: /* 0 >= 0 likely */
2538 ctx
->hflags
|= (opc
== OPC_BGEZALS
2540 : MIPS_HFLAG_BDS32
);
2541 /* Always take and link */
2543 ctx
->hflags
|= MIPS_HFLAG_B
;
2544 MIPS_DEBUG("balways and link");
2546 case OPC_BNE
: /* rx != rx */
2547 case OPC_BGTZ
: /* 0 > 0 */
2548 case OPC_BLTZ
: /* 0 < 0 */
2550 MIPS_DEBUG("bnever (NOP)");
2553 case OPC_BLTZAL
: /* 0 < 0 */
2554 ctx
->hflags
|= (opc
== OPC_BLTZALS
2556 : MIPS_HFLAG_BDS32
);
2557 /* Handle as an unconditional branch to get correct delay
2560 btgt
= ctx
->pc
+ (opc
== OPC_BLTZALS
? 6 : 8);
2561 ctx
->hflags
|= MIPS_HFLAG_B
;
2562 MIPS_DEBUG("bnever and link");
2564 case OPC_BLTZALL
: /* 0 < 0 likely */
2565 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 8);
2566 /* Skip the instruction in the delay slot */
2567 MIPS_DEBUG("bnever, link and skip");
2570 case OPC_BNEL
: /* rx != rx likely */
2571 case OPC_BGTZL
: /* 0 > 0 likely */
2572 case OPC_BLTZL
: /* 0 < 0 likely */
2573 /* Skip the instruction in the delay slot */
2574 MIPS_DEBUG("bnever and skip");
2578 ctx
->hflags
|= MIPS_HFLAG_B
;
2579 MIPS_DEBUG("j " TARGET_FMT_lx
, btgt
);
2583 ctx
->hflags
|= MIPS_HFLAG_BX
;
2588 ctx
->hflags
|= MIPS_HFLAG_B
;
2589 ctx
->hflags
|= ((opc
== OPC_JALS
|| opc
== OPC_JALXS
)
2591 : MIPS_HFLAG_BDS32
);
2592 MIPS_DEBUG("jal " TARGET_FMT_lx
, btgt
);
2595 ctx
->hflags
|= MIPS_HFLAG_BR
;
2596 if (insn_bytes
== 4)
2597 ctx
->hflags
|= MIPS_HFLAG_BDS32
;
2598 MIPS_DEBUG("jr %s", regnames
[rs
]);
2604 ctx
->hflags
|= MIPS_HFLAG_BR
;
2605 ctx
->hflags
|= (opc
== OPC_JALRS
2607 : MIPS_HFLAG_BDS32
);
2608 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
2611 MIPS_INVAL("branch/jump");
2612 generate_exception(ctx
, EXCP_RI
);
2618 tcg_gen_setcond_tl(TCG_COND_EQ
, bcond
, t0
, t1
);
2619 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
2620 regnames
[rs
], regnames
[rt
], btgt
);
2623 tcg_gen_setcond_tl(TCG_COND_EQ
, bcond
, t0
, t1
);
2624 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
2625 regnames
[rs
], regnames
[rt
], btgt
);
2628 tcg_gen_setcond_tl(TCG_COND_NE
, bcond
, t0
, t1
);
2629 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
2630 regnames
[rs
], regnames
[rt
], btgt
);
2633 tcg_gen_setcond_tl(TCG_COND_NE
, bcond
, t0
, t1
);
2634 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
2635 regnames
[rs
], regnames
[rt
], btgt
);
2638 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
2639 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2642 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
2643 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2647 ctx
->hflags
|= (opc
== OPC_BGEZALS
2649 : MIPS_HFLAG_BDS32
);
2650 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
2651 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2655 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
2657 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2660 tcg_gen_setcondi_tl(TCG_COND_GT
, bcond
, t0
, 0);
2661 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2664 tcg_gen_setcondi_tl(TCG_COND_GT
, bcond
, t0
, 0);
2665 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2668 tcg_gen_setcondi_tl(TCG_COND_LE
, bcond
, t0
, 0);
2669 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2672 tcg_gen_setcondi_tl(TCG_COND_LE
, bcond
, t0
, 0);
2673 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2676 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
2677 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2680 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
2681 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2685 ctx
->hflags
|= (opc
== OPC_BLTZALS
2687 : MIPS_HFLAG_BDS32
);
2688 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
2690 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2692 ctx
->hflags
|= MIPS_HFLAG_BC
;
2695 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
2697 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2699 ctx
->hflags
|= MIPS_HFLAG_BL
;
2702 MIPS_INVAL("conditional branch/jump");
2703 generate_exception(ctx
, EXCP_RI
);
2707 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
2708 blink
, ctx
->hflags
, btgt
);
2710 ctx
->btarget
= btgt
;
2712 int post_delay
= insn_bytes
;
2713 int lowbit
= !!(ctx
->hflags
& MIPS_HFLAG_M16
);
2715 if (opc
!= OPC_JALRC
)
2716 post_delay
+= ((ctx
->hflags
& MIPS_HFLAG_BDS16
) ? 2 : 4);
2718 tcg_gen_movi_tl(cpu_gpr
[blink
], ctx
->pc
+ post_delay
+ lowbit
);
2722 if (insn_bytes
== 2)
2723 ctx
->hflags
|= MIPS_HFLAG_B16
;
2728 /* special3 bitfield operations */
2729 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
2730 int rs
, int lsb
, int msb
)
2732 TCGv t0
= tcg_temp_new();
2733 TCGv t1
= tcg_temp_new();
2736 gen_load_gpr(t1
, rs
);
2741 tcg_gen_shri_tl(t0
, t1
, lsb
);
2743 tcg_gen_andi_tl(t0
, t0
, (1 << (msb
+ 1)) - 1);
2745 tcg_gen_ext32s_tl(t0
, t0
);
2748 #if defined(TARGET_MIPS64)
2750 tcg_gen_shri_tl(t0
, t1
, lsb
);
2752 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1 + 32)) - 1);
2756 tcg_gen_shri_tl(t0
, t1
, lsb
+ 32);
2757 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2760 tcg_gen_shri_tl(t0
, t1
, lsb
);
2761 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2767 mask
= ((msb
- lsb
+ 1 < 32) ? ((1 << (msb
- lsb
+ 1)) - 1) : ~0) << lsb
;
2768 gen_load_gpr(t0
, rt
);
2769 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2770 tcg_gen_shli_tl(t1
, t1
, lsb
);
2771 tcg_gen_andi_tl(t1
, t1
, mask
);
2772 tcg_gen_or_tl(t0
, t0
, t1
);
2773 tcg_gen_ext32s_tl(t0
, t0
);
2775 #if defined(TARGET_MIPS64)
2779 mask
= ((msb
- lsb
+ 1 + 32 < 64) ? ((1ULL << (msb
- lsb
+ 1 + 32)) - 1) : ~0ULL) << lsb
;
2780 gen_load_gpr(t0
, rt
);
2781 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2782 tcg_gen_shli_tl(t1
, t1
, lsb
);
2783 tcg_gen_andi_tl(t1
, t1
, mask
);
2784 tcg_gen_or_tl(t0
, t0
, t1
);
2789 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << (lsb
+ 32);
2790 gen_load_gpr(t0
, rt
);
2791 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2792 tcg_gen_shli_tl(t1
, t1
, lsb
+ 32);
2793 tcg_gen_andi_tl(t1
, t1
, mask
);
2794 tcg_gen_or_tl(t0
, t0
, t1
);
2799 gen_load_gpr(t0
, rt
);
2800 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2801 gen_load_gpr(t0
, rt
);
2802 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2803 tcg_gen_shli_tl(t1
, t1
, lsb
);
2804 tcg_gen_andi_tl(t1
, t1
, mask
);
2805 tcg_gen_or_tl(t0
, t0
, t1
);
2810 MIPS_INVAL("bitops");
2811 generate_exception(ctx
, EXCP_RI
);
2816 gen_store_gpr(t0
, rt
);
2821 static void gen_bshfl (DisasContext
*ctx
, uint32_t op2
, int rt
, int rd
)
2826 /* If no destination, treat it as a NOP. */
2831 t0
= tcg_temp_new();
2832 gen_load_gpr(t0
, rt
);
2836 TCGv t1
= tcg_temp_new();
2838 tcg_gen_shri_tl(t1
, t0
, 8);
2839 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF);
2840 tcg_gen_shli_tl(t0
, t0
, 8);
2841 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF);
2842 tcg_gen_or_tl(t0
, t0
, t1
);
2844 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
2848 tcg_gen_ext8s_tl(cpu_gpr
[rd
], t0
);
2851 tcg_gen_ext16s_tl(cpu_gpr
[rd
], t0
);
2853 #if defined(TARGET_MIPS64)
2856 TCGv t1
= tcg_temp_new();
2858 tcg_gen_shri_tl(t1
, t0
, 8);
2859 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF00FF00FFULL
);
2860 tcg_gen_shli_tl(t0
, t0
, 8);
2861 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF00FF00FFULL
);
2862 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
2868 TCGv t1
= tcg_temp_new();
2870 tcg_gen_shri_tl(t1
, t0
, 16);
2871 tcg_gen_andi_tl(t1
, t1
, 0x0000FFFF0000FFFFULL
);
2872 tcg_gen_shli_tl(t0
, t0
, 16);
2873 tcg_gen_andi_tl(t0
, t0
, ~0x0000FFFF0000FFFFULL
);
2874 tcg_gen_or_tl(t0
, t0
, t1
);
2875 tcg_gen_shri_tl(t1
, t0
, 32);
2876 tcg_gen_shli_tl(t0
, t0
, 32);
2877 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
2883 MIPS_INVAL("bsfhl");
2884 generate_exception(ctx
, EXCP_RI
);
2891 #ifndef CONFIG_USER_ONLY
2892 /* CP0 (MMU and control) */
2893 static inline void gen_mfc0_load32 (TCGv arg
, target_ulong off
)
2895 TCGv_i32 t0
= tcg_temp_new_i32();
2897 tcg_gen_ld_i32(t0
, cpu_env
, off
);
2898 tcg_gen_ext_i32_tl(arg
, t0
);
2899 tcg_temp_free_i32(t0
);
2902 static inline void gen_mfc0_load64 (TCGv arg
, target_ulong off
)
2904 tcg_gen_ld_tl(arg
, cpu_env
, off
);
2905 tcg_gen_ext32s_tl(arg
, arg
);
2908 static inline void gen_mtc0_store32 (TCGv arg
, target_ulong off
)
2910 TCGv_i32 t0
= tcg_temp_new_i32();
2912 tcg_gen_trunc_tl_i32(t0
, arg
);
2913 tcg_gen_st_i32(t0
, cpu_env
, off
);
2914 tcg_temp_free_i32(t0
);
2917 static inline void gen_mtc0_store64 (TCGv arg
, target_ulong off
)
2919 tcg_gen_ext32s_tl(arg
, arg
);
2920 tcg_gen_st_tl(arg
, cpu_env
, off
);
2923 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
2925 const char *rn
= "invalid";
2928 check_insn(env
, ctx
, ISA_MIPS32
);
2934 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Index
));
2938 check_insn(env
, ctx
, ASE_MT
);
2939 gen_helper_mfc0_mvpcontrol(arg
);
2943 check_insn(env
, ctx
, ASE_MT
);
2944 gen_helper_mfc0_mvpconf0(arg
);
2948 check_insn(env
, ctx
, ASE_MT
);
2949 gen_helper_mfc0_mvpconf1(arg
);
2959 gen_helper_mfc0_random(arg
);
2963 check_insn(env
, ctx
, ASE_MT
);
2964 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEControl
));
2968 check_insn(env
, ctx
, ASE_MT
);
2969 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf0
));
2973 check_insn(env
, ctx
, ASE_MT
);
2974 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf1
));
2978 check_insn(env
, ctx
, ASE_MT
);
2979 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_YQMask
));
2983 check_insn(env
, ctx
, ASE_MT
);
2984 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_VPESchedule
));
2988 check_insn(env
, ctx
, ASE_MT
);
2989 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_VPEScheFBack
));
2990 rn
= "VPEScheFBack";
2993 check_insn(env
, ctx
, ASE_MT
);
2994 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEOpt
));
3004 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
3005 tcg_gen_ext32s_tl(arg
, arg
);
3009 check_insn(env
, ctx
, ASE_MT
);
3010 gen_helper_mfc0_tcstatus(arg
);
3014 check_insn(env
, ctx
, ASE_MT
);
3015 gen_helper_mfc0_tcbind(arg
);
3019 check_insn(env
, ctx
, ASE_MT
);
3020 gen_helper_mfc0_tcrestart(arg
);
3024 check_insn(env
, ctx
, ASE_MT
);
3025 gen_helper_mfc0_tchalt(arg
);
3029 check_insn(env
, ctx
, ASE_MT
);
3030 gen_helper_mfc0_tccontext(arg
);
3034 check_insn(env
, ctx
, ASE_MT
);
3035 gen_helper_mfc0_tcschedule(arg
);
3039 check_insn(env
, ctx
, ASE_MT
);
3040 gen_helper_mfc0_tcschefback(arg
);
3050 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
3051 tcg_gen_ext32s_tl(arg
, arg
);
3061 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_Context
));
3062 tcg_gen_ext32s_tl(arg
, arg
);
3066 // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
3067 rn
= "ContextConfig";
3076 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageMask
));
3080 check_insn(env
, ctx
, ISA_MIPS32R2
);
3081 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageGrain
));
3091 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Wired
));
3095 check_insn(env
, ctx
, ISA_MIPS32R2
);
3096 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf0
));
3100 check_insn(env
, ctx
, ISA_MIPS32R2
);
3101 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf1
));
3105 check_insn(env
, ctx
, ISA_MIPS32R2
);
3106 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf2
));
3110 check_insn(env
, ctx
, ISA_MIPS32R2
);
3111 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf3
));
3115 check_insn(env
, ctx
, ISA_MIPS32R2
);
3116 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf4
));
3126 check_insn(env
, ctx
, ISA_MIPS32R2
);
3127 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_HWREna
));
3137 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
3138 tcg_gen_ext32s_tl(arg
, arg
);
3148 /* Mark as an IO operation because we read the time. */
3151 gen_helper_mfc0_count(arg
);
3154 ctx
->bstate
= BS_STOP
;
3158 /* 6,7 are implementation dependent */
3166 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
3167 tcg_gen_ext32s_tl(arg
, arg
);
3177 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Compare
));
3180 /* 6,7 are implementation dependent */
3188 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Status
));
3192 check_insn(env
, ctx
, ISA_MIPS32R2
);
3193 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_IntCtl
));
3197 check_insn(env
, ctx
, ISA_MIPS32R2
);
3198 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSCtl
));
3202 check_insn(env
, ctx
, ISA_MIPS32R2
);
3203 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSMap
));
3213 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Cause
));
3223 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
3224 tcg_gen_ext32s_tl(arg
, arg
);
3234 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PRid
));
3238 check_insn(env
, ctx
, ISA_MIPS32R2
);
3239 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_EBase
));
3249 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config0
));
3253 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config1
));
3257 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config2
));
3261 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config3
));
3264 /* 4,5 are reserved */
3265 /* 6,7 are implementation dependent */
3267 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config6
));
3271 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config7
));
3281 gen_helper_mfc0_lladdr(arg
);
3291 gen_helper_1i(mfc0_watchlo
, arg
, sel
);
3301 gen_helper_1i(mfc0_watchhi
, arg
, sel
);
3311 #if defined(TARGET_MIPS64)
3312 check_insn(env
, ctx
, ISA_MIPS3
);
3313 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
3314 tcg_gen_ext32s_tl(arg
, arg
);
3323 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3326 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Framemask
));
3334 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3335 rn
= "'Diagnostic"; /* implementation dependent */
3340 gen_helper_mfc0_debug(arg
); /* EJTAG support */
3344 // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
3345 rn
= "TraceControl";
3348 // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
3349 rn
= "TraceControl2";
3352 // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
3353 rn
= "UserTraceData";
3356 // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
3367 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
3368 tcg_gen_ext32s_tl(arg
, arg
);
3378 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Performance0
));
3379 rn
= "Performance0";
3382 // gen_helper_mfc0_performance1(arg);
3383 rn
= "Performance1";
3386 // gen_helper_mfc0_performance2(arg);
3387 rn
= "Performance2";
3390 // gen_helper_mfc0_performance3(arg);
3391 rn
= "Performance3";
3394 // gen_helper_mfc0_performance4(arg);
3395 rn
= "Performance4";
3398 // gen_helper_mfc0_performance5(arg);
3399 rn
= "Performance5";
3402 // gen_helper_mfc0_performance6(arg);
3403 rn
= "Performance6";
3406 // gen_helper_mfc0_performance7(arg);
3407 rn
= "Performance7";
3414 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3420 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3433 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagLo
));
3440 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataLo
));
3453 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagHi
));
3460 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataHi
));
3470 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
3471 tcg_gen_ext32s_tl(arg
, arg
);
3482 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DESAVE
));
3492 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3496 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3497 generate_exception(ctx
, EXCP_RI
);
3500 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
3502 const char *rn
= "invalid";
3505 check_insn(env
, ctx
, ISA_MIPS32
);
3514 gen_helper_mtc0_index(arg
);
3518 check_insn(env
, ctx
, ASE_MT
);
3519 gen_helper_mtc0_mvpcontrol(arg
);
3523 check_insn(env
, ctx
, ASE_MT
);
3528 check_insn(env
, ctx
, ASE_MT
);
3543 check_insn(env
, ctx
, ASE_MT
);
3544 gen_helper_mtc0_vpecontrol(arg
);
3548 check_insn(env
, ctx
, ASE_MT
);
3549 gen_helper_mtc0_vpeconf0(arg
);
3553 check_insn(env
, ctx
, ASE_MT
);
3554 gen_helper_mtc0_vpeconf1(arg
);
3558 check_insn(env
, ctx
, ASE_MT
);
3559 gen_helper_mtc0_yqmask(arg
);
3563 check_insn(env
, ctx
, ASE_MT
);
3564 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_VPESchedule
));
3568 check_insn(env
, ctx
, ASE_MT
);
3569 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_VPEScheFBack
));
3570 rn
= "VPEScheFBack";
3573 check_insn(env
, ctx
, ASE_MT
);
3574 gen_helper_mtc0_vpeopt(arg
);
3584 gen_helper_mtc0_entrylo0(arg
);
3588 check_insn(env
, ctx
, ASE_MT
);
3589 gen_helper_mtc0_tcstatus(arg
);
3593 check_insn(env
, ctx
, ASE_MT
);
3594 gen_helper_mtc0_tcbind(arg
);
3598 check_insn(env
, ctx
, ASE_MT
);
3599 gen_helper_mtc0_tcrestart(arg
);
3603 check_insn(env
, ctx
, ASE_MT
);
3604 gen_helper_mtc0_tchalt(arg
);
3608 check_insn(env
, ctx
, ASE_MT
);
3609 gen_helper_mtc0_tccontext(arg
);
3613 check_insn(env
, ctx
, ASE_MT
);
3614 gen_helper_mtc0_tcschedule(arg
);
3618 check_insn(env
, ctx
, ASE_MT
);
3619 gen_helper_mtc0_tcschefback(arg
);
3629 gen_helper_mtc0_entrylo1(arg
);
3639 gen_helper_mtc0_context(arg
);
3643 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
3644 rn
= "ContextConfig";
3653 gen_helper_mtc0_pagemask(arg
);
3657 check_insn(env
, ctx
, ISA_MIPS32R2
);
3658 gen_helper_mtc0_pagegrain(arg
);
3668 gen_helper_mtc0_wired(arg
);
3672 check_insn(env
, ctx
, ISA_MIPS32R2
);
3673 gen_helper_mtc0_srsconf0(arg
);
3677 check_insn(env
, ctx
, ISA_MIPS32R2
);
3678 gen_helper_mtc0_srsconf1(arg
);
3682 check_insn(env
, ctx
, ISA_MIPS32R2
);
3683 gen_helper_mtc0_srsconf2(arg
);
3687 check_insn(env
, ctx
, ISA_MIPS32R2
);
3688 gen_helper_mtc0_srsconf3(arg
);
3692 check_insn(env
, ctx
, ISA_MIPS32R2
);
3693 gen_helper_mtc0_srsconf4(arg
);
3703 check_insn(env
, ctx
, ISA_MIPS32R2
);
3704 gen_helper_mtc0_hwrena(arg
);
3718 gen_helper_mtc0_count(arg
);
3721 /* 6,7 are implementation dependent */
3729 gen_helper_mtc0_entryhi(arg
);
3739 gen_helper_mtc0_compare(arg
);
3742 /* 6,7 are implementation dependent */
3750 save_cpu_state(ctx
, 1);
3751 gen_helper_mtc0_status(arg
);
3752 /* BS_STOP isn't good enough here, hflags may have changed. */
3753 gen_save_pc(ctx
->pc
+ 4);
3754 ctx
->bstate
= BS_EXCP
;
3758 check_insn(env
, ctx
, ISA_MIPS32R2
);
3759 gen_helper_mtc0_intctl(arg
);
3760 /* Stop translation as we may have switched the execution mode */
3761 ctx
->bstate
= BS_STOP
;
3765 check_insn(env
, ctx
, ISA_MIPS32R2
);
3766 gen_helper_mtc0_srsctl(arg
);
3767 /* Stop translation as we may have switched the execution mode */
3768 ctx
->bstate
= BS_STOP
;
3772 check_insn(env
, ctx
, ISA_MIPS32R2
);
3773 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_SRSMap
));
3774 /* Stop translation as we may have switched the execution mode */
3775 ctx
->bstate
= BS_STOP
;
3785 save_cpu_state(ctx
, 1);
3786 gen_helper_mtc0_cause(arg
);
3796 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_EPC
));
3810 check_insn(env
, ctx
, ISA_MIPS32R2
);
3811 gen_helper_mtc0_ebase(arg
);
3821 gen_helper_mtc0_config0(arg
);
3823 /* Stop translation as we may have switched the execution mode */
3824 ctx
->bstate
= BS_STOP
;
3827 /* ignored, read only */
3831 gen_helper_mtc0_config2(arg
);
3833 /* Stop translation as we may have switched the execution mode */
3834 ctx
->bstate
= BS_STOP
;
3837 /* ignored, read only */
3840 /* 4,5 are reserved */
3841 /* 6,7 are implementation dependent */
3851 rn
= "Invalid config selector";
3858 gen_helper_mtc0_lladdr(arg
);
3868 gen_helper_1i(mtc0_watchlo
, arg
, sel
);
3878 gen_helper_1i(mtc0_watchhi
, arg
, sel
);
3888 #if defined(TARGET_MIPS64)
3889 check_insn(env
, ctx
, ISA_MIPS3
);
3890 gen_helper_mtc0_xcontext(arg
);
3899 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3902 gen_helper_mtc0_framemask(arg
);
3911 rn
= "Diagnostic"; /* implementation dependent */
3916 gen_helper_mtc0_debug(arg
); /* EJTAG support */
3917 /* BS_STOP isn't good enough here, hflags may have changed. */
3918 gen_save_pc(ctx
->pc
+ 4);
3919 ctx
->bstate
= BS_EXCP
;
3923 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
3924 rn
= "TraceControl";
3925 /* Stop translation as we may have switched the execution mode */
3926 ctx
->bstate
= BS_STOP
;
3929 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
3930 rn
= "TraceControl2";
3931 /* Stop translation as we may have switched the execution mode */
3932 ctx
->bstate
= BS_STOP
;
3935 /* Stop translation as we may have switched the execution mode */
3936 ctx
->bstate
= BS_STOP
;
3937 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
3938 rn
= "UserTraceData";
3939 /* Stop translation as we may have switched the execution mode */
3940 ctx
->bstate
= BS_STOP
;
3943 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
3944 /* Stop translation as we may have switched the execution mode */
3945 ctx
->bstate
= BS_STOP
;
3956 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_DEPC
));
3966 gen_helper_mtc0_performance0(arg
);
3967 rn
= "Performance0";
3970 // gen_helper_mtc0_performance1(arg);
3971 rn
= "Performance1";
3974 // gen_helper_mtc0_performance2(arg);
3975 rn
= "Performance2";
3978 // gen_helper_mtc0_performance3(arg);
3979 rn
= "Performance3";
3982 // gen_helper_mtc0_performance4(arg);
3983 rn
= "Performance4";
3986 // gen_helper_mtc0_performance5(arg);
3987 rn
= "Performance5";
3990 // gen_helper_mtc0_performance6(arg);
3991 rn
= "Performance6";
3994 // gen_helper_mtc0_performance7(arg);
3995 rn
= "Performance7";
4021 gen_helper_mtc0_taglo(arg
);
4028 gen_helper_mtc0_datalo(arg
);
4041 gen_helper_mtc0_taghi(arg
);
4048 gen_helper_mtc0_datahi(arg
);
4059 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_ErrorEPC
));
4070 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_DESAVE
));
4076 /* Stop translation as we may have switched the execution mode */
4077 ctx
->bstate
= BS_STOP
;
4082 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4083 /* For simplicity assume that all writes can cause interrupts. */
4086 ctx
->bstate
= BS_STOP
;
4091 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4092 generate_exception(ctx
, EXCP_RI
);
4095 #if defined(TARGET_MIPS64)
4096 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
4098 const char *rn
= "invalid";
4101 check_insn(env
, ctx
, ISA_MIPS64
);
4107 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Index
));
4111 check_insn(env
, ctx
, ASE_MT
);
4112 gen_helper_mfc0_mvpcontrol(arg
);
4116 check_insn(env
, ctx
, ASE_MT
);
4117 gen_helper_mfc0_mvpconf0(arg
);
4121 check_insn(env
, ctx
, ASE_MT
);
4122 gen_helper_mfc0_mvpconf1(arg
);
4132 gen_helper_mfc0_random(arg
);
4136 check_insn(env
, ctx
, ASE_MT
);
4137 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEControl
));
4141 check_insn(env
, ctx
, ASE_MT
);
4142 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf0
));
4146 check_insn(env
, ctx
, ASE_MT
);
4147 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf1
));
4151 check_insn(env
, ctx
, ASE_MT
);
4152 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_YQMask
));
4156 check_insn(env
, ctx
, ASE_MT
);
4157 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4161 check_insn(env
, ctx
, ASE_MT
);
4162 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4163 rn
= "VPEScheFBack";
4166 check_insn(env
, ctx
, ASE_MT
);
4167 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEOpt
));
4177 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
4181 check_insn(env
, ctx
, ASE_MT
);
4182 gen_helper_mfc0_tcstatus(arg
);
4186 check_insn(env
, ctx
, ASE_MT
);
4187 gen_helper_mfc0_tcbind(arg
);
4191 check_insn(env
, ctx
, ASE_MT
);
4192 gen_helper_dmfc0_tcrestart(arg
);
4196 check_insn(env
, ctx
, ASE_MT
);
4197 gen_helper_dmfc0_tchalt(arg
);
4201 check_insn(env
, ctx
, ASE_MT
);
4202 gen_helper_dmfc0_tccontext(arg
);
4206 check_insn(env
, ctx
, ASE_MT
);
4207 gen_helper_dmfc0_tcschedule(arg
);
4211 check_insn(env
, ctx
, ASE_MT
);
4212 gen_helper_dmfc0_tcschefback(arg
);
4222 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
4232 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_Context
));
4236 // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
4237 rn
= "ContextConfig";
4246 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageMask
));
4250 check_insn(env
, ctx
, ISA_MIPS32R2
);
4251 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageGrain
));
4261 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Wired
));
4265 check_insn(env
, ctx
, ISA_MIPS32R2
);
4266 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf0
));
4270 check_insn(env
, ctx
, ISA_MIPS32R2
);
4271 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf1
));
4275 check_insn(env
, ctx
, ISA_MIPS32R2
);
4276 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf2
));
4280 check_insn(env
, ctx
, ISA_MIPS32R2
);
4281 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf3
));
4285 check_insn(env
, ctx
, ISA_MIPS32R2
);
4286 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf4
));
4296 check_insn(env
, ctx
, ISA_MIPS32R2
);
4297 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_HWREna
));
4307 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
4317 /* Mark as an IO operation because we read the time. */
4320 gen_helper_mfc0_count(arg
);
4323 ctx
->bstate
= BS_STOP
;
4327 /* 6,7 are implementation dependent */
4335 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
4345 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Compare
));
4348 /* 6,7 are implementation dependent */
4356 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Status
));
4360 check_insn(env
, ctx
, ISA_MIPS32R2
);
4361 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_IntCtl
));
4365 check_insn(env
, ctx
, ISA_MIPS32R2
);
4366 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSCtl
));
4370 check_insn(env
, ctx
, ISA_MIPS32R2
);
4371 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSMap
));
4381 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Cause
));
4391 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4401 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PRid
));
4405 check_insn(env
, ctx
, ISA_MIPS32R2
);
4406 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_EBase
));
4416 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config0
));
4420 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config1
));
4424 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config2
));
4428 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config3
));
4431 /* 6,7 are implementation dependent */
4433 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config6
));
4437 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config7
));
4447 gen_helper_dmfc0_lladdr(arg
);
4457 gen_helper_1i(dmfc0_watchlo
, arg
, sel
);
4467 gen_helper_1i(mfc0_watchhi
, arg
, sel
);
4477 check_insn(env
, ctx
, ISA_MIPS3
);
4478 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
4486 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4489 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Framemask
));
4497 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4498 rn
= "'Diagnostic"; /* implementation dependent */
4503 gen_helper_mfc0_debug(arg
); /* EJTAG support */
4507 // gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
4508 rn
= "TraceControl";
4511 // gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
4512 rn
= "TraceControl2";
4515 // gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
4516 rn
= "UserTraceData";
4519 // gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
4530 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
4540 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Performance0
));
4541 rn
= "Performance0";
4544 // gen_helper_dmfc0_performance1(arg);
4545 rn
= "Performance1";
4548 // gen_helper_dmfc0_performance2(arg);
4549 rn
= "Performance2";
4552 // gen_helper_dmfc0_performance3(arg);
4553 rn
= "Performance3";
4556 // gen_helper_dmfc0_performance4(arg);
4557 rn
= "Performance4";
4560 // gen_helper_dmfc0_performance5(arg);
4561 rn
= "Performance5";
4564 // gen_helper_dmfc0_performance6(arg);
4565 rn
= "Performance6";
4568 // gen_helper_dmfc0_performance7(arg);
4569 rn
= "Performance7";
4576 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4583 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4596 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagLo
));
4603 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataLo
));
4616 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagHi
));
4623 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataHi
));
4633 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
4644 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DESAVE
));
4654 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4658 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4659 generate_exception(ctx
, EXCP_RI
);
4662 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
4664 const char *rn
= "invalid";
4667 check_insn(env
, ctx
, ISA_MIPS64
);
4676 gen_helper_mtc0_index(arg
);
4680 check_insn(env
, ctx
, ASE_MT
);
4681 gen_helper_mtc0_mvpcontrol(arg
);
4685 check_insn(env
, ctx
, ASE_MT
);
4690 check_insn(env
, ctx
, ASE_MT
);
4705 check_insn(env
, ctx
, ASE_MT
);
4706 gen_helper_mtc0_vpecontrol(arg
);
4710 check_insn(env
, ctx
, ASE_MT
);
4711 gen_helper_mtc0_vpeconf0(arg
);
4715 check_insn(env
, ctx
, ASE_MT
);
4716 gen_helper_mtc0_vpeconf1(arg
);
4720 check_insn(env
, ctx
, ASE_MT
);
4721 gen_helper_mtc0_yqmask(arg
);
4725 check_insn(env
, ctx
, ASE_MT
);
4726 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4730 check_insn(env
, ctx
, ASE_MT
);
4731 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4732 rn
= "VPEScheFBack";
4735 check_insn(env
, ctx
, ASE_MT
);
4736 gen_helper_mtc0_vpeopt(arg
);
4746 gen_helper_mtc0_entrylo0(arg
);
4750 check_insn(env
, ctx
, ASE_MT
);
4751 gen_helper_mtc0_tcstatus(arg
);
4755 check_insn(env
, ctx
, ASE_MT
);
4756 gen_helper_mtc0_tcbind(arg
);
4760 check_insn(env
, ctx
, ASE_MT
);
4761 gen_helper_mtc0_tcrestart(arg
);
4765 check_insn(env
, ctx
, ASE_MT
);
4766 gen_helper_mtc0_tchalt(arg
);
4770 check_insn(env
, ctx
, ASE_MT
);
4771 gen_helper_mtc0_tccontext(arg
);
4775 check_insn(env
, ctx
, ASE_MT
);
4776 gen_helper_mtc0_tcschedule(arg
);
4780 check_insn(env
, ctx
, ASE_MT
);
4781 gen_helper_mtc0_tcschefback(arg
);
4791 gen_helper_mtc0_entrylo1(arg
);
4801 gen_helper_mtc0_context(arg
);
4805 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
4806 rn
= "ContextConfig";
4815 gen_helper_mtc0_pagemask(arg
);
4819 check_insn(env
, ctx
, ISA_MIPS32R2
);
4820 gen_helper_mtc0_pagegrain(arg
);
4830 gen_helper_mtc0_wired(arg
);
4834 check_insn(env
, ctx
, ISA_MIPS32R2
);
4835 gen_helper_mtc0_srsconf0(arg
);
4839 check_insn(env
, ctx
, ISA_MIPS32R2
);
4840 gen_helper_mtc0_srsconf1(arg
);
4844 check_insn(env
, ctx
, ISA_MIPS32R2
);
4845 gen_helper_mtc0_srsconf2(arg
);
4849 check_insn(env
, ctx
, ISA_MIPS32R2
);
4850 gen_helper_mtc0_srsconf3(arg
);
4854 check_insn(env
, ctx
, ISA_MIPS32R2
);
4855 gen_helper_mtc0_srsconf4(arg
);
4865 check_insn(env
, ctx
, ISA_MIPS32R2
);
4866 gen_helper_mtc0_hwrena(arg
);
4880 gen_helper_mtc0_count(arg
);
4883 /* 6,7 are implementation dependent */
4887 /* Stop translation as we may have switched the execution mode */
4888 ctx
->bstate
= BS_STOP
;
4893 gen_helper_mtc0_entryhi(arg
);
4903 gen_helper_mtc0_compare(arg
);
4906 /* 6,7 are implementation dependent */
4910 /* Stop translation as we may have switched the execution mode */
4911 ctx
->bstate
= BS_STOP
;
4916 save_cpu_state(ctx
, 1);
4917 gen_helper_mtc0_status(arg
);
4918 /* BS_STOP isn't good enough here, hflags may have changed. */
4919 gen_save_pc(ctx
->pc
+ 4);
4920 ctx
->bstate
= BS_EXCP
;
4924 check_insn(env
, ctx
, ISA_MIPS32R2
);
4925 gen_helper_mtc0_intctl(arg
);
4926 /* Stop translation as we may have switched the execution mode */
4927 ctx
->bstate
= BS_STOP
;
4931 check_insn(env
, ctx
, ISA_MIPS32R2
);
4932 gen_helper_mtc0_srsctl(arg
);
4933 /* Stop translation as we may have switched the execution mode */
4934 ctx
->bstate
= BS_STOP
;
4938 check_insn(env
, ctx
, ISA_MIPS32R2
);
4939 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_SRSMap
));
4940 /* Stop translation as we may have switched the execution mode */
4941 ctx
->bstate
= BS_STOP
;
4951 save_cpu_state(ctx
, 1);
4952 gen_helper_mtc0_cause(arg
);
4962 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4976 check_insn(env
, ctx
, ISA_MIPS32R2
);
4977 gen_helper_mtc0_ebase(arg
);
4987 gen_helper_mtc0_config0(arg
);
4989 /* Stop translation as we may have switched the execution mode */
4990 ctx
->bstate
= BS_STOP
;
4993 /* ignored, read only */
4997 gen_helper_mtc0_config2(arg
);
4999 /* Stop translation as we may have switched the execution mode */
5000 ctx
->bstate
= BS_STOP
;
5006 /* 6,7 are implementation dependent */
5008 rn
= "Invalid config selector";
5015 gen_helper_mtc0_lladdr(arg
);
5025 gen_helper_1i(mtc0_watchlo
, arg
, sel
);
5035 gen_helper_1i(mtc0_watchhi
, arg
, sel
);
5045 check_insn(env
, ctx
, ISA_MIPS3
);
5046 gen_helper_mtc0_xcontext(arg
);
5054 /* Officially reserved, but sel 0 is used for R1x000 framemask */
5057 gen_helper_mtc0_framemask(arg
);
5066 rn
= "Diagnostic"; /* implementation dependent */
5071 gen_helper_mtc0_debug(arg
); /* EJTAG support */
5072 /* BS_STOP isn't good enough here, hflags may have changed. */
5073 gen_save_pc(ctx
->pc
+ 4);
5074 ctx
->bstate
= BS_EXCP
;
5078 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
5079 /* Stop translation as we may have switched the execution mode */
5080 ctx
->bstate
= BS_STOP
;
5081 rn
= "TraceControl";
5084 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
5085 /* Stop translation as we may have switched the execution mode */
5086 ctx
->bstate
= BS_STOP
;
5087 rn
= "TraceControl2";
5090 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
5091 /* Stop translation as we may have switched the execution mode */
5092 ctx
->bstate
= BS_STOP
;
5093 rn
= "UserTraceData";
5096 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
5097 /* Stop translation as we may have switched the execution mode */
5098 ctx
->bstate
= BS_STOP
;
5109 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
5119 gen_helper_mtc0_performance0(arg
);
5120 rn
= "Performance0";
5123 // gen_helper_mtc0_performance1(arg);
5124 rn
= "Performance1";
5127 // gen_helper_mtc0_performance2(arg);
5128 rn
= "Performance2";
5131 // gen_helper_mtc0_performance3(arg);
5132 rn
= "Performance3";
5135 // gen_helper_mtc0_performance4(arg);
5136 rn
= "Performance4";
5139 // gen_helper_mtc0_performance5(arg);
5140 rn
= "Performance5";
5143 // gen_helper_mtc0_performance6(arg);
5144 rn
= "Performance6";
5147 // gen_helper_mtc0_performance7(arg);
5148 rn
= "Performance7";
5174 gen_helper_mtc0_taglo(arg
);
5181 gen_helper_mtc0_datalo(arg
);
5194 gen_helper_mtc0_taghi(arg
);
5201 gen_helper_mtc0_datahi(arg
);
5212 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
5223 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_DESAVE
));
5229 /* Stop translation as we may have switched the execution mode */
5230 ctx
->bstate
= BS_STOP
;
5235 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5236 /* For simplicity assume that all writes can cause interrupts. */
5239 ctx
->bstate
= BS_STOP
;
5244 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5245 generate_exception(ctx
, EXCP_RI
);
5247 #endif /* TARGET_MIPS64 */
5249 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
, int rd
,
5250 int u
, int sel
, int h
)
5252 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5253 TCGv t0
= tcg_temp_local_new();
5255 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5256 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5257 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5258 tcg_gen_movi_tl(t0
, -1);
5259 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5260 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5261 tcg_gen_movi_tl(t0
, -1);
5267 gen_helper_mftc0_tcstatus(t0
);
5270 gen_helper_mftc0_tcbind(t0
);
5273 gen_helper_mftc0_tcrestart(t0
);
5276 gen_helper_mftc0_tchalt(t0
);
5279 gen_helper_mftc0_tccontext(t0
);
5282 gen_helper_mftc0_tcschedule(t0
);
5285 gen_helper_mftc0_tcschefback(t0
);
5288 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5295 gen_helper_mftc0_entryhi(t0
);
5298 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5304 gen_helper_mftc0_status(t0
);
5307 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5313 gen_helper_mftc0_debug(t0
);
5316 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5321 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5323 } else switch (sel
) {
5324 /* GPR registers. */
5326 gen_helper_1i(mftgpr
, t0
, rt
);
5328 /* Auxiliary CPU registers */
5332 gen_helper_1i(mftlo
, t0
, 0);
5335 gen_helper_1i(mfthi
, t0
, 0);
5338 gen_helper_1i(mftacx
, t0
, 0);
5341 gen_helper_1i(mftlo
, t0
, 1);
5344 gen_helper_1i(mfthi
, t0
, 1);
5347 gen_helper_1i(mftacx
, t0
, 1);
5350 gen_helper_1i(mftlo
, t0
, 2);
5353 gen_helper_1i(mfthi
, t0
, 2);
5356 gen_helper_1i(mftacx
, t0
, 2);
5359 gen_helper_1i(mftlo
, t0
, 3);
5362 gen_helper_1i(mfthi
, t0
, 3);
5365 gen_helper_1i(mftacx
, t0
, 3);
5368 gen_helper_mftdsp(t0
);
5374 /* Floating point (COP1). */
5376 /* XXX: For now we support only a single FPU context. */
5378 TCGv_i32 fp0
= tcg_temp_new_i32();
5380 gen_load_fpr32(fp0
, rt
);
5381 tcg_gen_ext_i32_tl(t0
, fp0
);
5382 tcg_temp_free_i32(fp0
);
5384 TCGv_i32 fp0
= tcg_temp_new_i32();
5386 gen_load_fpr32h(fp0
, rt
);
5387 tcg_gen_ext_i32_tl(t0
, fp0
);
5388 tcg_temp_free_i32(fp0
);
5392 /* XXX: For now we support only a single FPU context. */
5393 gen_helper_1i(cfc1
, t0
, rt
);
5395 /* COP2: Not implemented. */
5402 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5403 gen_store_gpr(t0
, rd
);
5409 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5410 generate_exception(ctx
, EXCP_RI
);
5413 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
, int rt
,
5414 int u
, int sel
, int h
)
5416 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5417 TCGv t0
= tcg_temp_local_new();
5419 gen_load_gpr(t0
, rt
);
5420 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5421 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5422 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5424 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5425 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5432 gen_helper_mttc0_tcstatus(t0
);
5435 gen_helper_mttc0_tcbind(t0
);
5438 gen_helper_mttc0_tcrestart(t0
);
5441 gen_helper_mttc0_tchalt(t0
);
5444 gen_helper_mttc0_tccontext(t0
);
5447 gen_helper_mttc0_tcschedule(t0
);
5450 gen_helper_mttc0_tcschefback(t0
);
5453 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5460 gen_helper_mttc0_entryhi(t0
);
5463 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5469 gen_helper_mttc0_status(t0
);
5472 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5478 gen_helper_mttc0_debug(t0
);
5481 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5486 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5488 } else switch (sel
) {
5489 /* GPR registers. */
5491 gen_helper_1i(mttgpr
, t0
, rd
);
5493 /* Auxiliary CPU registers */
5497 gen_helper_1i(mttlo
, t0
, 0);
5500 gen_helper_1i(mtthi
, t0
, 0);
5503 gen_helper_1i(mttacx
, t0
, 0);
5506 gen_helper_1i(mttlo
, t0
, 1);
5509 gen_helper_1i(mtthi
, t0
, 1);
5512 gen_helper_1i(mttacx
, t0
, 1);
5515 gen_helper_1i(mttlo
, t0
, 2);
5518 gen_helper_1i(mtthi
, t0
, 2);
5521 gen_helper_1i(mttacx
, t0
, 2);
5524 gen_helper_1i(mttlo
, t0
, 3);
5527 gen_helper_1i(mtthi
, t0
, 3);
5530 gen_helper_1i(mttacx
, t0
, 3);
5533 gen_helper_mttdsp(t0
);
5539 /* Floating point (COP1). */
5541 /* XXX: For now we support only a single FPU context. */
5543 TCGv_i32 fp0
= tcg_temp_new_i32();
5545 tcg_gen_trunc_tl_i32(fp0
, t0
);
5546 gen_store_fpr32(fp0
, rd
);
5547 tcg_temp_free_i32(fp0
);
5549 TCGv_i32 fp0
= tcg_temp_new_i32();
5551 tcg_gen_trunc_tl_i32(fp0
, t0
);
5552 gen_store_fpr32h(fp0
, rd
);
5553 tcg_temp_free_i32(fp0
);
5557 /* XXX: For now we support only a single FPU context. */
5558 gen_helper_1i(ctc1
, t0
, rd
);
5560 /* COP2: Not implemented. */
5567 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5573 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5574 generate_exception(ctx
, EXCP_RI
);
5577 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
5579 const char *opn
= "ldst";
5587 gen_mfc0(env
, ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
5592 TCGv t0
= tcg_temp_new();
5594 gen_load_gpr(t0
, rt
);
5595 gen_mtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5600 #if defined(TARGET_MIPS64)
5602 check_insn(env
, ctx
, ISA_MIPS3
);
5607 gen_dmfc0(env
, ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
5611 check_insn(env
, ctx
, ISA_MIPS3
);
5613 TCGv t0
= tcg_temp_new();
5615 gen_load_gpr(t0
, rt
);
5616 gen_dmtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5623 check_insn(env
, ctx
, ASE_MT
);
5628 gen_mftr(env
, ctx
, rt
, rd
, (ctx
->opcode
>> 5) & 1,
5629 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5633 check_insn(env
, ctx
, ASE_MT
);
5634 gen_mttr(env
, ctx
, rd
, rt
, (ctx
->opcode
>> 5) & 1,
5635 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5640 if (!env
->tlb
->helper_tlbwi
)
5646 if (!env
->tlb
->helper_tlbwr
)
5652 if (!env
->tlb
->helper_tlbp
)
5658 if (!env
->tlb
->helper_tlbr
)
5664 check_insn(env
, ctx
, ISA_MIPS2
);
5666 ctx
->bstate
= BS_EXCP
;
5670 check_insn(env
, ctx
, ISA_MIPS32
);
5671 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5673 generate_exception(ctx
, EXCP_RI
);
5676 ctx
->bstate
= BS_EXCP
;
5681 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
5682 /* If we get an exception, we want to restart at next instruction */
5684 save_cpu_state(ctx
, 1);
5687 ctx
->bstate
= BS_EXCP
;
5692 generate_exception(ctx
, EXCP_RI
);
5695 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
5697 #endif /* !CONFIG_USER_ONLY */
5699 /* CP1 Branches (before delay slot) */
5700 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
5701 int32_t cc
, int32_t offset
)
5703 target_ulong btarget
;
5704 const char *opn
= "cp1 cond branch";
5705 TCGv_i32 t0
= tcg_temp_new_i32();
5708 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
5710 btarget
= ctx
->pc
+ 4 + offset
;
5714 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5715 tcg_gen_not_i32(t0
, t0
);
5716 tcg_gen_andi_i32(t0
, t0
, 1);
5717 tcg_gen_extu_i32_tl(bcond
, t0
);
5721 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5722 tcg_gen_not_i32(t0
, t0
);
5723 tcg_gen_andi_i32(t0
, t0
, 1);
5724 tcg_gen_extu_i32_tl(bcond
, t0
);
5728 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5729 tcg_gen_andi_i32(t0
, t0
, 1);
5730 tcg_gen_extu_i32_tl(bcond
, t0
);
5734 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5735 tcg_gen_andi_i32(t0
, t0
, 1);
5736 tcg_gen_extu_i32_tl(bcond
, t0
);
5739 ctx
->hflags
|= MIPS_HFLAG_BL
;
5743 TCGv_i32 t1
= tcg_temp_new_i32();
5744 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5745 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5746 tcg_gen_nor_i32(t0
, t0
, t1
);
5747 tcg_temp_free_i32(t1
);
5748 tcg_gen_andi_i32(t0
, t0
, 1);
5749 tcg_gen_extu_i32_tl(bcond
, t0
);
5755 TCGv_i32 t1
= tcg_temp_new_i32();
5756 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5757 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5758 tcg_gen_or_i32(t0
, t0
, t1
);
5759 tcg_temp_free_i32(t1
);
5760 tcg_gen_andi_i32(t0
, t0
, 1);
5761 tcg_gen_extu_i32_tl(bcond
, t0
);
5767 TCGv_i32 t1
= tcg_temp_new_i32();
5768 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5769 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5770 tcg_gen_or_i32(t0
, t0
, t1
);
5771 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
5772 tcg_gen_or_i32(t0
, t0
, t1
);
5773 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
5774 tcg_gen_nor_i32(t0
, t0
, t1
);
5775 tcg_temp_free_i32(t1
);
5776 tcg_gen_andi_i32(t0
, t0
, 1);
5777 tcg_gen_extu_i32_tl(bcond
, t0
);
5783 TCGv_i32 t1
= tcg_temp_new_i32();
5784 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5785 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5786 tcg_gen_or_i32(t0
, t0
, t1
);
5787 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
5788 tcg_gen_or_i32(t0
, t0
, t1
);
5789 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
5790 tcg_gen_or_i32(t0
, t0
, t1
);
5791 tcg_temp_free_i32(t1
);
5792 tcg_gen_andi_i32(t0
, t0
, 1);
5793 tcg_gen_extu_i32_tl(bcond
, t0
);
5797 ctx
->hflags
|= MIPS_HFLAG_BC
;
5801 generate_exception (ctx
, EXCP_RI
);
5804 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
5805 ctx
->hflags
, btarget
);
5806 ctx
->btarget
= btarget
;
5809 tcg_temp_free_i32(t0
);
5812 /* Coprocessor 1 (FPU) */
5814 #define FOP(func, fmt) (((fmt) << 21) | (func))
5817 OPC_ADD_S
= FOP(0, FMT_S
),
5818 OPC_SUB_S
= FOP(1, FMT_S
),
5819 OPC_MUL_S
= FOP(2, FMT_S
),
5820 OPC_DIV_S
= FOP(3, FMT_S
),
5821 OPC_SQRT_S
= FOP(4, FMT_S
),
5822 OPC_ABS_S
= FOP(5, FMT_S
),
5823 OPC_MOV_S
= FOP(6, FMT_S
),
5824 OPC_NEG_S
= FOP(7, FMT_S
),
5825 OPC_ROUND_L_S
= FOP(8, FMT_S
),
5826 OPC_TRUNC_L_S
= FOP(9, FMT_S
),
5827 OPC_CEIL_L_S
= FOP(10, FMT_S
),
5828 OPC_FLOOR_L_S
= FOP(11, FMT_S
),
5829 OPC_ROUND_W_S
= FOP(12, FMT_S
),
5830 OPC_TRUNC_W_S
= FOP(13, FMT_S
),
5831 OPC_CEIL_W_S
= FOP(14, FMT_S
),
5832 OPC_FLOOR_W_S
= FOP(15, FMT_S
),
5833 OPC_MOVCF_S
= FOP(17, FMT_S
),
5834 OPC_MOVZ_S
= FOP(18, FMT_S
),
5835 OPC_MOVN_S
= FOP(19, FMT_S
),
5836 OPC_RECIP_S
= FOP(21, FMT_S
),
5837 OPC_RSQRT_S
= FOP(22, FMT_S
),
5838 OPC_RECIP2_S
= FOP(28, FMT_S
),
5839 OPC_RECIP1_S
= FOP(29, FMT_S
),
5840 OPC_RSQRT1_S
= FOP(30, FMT_S
),
5841 OPC_RSQRT2_S
= FOP(31, FMT_S
),
5842 OPC_CVT_D_S
= FOP(33, FMT_S
),
5843 OPC_CVT_W_S
= FOP(36, FMT_S
),
5844 OPC_CVT_L_S
= FOP(37, FMT_S
),
5845 OPC_CVT_PS_S
= FOP(38, FMT_S
),
5846 OPC_CMP_F_S
= FOP (48, FMT_S
),
5847 OPC_CMP_UN_S
= FOP (49, FMT_S
),
5848 OPC_CMP_EQ_S
= FOP (50, FMT_S
),
5849 OPC_CMP_UEQ_S
= FOP (51, FMT_S
),
5850 OPC_CMP_OLT_S
= FOP (52, FMT_S
),
5851 OPC_CMP_ULT_S
= FOP (53, FMT_S
),
5852 OPC_CMP_OLE_S
= FOP (54, FMT_S
),
5853 OPC_CMP_ULE_S
= FOP (55, FMT_S
),
5854 OPC_CMP_SF_S
= FOP (56, FMT_S
),
5855 OPC_CMP_NGLE_S
= FOP (57, FMT_S
),
5856 OPC_CMP_SEQ_S
= FOP (58, FMT_S
),
5857 OPC_CMP_NGL_S
= FOP (59, FMT_S
),
5858 OPC_CMP_LT_S
= FOP (60, FMT_S
),
5859 OPC_CMP_NGE_S
= FOP (61, FMT_S
),
5860 OPC_CMP_LE_S
= FOP (62, FMT_S
),
5861 OPC_CMP_NGT_S
= FOP (63, FMT_S
),
5863 OPC_ADD_D
= FOP(0, FMT_D
),
5864 OPC_SUB_D
= FOP(1, FMT_D
),
5865 OPC_MUL_D
= FOP(2, FMT_D
),
5866 OPC_DIV_D
= FOP(3, FMT_D
),
5867 OPC_SQRT_D
= FOP(4, FMT_D
),
5868 OPC_ABS_D
= FOP(5, FMT_D
),
5869 OPC_MOV_D
= FOP(6, FMT_D
),
5870 OPC_NEG_D
= FOP(7, FMT_D
),
5871 OPC_ROUND_L_D
= FOP(8, FMT_D
),
5872 OPC_TRUNC_L_D
= FOP(9, FMT_D
),
5873 OPC_CEIL_L_D
= FOP(10, FMT_D
),
5874 OPC_FLOOR_L_D
= FOP(11, FMT_D
),
5875 OPC_ROUND_W_D
= FOP(12, FMT_D
),
5876 OPC_TRUNC_W_D
= FOP(13, FMT_D
),
5877 OPC_CEIL_W_D
= FOP(14, FMT_D
),
5878 OPC_FLOOR_W_D
= FOP(15, FMT_D
),
5879 OPC_MOVCF_D
= FOP(17, FMT_D
),
5880 OPC_MOVZ_D
= FOP(18, FMT_D
),
5881 OPC_MOVN_D
= FOP(19, FMT_D
),
5882 OPC_RECIP_D
= FOP(21, FMT_D
),
5883 OPC_RSQRT_D
= FOP(22, FMT_D
),
5884 OPC_RECIP2_D
= FOP(28, FMT_D
),
5885 OPC_RECIP1_D
= FOP(29, FMT_D
),
5886 OPC_RSQRT1_D
= FOP(30, FMT_D
),
5887 OPC_RSQRT2_D
= FOP(31, FMT_D
),
5888 OPC_CVT_S_D
= FOP(32, FMT_D
),
5889 OPC_CVT_W_D
= FOP(36, FMT_D
),
5890 OPC_CVT_L_D
= FOP(37, FMT_D
),
5891 OPC_CMP_F_D
= FOP (48, FMT_D
),
5892 OPC_CMP_UN_D
= FOP (49, FMT_D
),
5893 OPC_CMP_EQ_D
= FOP (50, FMT_D
),
5894 OPC_CMP_UEQ_D
= FOP (51, FMT_D
),
5895 OPC_CMP_OLT_D
= FOP (52, FMT_D
),
5896 OPC_CMP_ULT_D
= FOP (53, FMT_D
),
5897 OPC_CMP_OLE_D
= FOP (54, FMT_D
),
5898 OPC_CMP_ULE_D
= FOP (55, FMT_D
),
5899 OPC_CMP_SF_D
= FOP (56, FMT_D
),
5900 OPC_CMP_NGLE_D
= FOP (57, FMT_D
),
5901 OPC_CMP_SEQ_D
= FOP (58, FMT_D
),
5902 OPC_CMP_NGL_D
= FOP (59, FMT_D
),
5903 OPC_CMP_LT_D
= FOP (60, FMT_D
),
5904 OPC_CMP_NGE_D
= FOP (61, FMT_D
),
5905 OPC_CMP_LE_D
= FOP (62, FMT_D
),
5906 OPC_CMP_NGT_D
= FOP (63, FMT_D
),
5908 OPC_CVT_S_W
= FOP(32, FMT_W
),
5909 OPC_CVT_D_W
= FOP(33, FMT_W
),
5910 OPC_CVT_S_L
= FOP(32, FMT_L
),
5911 OPC_CVT_D_L
= FOP(33, FMT_L
),
5912 OPC_CVT_PS_PW
= FOP(38, FMT_W
),
5914 OPC_ADD_PS
= FOP(0, FMT_PS
),
5915 OPC_SUB_PS
= FOP(1, FMT_PS
),
5916 OPC_MUL_PS
= FOP(2, FMT_PS
),
5917 OPC_DIV_PS
= FOP(3, FMT_PS
),
5918 OPC_ABS_PS
= FOP(5, FMT_PS
),
5919 OPC_MOV_PS
= FOP(6, FMT_PS
),
5920 OPC_NEG_PS
= FOP(7, FMT_PS
),
5921 OPC_MOVCF_PS
= FOP(17, FMT_PS
),
5922 OPC_MOVZ_PS
= FOP(18, FMT_PS
),
5923 OPC_MOVN_PS
= FOP(19, FMT_PS
),
5924 OPC_ADDR_PS
= FOP(24, FMT_PS
),
5925 OPC_MULR_PS
= FOP(26, FMT_PS
),
5926 OPC_RECIP2_PS
= FOP(28, FMT_PS
),
5927 OPC_RECIP1_PS
= FOP(29, FMT_PS
),
5928 OPC_RSQRT1_PS
= FOP(30, FMT_PS
),
5929 OPC_RSQRT2_PS
= FOP(31, FMT_PS
),
5931 OPC_CVT_S_PU
= FOP(32, FMT_PS
),
5932 OPC_CVT_PW_PS
= FOP(36, FMT_PS
),
5933 OPC_CVT_S_PL
= FOP(40, FMT_PS
),
5934 OPC_PLL_PS
= FOP(44, FMT_PS
),
5935 OPC_PLU_PS
= FOP(45, FMT_PS
),
5936 OPC_PUL_PS
= FOP(46, FMT_PS
),
5937 OPC_PUU_PS
= FOP(47, FMT_PS
),
5938 OPC_CMP_F_PS
= FOP (48, FMT_PS
),
5939 OPC_CMP_UN_PS
= FOP (49, FMT_PS
),
5940 OPC_CMP_EQ_PS
= FOP (50, FMT_PS
),
5941 OPC_CMP_UEQ_PS
= FOP (51, FMT_PS
),
5942 OPC_CMP_OLT_PS
= FOP (52, FMT_PS
),
5943 OPC_CMP_ULT_PS
= FOP (53, FMT_PS
),
5944 OPC_CMP_OLE_PS
= FOP (54, FMT_PS
),
5945 OPC_CMP_ULE_PS
= FOP (55, FMT_PS
),
5946 OPC_CMP_SF_PS
= FOP (56, FMT_PS
),
5947 OPC_CMP_NGLE_PS
= FOP (57, FMT_PS
),
5948 OPC_CMP_SEQ_PS
= FOP (58, FMT_PS
),
5949 OPC_CMP_NGL_PS
= FOP (59, FMT_PS
),
5950 OPC_CMP_LT_PS
= FOP (60, FMT_PS
),
5951 OPC_CMP_NGE_PS
= FOP (61, FMT_PS
),
5952 OPC_CMP_LE_PS
= FOP (62, FMT_PS
),
5953 OPC_CMP_NGT_PS
= FOP (63, FMT_PS
),
5956 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
5958 const char *opn
= "cp1 move";
5959 TCGv t0
= tcg_temp_new();
5964 TCGv_i32 fp0
= tcg_temp_new_i32();
5966 gen_load_fpr32(fp0
, fs
);
5967 tcg_gen_ext_i32_tl(t0
, fp0
);
5968 tcg_temp_free_i32(fp0
);
5970 gen_store_gpr(t0
, rt
);
5974 gen_load_gpr(t0
, rt
);
5976 TCGv_i32 fp0
= tcg_temp_new_i32();
5978 tcg_gen_trunc_tl_i32(fp0
, t0
);
5979 gen_store_fpr32(fp0
, fs
);
5980 tcg_temp_free_i32(fp0
);
5985 gen_helper_1i(cfc1
, t0
, fs
);
5986 gen_store_gpr(t0
, rt
);
5990 gen_load_gpr(t0
, rt
);
5991 gen_helper_1i(ctc1
, t0
, fs
);
5994 #if defined(TARGET_MIPS64)
5996 gen_load_fpr64(ctx
, t0
, fs
);
5997 gen_store_gpr(t0
, rt
);
6001 gen_load_gpr(t0
, rt
);
6002 gen_store_fpr64(ctx
, t0
, fs
);
6008 TCGv_i32 fp0
= tcg_temp_new_i32();
6010 gen_load_fpr32h(fp0
, fs
);
6011 tcg_gen_ext_i32_tl(t0
, fp0
);
6012 tcg_temp_free_i32(fp0
);
6014 gen_store_gpr(t0
, rt
);
6018 gen_load_gpr(t0
, rt
);
6020 TCGv_i32 fp0
= tcg_temp_new_i32();
6022 tcg_gen_trunc_tl_i32(fp0
, t0
);
6023 gen_store_fpr32h(fp0
, fs
);
6024 tcg_temp_free_i32(fp0
);
6030 generate_exception (ctx
, EXCP_RI
);
6033 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
6039 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
6055 l1
= gen_new_label();
6056 t0
= tcg_temp_new_i32();
6057 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
6058 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
6059 tcg_temp_free_i32(t0
);
6061 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
6063 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
6068 static inline void gen_movcf_s (int fs
, int fd
, int cc
, int tf
)
6071 TCGv_i32 t0
= tcg_temp_new_i32();
6072 int l1
= gen_new_label();
6079 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
6080 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
6081 gen_load_fpr32(t0
, fs
);
6082 gen_store_fpr32(t0
, fd
);
6084 tcg_temp_free_i32(t0
);
6087 static inline void gen_movcf_d (DisasContext
*ctx
, int fs
, int fd
, int cc
, int tf
)
6090 TCGv_i32 t0
= tcg_temp_new_i32();
6092 int l1
= gen_new_label();
6099 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
6100 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
6101 tcg_temp_free_i32(t0
);
6102 fp0
= tcg_temp_new_i64();
6103 gen_load_fpr64(ctx
, fp0
, fs
);
6104 gen_store_fpr64(ctx
, fp0
, fd
);
6105 tcg_temp_free_i64(fp0
);
6109 static inline void gen_movcf_ps (int fs
, int fd
, int cc
, int tf
)
6112 TCGv_i32 t0
= tcg_temp_new_i32();
6113 int l1
= gen_new_label();
6114 int l2
= gen_new_label();
6121 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
6122 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
6123 gen_load_fpr32(t0
, fs
);
6124 gen_store_fpr32(t0
, fd
);
6127 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
+1));
6128 tcg_gen_brcondi_i32(cond
, t0
, 0, l2
);
6129 gen_load_fpr32h(t0
, fs
);
6130 gen_store_fpr32h(t0
, fd
);
6131 tcg_temp_free_i32(t0
);
6136 static void gen_farith (DisasContext
*ctx
, enum fopcode op1
,
6137 int ft
, int fs
, int fd
, int cc
)
6139 const char *opn
= "farith";
6140 const char *condnames
[] = {
6158 const char *condnames_abs
[] = {
6176 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
6177 uint32_t func
= ctx
->opcode
& 0x3f;
6182 TCGv_i32 fp0
= tcg_temp_new_i32();
6183 TCGv_i32 fp1
= tcg_temp_new_i32();
6185 gen_load_fpr32(fp0
, fs
);
6186 gen_load_fpr32(fp1
, ft
);
6187 gen_helper_float_add_s(fp0
, fp0
, fp1
);
6188 tcg_temp_free_i32(fp1
);
6189 gen_store_fpr32(fp0
, fd
);
6190 tcg_temp_free_i32(fp0
);
6197 TCGv_i32 fp0
= tcg_temp_new_i32();
6198 TCGv_i32 fp1
= tcg_temp_new_i32();
6200 gen_load_fpr32(fp0
, fs
);
6201 gen_load_fpr32(fp1
, ft
);
6202 gen_helper_float_sub_s(fp0
, fp0
, fp1
);
6203 tcg_temp_free_i32(fp1
);
6204 gen_store_fpr32(fp0
, fd
);
6205 tcg_temp_free_i32(fp0
);
6212 TCGv_i32 fp0
= tcg_temp_new_i32();
6213 TCGv_i32 fp1
= tcg_temp_new_i32();
6215 gen_load_fpr32(fp0
, fs
);
6216 gen_load_fpr32(fp1
, ft
);
6217 gen_helper_float_mul_s(fp0
, fp0
, fp1
);
6218 tcg_temp_free_i32(fp1
);
6219 gen_store_fpr32(fp0
, fd
);
6220 tcg_temp_free_i32(fp0
);
6227 TCGv_i32 fp0
= tcg_temp_new_i32();
6228 TCGv_i32 fp1
= tcg_temp_new_i32();
6230 gen_load_fpr32(fp0
, fs
);
6231 gen_load_fpr32(fp1
, ft
);
6232 gen_helper_float_div_s(fp0
, fp0
, fp1
);
6233 tcg_temp_free_i32(fp1
);
6234 gen_store_fpr32(fp0
, fd
);
6235 tcg_temp_free_i32(fp0
);
6242 TCGv_i32 fp0
= tcg_temp_new_i32();
6244 gen_load_fpr32(fp0
, fs
);
6245 gen_helper_float_sqrt_s(fp0
, fp0
);
6246 gen_store_fpr32(fp0
, fd
);
6247 tcg_temp_free_i32(fp0
);
6253 TCGv_i32 fp0
= tcg_temp_new_i32();
6255 gen_load_fpr32(fp0
, fs
);
6256 gen_helper_float_abs_s(fp0
, fp0
);
6257 gen_store_fpr32(fp0
, fd
);
6258 tcg_temp_free_i32(fp0
);
6264 TCGv_i32 fp0
= tcg_temp_new_i32();
6266 gen_load_fpr32(fp0
, fs
);
6267 gen_store_fpr32(fp0
, fd
);
6268 tcg_temp_free_i32(fp0
);
6274 TCGv_i32 fp0
= tcg_temp_new_i32();
6276 gen_load_fpr32(fp0
, fs
);
6277 gen_helper_float_chs_s(fp0
, fp0
);
6278 gen_store_fpr32(fp0
, fd
);
6279 tcg_temp_free_i32(fp0
);
6284 check_cp1_64bitmode(ctx
);
6286 TCGv_i32 fp32
= tcg_temp_new_i32();
6287 TCGv_i64 fp64
= tcg_temp_new_i64();
6289 gen_load_fpr32(fp32
, fs
);
6290 gen_helper_float_roundl_s(fp64
, fp32
);
6291 tcg_temp_free_i32(fp32
);
6292 gen_store_fpr64(ctx
, fp64
, fd
);
6293 tcg_temp_free_i64(fp64
);
6298 check_cp1_64bitmode(ctx
);
6300 TCGv_i32 fp32
= tcg_temp_new_i32();
6301 TCGv_i64 fp64
= tcg_temp_new_i64();
6303 gen_load_fpr32(fp32
, fs
);
6304 gen_helper_float_truncl_s(fp64
, fp32
);
6305 tcg_temp_free_i32(fp32
);
6306 gen_store_fpr64(ctx
, fp64
, fd
);
6307 tcg_temp_free_i64(fp64
);
6312 check_cp1_64bitmode(ctx
);
6314 TCGv_i32 fp32
= tcg_temp_new_i32();
6315 TCGv_i64 fp64
= tcg_temp_new_i64();
6317 gen_load_fpr32(fp32
, fs
);
6318 gen_helper_float_ceill_s(fp64
, fp32
);
6319 tcg_temp_free_i32(fp32
);
6320 gen_store_fpr64(ctx
, fp64
, fd
);
6321 tcg_temp_free_i64(fp64
);
6326 check_cp1_64bitmode(ctx
);
6328 TCGv_i32 fp32
= tcg_temp_new_i32();
6329 TCGv_i64 fp64
= tcg_temp_new_i64();
6331 gen_load_fpr32(fp32
, fs
);
6332 gen_helper_float_floorl_s(fp64
, fp32
);
6333 tcg_temp_free_i32(fp32
);
6334 gen_store_fpr64(ctx
, fp64
, fd
);
6335 tcg_temp_free_i64(fp64
);
6341 TCGv_i32 fp0
= tcg_temp_new_i32();
6343 gen_load_fpr32(fp0
, fs
);
6344 gen_helper_float_roundw_s(fp0
, fp0
);
6345 gen_store_fpr32(fp0
, fd
);
6346 tcg_temp_free_i32(fp0
);
6352 TCGv_i32 fp0
= tcg_temp_new_i32();
6354 gen_load_fpr32(fp0
, fs
);
6355 gen_helper_float_truncw_s(fp0
, fp0
);
6356 gen_store_fpr32(fp0
, fd
);
6357 tcg_temp_free_i32(fp0
);
6363 TCGv_i32 fp0
= tcg_temp_new_i32();
6365 gen_load_fpr32(fp0
, fs
);
6366 gen_helper_float_ceilw_s(fp0
, fp0
);
6367 gen_store_fpr32(fp0
, fd
);
6368 tcg_temp_free_i32(fp0
);
6374 TCGv_i32 fp0
= tcg_temp_new_i32();
6376 gen_load_fpr32(fp0
, fs
);
6377 gen_helper_float_floorw_s(fp0
, fp0
);
6378 gen_store_fpr32(fp0
, fd
);
6379 tcg_temp_free_i32(fp0
);
6384 gen_movcf_s(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6389 int l1
= gen_new_label();
6393 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6395 fp0
= tcg_temp_new_i32();
6396 gen_load_fpr32(fp0
, fs
);
6397 gen_store_fpr32(fp0
, fd
);
6398 tcg_temp_free_i32(fp0
);
6405 int l1
= gen_new_label();
6409 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
6410 fp0
= tcg_temp_new_i32();
6411 gen_load_fpr32(fp0
, fs
);
6412 gen_store_fpr32(fp0
, fd
);
6413 tcg_temp_free_i32(fp0
);
6422 TCGv_i32 fp0
= tcg_temp_new_i32();
6424 gen_load_fpr32(fp0
, fs
);
6425 gen_helper_float_recip_s(fp0
, fp0
);
6426 gen_store_fpr32(fp0
, fd
);
6427 tcg_temp_free_i32(fp0
);
6434 TCGv_i32 fp0
= tcg_temp_new_i32();
6436 gen_load_fpr32(fp0
, fs
);
6437 gen_helper_float_rsqrt_s(fp0
, fp0
);
6438 gen_store_fpr32(fp0
, fd
);
6439 tcg_temp_free_i32(fp0
);
6444 check_cp1_64bitmode(ctx
);
6446 TCGv_i32 fp0
= tcg_temp_new_i32();
6447 TCGv_i32 fp1
= tcg_temp_new_i32();
6449 gen_load_fpr32(fp0
, fs
);
6450 gen_load_fpr32(fp1
, fd
);
6451 gen_helper_float_recip2_s(fp0
, fp0
, fp1
);
6452 tcg_temp_free_i32(fp1
);
6453 gen_store_fpr32(fp0
, fd
);
6454 tcg_temp_free_i32(fp0
);
6459 check_cp1_64bitmode(ctx
);
6461 TCGv_i32 fp0
= tcg_temp_new_i32();
6463 gen_load_fpr32(fp0
, fs
);
6464 gen_helper_float_recip1_s(fp0
, fp0
);
6465 gen_store_fpr32(fp0
, fd
);
6466 tcg_temp_free_i32(fp0
);
6471 check_cp1_64bitmode(ctx
);
6473 TCGv_i32 fp0
= tcg_temp_new_i32();
6475 gen_load_fpr32(fp0
, fs
);
6476 gen_helper_float_rsqrt1_s(fp0
, fp0
);
6477 gen_store_fpr32(fp0
, fd
);
6478 tcg_temp_free_i32(fp0
);
6483 check_cp1_64bitmode(ctx
);
6485 TCGv_i32 fp0
= tcg_temp_new_i32();
6486 TCGv_i32 fp1
= tcg_temp_new_i32();
6488 gen_load_fpr32(fp0
, fs
);
6489 gen_load_fpr32(fp1
, ft
);
6490 gen_helper_float_rsqrt2_s(fp0
, fp0
, fp1
);
6491 tcg_temp_free_i32(fp1
);
6492 gen_store_fpr32(fp0
, fd
);
6493 tcg_temp_free_i32(fp0
);
6498 check_cp1_registers(ctx
, fd
);
6500 TCGv_i32 fp32
= tcg_temp_new_i32();
6501 TCGv_i64 fp64
= tcg_temp_new_i64();
6503 gen_load_fpr32(fp32
, fs
);
6504 gen_helper_float_cvtd_s(fp64
, fp32
);
6505 tcg_temp_free_i32(fp32
);
6506 gen_store_fpr64(ctx
, fp64
, fd
);
6507 tcg_temp_free_i64(fp64
);
6513 TCGv_i32 fp0
= tcg_temp_new_i32();
6515 gen_load_fpr32(fp0
, fs
);
6516 gen_helper_float_cvtw_s(fp0
, fp0
);
6517 gen_store_fpr32(fp0
, fd
);
6518 tcg_temp_free_i32(fp0
);
6523 check_cp1_64bitmode(ctx
);
6525 TCGv_i32 fp32
= tcg_temp_new_i32();
6526 TCGv_i64 fp64
= tcg_temp_new_i64();
6528 gen_load_fpr32(fp32
, fs
);
6529 gen_helper_float_cvtl_s(fp64
, fp32
);
6530 tcg_temp_free_i32(fp32
);
6531 gen_store_fpr64(ctx
, fp64
, fd
);
6532 tcg_temp_free_i64(fp64
);
6537 check_cp1_64bitmode(ctx
);
6539 TCGv_i64 fp64
= tcg_temp_new_i64();
6540 TCGv_i32 fp32_0
= tcg_temp_new_i32();
6541 TCGv_i32 fp32_1
= tcg_temp_new_i32();
6543 gen_load_fpr32(fp32_0
, fs
);
6544 gen_load_fpr32(fp32_1
, ft
);
6545 tcg_gen_concat_i32_i64(fp64
, fp32_0
, fp32_1
);
6546 tcg_temp_free_i32(fp32_1
);
6547 tcg_temp_free_i32(fp32_0
);
6548 gen_store_fpr64(ctx
, fp64
, fd
);
6549 tcg_temp_free_i64(fp64
);
6562 case OPC_CMP_NGLE_S
:
6569 if (ctx
->opcode
& (1 << 6)) {
6570 gen_cmpabs_s(ctx
, func
-48, ft
, fs
, cc
);
6571 opn
= condnames_abs
[func
-48];
6573 gen_cmp_s(ctx
, func
-48, ft
, fs
, cc
);
6574 opn
= condnames
[func
-48];
6578 check_cp1_registers(ctx
, fs
| ft
| fd
);
6580 TCGv_i64 fp0
= tcg_temp_new_i64();
6581 TCGv_i64 fp1
= tcg_temp_new_i64();
6583 gen_load_fpr64(ctx
, fp0
, fs
);
6584 gen_load_fpr64(ctx
, fp1
, ft
);
6585 gen_helper_float_add_d(fp0
, fp0
, fp1
);
6586 tcg_temp_free_i64(fp1
);
6587 gen_store_fpr64(ctx
, fp0
, fd
);
6588 tcg_temp_free_i64(fp0
);
6594 check_cp1_registers(ctx
, fs
| ft
| fd
);
6596 TCGv_i64 fp0
= tcg_temp_new_i64();
6597 TCGv_i64 fp1
= tcg_temp_new_i64();
6599 gen_load_fpr64(ctx
, fp0
, fs
);
6600 gen_load_fpr64(ctx
, fp1
, ft
);
6601 gen_helper_float_sub_d(fp0
, fp0
, fp1
);
6602 tcg_temp_free_i64(fp1
);
6603 gen_store_fpr64(ctx
, fp0
, fd
);
6604 tcg_temp_free_i64(fp0
);
6610 check_cp1_registers(ctx
, fs
| ft
| fd
);
6612 TCGv_i64 fp0
= tcg_temp_new_i64();
6613 TCGv_i64 fp1
= tcg_temp_new_i64();
6615 gen_load_fpr64(ctx
, fp0
, fs
);
6616 gen_load_fpr64(ctx
, fp1
, ft
);
6617 gen_helper_float_mul_d(fp0
, fp0
, fp1
);
6618 tcg_temp_free_i64(fp1
);
6619 gen_store_fpr64(ctx
, fp0
, fd
);
6620 tcg_temp_free_i64(fp0
);
6626 check_cp1_registers(ctx
, fs
| ft
| fd
);
6628 TCGv_i64 fp0
= tcg_temp_new_i64();
6629 TCGv_i64 fp1
= tcg_temp_new_i64();
6631 gen_load_fpr64(ctx
, fp0
, fs
);
6632 gen_load_fpr64(ctx
, fp1
, ft
);
6633 gen_helper_float_div_d(fp0
, fp0
, fp1
);
6634 tcg_temp_free_i64(fp1
);
6635 gen_store_fpr64(ctx
, fp0
, fd
);
6636 tcg_temp_free_i64(fp0
);
6642 check_cp1_registers(ctx
, fs
| fd
);
6644 TCGv_i64 fp0
= tcg_temp_new_i64();
6646 gen_load_fpr64(ctx
, fp0
, fs
);
6647 gen_helper_float_sqrt_d(fp0
, fp0
);
6648 gen_store_fpr64(ctx
, fp0
, fd
);
6649 tcg_temp_free_i64(fp0
);
6654 check_cp1_registers(ctx
, fs
| fd
);
6656 TCGv_i64 fp0
= tcg_temp_new_i64();
6658 gen_load_fpr64(ctx
, fp0
, fs
);
6659 gen_helper_float_abs_d(fp0
, fp0
);
6660 gen_store_fpr64(ctx
, fp0
, fd
);
6661 tcg_temp_free_i64(fp0
);
6666 check_cp1_registers(ctx
, fs
| fd
);
6668 TCGv_i64 fp0
= tcg_temp_new_i64();
6670 gen_load_fpr64(ctx
, fp0
, fs
);
6671 gen_store_fpr64(ctx
, fp0
, fd
);
6672 tcg_temp_free_i64(fp0
);
6677 check_cp1_registers(ctx
, fs
| fd
);
6679 TCGv_i64 fp0
= tcg_temp_new_i64();
6681 gen_load_fpr64(ctx
, fp0
, fs
);
6682 gen_helper_float_chs_d(fp0
, fp0
);
6683 gen_store_fpr64(ctx
, fp0
, fd
);
6684 tcg_temp_free_i64(fp0
);
6689 check_cp1_64bitmode(ctx
);
6691 TCGv_i64 fp0
= tcg_temp_new_i64();
6693 gen_load_fpr64(ctx
, fp0
, fs
);
6694 gen_helper_float_roundl_d(fp0
, fp0
);
6695 gen_store_fpr64(ctx
, fp0
, fd
);
6696 tcg_temp_free_i64(fp0
);
6701 check_cp1_64bitmode(ctx
);
6703 TCGv_i64 fp0
= tcg_temp_new_i64();
6705 gen_load_fpr64(ctx
, fp0
, fs
);
6706 gen_helper_float_truncl_d(fp0
, fp0
);
6707 gen_store_fpr64(ctx
, fp0
, fd
);
6708 tcg_temp_free_i64(fp0
);
6713 check_cp1_64bitmode(ctx
);
6715 TCGv_i64 fp0
= tcg_temp_new_i64();
6717 gen_load_fpr64(ctx
, fp0
, fs
);
6718 gen_helper_float_ceill_d(fp0
, fp0
);
6719 gen_store_fpr64(ctx
, fp0
, fd
);
6720 tcg_temp_free_i64(fp0
);
6725 check_cp1_64bitmode(ctx
);
6727 TCGv_i64 fp0
= tcg_temp_new_i64();
6729 gen_load_fpr64(ctx
, fp0
, fs
);
6730 gen_helper_float_floorl_d(fp0
, fp0
);
6731 gen_store_fpr64(ctx
, fp0
, fd
);
6732 tcg_temp_free_i64(fp0
);
6737 check_cp1_registers(ctx
, fs
);
6739 TCGv_i32 fp32
= tcg_temp_new_i32();
6740 TCGv_i64 fp64
= tcg_temp_new_i64();
6742 gen_load_fpr64(ctx
, fp64
, fs
);
6743 gen_helper_float_roundw_d(fp32
, fp64
);
6744 tcg_temp_free_i64(fp64
);
6745 gen_store_fpr32(fp32
, fd
);
6746 tcg_temp_free_i32(fp32
);
6751 check_cp1_registers(ctx
, fs
);
6753 TCGv_i32 fp32
= tcg_temp_new_i32();
6754 TCGv_i64 fp64
= tcg_temp_new_i64();
6756 gen_load_fpr64(ctx
, fp64
, fs
);
6757 gen_helper_float_truncw_d(fp32
, fp64
);
6758 tcg_temp_free_i64(fp64
);
6759 gen_store_fpr32(fp32
, fd
);
6760 tcg_temp_free_i32(fp32
);
6765 check_cp1_registers(ctx
, fs
);
6767 TCGv_i32 fp32
= tcg_temp_new_i32();
6768 TCGv_i64 fp64
= tcg_temp_new_i64();
6770 gen_load_fpr64(ctx
, fp64
, fs
);
6771 gen_helper_float_ceilw_d(fp32
, fp64
);
6772 tcg_temp_free_i64(fp64
);
6773 gen_store_fpr32(fp32
, fd
);
6774 tcg_temp_free_i32(fp32
);
6779 check_cp1_registers(ctx
, fs
);
6781 TCGv_i32 fp32
= tcg_temp_new_i32();
6782 TCGv_i64 fp64
= tcg_temp_new_i64();
6784 gen_load_fpr64(ctx
, fp64
, fs
);
6785 gen_helper_float_floorw_d(fp32
, fp64
);
6786 tcg_temp_free_i64(fp64
);
6787 gen_store_fpr32(fp32
, fd
);
6788 tcg_temp_free_i32(fp32
);
6793 gen_movcf_d(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6798 int l1
= gen_new_label();
6802 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6804 fp0
= tcg_temp_new_i64();
6805 gen_load_fpr64(ctx
, fp0
, fs
);
6806 gen_store_fpr64(ctx
, fp0
, fd
);
6807 tcg_temp_free_i64(fp0
);
6814 int l1
= gen_new_label();
6818 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
6819 fp0
= tcg_temp_new_i64();
6820 gen_load_fpr64(ctx
, fp0
, fs
);
6821 gen_store_fpr64(ctx
, fp0
, fd
);
6822 tcg_temp_free_i64(fp0
);
6829 check_cp1_64bitmode(ctx
);
6831 TCGv_i64 fp0
= tcg_temp_new_i64();
6833 gen_load_fpr64(ctx
, fp0
, fs
);
6834 gen_helper_float_recip_d(fp0
, fp0
);
6835 gen_store_fpr64(ctx
, fp0
, fd
);
6836 tcg_temp_free_i64(fp0
);
6841 check_cp1_64bitmode(ctx
);
6843 TCGv_i64 fp0
= tcg_temp_new_i64();
6845 gen_load_fpr64(ctx
, fp0
, fs
);
6846 gen_helper_float_rsqrt_d(fp0
, fp0
);
6847 gen_store_fpr64(ctx
, fp0
, fd
);
6848 tcg_temp_free_i64(fp0
);
6853 check_cp1_64bitmode(ctx
);
6855 TCGv_i64 fp0
= tcg_temp_new_i64();
6856 TCGv_i64 fp1
= tcg_temp_new_i64();
6858 gen_load_fpr64(ctx
, fp0
, fs
);
6859 gen_load_fpr64(ctx
, fp1
, ft
);
6860 gen_helper_float_recip2_d(fp0
, fp0
, fp1
);
6861 tcg_temp_free_i64(fp1
);
6862 gen_store_fpr64(ctx
, fp0
, fd
);
6863 tcg_temp_free_i64(fp0
);
6868 check_cp1_64bitmode(ctx
);
6870 TCGv_i64 fp0
= tcg_temp_new_i64();
6872 gen_load_fpr64(ctx
, fp0
, fs
);
6873 gen_helper_float_recip1_d(fp0
, fp0
);
6874 gen_store_fpr64(ctx
, fp0
, fd
);
6875 tcg_temp_free_i64(fp0
);
6880 check_cp1_64bitmode(ctx
);
6882 TCGv_i64 fp0
= tcg_temp_new_i64();
6884 gen_load_fpr64(ctx
, fp0
, fs
);
6885 gen_helper_float_rsqrt1_d(fp0
, fp0
);
6886 gen_store_fpr64(ctx
, fp0
, fd
);
6887 tcg_temp_free_i64(fp0
);
6892 check_cp1_64bitmode(ctx
);
6894 TCGv_i64 fp0
= tcg_temp_new_i64();
6895 TCGv_i64 fp1
= tcg_temp_new_i64();
6897 gen_load_fpr64(ctx
, fp0
, fs
);
6898 gen_load_fpr64(ctx
, fp1
, ft
);
6899 gen_helper_float_rsqrt2_d(fp0
, fp0
, fp1
);
6900 tcg_temp_free_i64(fp1
);
6901 gen_store_fpr64(ctx
, fp0
, fd
);
6902 tcg_temp_free_i64(fp0
);
6915 case OPC_CMP_NGLE_D
:
6922 if (ctx
->opcode
& (1 << 6)) {
6923 gen_cmpabs_d(ctx
, func
-48, ft
, fs
, cc
);
6924 opn
= condnames_abs
[func
-48];
6926 gen_cmp_d(ctx
, func
-48, ft
, fs
, cc
);
6927 opn
= condnames
[func
-48];
6931 check_cp1_registers(ctx
, fs
);
6933 TCGv_i32 fp32
= tcg_temp_new_i32();
6934 TCGv_i64 fp64
= tcg_temp_new_i64();
6936 gen_load_fpr64(ctx
, fp64
, fs
);
6937 gen_helper_float_cvts_d(fp32
, fp64
);
6938 tcg_temp_free_i64(fp64
);
6939 gen_store_fpr32(fp32
, fd
);
6940 tcg_temp_free_i32(fp32
);
6945 check_cp1_registers(ctx
, fs
);
6947 TCGv_i32 fp32
= tcg_temp_new_i32();
6948 TCGv_i64 fp64
= tcg_temp_new_i64();
6950 gen_load_fpr64(ctx
, fp64
, fs
);
6951 gen_helper_float_cvtw_d(fp32
, fp64
);
6952 tcg_temp_free_i64(fp64
);
6953 gen_store_fpr32(fp32
, fd
);
6954 tcg_temp_free_i32(fp32
);
6959 check_cp1_64bitmode(ctx
);
6961 TCGv_i64 fp0
= tcg_temp_new_i64();
6963 gen_load_fpr64(ctx
, fp0
, fs
);
6964 gen_helper_float_cvtl_d(fp0
, fp0
);
6965 gen_store_fpr64(ctx
, fp0
, fd
);
6966 tcg_temp_free_i64(fp0
);
6972 TCGv_i32 fp0
= tcg_temp_new_i32();
6974 gen_load_fpr32(fp0
, fs
);
6975 gen_helper_float_cvts_w(fp0
, fp0
);
6976 gen_store_fpr32(fp0
, fd
);
6977 tcg_temp_free_i32(fp0
);
6982 check_cp1_registers(ctx
, fd
);
6984 TCGv_i32 fp32
= tcg_temp_new_i32();
6985 TCGv_i64 fp64
= tcg_temp_new_i64();
6987 gen_load_fpr32(fp32
, fs
);
6988 gen_helper_float_cvtd_w(fp64
, fp32
);
6989 tcg_temp_free_i32(fp32
);
6990 gen_store_fpr64(ctx
, fp64
, fd
);
6991 tcg_temp_free_i64(fp64
);
6996 check_cp1_64bitmode(ctx
);
6998 TCGv_i32 fp32
= tcg_temp_new_i32();
6999 TCGv_i64 fp64
= tcg_temp_new_i64();
7001 gen_load_fpr64(ctx
, fp64
, fs
);
7002 gen_helper_float_cvts_l(fp32
, fp64
);
7003 tcg_temp_free_i64(fp64
);
7004 gen_store_fpr32(fp32
, fd
);
7005 tcg_temp_free_i32(fp32
);
7010 check_cp1_64bitmode(ctx
);
7012 TCGv_i64 fp0
= tcg_temp_new_i64();
7014 gen_load_fpr64(ctx
, fp0
, fs
);
7015 gen_helper_float_cvtd_l(fp0
, fp0
);
7016 gen_store_fpr64(ctx
, fp0
, fd
);
7017 tcg_temp_free_i64(fp0
);
7022 check_cp1_64bitmode(ctx
);
7024 TCGv_i64 fp0
= tcg_temp_new_i64();
7026 gen_load_fpr64(ctx
, fp0
, fs
);
7027 gen_helper_float_cvtps_pw(fp0
, fp0
);
7028 gen_store_fpr64(ctx
, fp0
, fd
);
7029 tcg_temp_free_i64(fp0
);
7034 check_cp1_64bitmode(ctx
);
7036 TCGv_i64 fp0
= tcg_temp_new_i64();
7037 TCGv_i64 fp1
= tcg_temp_new_i64();
7039 gen_load_fpr64(ctx
, fp0
, fs
);
7040 gen_load_fpr64(ctx
, fp1
, ft
);
7041 gen_helper_float_add_ps(fp0
, fp0
, fp1
);
7042 tcg_temp_free_i64(fp1
);
7043 gen_store_fpr64(ctx
, fp0
, fd
);
7044 tcg_temp_free_i64(fp0
);
7049 check_cp1_64bitmode(ctx
);
7051 TCGv_i64 fp0
= tcg_temp_new_i64();
7052 TCGv_i64 fp1
= tcg_temp_new_i64();
7054 gen_load_fpr64(ctx
, fp0
, fs
);
7055 gen_load_fpr64(ctx
, fp1
, ft
);
7056 gen_helper_float_sub_ps(fp0
, fp0
, fp1
);
7057 tcg_temp_free_i64(fp1
);
7058 gen_store_fpr64(ctx
, fp0
, fd
);
7059 tcg_temp_free_i64(fp0
);
7064 check_cp1_64bitmode(ctx
);
7066 TCGv_i64 fp0
= tcg_temp_new_i64();
7067 TCGv_i64 fp1
= tcg_temp_new_i64();
7069 gen_load_fpr64(ctx
, fp0
, fs
);
7070 gen_load_fpr64(ctx
, fp1
, ft
);
7071 gen_helper_float_mul_ps(fp0
, fp0
, fp1
);
7072 tcg_temp_free_i64(fp1
);
7073 gen_store_fpr64(ctx
, fp0
, fd
);
7074 tcg_temp_free_i64(fp0
);
7079 check_cp1_64bitmode(ctx
);
7081 TCGv_i64 fp0
= tcg_temp_new_i64();
7083 gen_load_fpr64(ctx
, fp0
, fs
);
7084 gen_helper_float_abs_ps(fp0
, fp0
);
7085 gen_store_fpr64(ctx
, fp0
, fd
);
7086 tcg_temp_free_i64(fp0
);
7091 check_cp1_64bitmode(ctx
);
7093 TCGv_i64 fp0
= tcg_temp_new_i64();
7095 gen_load_fpr64(ctx
, fp0
, fs
);
7096 gen_store_fpr64(ctx
, fp0
, fd
);
7097 tcg_temp_free_i64(fp0
);
7102 check_cp1_64bitmode(ctx
);
7104 TCGv_i64 fp0
= tcg_temp_new_i64();
7106 gen_load_fpr64(ctx
, fp0
, fs
);
7107 gen_helper_float_chs_ps(fp0
, fp0
);
7108 gen_store_fpr64(ctx
, fp0
, fd
);
7109 tcg_temp_free_i64(fp0
);
7114 check_cp1_64bitmode(ctx
);
7115 gen_movcf_ps(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
7119 check_cp1_64bitmode(ctx
);
7121 int l1
= gen_new_label();
7125 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
7126 fp0
= tcg_temp_new_i64();
7127 gen_load_fpr64(ctx
, fp0
, fs
);
7128 gen_store_fpr64(ctx
, fp0
, fd
);
7129 tcg_temp_free_i64(fp0
);
7135 check_cp1_64bitmode(ctx
);
7137 int l1
= gen_new_label();
7141 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
7142 fp0
= tcg_temp_new_i64();
7143 gen_load_fpr64(ctx
, fp0
, fs
);
7144 gen_store_fpr64(ctx
, fp0
, fd
);
7145 tcg_temp_free_i64(fp0
);
7152 check_cp1_64bitmode(ctx
);
7154 TCGv_i64 fp0
= tcg_temp_new_i64();
7155 TCGv_i64 fp1
= tcg_temp_new_i64();
7157 gen_load_fpr64(ctx
, fp0
, ft
);
7158 gen_load_fpr64(ctx
, fp1
, fs
);
7159 gen_helper_float_addr_ps(fp0
, fp0
, fp1
);
7160 tcg_temp_free_i64(fp1
);
7161 gen_store_fpr64(ctx
, fp0
, fd
);
7162 tcg_temp_free_i64(fp0
);
7167 check_cp1_64bitmode(ctx
);
7169 TCGv_i64 fp0
= tcg_temp_new_i64();
7170 TCGv_i64 fp1
= tcg_temp_new_i64();
7172 gen_load_fpr64(ctx
, fp0
, ft
);
7173 gen_load_fpr64(ctx
, fp1
, fs
);
7174 gen_helper_float_mulr_ps(fp0
, fp0
, fp1
);
7175 tcg_temp_free_i64(fp1
);
7176 gen_store_fpr64(ctx
, fp0
, fd
);
7177 tcg_temp_free_i64(fp0
);
7182 check_cp1_64bitmode(ctx
);
7184 TCGv_i64 fp0
= tcg_temp_new_i64();
7185 TCGv_i64 fp1
= tcg_temp_new_i64();
7187 gen_load_fpr64(ctx
, fp0
, fs
);
7188 gen_load_fpr64(ctx
, fp1
, fd
);
7189 gen_helper_float_recip2_ps(fp0
, fp0
, fp1
);
7190 tcg_temp_free_i64(fp1
);
7191 gen_store_fpr64(ctx
, fp0
, fd
);
7192 tcg_temp_free_i64(fp0
);
7197 check_cp1_64bitmode(ctx
);
7199 TCGv_i64 fp0
= tcg_temp_new_i64();
7201 gen_load_fpr64(ctx
, fp0
, fs
);
7202 gen_helper_float_recip1_ps(fp0
, fp0
);
7203 gen_store_fpr64(ctx
, fp0
, fd
);
7204 tcg_temp_free_i64(fp0
);
7209 check_cp1_64bitmode(ctx
);
7211 TCGv_i64 fp0
= tcg_temp_new_i64();
7213 gen_load_fpr64(ctx
, fp0
, fs
);
7214 gen_helper_float_rsqrt1_ps(fp0
, fp0
);
7215 gen_store_fpr64(ctx
, fp0
, fd
);
7216 tcg_temp_free_i64(fp0
);
7221 check_cp1_64bitmode(ctx
);
7223 TCGv_i64 fp0
= tcg_temp_new_i64();
7224 TCGv_i64 fp1
= tcg_temp_new_i64();
7226 gen_load_fpr64(ctx
, fp0
, fs
);
7227 gen_load_fpr64(ctx
, fp1
, ft
);
7228 gen_helper_float_rsqrt2_ps(fp0
, fp0
, fp1
);
7229 tcg_temp_free_i64(fp1
);
7230 gen_store_fpr64(ctx
, fp0
, fd
);
7231 tcg_temp_free_i64(fp0
);
7236 check_cp1_64bitmode(ctx
);
7238 TCGv_i32 fp0
= tcg_temp_new_i32();
7240 gen_load_fpr32h(fp0
, fs
);
7241 gen_helper_float_cvts_pu(fp0
, fp0
);
7242 gen_store_fpr32(fp0
, fd
);
7243 tcg_temp_free_i32(fp0
);
7248 check_cp1_64bitmode(ctx
);
7250 TCGv_i64 fp0
= tcg_temp_new_i64();
7252 gen_load_fpr64(ctx
, fp0
, fs
);
7253 gen_helper_float_cvtpw_ps(fp0
, fp0
);
7254 gen_store_fpr64(ctx
, fp0
, fd
);
7255 tcg_temp_free_i64(fp0
);
7260 check_cp1_64bitmode(ctx
);
7262 TCGv_i32 fp0
= tcg_temp_new_i32();
7264 gen_load_fpr32(fp0
, fs
);
7265 gen_helper_float_cvts_pl(fp0
, fp0
);
7266 gen_store_fpr32(fp0
, fd
);
7267 tcg_temp_free_i32(fp0
);
7272 check_cp1_64bitmode(ctx
);
7274 TCGv_i32 fp0
= tcg_temp_new_i32();
7275 TCGv_i32 fp1
= tcg_temp_new_i32();
7277 gen_load_fpr32(fp0
, fs
);
7278 gen_load_fpr32(fp1
, ft
);
7279 gen_store_fpr32h(fp0
, fd
);
7280 gen_store_fpr32(fp1
, fd
);
7281 tcg_temp_free_i32(fp0
);
7282 tcg_temp_free_i32(fp1
);
7287 check_cp1_64bitmode(ctx
);
7289 TCGv_i32 fp0
= tcg_temp_new_i32();
7290 TCGv_i32 fp1
= tcg_temp_new_i32();
7292 gen_load_fpr32(fp0
, fs
);
7293 gen_load_fpr32h(fp1
, ft
);
7294 gen_store_fpr32(fp1
, fd
);
7295 gen_store_fpr32h(fp0
, fd
);
7296 tcg_temp_free_i32(fp0
);
7297 tcg_temp_free_i32(fp1
);
7302 check_cp1_64bitmode(ctx
);
7304 TCGv_i32 fp0
= tcg_temp_new_i32();
7305 TCGv_i32 fp1
= tcg_temp_new_i32();
7307 gen_load_fpr32h(fp0
, fs
);
7308 gen_load_fpr32(fp1
, ft
);
7309 gen_store_fpr32(fp1
, fd
);
7310 gen_store_fpr32h(fp0
, fd
);
7311 tcg_temp_free_i32(fp0
);
7312 tcg_temp_free_i32(fp1
);
7317 check_cp1_64bitmode(ctx
);
7319 TCGv_i32 fp0
= tcg_temp_new_i32();
7320 TCGv_i32 fp1
= tcg_temp_new_i32();
7322 gen_load_fpr32h(fp0
, fs
);
7323 gen_load_fpr32h(fp1
, ft
);
7324 gen_store_fpr32(fp1
, fd
);
7325 gen_store_fpr32h(fp0
, fd
);
7326 tcg_temp_free_i32(fp0
);
7327 tcg_temp_free_i32(fp1
);
7334 case OPC_CMP_UEQ_PS
:
7335 case OPC_CMP_OLT_PS
:
7336 case OPC_CMP_ULT_PS
:
7337 case OPC_CMP_OLE_PS
:
7338 case OPC_CMP_ULE_PS
:
7340 case OPC_CMP_NGLE_PS
:
7341 case OPC_CMP_SEQ_PS
:
7342 case OPC_CMP_NGL_PS
:
7344 case OPC_CMP_NGE_PS
:
7346 case OPC_CMP_NGT_PS
:
7347 if (ctx
->opcode
& (1 << 6)) {
7348 gen_cmpabs_ps(ctx
, func
-48, ft
, fs
, cc
);
7349 opn
= condnames_abs
[func
-48];
7351 gen_cmp_ps(ctx
, func
-48, ft
, fs
, cc
);
7352 opn
= condnames
[func
-48];
7357 generate_exception (ctx
, EXCP_RI
);
7362 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
7365 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
7368 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
7373 /* Coprocessor 3 (FPU) */
7374 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
7375 int fd
, int fs
, int base
, int index
)
7377 const char *opn
= "extended float load/store";
7379 TCGv t0
= tcg_temp_new();
7382 gen_load_gpr(t0
, index
);
7383 } else if (index
== 0) {
7384 gen_load_gpr(t0
, base
);
7386 gen_load_gpr(t0
, index
);
7387 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], t0
);
7389 /* Don't do NOP if destination is zero: we must perform the actual
7391 save_cpu_state(ctx
, 0);
7396 TCGv_i32 fp0
= tcg_temp_new_i32();
7398 tcg_gen_qemu_ld32s(t0
, t0
, ctx
->mem_idx
);
7399 tcg_gen_trunc_tl_i32(fp0
, t0
);
7400 gen_store_fpr32(fp0
, fd
);
7401 tcg_temp_free_i32(fp0
);
7407 check_cp1_registers(ctx
, fd
);
7409 TCGv_i64 fp0
= tcg_temp_new_i64();
7411 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7412 gen_store_fpr64(ctx
, fp0
, fd
);
7413 tcg_temp_free_i64(fp0
);
7418 check_cp1_64bitmode(ctx
);
7419 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7421 TCGv_i64 fp0
= tcg_temp_new_i64();
7423 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7424 gen_store_fpr64(ctx
, fp0
, fd
);
7425 tcg_temp_free_i64(fp0
);
7432 TCGv_i32 fp0
= tcg_temp_new_i32();
7433 TCGv t1
= tcg_temp_new();
7435 gen_load_fpr32(fp0
, fs
);
7436 tcg_gen_extu_i32_tl(t1
, fp0
);
7437 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
7438 tcg_temp_free_i32(fp0
);
7446 check_cp1_registers(ctx
, fs
);
7448 TCGv_i64 fp0
= tcg_temp_new_i64();
7450 gen_load_fpr64(ctx
, fp0
, fs
);
7451 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7452 tcg_temp_free_i64(fp0
);
7458 check_cp1_64bitmode(ctx
);
7459 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7461 TCGv_i64 fp0
= tcg_temp_new_i64();
7463 gen_load_fpr64(ctx
, fp0
, fs
);
7464 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7465 tcg_temp_free_i64(fp0
);
7472 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
7473 regnames
[index
], regnames
[base
]);
7476 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
7477 int fd
, int fr
, int fs
, int ft
)
7479 const char *opn
= "flt3_arith";
7483 check_cp1_64bitmode(ctx
);
7485 TCGv t0
= tcg_temp_local_new();
7486 TCGv_i32 fp
= tcg_temp_new_i32();
7487 TCGv_i32 fph
= tcg_temp_new_i32();
7488 int l1
= gen_new_label();
7489 int l2
= gen_new_label();
7491 gen_load_gpr(t0
, fr
);
7492 tcg_gen_andi_tl(t0
, t0
, 0x7);
7494 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
7495 gen_load_fpr32(fp
, fs
);
7496 gen_load_fpr32h(fph
, fs
);
7497 gen_store_fpr32(fp
, fd
);
7498 gen_store_fpr32h(fph
, fd
);
7501 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 4, l2
);
7503 #ifdef TARGET_WORDS_BIGENDIAN
7504 gen_load_fpr32(fp
, fs
);
7505 gen_load_fpr32h(fph
, ft
);
7506 gen_store_fpr32h(fp
, fd
);
7507 gen_store_fpr32(fph
, fd
);
7509 gen_load_fpr32h(fph
, fs
);
7510 gen_load_fpr32(fp
, ft
);
7511 gen_store_fpr32(fph
, fd
);
7512 gen_store_fpr32h(fp
, fd
);
7515 tcg_temp_free_i32(fp
);
7516 tcg_temp_free_i32(fph
);
7523 TCGv_i32 fp0
= tcg_temp_new_i32();
7524 TCGv_i32 fp1
= tcg_temp_new_i32();
7525 TCGv_i32 fp2
= tcg_temp_new_i32();
7527 gen_load_fpr32(fp0
, fs
);
7528 gen_load_fpr32(fp1
, ft
);
7529 gen_load_fpr32(fp2
, fr
);
7530 gen_helper_float_muladd_s(fp2
, fp0
, fp1
, fp2
);
7531 tcg_temp_free_i32(fp0
);
7532 tcg_temp_free_i32(fp1
);
7533 gen_store_fpr32(fp2
, fd
);
7534 tcg_temp_free_i32(fp2
);
7540 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7542 TCGv_i64 fp0
= tcg_temp_new_i64();
7543 TCGv_i64 fp1
= tcg_temp_new_i64();
7544 TCGv_i64 fp2
= tcg_temp_new_i64();
7546 gen_load_fpr64(ctx
, fp0
, fs
);
7547 gen_load_fpr64(ctx
, fp1
, ft
);
7548 gen_load_fpr64(ctx
, fp2
, fr
);
7549 gen_helper_float_muladd_d(fp2
, fp0
, fp1
, fp2
);
7550 tcg_temp_free_i64(fp0
);
7551 tcg_temp_free_i64(fp1
);
7552 gen_store_fpr64(ctx
, fp2
, fd
);
7553 tcg_temp_free_i64(fp2
);
7558 check_cp1_64bitmode(ctx
);
7560 TCGv_i64 fp0
= tcg_temp_new_i64();
7561 TCGv_i64 fp1
= tcg_temp_new_i64();
7562 TCGv_i64 fp2
= tcg_temp_new_i64();
7564 gen_load_fpr64(ctx
, fp0
, fs
);
7565 gen_load_fpr64(ctx
, fp1
, ft
);
7566 gen_load_fpr64(ctx
, fp2
, fr
);
7567 gen_helper_float_muladd_ps(fp2
, fp0
, fp1
, fp2
);
7568 tcg_temp_free_i64(fp0
);
7569 tcg_temp_free_i64(fp1
);
7570 gen_store_fpr64(ctx
, fp2
, fd
);
7571 tcg_temp_free_i64(fp2
);
7578 TCGv_i32 fp0
= tcg_temp_new_i32();
7579 TCGv_i32 fp1
= tcg_temp_new_i32();
7580 TCGv_i32 fp2
= tcg_temp_new_i32();
7582 gen_load_fpr32(fp0
, fs
);
7583 gen_load_fpr32(fp1
, ft
);
7584 gen_load_fpr32(fp2
, fr
);
7585 gen_helper_float_mulsub_s(fp2
, fp0
, fp1
, fp2
);
7586 tcg_temp_free_i32(fp0
);
7587 tcg_temp_free_i32(fp1
);
7588 gen_store_fpr32(fp2
, fd
);
7589 tcg_temp_free_i32(fp2
);
7595 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7597 TCGv_i64 fp0
= tcg_temp_new_i64();
7598 TCGv_i64 fp1
= tcg_temp_new_i64();
7599 TCGv_i64 fp2
= tcg_temp_new_i64();
7601 gen_load_fpr64(ctx
, fp0
, fs
);
7602 gen_load_fpr64(ctx
, fp1
, ft
);
7603 gen_load_fpr64(ctx
, fp2
, fr
);
7604 gen_helper_float_mulsub_d(fp2
, fp0
, fp1
, fp2
);
7605 tcg_temp_free_i64(fp0
);
7606 tcg_temp_free_i64(fp1
);
7607 gen_store_fpr64(ctx
, fp2
, fd
);
7608 tcg_temp_free_i64(fp2
);
7613 check_cp1_64bitmode(ctx
);
7615 TCGv_i64 fp0
= tcg_temp_new_i64();
7616 TCGv_i64 fp1
= tcg_temp_new_i64();
7617 TCGv_i64 fp2
= tcg_temp_new_i64();
7619 gen_load_fpr64(ctx
, fp0
, fs
);
7620 gen_load_fpr64(ctx
, fp1
, ft
);
7621 gen_load_fpr64(ctx
, fp2
, fr
);
7622 gen_helper_float_mulsub_ps(fp2
, fp0
, fp1
, fp2
);
7623 tcg_temp_free_i64(fp0
);
7624 tcg_temp_free_i64(fp1
);
7625 gen_store_fpr64(ctx
, fp2
, fd
);
7626 tcg_temp_free_i64(fp2
);
7633 TCGv_i32 fp0
= tcg_temp_new_i32();
7634 TCGv_i32 fp1
= tcg_temp_new_i32();
7635 TCGv_i32 fp2
= tcg_temp_new_i32();
7637 gen_load_fpr32(fp0
, fs
);
7638 gen_load_fpr32(fp1
, ft
);
7639 gen_load_fpr32(fp2
, fr
);
7640 gen_helper_float_nmuladd_s(fp2
, fp0
, fp1
, fp2
);
7641 tcg_temp_free_i32(fp0
);
7642 tcg_temp_free_i32(fp1
);
7643 gen_store_fpr32(fp2
, fd
);
7644 tcg_temp_free_i32(fp2
);
7650 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7652 TCGv_i64 fp0
= tcg_temp_new_i64();
7653 TCGv_i64 fp1
= tcg_temp_new_i64();
7654 TCGv_i64 fp2
= tcg_temp_new_i64();
7656 gen_load_fpr64(ctx
, fp0
, fs
);
7657 gen_load_fpr64(ctx
, fp1
, ft
);
7658 gen_load_fpr64(ctx
, fp2
, fr
);
7659 gen_helper_float_nmuladd_d(fp2
, fp0
, fp1
, fp2
);
7660 tcg_temp_free_i64(fp0
);
7661 tcg_temp_free_i64(fp1
);
7662 gen_store_fpr64(ctx
, fp2
, fd
);
7663 tcg_temp_free_i64(fp2
);
7668 check_cp1_64bitmode(ctx
);
7670 TCGv_i64 fp0
= tcg_temp_new_i64();
7671 TCGv_i64 fp1
= tcg_temp_new_i64();
7672 TCGv_i64 fp2
= tcg_temp_new_i64();
7674 gen_load_fpr64(ctx
, fp0
, fs
);
7675 gen_load_fpr64(ctx
, fp1
, ft
);
7676 gen_load_fpr64(ctx
, fp2
, fr
);
7677 gen_helper_float_nmuladd_ps(fp2
, fp0
, fp1
, fp2
);
7678 tcg_temp_free_i64(fp0
);
7679 tcg_temp_free_i64(fp1
);
7680 gen_store_fpr64(ctx
, fp2
, fd
);
7681 tcg_temp_free_i64(fp2
);
7688 TCGv_i32 fp0
= tcg_temp_new_i32();
7689 TCGv_i32 fp1
= tcg_temp_new_i32();
7690 TCGv_i32 fp2
= tcg_temp_new_i32();
7692 gen_load_fpr32(fp0
, fs
);
7693 gen_load_fpr32(fp1
, ft
);
7694 gen_load_fpr32(fp2
, fr
);
7695 gen_helper_float_nmulsub_s(fp2
, fp0
, fp1
, fp2
);
7696 tcg_temp_free_i32(fp0
);
7697 tcg_temp_free_i32(fp1
);
7698 gen_store_fpr32(fp2
, fd
);
7699 tcg_temp_free_i32(fp2
);
7705 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7707 TCGv_i64 fp0
= tcg_temp_new_i64();
7708 TCGv_i64 fp1
= tcg_temp_new_i64();
7709 TCGv_i64 fp2
= tcg_temp_new_i64();
7711 gen_load_fpr64(ctx
, fp0
, fs
);
7712 gen_load_fpr64(ctx
, fp1
, ft
);
7713 gen_load_fpr64(ctx
, fp2
, fr
);
7714 gen_helper_float_nmulsub_d(fp2
, fp0
, fp1
, fp2
);
7715 tcg_temp_free_i64(fp0
);
7716 tcg_temp_free_i64(fp1
);
7717 gen_store_fpr64(ctx
, fp2
, fd
);
7718 tcg_temp_free_i64(fp2
);
7723 check_cp1_64bitmode(ctx
);
7725 TCGv_i64 fp0
= tcg_temp_new_i64();
7726 TCGv_i64 fp1
= tcg_temp_new_i64();
7727 TCGv_i64 fp2
= tcg_temp_new_i64();
7729 gen_load_fpr64(ctx
, fp0
, fs
);
7730 gen_load_fpr64(ctx
, fp1
, ft
);
7731 gen_load_fpr64(ctx
, fp2
, fr
);
7732 gen_helper_float_nmulsub_ps(fp2
, fp0
, fp1
, fp2
);
7733 tcg_temp_free_i64(fp0
);
7734 tcg_temp_free_i64(fp1
);
7735 gen_store_fpr64(ctx
, fp2
, fd
);
7736 tcg_temp_free_i64(fp2
);
7742 generate_exception (ctx
, EXCP_RI
);
7745 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
7746 fregnames
[fs
], fregnames
[ft
]);
7750 gen_rdhwr (CPUState
*env
, DisasContext
*ctx
, int rt
, int rd
)
7754 check_insn(env
, ctx
, ISA_MIPS32R2
);
7755 t0
= tcg_temp_new();
7759 save_cpu_state(ctx
, 1);
7760 gen_helper_rdhwr_cpunum(t0
);
7761 gen_store_gpr(t0
, rt
);
7764 save_cpu_state(ctx
, 1);
7765 gen_helper_rdhwr_synci_step(t0
);
7766 gen_store_gpr(t0
, rt
);
7769 save_cpu_state(ctx
, 1);
7770 gen_helper_rdhwr_cc(t0
);
7771 gen_store_gpr(t0
, rt
);
7774 save_cpu_state(ctx
, 1);
7775 gen_helper_rdhwr_ccres(t0
);
7776 gen_store_gpr(t0
, rt
);
7779 #if defined(CONFIG_USER_ONLY)
7780 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, tls_value
));
7781 gen_store_gpr(t0
, rt
);
7784 /* XXX: Some CPUs implement this in hardware.
7785 Not supported yet. */
7787 default: /* Invalid */
7788 MIPS_INVAL("rdhwr");
7789 generate_exception(ctx
, EXCP_RI
);
7795 static void handle_delay_slot (CPUState
*env
, DisasContext
*ctx
,
7798 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
7799 int proc_hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
7800 /* Branches completion */
7801 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
7802 ctx
->bstate
= BS_BRANCH
;
7803 save_cpu_state(ctx
, 0);
7804 /* FIXME: Need to clear can_do_io. */
7805 switch (proc_hflags
& MIPS_HFLAG_BMASK_BASE
) {
7807 /* unconditional branch */
7808 MIPS_DEBUG("unconditional branch");
7809 if (proc_hflags
& MIPS_HFLAG_BX
) {
7810 tcg_gen_xori_i32(hflags
, hflags
, MIPS_HFLAG_M16
);
7812 gen_goto_tb(ctx
, 0, ctx
->btarget
);
7815 /* blikely taken case */
7816 MIPS_DEBUG("blikely branch taken");
7817 gen_goto_tb(ctx
, 0, ctx
->btarget
);
7820 /* Conditional branch */
7821 MIPS_DEBUG("conditional branch");
7823 int l1
= gen_new_label();
7825 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
7826 gen_goto_tb(ctx
, 1, ctx
->pc
+ insn_bytes
);
7828 gen_goto_tb(ctx
, 0, ctx
->btarget
);
7832 /* unconditional branch to register */
7833 MIPS_DEBUG("branch to register");
7834 if (env
->insn_flags
& (ASE_MIPS16
| ASE_MICROMIPS
)) {
7835 TCGv t0
= tcg_temp_new();
7836 TCGv_i32 t1
= tcg_temp_new_i32();
7838 tcg_gen_andi_tl(t0
, btarget
, 0x1);
7839 tcg_gen_trunc_tl_i32(t1
, t0
);
7841 tcg_gen_andi_i32(hflags
, hflags
, ~(uint32_t)MIPS_HFLAG_M16
);
7842 tcg_gen_shli_i32(t1
, t1
, MIPS_HFLAG_M16_SHIFT
);
7843 tcg_gen_or_i32(hflags
, hflags
, t1
);
7844 tcg_temp_free_i32(t1
);
7846 tcg_gen_andi_tl(cpu_PC
, btarget
, ~(target_ulong
)0x1);
7848 tcg_gen_mov_tl(cpu_PC
, btarget
);
7850 if (ctx
->singlestep_enabled
) {
7851 save_cpu_state(ctx
, 0);
7852 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
7857 MIPS_DEBUG("unknown branch");
7863 /* ISA extensions (ASEs) */
7864 /* MIPS16 extension to MIPS32 */
7866 /* MIPS16 major opcodes */
7868 M16_OPC_ADDIUSP
= 0x00,
7869 M16_OPC_ADDIUPC
= 0x01,
7872 M16_OPC_BEQZ
= 0x04,
7873 M16_OPC_BNEQZ
= 0x05,
7874 M16_OPC_SHIFT
= 0x06,
7876 M16_OPC_RRIA
= 0x08,
7877 M16_OPC_ADDIU8
= 0x09,
7878 M16_OPC_SLTI
= 0x0a,
7879 M16_OPC_SLTIU
= 0x0b,
7882 M16_OPC_CMPI
= 0x0e,
7886 M16_OPC_LWSP
= 0x12,
7890 M16_OPC_LWPC
= 0x16,
7894 M16_OPC_SWSP
= 0x1a,
7898 M16_OPC_EXTEND
= 0x1e,
7902 /* I8 funct field */
7921 /* RR funct field */
7955 /* I64 funct field */
7967 /* RR ry field for CNVT */
7969 RR_RY_CNVT_ZEB
= 0x0,
7970 RR_RY_CNVT_ZEH
= 0x1,
7971 RR_RY_CNVT_ZEW
= 0x2,
7972 RR_RY_CNVT_SEB
= 0x4,
7973 RR_RY_CNVT_SEH
= 0x5,
7974 RR_RY_CNVT_SEW
= 0x6,
7977 static int xlat (int r
)
7979 static int map
[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
7984 static void gen_mips16_save (DisasContext
*ctx
,
7985 int xsregs
, int aregs
,
7986 int do_ra
, int do_s0
, int do_s1
,
7989 TCGv t0
= tcg_temp_new();
7990 TCGv t1
= tcg_temp_new();
8020 generate_exception(ctx
, EXCP_RI
);
8026 gen_base_offset_addr(ctx
, t0
, 29, 12);
8027 gen_load_gpr(t1
, 7);
8028 op_st_sw(t1
, t0
, ctx
);
8031 gen_base_offset_addr(ctx
, t0
, 29, 8);
8032 gen_load_gpr(t1
, 6);
8033 op_st_sw(t1
, t0
, ctx
);
8036 gen_base_offset_addr(ctx
, t0
, 29, 4);
8037 gen_load_gpr(t1
, 5);
8038 op_st_sw(t1
, t0
, ctx
);
8041 gen_base_offset_addr(ctx
, t0
, 29, 0);
8042 gen_load_gpr(t1
, 4);
8043 op_st_sw(t1
, t0
, ctx
);
8046 gen_load_gpr(t0
, 29);
8048 #define DECR_AND_STORE(reg) do { \
8049 tcg_gen_subi_tl(t0, t0, 4); \
8050 gen_load_gpr(t1, reg); \
8051 op_st_sw(t1, t0, ctx); \
8115 generate_exception(ctx
, EXCP_RI
);
8131 #undef DECR_AND_STORE
8133 tcg_gen_subi_tl(cpu_gpr
[29], cpu_gpr
[29], framesize
);
8138 static void gen_mips16_restore (DisasContext
*ctx
,
8139 int xsregs
, int aregs
,
8140 int do_ra
, int do_s0
, int do_s1
,
8144 TCGv t0
= tcg_temp_new();
8145 TCGv t1
= tcg_temp_new();
8147 tcg_gen_addi_tl(t0
, cpu_gpr
[29], framesize
);
8149 #define DECR_AND_LOAD(reg) do { \
8150 tcg_gen_subi_tl(t0, t0, 4); \
8151 op_ld_lw(t1, t0, ctx); \
8152 gen_store_gpr(t1, reg); \
8216 generate_exception(ctx
, EXCP_RI
);
8232 #undef DECR_AND_LOAD
8234 tcg_gen_addi_tl(cpu_gpr
[29], cpu_gpr
[29], framesize
);
8239 static void gen_addiupc (DisasContext
*ctx
, int rx
, int imm
,
8240 int is_64_bit
, int extended
)
8244 if (extended
&& (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
8245 generate_exception(ctx
, EXCP_RI
);
8249 t0
= tcg_temp_new();
8251 tcg_gen_movi_tl(t0
, pc_relative_pc(ctx
));
8252 tcg_gen_addi_tl(cpu_gpr
[rx
], t0
, imm
);
8254 tcg_gen_ext32s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8260 #if defined(TARGET_MIPS64)
8261 static void decode_i64_mips16 (CPUState
*env
, DisasContext
*ctx
,
8262 int ry
, int funct
, int16_t offset
,
8268 offset
= extended
? offset
: offset
<< 3;
8269 gen_ld(env
, ctx
, OPC_LD
, ry
, 29, offset
);
8273 offset
= extended
? offset
: offset
<< 3;
8274 gen_st(ctx
, OPC_SD
, ry
, 29, offset
);
8278 offset
= extended
? offset
: (ctx
->opcode
& 0xff) << 3;
8279 gen_st(ctx
, OPC_SD
, 31, 29, offset
);
8283 offset
= extended
? offset
: ((int8_t)ctx
->opcode
) << 3;
8284 gen_arith_imm(env
, ctx
, OPC_DADDIU
, 29, 29, offset
);
8287 if (extended
&& (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
8288 generate_exception(ctx
, EXCP_RI
);
8290 offset
= extended
? offset
: offset
<< 3;
8291 gen_ld(env
, ctx
, OPC_LDPC
, ry
, 0, offset
);
8296 offset
= extended
? offset
: ((int8_t)(offset
<< 3)) >> 3;
8297 gen_arith_imm(env
, ctx
, OPC_DADDIU
, ry
, ry
, offset
);
8301 offset
= extended
? offset
: offset
<< 2;
8302 gen_addiupc(ctx
, ry
, offset
, 1, extended
);
8306 offset
= extended
? offset
: offset
<< 2;
8307 gen_arith_imm(env
, ctx
, OPC_DADDIU
, ry
, 29, offset
);
8313 static int decode_extended_mips16_opc (CPUState
*env
, DisasContext
*ctx
,
8316 int extend
= lduw_code(ctx
->pc
+ 2);
8317 int op
, rx
, ry
, funct
, sa
;
8318 int16_t imm
, offset
;
8320 ctx
->opcode
= (ctx
->opcode
<< 16) | extend
;
8321 op
= (ctx
->opcode
>> 11) & 0x1f;
8322 sa
= (ctx
->opcode
>> 22) & 0x1f;
8323 funct
= (ctx
->opcode
>> 8) & 0x7;
8324 rx
= xlat((ctx
->opcode
>> 8) & 0x7);
8325 ry
= xlat((ctx
->opcode
>> 5) & 0x7);
8326 offset
= imm
= (int16_t) (((ctx
->opcode
>> 16) & 0x1f) << 11
8327 | ((ctx
->opcode
>> 21) & 0x3f) << 5
8328 | (ctx
->opcode
& 0x1f));
8330 /* The extended opcodes cleverly reuse the opcodes from their 16-bit
8333 case M16_OPC_ADDIUSP
:
8334 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, 29, imm
);
8336 case M16_OPC_ADDIUPC
:
8337 gen_addiupc(ctx
, rx
, imm
, 0, 1);
8340 gen_compute_branch(ctx
, OPC_BEQ
, 4, 0, 0, offset
<< 1);
8341 /* No delay slot, so just process as a normal instruction */
8344 gen_compute_branch(ctx
, OPC_BEQ
, 4, rx
, 0, offset
<< 1);
8345 /* No delay slot, so just process as a normal instruction */
8348 gen_compute_branch(ctx
, OPC_BNE
, 4, rx
, 0, offset
<< 1);
8349 /* No delay slot, so just process as a normal instruction */
8352 switch (ctx
->opcode
& 0x3) {
8354 gen_shift_imm(env
, ctx
, OPC_SLL
, rx
, ry
, sa
);
8357 #if defined(TARGET_MIPS64)
8359 gen_shift_imm(env
, ctx
, OPC_DSLL
, rx
, ry
, sa
);
8361 generate_exception(ctx
, EXCP_RI
);
8365 gen_shift_imm(env
, ctx
, OPC_SRL
, rx
, ry
, sa
);
8368 gen_shift_imm(env
, ctx
, OPC_SRA
, rx
, ry
, sa
);
8372 #if defined(TARGET_MIPS64)
8375 gen_ld(env
, ctx
, OPC_LD
, ry
, rx
, offset
);
8379 imm
= ctx
->opcode
& 0xf;
8380 imm
= imm
| ((ctx
->opcode
>> 20) & 0x7f) << 4;
8381 imm
= imm
| ((ctx
->opcode
>> 16) & 0xf) << 11;
8382 imm
= (int16_t) (imm
<< 1) >> 1;
8383 if ((ctx
->opcode
>> 4) & 0x1) {
8384 #if defined(TARGET_MIPS64)
8386 gen_arith_imm(env
, ctx
, OPC_DADDIU
, ry
, rx
, imm
);
8388 generate_exception(ctx
, EXCP_RI
);
8391 gen_arith_imm(env
, ctx
, OPC_ADDIU
, ry
, rx
, imm
);
8394 case M16_OPC_ADDIU8
:
8395 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, rx
, imm
);
8398 gen_slt_imm(env
, OPC_SLTI
, 24, rx
, imm
);
8401 gen_slt_imm(env
, OPC_SLTIU
, 24, rx
, imm
);
8406 gen_compute_branch(ctx
, OPC_BEQ
, 4, 24, 0, offset
<< 1);
8409 gen_compute_branch(ctx
, OPC_BNE
, 4, 24, 0, offset
<< 1);
8412 gen_st(ctx
, OPC_SW
, 31, 29, imm
);
8415 gen_arith_imm(env
, ctx
, OPC_ADDIU
, 29, 29, imm
);
8419 int xsregs
= (ctx
->opcode
>> 24) & 0x7;
8420 int aregs
= (ctx
->opcode
>> 16) & 0xf;
8421 int do_ra
= (ctx
->opcode
>> 6) & 0x1;
8422 int do_s0
= (ctx
->opcode
>> 5) & 0x1;
8423 int do_s1
= (ctx
->opcode
>> 4) & 0x1;
8424 int framesize
= (((ctx
->opcode
>> 20) & 0xf) << 4
8425 | (ctx
->opcode
& 0xf)) << 3;
8427 if (ctx
->opcode
& (1 << 7)) {
8428 gen_mips16_save(ctx
, xsregs
, aregs
,
8429 do_ra
, do_s0
, do_s1
,
8432 gen_mips16_restore(ctx
, xsregs
, aregs
,
8433 do_ra
, do_s0
, do_s1
,
8439 generate_exception(ctx
, EXCP_RI
);
8444 tcg_gen_movi_tl(cpu_gpr
[rx
], (uint16_t) imm
);
8447 tcg_gen_xori_tl(cpu_gpr
[24], cpu_gpr
[rx
], (uint16_t) imm
);
8449 #if defined(TARGET_MIPS64)
8451 gen_st(ctx
, OPC_SD
, ry
, rx
, offset
);
8455 gen_ld(env
, ctx
, OPC_LB
, ry
, rx
, offset
);
8458 gen_ld(env
, ctx
, OPC_LH
, ry
, rx
, offset
);
8461 gen_ld(env
, ctx
, OPC_LW
, rx
, 29, offset
);
8464 gen_ld(env
, ctx
, OPC_LW
, ry
, rx
, offset
);
8467 gen_ld(env
, ctx
, OPC_LBU
, ry
, rx
, offset
);
8470 gen_ld(env
, ctx
, OPC_LHU
, ry
, rx
, offset
);
8473 gen_ld(env
, ctx
, OPC_LWPC
, rx
, 0, offset
);
8475 #if defined(TARGET_MIPS64)
8477 gen_ld(env
, ctx
, OPC_LWU
, ry
, rx
, offset
);
8481 gen_st(ctx
, OPC_SB
, ry
, rx
, offset
);
8484 gen_st(ctx
, OPC_SH
, ry
, rx
, offset
);
8487 gen_st(ctx
, OPC_SW
, rx
, 29, offset
);
8490 gen_st(ctx
, OPC_SW
, ry
, rx
, offset
);
8492 #if defined(TARGET_MIPS64)
8494 decode_i64_mips16(env
, ctx
, ry
, funct
, offset
, 1);
8498 generate_exception(ctx
, EXCP_RI
);
8505 static int decode_mips16_opc (CPUState
*env
, DisasContext
*ctx
,
8510 int op
, cnvt_op
, op1
, offset
;
8514 op
= (ctx
->opcode
>> 11) & 0x1f;
8515 sa
= (ctx
->opcode
>> 2) & 0x7;
8516 sa
= sa
== 0 ? 8 : sa
;
8517 rx
= xlat((ctx
->opcode
>> 8) & 0x7);
8518 cnvt_op
= (ctx
->opcode
>> 5) & 0x7;
8519 ry
= xlat((ctx
->opcode
>> 5) & 0x7);
8520 op1
= offset
= ctx
->opcode
& 0x1f;
8525 case M16_OPC_ADDIUSP
:
8527 int16_t imm
= ((uint8_t) ctx
->opcode
) << 2;
8529 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, 29, imm
);
8532 case M16_OPC_ADDIUPC
:
8533 gen_addiupc(ctx
, rx
, ((uint8_t) ctx
->opcode
) << 2, 0, 0);
8536 offset
= (ctx
->opcode
& 0x7ff) << 1;
8537 offset
= (int16_t)(offset
<< 4) >> 4;
8538 gen_compute_branch(ctx
, OPC_BEQ
, 2, 0, 0, offset
);
8539 /* No delay slot, so just process as a normal instruction */
8542 offset
= lduw_code(ctx
->pc
+ 2);
8543 offset
= (((ctx
->opcode
& 0x1f) << 21)
8544 | ((ctx
->opcode
>> 5) & 0x1f) << 16
8546 op
= ((ctx
->opcode
>> 10) & 0x1) ? OPC_JALXS
: OPC_JALS
;
8547 gen_compute_branch(ctx
, op
, 4, rx
, ry
, offset
);
8552 gen_compute_branch(ctx
, OPC_BEQ
, 2, rx
, 0, ((int8_t)ctx
->opcode
) << 1);
8553 /* No delay slot, so just process as a normal instruction */
8556 gen_compute_branch(ctx
, OPC_BNE
, 2, rx
, 0, ((int8_t)ctx
->opcode
) << 1);
8557 /* No delay slot, so just process as a normal instruction */
8560 switch (ctx
->opcode
& 0x3) {
8562 gen_shift_imm(env
, ctx
, OPC_SLL
, rx
, ry
, sa
);
8565 #if defined(TARGET_MIPS64)
8567 gen_shift_imm(env
, ctx
, OPC_DSLL
, rx
, ry
, sa
);
8569 generate_exception(ctx
, EXCP_RI
);
8573 gen_shift_imm(env
, ctx
, OPC_SRL
, rx
, ry
, sa
);
8576 gen_shift_imm(env
, ctx
, OPC_SRA
, rx
, ry
, sa
);
8580 #if defined(TARGET_MIPS64)
8583 gen_ld(env
, ctx
, OPC_LD
, ry
, rx
, offset
<< 3);
8588 int16_t imm
= (int8_t)((ctx
->opcode
& 0xf) << 4) >> 4;
8590 if ((ctx
->opcode
>> 4) & 1) {
8591 #if defined(TARGET_MIPS64)
8593 gen_arith_imm(env
, ctx
, OPC_DADDIU
, ry
, rx
, imm
);
8595 generate_exception(ctx
, EXCP_RI
);
8598 gen_arith_imm(env
, ctx
, OPC_ADDIU
, ry
, rx
, imm
);
8602 case M16_OPC_ADDIU8
:
8604 int16_t imm
= (int8_t) ctx
->opcode
;
8606 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, rx
, imm
);
8611 int16_t imm
= (uint8_t) ctx
->opcode
;
8613 gen_slt_imm(env
, OPC_SLTI
, 24, rx
, imm
);
8618 int16_t imm
= (uint8_t) ctx
->opcode
;
8620 gen_slt_imm(env
, OPC_SLTIU
, 24, rx
, imm
);
8627 funct
= (ctx
->opcode
>> 8) & 0x7;
8630 gen_compute_branch(ctx
, OPC_BEQ
, 2, 24, 0,
8631 ((int8_t)ctx
->opcode
) << 1);
8634 gen_compute_branch(ctx
, OPC_BNE
, 2, 24, 0,
8635 ((int8_t)ctx
->opcode
) << 1);
8638 gen_st(ctx
, OPC_SW
, 31, 29, (ctx
->opcode
& 0xff) << 2);
8641 gen_arith_imm(env
, ctx
, OPC_ADDIU
, 29, 29,
8642 ((int8_t)ctx
->opcode
) << 3);
8646 int do_ra
= ctx
->opcode
& (1 << 6);
8647 int do_s0
= ctx
->opcode
& (1 << 5);
8648 int do_s1
= ctx
->opcode
& (1 << 4);
8649 int framesize
= ctx
->opcode
& 0xf;
8651 if (framesize
== 0) {
8654 framesize
= framesize
<< 3;
8657 if (ctx
->opcode
& (1 << 7)) {
8658 gen_mips16_save(ctx
, 0, 0,
8659 do_ra
, do_s0
, do_s1
, framesize
);
8661 gen_mips16_restore(ctx
, 0, 0,
8662 do_ra
, do_s0
, do_s1
, framesize
);
8668 int rz
= xlat(ctx
->opcode
& 0x7);
8670 reg32
= (((ctx
->opcode
>> 3) & 0x3) << 3) |
8671 ((ctx
->opcode
>> 5) & 0x7);
8672 gen_arith(env
, ctx
, OPC_ADDU
, reg32
, rz
, 0);
8676 reg32
= ctx
->opcode
& 0x1f;
8677 gen_arith(env
, ctx
, OPC_ADDU
, ry
, reg32
, 0);
8680 generate_exception(ctx
, EXCP_RI
);
8687 int16_t imm
= (uint8_t) ctx
->opcode
;
8689 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, 0, imm
);
8694 int16_t imm
= (uint8_t) ctx
->opcode
;
8696 gen_logic_imm(env
, OPC_XORI
, 24, rx
, imm
);
8699 #if defined(TARGET_MIPS64)
8702 gen_st(ctx
, OPC_SD
, ry
, rx
, offset
<< 3);
8706 gen_ld(env
, ctx
, OPC_LB
, ry
, rx
, offset
);
8709 gen_ld(env
, ctx
, OPC_LH
, ry
, rx
, offset
<< 1);
8712 gen_ld(env
, ctx
, OPC_LW
, rx
, 29, ((uint8_t)ctx
->opcode
) << 2);
8715 gen_ld(env
, ctx
, OPC_LW
, ry
, rx
, offset
<< 2);
8718 gen_ld(env
, ctx
, OPC_LBU
, ry
, rx
, offset
);
8721 gen_ld(env
, ctx
, OPC_LHU
, ry
, rx
, offset
<< 1);
8724 gen_ld(env
, ctx
, OPC_LWPC
, rx
, 0, ((uint8_t)ctx
->opcode
) << 2);
8726 #if defined (TARGET_MIPS64)
8729 gen_ld(env
, ctx
, OPC_LWU
, ry
, rx
, offset
<< 2);
8733 gen_st(ctx
, OPC_SB
, ry
, rx
, offset
);
8736 gen_st(ctx
, OPC_SH
, ry
, rx
, offset
<< 1);
8739 gen_st(ctx
, OPC_SW
, rx
, 29, ((uint8_t)ctx
->opcode
) << 2);
8742 gen_st(ctx
, OPC_SW
, ry
, rx
, offset
<< 2);
8746 int rz
= xlat((ctx
->opcode
>> 2) & 0x7);
8749 switch (ctx
->opcode
& 0x3) {
8751 mips32_op
= OPC_ADDU
;
8754 mips32_op
= OPC_SUBU
;
8756 #if defined(TARGET_MIPS64)
8758 mips32_op
= OPC_DADDU
;
8762 mips32_op
= OPC_DSUBU
;
8767 generate_exception(ctx
, EXCP_RI
);
8771 gen_arith(env
, ctx
, mips32_op
, rz
, rx
, ry
);
8780 int nd
= (ctx
->opcode
>> 7) & 0x1;
8781 int link
= (ctx
->opcode
>> 6) & 0x1;
8782 int ra
= (ctx
->opcode
>> 5) & 0x1;
8785 op
= nd
? OPC_JALRC
: OPC_JALRS
;
8790 gen_compute_branch(ctx
, op
, 2, ra
? 31 : rx
, 31, 0);
8797 /* XXX: not clear which exception should be raised
8798 * when in debug mode...
8800 check_insn(env
, ctx
, ISA_MIPS32
);
8801 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
8802 generate_exception(ctx
, EXCP_DBp
);
8804 generate_exception(ctx
, EXCP_DBp
);
8808 gen_slt(env
, OPC_SLT
, 24, rx
, ry
);
8811 gen_slt(env
, OPC_SLTU
, 24, rx
, ry
);
8814 generate_exception(ctx
, EXCP_BREAK
);
8817 gen_shift(env
, ctx
, OPC_SLLV
, ry
, rx
, ry
);
8820 gen_shift(env
, ctx
, OPC_SRLV
, ry
, rx
, ry
);
8823 gen_shift(env
, ctx
, OPC_SRAV
, ry
, rx
, ry
);
8825 #if defined (TARGET_MIPS64)
8828 gen_shift_imm(env
, ctx
, OPC_DSRL
, ry
, ry
, sa
);
8832 gen_logic(env
, OPC_XOR
, 24, rx
, ry
);
8835 gen_arith(env
, ctx
, OPC_SUBU
, rx
, 0, ry
);
8838 gen_logic(env
, OPC_AND
, rx
, rx
, ry
);
8841 gen_logic(env
, OPC_OR
, rx
, rx
, ry
);
8844 gen_logic(env
, OPC_XOR
, rx
, rx
, ry
);
8847 gen_logic(env
, OPC_NOR
, rx
, ry
, 0);
8850 gen_HILO(ctx
, OPC_MFHI
, rx
);
8854 case RR_RY_CNVT_ZEB
:
8855 tcg_gen_ext8u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8857 case RR_RY_CNVT_ZEH
:
8858 tcg_gen_ext16u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8860 case RR_RY_CNVT_SEB
:
8861 tcg_gen_ext8s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8863 case RR_RY_CNVT_SEH
:
8864 tcg_gen_ext16s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8866 #if defined (TARGET_MIPS64)
8867 case RR_RY_CNVT_ZEW
:
8869 tcg_gen_ext32u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8871 case RR_RY_CNVT_SEW
:
8873 tcg_gen_ext32s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8877 generate_exception(ctx
, EXCP_RI
);
8882 gen_HILO(ctx
, OPC_MFLO
, rx
);
8884 #if defined (TARGET_MIPS64)
8887 gen_shift_imm(env
, ctx
, OPC_DSRA
, ry
, ry
, sa
);
8891 gen_shift(env
, ctx
, OPC_DSLLV
, ry
, rx
, ry
);
8895 gen_shift(env
, ctx
, OPC_DSRLV
, ry
, rx
, ry
);
8899 gen_shift(env
, ctx
, OPC_DSRAV
, ry
, rx
, ry
);
8903 gen_muldiv(ctx
, OPC_MULT
, rx
, ry
);
8906 gen_muldiv(ctx
, OPC_MULTU
, rx
, ry
);
8909 gen_muldiv(ctx
, OPC_DIV
, rx
, ry
);
8912 gen_muldiv(ctx
, OPC_DIVU
, rx
, ry
);
8914 #if defined (TARGET_MIPS64)
8917 gen_muldiv(ctx
, OPC_DMULT
, rx
, ry
);
8921 gen_muldiv(ctx
, OPC_DMULTU
, rx
, ry
);
8925 gen_muldiv(ctx
, OPC_DDIV
, rx
, ry
);
8929 gen_muldiv(ctx
, OPC_DDIVU
, rx
, ry
);
8933 generate_exception(ctx
, EXCP_RI
);
8937 case M16_OPC_EXTEND
:
8938 decode_extended_mips16_opc(env
, ctx
, is_branch
);
8941 #if defined(TARGET_MIPS64)
8943 funct
= (ctx
->opcode
>> 8) & 0x7;
8944 decode_i64_mips16(env
, ctx
, ry
, funct
, offset
, 0);
8948 generate_exception(ctx
, EXCP_RI
);
8955 /* microMIPS extension to MIPS32 */
8957 /* microMIPS32 major opcodes */
8996 /* 0x20 is reserved */
9006 /* 0x28 and 0x29 are reserved */
9016 /* 0x30 and 0x31 are reserved */
9026 /* 0x38 and 0x39 are reserved */
9037 /* POOL32A encoding of minor opcode field */
9040 /* These opcodes are distinguished only by bits 9..6; those bits are
9041 * what are recorded below. */
9067 /* The following can be distinguished by their lower 6 bits. */
9073 /* POOL32AXF encoding of minor opcode field extension */
9087 /* bits 13..12 for 0x01 */
9093 /* bits 13..12 for 0x2a */
9099 /* bits 13..12 for 0x32 */
9103 /* bits 15..12 for 0x2c */
9119 /* bits 15..12 for 0x34 */
9127 /* bits 15..12 for 0x3c */
9129 JR
= 0x0, /* alias */
9134 /* bits 15..12 for 0x05 */
9138 /* bits 15..12 for 0x0d */
9148 /* bits 15..12 for 0x15 */
9154 /* bits 15..12 for 0x1d */
9158 /* bits 15..12 for 0x2d */
9163 /* bits 15..12 for 0x35 */
9170 /* POOL32B encoding of minor opcode field (bits 15..12) */
9186 /* POOL32C encoding of minor opcode field (bits 15..12) */
9194 /* 0xa is reserved */
9201 /* 0x6 is reserved */
9207 /* POOL32F encoding of minor opcode field (bits 5..0) */
9210 /* These are the bit 7..6 values */
9221 /* These are the bit 8..6 values */
9265 CABS_COND_FMT
= 0x1c, /* MIPS3D */
9269 /* POOL32Fxf encoding of minor opcode extension field */
9307 /* POOL32I encoding of minor opcode field (bits 25..21) */
9332 /* These overlap and are distinguished by bit16 of the instruction */
9341 /* POOL16A encoding of minor opcode field */
9348 /* POOL16B encoding of minor opcode field */
9355 /* POOL16C encoding of minor opcode field */
9375 /* POOL16D encoding of minor opcode field */
9382 /* POOL16E encoding of minor opcode field */
9389 static int mmreg (int r
)
9391 static const int map
[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
9396 /* Used for 16-bit store instructions. */
9397 static int mmreg2 (int r
)
9399 static const int map
[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
9404 #define uMIPS_RD(op) ((op >> 7) & 0x7)
9405 #define uMIPS_RS(op) ((op >> 4) & 0x7)
9406 #define uMIPS_RS2(op) uMIPS_RS(op)
9407 #define uMIPS_RS1(op) ((op >> 1) & 0x7)
9408 #define uMIPS_RD5(op) ((op >> 5) & 0x1f)
9409 #define uMIPS_RS5(op) (op & 0x1f)
9411 /* Signed immediate */
9412 #define SIMM(op, start, width) \
9413 ((int32_t)(((op >> start) & ((~0U) >> (32-width))) \
9416 /* Zero-extended immediate */
9417 #define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32-width)))
9419 static void gen_addiur1sp (CPUState
*env
, DisasContext
*ctx
)
9421 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
9423 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rd
, 29, ((ctx
->opcode
>> 1) & 0x3f) << 2);
9426 static void gen_addiur2 (CPUState
*env
, DisasContext
*ctx
)
9428 static const int decoded_imm
[] = { 1, 4, 8, 12, 16, 20, 24, -1 };
9429 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
9430 int rs
= mmreg(uMIPS_RS(ctx
->opcode
));
9432 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rd
, rs
, decoded_imm
[ZIMM(ctx
->opcode
, 1, 3)]);
9435 static void gen_addiusp (CPUState
*env
, DisasContext
*ctx
)
9437 int encoded
= ZIMM(ctx
->opcode
, 1, 9);
9441 decoded
= 256 + encoded
;
9442 } else if (encoded
<= 255) {
9444 } else if (encoded
<= 509) {
9445 decoded
= encoded
- 512;
9447 decoded
= encoded
- 768;
9450 gen_arith_imm(env
, ctx
, OPC_ADDIU
, 29, 29, decoded
<< 2);
9453 static void gen_addius5 (CPUState
*env
, DisasContext
*ctx
)
9455 int imm
= SIMM(ctx
->opcode
, 1, 4);
9456 int rd
= (ctx
->opcode
>> 5) & 0x1f;
9458 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rd
, rd
, imm
);
9461 static void gen_andi16 (CPUState
*env
, DisasContext
*ctx
)
9463 static const int decoded_imm
[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16,
9464 31, 32, 63, 64, 255, 32768, 65535 };
9465 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
9466 int rs
= mmreg(uMIPS_RS(ctx
->opcode
));
9467 int encoded
= ZIMM(ctx
->opcode
, 0, 4);
9469 gen_logic_imm(env
, OPC_ANDI
, rd
, rs
, decoded_imm
[encoded
]);
9472 static void gen_ldst_multiple (DisasContext
*ctx
, uint32_t opc
, int reglist
,
9473 int base
, int16_t offset
)
9478 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
9479 generate_exception(ctx
, EXCP_RI
);
9483 t0
= tcg_temp_new();
9485 gen_base_offset_addr(ctx
, t0
, base
, offset
);
9487 t1
= tcg_const_tl(reglist
);
9488 t2
= tcg_const_i32(ctx
->mem_idx
);
9490 save_cpu_state(ctx
, 1);
9493 gen_helper_lwm(t0
, t1
, t2
);
9496 gen_helper_swm(t0
, t1
, t2
);
9498 #ifdef TARGET_MIPS64
9500 gen_helper_ldm(t0
, t1
, t2
);
9503 gen_helper_sdm(t0
, t1
, t2
);
9507 MIPS_DEBUG("%s, %x, %d(%s)", opn
, reglist
, offset
, regnames
[base
]);
9510 tcg_temp_free_i32(t2
);
9514 static void gen_pool16c_insn (CPUState
*env
, DisasContext
*ctx
, int *is_branch
)
9516 int rd
= mmreg((ctx
->opcode
>> 3) & 0x7);
9517 int rs
= mmreg(ctx
->opcode
& 0x7);
9520 switch (((ctx
->opcode
) >> 4) & 0x3f) {
9525 gen_logic(env
, OPC_NOR
, rd
, rs
, 0);
9531 gen_logic(env
, OPC_XOR
, rd
, rd
, rs
);
9537 gen_logic(env
, OPC_AND
, rd
, rd
, rs
);
9543 gen_logic(env
, OPC_OR
, rd
, rd
, rs
);
9550 static const int lwm_convert
[] = { 0x11, 0x12, 0x13, 0x14 };
9551 int offset
= ZIMM(ctx
->opcode
, 0, 4);
9553 gen_ldst_multiple(ctx
, LWM32
, lwm_convert
[(ctx
->opcode
>> 4) & 0x3],
9562 static const int swm_convert
[] = { 0x11, 0x12, 0x13, 0x14 };
9563 int offset
= ZIMM(ctx
->opcode
, 0, 4);
9565 gen_ldst_multiple(ctx
, SWM32
, swm_convert
[(ctx
->opcode
>> 4) & 0x3],
9572 int reg
= ctx
->opcode
& 0x1f;
9574 gen_compute_branch(ctx
, OPC_JR
, 2, reg
, 0, 0);
9581 int reg
= ctx
->opcode
& 0x1f;
9583 gen_compute_branch(ctx
, OPC_JR
, 2, reg
, 0, 0);
9584 /* Let normal delay slot handling in our caller take us
9585 to the branch target. */
9597 int reg
= ctx
->opcode
& 0x1f;
9599 gen_compute_branch(ctx
, opc
, 2, reg
, 31, 0);
9605 gen_HILO(ctx
, OPC_MFHI
, uMIPS_RS5(ctx
->opcode
));
9609 gen_HILO(ctx
, OPC_MFLO
, uMIPS_RS5(ctx
->opcode
));
9612 generate_exception(ctx
, EXCP_BREAK
);
9615 /* XXX: not clear which exception should be raised
9616 * when in debug mode...
9618 check_insn(env
, ctx
, ISA_MIPS32
);
9619 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
9620 generate_exception(ctx
, EXCP_DBp
);
9622 generate_exception(ctx
, EXCP_DBp
);
9628 int imm
= ZIMM(ctx
->opcode
, 0, 5);
9630 gen_compute_branch(ctx
, OPC_JR
, 2, 31, 0, 0);
9631 gen_arith_imm(env
, ctx
, OPC_ADDIU
, 29, 29, imm
<< 2);
9632 /* Let normal delay slot handling in our caller take us
9633 to the branch target. */
9637 generate_exception(ctx
, EXCP_RI
);
9642 static void gen_ldxs (DisasContext
*ctx
, int base
, int index
, int rd
)
9644 TCGv t0
= tcg_temp_new();
9645 TCGv t1
= tcg_temp_new();
9647 gen_load_gpr(t0
, base
);
9650 gen_load_gpr(t1
, index
);
9651 tcg_gen_shli_tl(t1
, t1
, 2);
9652 gen_op_addr_add(ctx
, t0
, t1
, t0
);
9655 save_cpu_state(ctx
, 0);
9656 op_ld_lw(t1
, t0
, ctx
);
9657 gen_store_gpr(t1
, rd
);
9663 static void gen_ldst_pair (DisasContext
*ctx
, uint32_t opc
, int rd
,
9664 int base
, int16_t offset
)
9666 const char *opn
= "ldst_pair";
9669 if (ctx
->hflags
& MIPS_HFLAG_BMASK
|| rd
== 31 || rd
== base
) {
9670 generate_exception(ctx
, EXCP_RI
);
9674 t0
= tcg_temp_new();
9675 t1
= tcg_temp_new();
9677 gen_base_offset_addr(ctx
, t0
, base
, offset
);
9681 save_cpu_state(ctx
, 0);
9682 op_ld_lw(t1
, t0
, ctx
);
9683 gen_store_gpr(t1
, rd
);
9684 tcg_gen_movi_tl(t1
, 4);
9685 gen_op_addr_add(ctx
, t0
, t0
, t1
);
9686 op_ld_lw(t1
, t0
, ctx
);
9687 gen_store_gpr(t1
, rd
+1);
9691 save_cpu_state(ctx
, 1);
9692 gen_load_gpr(t1
, rd
);
9693 op_st_sw(t1
, t0
, ctx
);
9694 tcg_gen_movi_tl(t1
, 4);
9695 gen_op_addr_add(ctx
, t0
, t0
, t1
);
9696 gen_load_gpr(t1
, rd
+1);
9697 op_st_sw(t1
, t0
, ctx
);
9700 #ifdef TARGET_MIPS64
9702 save_cpu_state(ctx
, 0);
9703 op_ld_ld(t1
, t0
, ctx
);
9704 gen_store_gpr(t1
, rd
);
9705 tcg_gen_movi_tl(t1
, 8);
9706 gen_op_addr_add(ctx
, t0
, t0
, t1
);
9707 op_ld_ld(t1
, t0
, ctx
);
9708 gen_store_gpr(t1
, rd
+1);
9712 save_cpu_state(ctx
, 1);
9713 gen_load_gpr(t1
, rd
);
9714 op_st_sd(t1
, t0
, ctx
);
9715 tcg_gen_movi_tl(t1
, 8);
9716 gen_op_addr_add(ctx
, t0
, t0
, t1
);
9717 gen_load_gpr(t1
, rd
+1);
9718 op_st_sd(t1
, t0
, ctx
);
9723 MIPS_DEBUG("%s, %s, %d(%s)", opn
, regnames
[rd
], offset
, regnames
[base
]);
9728 static void gen_pool32axf (CPUState
*env
, DisasContext
*ctx
, int rt
, int rs
,
9731 int extension
= (ctx
->opcode
>> 6) & 0x3f;
9732 int minor
= (ctx
->opcode
>> 12) & 0xf;
9735 switch (extension
) {
9737 mips32_op
= OPC_TEQ
;
9740 mips32_op
= OPC_TGE
;
9743 mips32_op
= OPC_TGEU
;
9746 mips32_op
= OPC_TLT
;
9749 mips32_op
= OPC_TLTU
;
9752 mips32_op
= OPC_TNE
;
9754 gen_trap(ctx
, mips32_op
, rs
, rt
, -1);
9756 #ifndef CONFIG_USER_ONLY
9763 gen_mfc0(env
, ctx
, cpu_gpr
[rt
], rs
, (ctx
->opcode
>> 11) & 0x7);
9768 TCGv t0
= tcg_temp_new();
9770 gen_load_gpr(t0
, rt
);
9771 gen_mtc0(env
, ctx
, t0
, rs
, (ctx
->opcode
>> 11) & 0x7);
9779 gen_bshfl(ctx
, OPC_SEB
, rs
, rt
);
9782 gen_bshfl(ctx
, OPC_SEH
, rs
, rt
);
9785 mips32_op
= OPC_CLO
;
9788 mips32_op
= OPC_CLZ
;
9790 check_insn(env
, ctx
, ISA_MIPS32
);
9791 gen_cl(ctx
, mips32_op
, rt
, rs
);
9794 gen_rdhwr(env
, ctx
, rt
, rs
);
9797 gen_bshfl(ctx
, OPC_WSBH
, rs
, rt
);
9800 mips32_op
= OPC_MULT
;
9803 mips32_op
= OPC_MULTU
;
9806 mips32_op
= OPC_DIV
;
9809 mips32_op
= OPC_DIVU
;
9812 mips32_op
= OPC_MADD
;
9815 mips32_op
= OPC_MADDU
;
9818 mips32_op
= OPC_MSUB
;
9821 mips32_op
= OPC_MSUBU
;
9823 check_insn(env
, ctx
, ISA_MIPS32
);
9824 gen_muldiv(ctx
, mips32_op
, rs
, rt
);
9827 goto pool32axf_invalid
;
9838 generate_exception_err(ctx
, EXCP_CpU
, 2);
9841 goto pool32axf_invalid
;
9848 gen_compute_branch (ctx
, OPC_JALR
, 4, rs
, rt
, 0);
9853 gen_compute_branch (ctx
, OPC_JALRS
, 4, rs
, rt
, 0);
9857 goto pool32axf_invalid
;
9863 check_insn(env
, ctx
, ISA_MIPS32R2
);
9864 gen_load_srsgpr(rt
, rs
);
9867 check_insn(env
, ctx
, ISA_MIPS32R2
);
9868 gen_store_srsgpr(rt
, rs
);
9871 goto pool32axf_invalid
;
9874 #ifndef CONFIG_USER_ONLY
9878 mips32_op
= OPC_TLBP
;
9881 mips32_op
= OPC_TLBR
;
9884 mips32_op
= OPC_TLBWI
;
9887 mips32_op
= OPC_TLBWR
;
9890 mips32_op
= OPC_WAIT
;
9893 mips32_op
= OPC_DERET
;
9896 mips32_op
= OPC_ERET
;
9898 gen_cp0(env
, ctx
, mips32_op
, rt
, rs
);
9901 goto pool32axf_invalid
;
9908 TCGv t0
= tcg_temp_new();
9910 save_cpu_state(ctx
, 1);
9912 gen_store_gpr(t0
, rs
);
9913 /* Stop translation as we may have switched the execution mode */
9914 ctx
->bstate
= BS_STOP
;
9920 TCGv t0
= tcg_temp_new();
9922 save_cpu_state(ctx
, 1);
9924 gen_store_gpr(t0
, rs
);
9925 /* Stop translation as we may have switched the execution mode */
9926 ctx
->bstate
= BS_STOP
;
9931 goto pool32axf_invalid
;
9941 generate_exception(ctx
, EXCP_SYSCALL
);
9942 ctx
->bstate
= BS_STOP
;
9945 check_insn(env
, ctx
, ISA_MIPS32
);
9946 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
9947 generate_exception(ctx
, EXCP_DBp
);
9949 generate_exception(ctx
, EXCP_DBp
);
9953 goto pool32axf_invalid
;
9959 gen_HILO(ctx
, OPC_MFHI
, rs
);
9962 gen_HILO(ctx
, OPC_MFLO
, rs
);
9965 gen_HILO(ctx
, OPC_MTHI
, rs
);
9968 gen_HILO(ctx
, OPC_MTLO
, rs
);
9971 goto pool32axf_invalid
;
9976 MIPS_INVAL("pool32axf");
9977 generate_exception(ctx
, EXCP_RI
);
9982 /* Values for microMIPS fmt field. Variable-width, depending on which
9983 formats the instruction supports. */
10002 static void gen_pool32fxf (CPUState
*env
, DisasContext
*ctx
, int rt
, int rs
)
10004 int extension
= (ctx
->opcode
>> 6) & 0x3ff;
10005 uint32_t mips32_op
;
10007 #define FLOAT_1BIT_FMT(opc, fmt) (fmt << 8) | opc
10008 #define FLOAT_2BIT_FMT(opc, fmt) (fmt << 7) | opc
10009 #define COND_FLOAT_MOV(opc, cond) (cond << 7) | opc
10011 switch (extension
) {
10012 case FLOAT_1BIT_FMT(CFC1
, 0):
10013 mips32_op
= OPC_CFC1
;
10015 case FLOAT_1BIT_FMT(CTC1
, 0):
10016 mips32_op
= OPC_CTC1
;
10018 case FLOAT_1BIT_FMT(MFC1
, 0):
10019 mips32_op
= OPC_MFC1
;
10021 case FLOAT_1BIT_FMT(MTC1
, 0):
10022 mips32_op
= OPC_MTC1
;
10024 case FLOAT_1BIT_FMT(MFHC1
, 0):
10025 mips32_op
= OPC_MFHC1
;
10027 case FLOAT_1BIT_FMT(MTHC1
, 0):
10028 mips32_op
= OPC_MTHC1
;
10030 gen_cp1(ctx
, mips32_op
, rt
, rs
);
10033 /* Reciprocal square root */
10034 case FLOAT_1BIT_FMT(RSQRT_FMT
, FMT_SD_S
):
10035 mips32_op
= OPC_RSQRT_S
;
10037 case FLOAT_1BIT_FMT(RSQRT_FMT
, FMT_SD_D
):
10038 mips32_op
= OPC_RSQRT_D
;
10042 case FLOAT_1BIT_FMT(SQRT_FMT
, FMT_SD_S
):
10043 mips32_op
= OPC_SQRT_S
;
10045 case FLOAT_1BIT_FMT(SQRT_FMT
, FMT_SD_D
):
10046 mips32_op
= OPC_SQRT_D
;
10050 case FLOAT_1BIT_FMT(RECIP_FMT
, FMT_SD_S
):
10051 mips32_op
= OPC_RECIP_S
;
10053 case FLOAT_1BIT_FMT(RECIP_FMT
, FMT_SD_D
):
10054 mips32_op
= OPC_RECIP_D
;
10058 case FLOAT_1BIT_FMT(FLOOR_L
, FMT_SD_S
):
10059 mips32_op
= OPC_FLOOR_L_S
;
10061 case FLOAT_1BIT_FMT(FLOOR_L
, FMT_SD_D
):
10062 mips32_op
= OPC_FLOOR_L_D
;
10064 case FLOAT_1BIT_FMT(FLOOR_W
, FMT_SD_S
):
10065 mips32_op
= OPC_FLOOR_W_S
;
10067 case FLOAT_1BIT_FMT(FLOOR_W
, FMT_SD_D
):
10068 mips32_op
= OPC_FLOOR_W_D
;
10072 case FLOAT_1BIT_FMT(CEIL_L
, FMT_SD_S
):
10073 mips32_op
= OPC_CEIL_L_S
;
10075 case FLOAT_1BIT_FMT(CEIL_L
, FMT_SD_D
):
10076 mips32_op
= OPC_CEIL_L_D
;
10078 case FLOAT_1BIT_FMT(CEIL_W
, FMT_SD_S
):
10079 mips32_op
= OPC_CEIL_W_S
;
10081 case FLOAT_1BIT_FMT(CEIL_W
, FMT_SD_D
):
10082 mips32_op
= OPC_CEIL_W_D
;
10086 case FLOAT_1BIT_FMT(TRUNC_L
, FMT_SD_S
):
10087 mips32_op
= OPC_TRUNC_L_S
;
10089 case FLOAT_1BIT_FMT(TRUNC_L
, FMT_SD_D
):
10090 mips32_op
= OPC_TRUNC_L_D
;
10092 case FLOAT_1BIT_FMT(TRUNC_W
, FMT_SD_S
):
10093 mips32_op
= OPC_TRUNC_W_S
;
10095 case FLOAT_1BIT_FMT(TRUNC_W
, FMT_SD_D
):
10096 mips32_op
= OPC_TRUNC_W_D
;
10100 case FLOAT_1BIT_FMT(ROUND_L
, FMT_SD_S
):
10101 mips32_op
= OPC_ROUND_L_S
;
10103 case FLOAT_1BIT_FMT(ROUND_L
, FMT_SD_D
):
10104 mips32_op
= OPC_ROUND_L_D
;
10106 case FLOAT_1BIT_FMT(ROUND_W
, FMT_SD_S
):
10107 mips32_op
= OPC_ROUND_W_S
;
10109 case FLOAT_1BIT_FMT(ROUND_W
, FMT_SD_D
):
10110 mips32_op
= OPC_ROUND_W_D
;
10113 /* Integer to floating-point conversion */
10114 case FLOAT_1BIT_FMT(CVT_L
, FMT_SD_S
):
10115 mips32_op
= OPC_CVT_L_S
;
10117 case FLOAT_1BIT_FMT(CVT_L
, FMT_SD_D
):
10118 mips32_op
= OPC_CVT_L_D
;
10120 case FLOAT_1BIT_FMT(CVT_W
, FMT_SD_S
):
10121 mips32_op
= OPC_CVT_W_S
;
10123 case FLOAT_1BIT_FMT(CVT_W
, FMT_SD_D
):
10124 mips32_op
= OPC_CVT_W_D
;
10127 /* Paired-foo conversions */
10128 case FLOAT_1BIT_FMT(CVT_S_PL
, 0):
10129 mips32_op
= OPC_CVT_S_PL
;
10131 case FLOAT_1BIT_FMT(CVT_S_PU
, 0):
10132 mips32_op
= OPC_CVT_S_PU
;
10134 case FLOAT_1BIT_FMT(CVT_PW_PS
, 0):
10135 mips32_op
= OPC_CVT_PW_PS
;
10137 case FLOAT_1BIT_FMT(CVT_PS_PW
, 0):
10138 mips32_op
= OPC_CVT_PS_PW
;
10141 /* Floating-point moves */
10142 case FLOAT_2BIT_FMT(MOV_FMT
, FMT_SDPS_S
):
10143 mips32_op
= OPC_MOV_S
;
10145 case FLOAT_2BIT_FMT(MOV_FMT
, FMT_SDPS_D
):
10146 mips32_op
= OPC_MOV_D
;
10148 case FLOAT_2BIT_FMT(MOV_FMT
, FMT_SDPS_PS
):
10149 mips32_op
= OPC_MOV_PS
;
10152 /* Absolute value */
10153 case FLOAT_2BIT_FMT(ABS_FMT
, FMT_SDPS_S
):
10154 mips32_op
= OPC_ABS_S
;
10156 case FLOAT_2BIT_FMT(ABS_FMT
, FMT_SDPS_D
):
10157 mips32_op
= OPC_ABS_D
;
10159 case FLOAT_2BIT_FMT(ABS_FMT
, FMT_SDPS_PS
):
10160 mips32_op
= OPC_ABS_PS
;
10164 case FLOAT_2BIT_FMT(NEG_FMT
, FMT_SDPS_S
):
10165 mips32_op
= OPC_NEG_S
;
10167 case FLOAT_2BIT_FMT(NEG_FMT
, FMT_SDPS_D
):
10168 mips32_op
= OPC_NEG_D
;
10170 case FLOAT_2BIT_FMT(NEG_FMT
, FMT_SDPS_PS
):
10171 mips32_op
= OPC_NEG_PS
;
10174 /* Reciprocal square root step */
10175 case FLOAT_2BIT_FMT(RSQRT1_FMT
, FMT_SDPS_S
):
10176 mips32_op
= OPC_RSQRT1_S
;
10178 case FLOAT_2BIT_FMT(RSQRT1_FMT
, FMT_SDPS_D
):
10179 mips32_op
= OPC_RSQRT1_D
;
10181 case FLOAT_2BIT_FMT(RSQRT1_FMT
, FMT_SDPS_PS
):
10182 mips32_op
= OPC_RSQRT1_PS
;
10185 /* Reciprocal step */
10186 case FLOAT_2BIT_FMT(RECIP1_FMT
, FMT_SDPS_S
):
10187 mips32_op
= OPC_RECIP1_S
;
10189 case FLOAT_2BIT_FMT(RECIP1_FMT
, FMT_SDPS_D
):
10190 mips32_op
= OPC_RECIP1_S
;
10192 case FLOAT_2BIT_FMT(RECIP1_FMT
, FMT_SDPS_PS
):
10193 mips32_op
= OPC_RECIP1_PS
;
10196 /* Conversions from double */
10197 case FLOAT_2BIT_FMT(CVT_D
, FMT_SWL_S
):
10198 mips32_op
= OPC_CVT_D_S
;
10200 case FLOAT_2BIT_FMT(CVT_D
, FMT_SWL_W
):
10201 mips32_op
= OPC_CVT_D_W
;
10203 case FLOAT_2BIT_FMT(CVT_D
, FMT_SWL_L
):
10204 mips32_op
= OPC_CVT_D_L
;
10207 /* Conversions from single */
10208 case FLOAT_2BIT_FMT(CVT_S
, FMT_DWL_D
):
10209 mips32_op
= OPC_CVT_S_D
;
10211 case FLOAT_2BIT_FMT(CVT_S
, FMT_DWL_W
):
10212 mips32_op
= OPC_CVT_S_W
;
10214 case FLOAT_2BIT_FMT(CVT_S
, FMT_DWL_L
):
10215 mips32_op
= OPC_CVT_S_L
;
10217 gen_farith(ctx
, mips32_op
, -1, rs
, rt
, 0);
10220 /* Conditional moves on floating-point codes */
10221 case COND_FLOAT_MOV(MOVT
, 0):
10222 case COND_FLOAT_MOV(MOVT
, 1):
10223 case COND_FLOAT_MOV(MOVT
, 2):
10224 case COND_FLOAT_MOV(MOVT
, 3):
10225 case COND_FLOAT_MOV(MOVT
, 4):
10226 case COND_FLOAT_MOV(MOVT
, 5):
10227 case COND_FLOAT_MOV(MOVT
, 6):
10228 case COND_FLOAT_MOV(MOVT
, 7):
10229 gen_movci(ctx
, rt
, rs
, (ctx
->opcode
>> 13) & 0x7, 1);
10231 case COND_FLOAT_MOV(MOVF
, 0):
10232 case COND_FLOAT_MOV(MOVF
, 1):
10233 case COND_FLOAT_MOV(MOVF
, 2):
10234 case COND_FLOAT_MOV(MOVF
, 3):
10235 case COND_FLOAT_MOV(MOVF
, 4):
10236 case COND_FLOAT_MOV(MOVF
, 5):
10237 case COND_FLOAT_MOV(MOVF
, 6):
10238 case COND_FLOAT_MOV(MOVF
, 7):
10239 gen_movci(ctx
, rt
, rs
, (ctx
->opcode
>> 13) & 0x7, 0);
10242 MIPS_INVAL("pool32fxf");
10243 generate_exception(ctx
, EXCP_RI
);
10248 static void decode_micromips32_opc (CPUState
*env
, DisasContext
*ctx
,
10249 uint16_t insn_hw1
, int *is_branch
)
10253 int rt
, rs
, rd
, rr
;
10255 uint32_t op
, minor
, mips32_op
;
10256 uint32_t cond
, fmt
, cc
;
10258 insn
= lduw_code(ctx
->pc
+ 2);
10259 ctx
->opcode
= (ctx
->opcode
<< 16) | insn
;
10261 rt
= (ctx
->opcode
>> 21) & 0x1f;
10262 rs
= (ctx
->opcode
>> 16) & 0x1f;
10263 rd
= (ctx
->opcode
>> 11) & 0x1f;
10264 rr
= (ctx
->opcode
>> 6) & 0x1f;
10265 imm
= (int16_t) ctx
->opcode
;
10267 op
= (ctx
->opcode
>> 26) & 0x3f;
10270 minor
= ctx
->opcode
& 0x3f;
10273 minor
= (ctx
->opcode
>> 6) & 0xf;
10276 mips32_op
= OPC_SLL
;
10279 mips32_op
= OPC_SRA
;
10282 mips32_op
= OPC_SRL
;
10285 mips32_op
= OPC_ROTR
;
10287 gen_shift_imm(env
, ctx
, mips32_op
, rt
, rs
, rd
);
10290 goto pool32a_invalid
;
10294 minor
= (ctx
->opcode
>> 6) & 0xf;
10298 mips32_op
= OPC_ADD
;
10301 mips32_op
= OPC_ADDU
;
10304 mips32_op
= OPC_SUB
;
10307 mips32_op
= OPC_SUBU
;
10310 mips32_op
= OPC_MUL
;
10312 gen_arith(env
, ctx
, mips32_op
, rd
, rs
, rt
);
10316 mips32_op
= OPC_SLLV
;
10319 mips32_op
= OPC_SRLV
;
10322 mips32_op
= OPC_SRAV
;
10325 mips32_op
= OPC_ROTRV
;
10327 gen_shift(env
, ctx
, mips32_op
, rd
, rs
, rt
);
10329 /* Logical operations */
10331 mips32_op
= OPC_AND
;
10334 mips32_op
= OPC_OR
;
10337 mips32_op
= OPC_NOR
;
10340 mips32_op
= OPC_XOR
;
10342 gen_logic(env
, mips32_op
, rd
, rs
, rt
);
10344 /* Set less than */
10346 mips32_op
= OPC_SLT
;
10349 mips32_op
= OPC_SLTU
;
10351 gen_slt(env
, mips32_op
, rd
, rs
, rt
);
10354 goto pool32a_invalid
;
10358 minor
= (ctx
->opcode
>> 6) & 0xf;
10360 /* Conditional moves */
10362 mips32_op
= OPC_MOVN
;
10365 mips32_op
= OPC_MOVZ
;
10367 gen_cond_move(env
, mips32_op
, rd
, rs
, rt
);
10370 gen_ldxs(ctx
, rs
, rt
, rd
);
10373 goto pool32a_invalid
;
10377 gen_bitops(ctx
, OPC_INS
, rt
, rs
, rr
, rd
);
10380 gen_bitops(ctx
, OPC_EXT
, rt
, rs
, rr
, rd
);
10383 gen_pool32axf(env
, ctx
, rt
, rs
, is_branch
);
10386 generate_exception(ctx
, EXCP_BREAK
);
10390 MIPS_INVAL("pool32a");
10391 generate_exception(ctx
, EXCP_RI
);
10396 minor
= (ctx
->opcode
>> 12) & 0xf;
10399 /* Treat as no-op. */
10403 /* COP2: Not implemented. */
10404 generate_exception_err(ctx
, EXCP_CpU
, 2);
10408 #ifdef TARGET_MIPS64
10412 gen_ldst_pair(ctx
, minor
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
10416 #ifdef TARGET_MIPS64
10420 gen_ldst_multiple(ctx
, minor
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
10423 MIPS_INVAL("pool32b");
10424 generate_exception(ctx
, EXCP_RI
);
10429 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
10430 minor
= ctx
->opcode
& 0x3f;
10431 check_cp1_enabled(ctx
);
10434 mips32_op
= OPC_ALNV_PS
;
10437 mips32_op
= OPC_MADD_S
;
10440 mips32_op
= OPC_MADD_D
;
10443 mips32_op
= OPC_MADD_PS
;
10446 mips32_op
= OPC_MSUB_S
;
10449 mips32_op
= OPC_MSUB_D
;
10452 mips32_op
= OPC_MSUB_PS
;
10455 mips32_op
= OPC_NMADD_S
;
10458 mips32_op
= OPC_NMADD_D
;
10461 mips32_op
= OPC_NMADD_PS
;
10464 mips32_op
= OPC_NMSUB_S
;
10467 mips32_op
= OPC_NMSUB_D
;
10470 mips32_op
= OPC_NMSUB_PS
;
10472 gen_flt3_arith(ctx
, mips32_op
, rd
, rr
, rs
, rt
);
10474 case CABS_COND_FMT
:
10475 cond
= (ctx
->opcode
>> 6) & 0xf;
10476 cc
= (ctx
->opcode
>> 13) & 0x7;
10477 fmt
= (ctx
->opcode
>> 10) & 0x3;
10480 gen_cmpabs_s(ctx
, cond
, rt
, rs
, cc
);
10483 gen_cmpabs_d(ctx
, cond
, rt
, rs
, cc
);
10486 gen_cmpabs_ps(ctx
, cond
, rt
, rs
, cc
);
10489 goto pool32f_invalid
;
10493 cond
= (ctx
->opcode
>> 6) & 0xf;
10494 cc
= (ctx
->opcode
>> 13) & 0x7;
10495 fmt
= (ctx
->opcode
>> 10) & 0x3;
10498 gen_cmp_s(ctx
, cond
, rt
, rs
, cc
);
10501 gen_cmp_d(ctx
, cond
, rt
, rs
, cc
);
10504 gen_cmp_ps(ctx
, cond
, rt
, rs
, cc
);
10507 goto pool32f_invalid
;
10511 gen_pool32fxf(env
, ctx
, rt
, rs
);
10515 switch ((ctx
->opcode
>> 6) & 0x7) {
10517 mips32_op
= OPC_PLL_PS
;
10520 mips32_op
= OPC_PLU_PS
;
10523 mips32_op
= OPC_PUL_PS
;
10526 mips32_op
= OPC_PUU_PS
;
10529 mips32_op
= OPC_CVT_PS_S
;
10531 gen_farith(ctx
, mips32_op
, rt
, rs
, rd
, 0);
10534 goto pool32f_invalid
;
10539 switch ((ctx
->opcode
>> 6) & 0x7) {
10541 mips32_op
= OPC_LWXC1
;
10544 mips32_op
= OPC_SWXC1
;
10547 mips32_op
= OPC_LDXC1
;
10550 mips32_op
= OPC_SDXC1
;
10553 mips32_op
= OPC_LUXC1
;
10556 mips32_op
= OPC_SUXC1
;
10558 gen_flt3_ldst(ctx
, mips32_op
, rd
, rd
, rt
, rs
);
10561 goto pool32f_invalid
;
10566 fmt
= (ctx
->opcode
>> 9) & 0x3;
10567 switch ((ctx
->opcode
>> 6) & 0x7) {
10571 mips32_op
= OPC_RSQRT2_S
;
10574 mips32_op
= OPC_RSQRT2_D
;
10577 mips32_op
= OPC_RSQRT2_PS
;
10580 goto pool32f_invalid
;
10586 mips32_op
= OPC_RECIP2_S
;
10589 mips32_op
= OPC_RECIP2_D
;
10592 mips32_op
= OPC_RECIP2_PS
;
10595 goto pool32f_invalid
;
10599 mips32_op
= OPC_ADDR_PS
;
10602 mips32_op
= OPC_MULR_PS
;
10604 gen_farith(ctx
, mips32_op
, rt
, rs
, rd
, 0);
10607 goto pool32f_invalid
;
10611 /* MOV[FT].fmt and PREFX */
10612 cc
= (ctx
->opcode
>> 13) & 0x7;
10613 fmt
= (ctx
->opcode
>> 9) & 0x3;
10614 switch ((ctx
->opcode
>> 6) & 0x7) {
10618 gen_movcf_s(rs
, rt
, cc
, 0);
10621 gen_movcf_d(ctx
, rs
, rt
, cc
, 0);
10624 gen_movcf_ps(rs
, rt
, cc
, 0);
10627 goto pool32f_invalid
;
10633 gen_movcf_s(rs
, rt
, cc
, 1);
10636 gen_movcf_d(ctx
, rs
, rt
, cc
, 1);
10639 gen_movcf_ps(rs
, rt
, cc
, 1);
10642 goto pool32f_invalid
;
10648 goto pool32f_invalid
;
10651 #define FINSN_3ARG_SDPS(prfx) \
10652 switch ((ctx->opcode >> 8) & 0x3) { \
10654 mips32_op = OPC_##prfx##_S; \
10657 mips32_op = OPC_##prfx##_D; \
10659 case FMT_SDPS_PS: \
10660 mips32_op = OPC_##prfx##_PS; \
10663 goto pool32f_invalid; \
10666 /* regular FP ops */
10667 switch ((ctx
->opcode
>> 6) & 0x3) {
10669 FINSN_3ARG_SDPS(ADD
);
10672 FINSN_3ARG_SDPS(SUB
);
10675 FINSN_3ARG_SDPS(MUL
);
10678 fmt
= (ctx
->opcode
>> 8) & 0x3;
10680 mips32_op
= OPC_DIV_D
;
10681 } else if (fmt
== 0) {
10682 mips32_op
= OPC_DIV_S
;
10684 goto pool32f_invalid
;
10688 goto pool32f_invalid
;
10693 switch ((ctx
->opcode
>> 6) & 0x3) {
10695 FINSN_3ARG_SDPS(MOVN
);
10698 FINSN_3ARG_SDPS(MOVZ
);
10701 goto pool32f_invalid
;
10705 gen_farith(ctx
, mips32_op
, rt
, rs
, rd
, 0);
10709 MIPS_INVAL("pool32f");
10710 generate_exception(ctx
, EXCP_RI
);
10714 generate_exception_err(ctx
, EXCP_CpU
, 1);
10718 minor
= (ctx
->opcode
>> 21) & 0x1f;
10721 mips32_op
= OPC_BLTZ
;
10724 mips32_op
= OPC_BLTZAL
;
10727 mips32_op
= OPC_BLTZALS
;
10730 mips32_op
= OPC_BGEZ
;
10733 mips32_op
= OPC_BGEZAL
;
10736 mips32_op
= OPC_BGEZALS
;
10739 mips32_op
= OPC_BLEZ
;
10742 mips32_op
= OPC_BGTZ
;
10744 gen_compute_branch(ctx
, mips32_op
, 4, rs
, -1, imm
<< 1);
10750 mips32_op
= OPC_TLTI
;
10753 mips32_op
= OPC_TGEI
;
10756 mips32_op
= OPC_TLTIU
;
10759 mips32_op
= OPC_TGEIU
;
10762 mips32_op
= OPC_TNEI
;
10765 mips32_op
= OPC_TEQI
;
10767 gen_trap(ctx
, mips32_op
, rs
, -1, imm
);
10772 gen_compute_branch(ctx
, minor
== BNEZC
? OPC_BNE
: OPC_BEQ
,
10773 4, rs
, 0, imm
<< 1);
10774 /* Compact branches don't have a delay slot, so just let
10775 the normal delay slot handling take us to the branch
10779 gen_logic_imm(env
, OPC_LUI
, rs
, -1, imm
);
10785 /* COP2: Not implemented. */
10786 generate_exception_err(ctx
, EXCP_CpU
, 2);
10789 mips32_op
= (ctx
->opcode
& (1 << 16)) ? OPC_BC1FANY2
: OPC_BC1F
;
10792 mips32_op
= (ctx
->opcode
& (1 << 16)) ? OPC_BC1TANY2
: OPC_BC1T
;
10795 mips32_op
= OPC_BC1FANY4
;
10798 mips32_op
= OPC_BC1TANY4
;
10801 check_insn(env
, ctx
, ASE_MIPS3D
);
10804 gen_compute_branch1(env
, ctx
, mips32_op
,
10805 (ctx
->opcode
>> 18) & 0x7, imm
<< 1);
10810 /* MIPS DSP: not implemented */
10813 MIPS_INVAL("pool32i");
10814 generate_exception(ctx
, EXCP_RI
);
10819 minor
= (ctx
->opcode
>> 12) & 0xf;
10822 mips32_op
= OPC_LWL
;
10825 mips32_op
= OPC_SWL
;
10828 mips32_op
= OPC_LWR
;
10831 mips32_op
= OPC_SWR
;
10833 #if defined(TARGET_MIPS64)
10835 mips32_op
= OPC_LDL
;
10838 mips32_op
= OPC_SDL
;
10841 mips32_op
= OPC_LDR
;
10844 mips32_op
= OPC_SDR
;
10847 mips32_op
= OPC_LWU
;
10850 mips32_op
= OPC_LLD
;
10854 mips32_op
= OPC_LL
;
10857 gen_ld(env
, ctx
, mips32_op
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
10860 gen_st(ctx
, mips32_op
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
10863 gen_st_cond(ctx
, OPC_SC
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
10865 #if defined(TARGET_MIPS64)
10867 gen_st_cond(ctx
, OPC_SCD
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
10871 /* Treat as no-op */
10874 MIPS_INVAL("pool32c");
10875 generate_exception(ctx
, EXCP_RI
);
10880 mips32_op
= OPC_ADDI
;
10883 mips32_op
= OPC_ADDIU
;
10885 gen_arith_imm(env
, ctx
, mips32_op
, rt
, rs
, imm
);
10888 /* Logical operations */
10890 mips32_op
= OPC_ORI
;
10893 mips32_op
= OPC_XORI
;
10896 mips32_op
= OPC_ANDI
;
10898 gen_logic_imm(env
, mips32_op
, rt
, rs
, imm
);
10901 /* Set less than immediate */
10903 mips32_op
= OPC_SLTI
;
10906 mips32_op
= OPC_SLTIU
;
10908 gen_slt_imm(env
, mips32_op
, rt
, rs
, imm
);
10911 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
10912 gen_compute_branch(ctx
, OPC_JALX
, 4, rt
, rs
, offset
);
10916 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 1;
10917 gen_compute_branch(ctx
, OPC_JALS
, 4, rt
, rs
, offset
);
10921 gen_compute_branch(ctx
, OPC_BEQ
, 4, rt
, rs
, imm
<< 1);
10925 gen_compute_branch(ctx
, OPC_BNE
, 4, rt
, rs
, imm
<< 1);
10929 gen_compute_branch(ctx
, OPC_J
, 4, rt
, rs
,
10930 (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 1);
10934 gen_compute_branch(ctx
, OPC_JAL
, 4, rt
, rs
,
10935 (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 1);
10938 /* Floating point (COP1) */
10940 mips32_op
= OPC_LWC1
;
10943 mips32_op
= OPC_LDC1
;
10946 mips32_op
= OPC_SWC1
;
10949 mips32_op
= OPC_SDC1
;
10951 gen_cop1_ldst(env
, ctx
, mips32_op
, rt
, rs
, imm
);
10955 int reg
= mmreg(ZIMM(ctx
->opcode
, 23, 3));
10956 int offset
= SIMM(ctx
->opcode
, 0, 23) << 2;
10958 gen_addiupc(ctx
, reg
, offset
, 0, 0);
10961 /* Loads and stores */
10963 mips32_op
= OPC_LB
;
10966 mips32_op
= OPC_LBU
;
10969 mips32_op
= OPC_LH
;
10972 mips32_op
= OPC_LHU
;
10975 mips32_op
= OPC_LW
;
10977 #ifdef TARGET_MIPS64
10979 mips32_op
= OPC_LD
;
10982 mips32_op
= OPC_SD
;
10986 mips32_op
= OPC_SB
;
10989 mips32_op
= OPC_SH
;
10992 mips32_op
= OPC_SW
;
10995 gen_ld(env
, ctx
, mips32_op
, rt
, rs
, imm
);
10998 gen_st(ctx
, mips32_op
, rt
, rs
, imm
);
11001 generate_exception(ctx
, EXCP_RI
);
11006 static int decode_micromips_opc (CPUState
*env
, DisasContext
*ctx
, int *is_branch
)
11010 /* make sure instructions are on a halfword boundary */
11011 if (ctx
->pc
& 0x1) {
11012 env
->CP0_BadVAddr
= ctx
->pc
;
11013 generate_exception(ctx
, EXCP_AdEL
);
11014 ctx
->bstate
= BS_STOP
;
11018 op
= (ctx
->opcode
>> 10) & 0x3f;
11019 /* Enforce properly-sized instructions in a delay slot */
11020 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
11021 int bits
= ctx
->hflags
& MIPS_HFLAG_BMASK_EXT
;
11055 case POOL48A
: /* ??? */
11060 if (bits
& MIPS_HFLAG_BDS16
) {
11061 generate_exception(ctx
, EXCP_RI
);
11062 /* Just stop translation; the user is confused. */
11063 ctx
->bstate
= BS_STOP
;
11088 if (bits
& MIPS_HFLAG_BDS32
) {
11089 generate_exception(ctx
, EXCP_RI
);
11090 /* Just stop translation; the user is confused. */
11091 ctx
->bstate
= BS_STOP
;
11102 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
11103 int rs1
= mmreg(uMIPS_RS1(ctx
->opcode
));
11104 int rs2
= mmreg(uMIPS_RS2(ctx
->opcode
));
11107 switch (ctx
->opcode
& 0x1) {
11116 gen_arith(env
, ctx
, opc
, rd
, rs1
, rs2
);
11121 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
11122 int rs
= mmreg(uMIPS_RS(ctx
->opcode
));
11123 int amount
= (ctx
->opcode
>> 1) & 0x7;
11125 amount
= amount
== 0 ? 8 : amount
;
11127 switch (ctx
->opcode
& 0x1) {
11136 gen_shift_imm(env
, ctx
, opc
, rd
, rs
, amount
);
11140 gen_pool16c_insn(env
, ctx
, is_branch
);
11144 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
11145 int rb
= 28; /* GP */
11146 int16_t offset
= SIMM(ctx
->opcode
, 0, 7) << 2;
11148 gen_ld(env
, ctx
, OPC_LW
, rd
, rb
, offset
);
11152 if (ctx
->opcode
& 1) {
11153 generate_exception(ctx
, EXCP_RI
);
11156 int enc_dest
= uMIPS_RD(ctx
->opcode
);
11157 int enc_rt
= uMIPS_RS2(ctx
->opcode
);
11158 int enc_rs
= uMIPS_RS1(ctx
->opcode
);
11159 int rd
, rs
, re
, rt
;
11160 static const int rd_enc
[] = { 5, 5, 6, 4, 4, 4, 4, 4 };
11161 static const int re_enc
[] = { 6, 7, 7, 21, 22, 5, 6, 7 };
11162 static const int rs_rt_enc
[] = { 0, 17, 2, 3, 16, 18, 19, 20 };
11164 rd
= rd_enc
[enc_dest
];
11165 re
= re_enc
[enc_dest
];
11166 rs
= rs_rt_enc
[enc_rs
];
11167 rt
= rs_rt_enc
[enc_rt
];
11169 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rd
, rs
, 0);
11170 gen_arith_imm(env
, ctx
, OPC_ADDIU
, re
, rt
, 0);
11175 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
11176 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
11177 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4);
11178 offset
= (offset
== 0xf ? -1 : offset
);
11180 gen_ld(env
, ctx
, OPC_LBU
, rd
, rb
, offset
);
11185 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
11186 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
11187 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 1;
11189 gen_ld(env
, ctx
, OPC_LHU
, rd
, rb
, offset
);
11194 int rd
= (ctx
->opcode
>> 5) & 0x1f;
11195 int rb
= 29; /* SP */
11196 int16_t offset
= ZIMM(ctx
->opcode
, 0, 5) << 2;
11198 gen_ld(env
, ctx
, OPC_LW
, rd
, rb
, offset
);
11203 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
11204 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
11205 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 2;
11207 gen_ld(env
, ctx
, OPC_LW
, rd
, rb
, offset
);
11212 int rd
= mmreg2(uMIPS_RD(ctx
->opcode
));
11213 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
11214 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4);
11216 gen_st(ctx
, OPC_SB
, rd
, rb
, offset
);
11221 int rd
= mmreg2(uMIPS_RD(ctx
->opcode
));
11222 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
11223 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 1;
11225 gen_st(ctx
, OPC_SH
, rd
, rb
, offset
);
11230 int rd
= (ctx
->opcode
>> 5) & 0x1f;
11231 int rb
= 29; /* SP */
11232 int16_t offset
= ZIMM(ctx
->opcode
, 0, 5) << 2;
11234 gen_st(ctx
, OPC_SW
, rd
, rb
, offset
);
11239 int rd
= mmreg2(uMIPS_RD(ctx
->opcode
));
11240 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
11241 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 2;
11243 gen_st(ctx
, OPC_SW
, rd
, rb
, offset
);
11248 int rd
= uMIPS_RD5(ctx
->opcode
);
11249 int rs
= uMIPS_RS5(ctx
->opcode
);
11251 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rd
, rs
, 0);
11255 gen_andi16(env
, ctx
);
11258 switch (ctx
->opcode
& 0x1) {
11260 gen_addius5(env
, ctx
);
11263 gen_addiusp(env
, ctx
);
11268 switch (ctx
->opcode
& 0x1) {
11270 gen_addiur2(env
, ctx
);
11273 gen_addiur1sp(env
, ctx
);
11278 gen_compute_branch(ctx
, OPC_BEQ
, 2, 0, 0,
11279 SIMM(ctx
->opcode
, 0, 10) << 1);
11284 gen_compute_branch(ctx
, op
== BNEZ16
? OPC_BNE
: OPC_BEQ
, 2,
11285 mmreg(uMIPS_RD(ctx
->opcode
)),
11286 0, SIMM(ctx
->opcode
, 0, 7) << 1);
11291 int reg
= mmreg(uMIPS_RD(ctx
->opcode
));
11292 int imm
= ZIMM(ctx
->opcode
, 0, 7);
11294 imm
= (imm
== 0x7f ? -1 : imm
);
11295 tcg_gen_movi_tl(cpu_gpr
[reg
], imm
);
11305 generate_exception(ctx
, EXCP_RI
);
11308 decode_micromips32_opc (env
, ctx
, op
, is_branch
);
11315 /* SmartMIPS extension to MIPS32 */
11317 #if defined(TARGET_MIPS64)
11319 /* MDMX extension to MIPS64 */
11323 static void decode_opc (CPUState
*env
, DisasContext
*ctx
, int *is_branch
)
11326 int rs
, rt
, rd
, sa
;
11327 uint32_t op
, op1
, op2
;
11330 /* make sure instructions are on a word boundary */
11331 if (ctx
->pc
& 0x3) {
11332 env
->CP0_BadVAddr
= ctx
->pc
;
11333 generate_exception(ctx
, EXCP_AdEL
);
11337 /* Handle blikely not taken case */
11338 if ((ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) == MIPS_HFLAG_BL
) {
11339 int l1
= gen_new_label();
11341 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
11342 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
11343 tcg_gen_movi_i32(hflags
, ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
11344 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
11348 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)))
11349 tcg_gen_debug_insn_start(ctx
->pc
);
11351 op
= MASK_OP_MAJOR(ctx
->opcode
);
11352 rs
= (ctx
->opcode
>> 21) & 0x1f;
11353 rt
= (ctx
->opcode
>> 16) & 0x1f;
11354 rd
= (ctx
->opcode
>> 11) & 0x1f;
11355 sa
= (ctx
->opcode
>> 6) & 0x1f;
11356 imm
= (int16_t)ctx
->opcode
;
11359 op1
= MASK_SPECIAL(ctx
->opcode
);
11361 case OPC_SLL
: /* Shift with immediate */
11363 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
11366 switch ((ctx
->opcode
>> 21) & 0x1f) {
11368 /* rotr is decoded as srl on non-R2 CPUs */
11369 if (env
->insn_flags
& ISA_MIPS32R2
) {
11374 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
11377 generate_exception(ctx
, EXCP_RI
);
11381 case OPC_MOVN
: /* Conditional move */
11383 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
|
11384 INSN_LOONGSON2E
| INSN_LOONGSON2F
);
11385 gen_cond_move(env
, op1
, rd
, rs
, rt
);
11387 case OPC_ADD
... OPC_SUBU
:
11388 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
11390 case OPC_SLLV
: /* Shifts */
11392 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
11395 switch ((ctx
->opcode
>> 6) & 0x1f) {
11397 /* rotrv is decoded as srlv on non-R2 CPUs */
11398 if (env
->insn_flags
& ISA_MIPS32R2
) {
11403 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
11406 generate_exception(ctx
, EXCP_RI
);
11410 case OPC_SLT
: /* Set on less than */
11412 gen_slt(env
, op1
, rd
, rs
, rt
);
11414 case OPC_AND
: /* Logic*/
11418 gen_logic(env
, op1
, rd
, rs
, rt
);
11420 case OPC_MULT
... OPC_DIVU
:
11422 check_insn(env
, ctx
, INSN_VR54XX
);
11423 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
11424 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
11426 gen_muldiv(ctx
, op1
, rs
, rt
);
11428 case OPC_JR
... OPC_JALR
:
11429 gen_compute_branch(ctx
, op1
, 4, rs
, rd
, sa
);
11432 case OPC_TGE
... OPC_TEQ
: /* Traps */
11434 gen_trap(ctx
, op1
, rs
, rt
, -1);
11436 case OPC_MFHI
: /* Move from HI/LO */
11438 gen_HILO(ctx
, op1
, rd
);
11441 case OPC_MTLO
: /* Move to HI/LO */
11442 gen_HILO(ctx
, op1
, rs
);
11444 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
11445 #ifdef MIPS_STRICT_STANDARD
11446 MIPS_INVAL("PMON / selsl");
11447 generate_exception(ctx
, EXCP_RI
);
11449 gen_helper_0i(pmon
, sa
);
11453 generate_exception(ctx
, EXCP_SYSCALL
);
11454 ctx
->bstate
= BS_STOP
;
11457 generate_exception(ctx
, EXCP_BREAK
);
11460 #ifdef MIPS_STRICT_STANDARD
11461 MIPS_INVAL("SPIM");
11462 generate_exception(ctx
, EXCP_RI
);
11464 /* Implemented as RI exception for now. */
11465 MIPS_INVAL("spim (unofficial)");
11466 generate_exception(ctx
, EXCP_RI
);
11470 /* Treat as NOP. */
11474 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
11475 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
11476 check_cp1_enabled(ctx
);
11477 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
11478 (ctx
->opcode
>> 16) & 1);
11480 generate_exception_err(ctx
, EXCP_CpU
, 1);
11484 #if defined(TARGET_MIPS64)
11485 /* MIPS64 specific opcodes */
11490 check_insn(env
, ctx
, ISA_MIPS3
);
11491 check_mips_64(ctx
);
11492 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
11495 switch ((ctx
->opcode
>> 21) & 0x1f) {
11497 /* drotr is decoded as dsrl on non-R2 CPUs */
11498 if (env
->insn_flags
& ISA_MIPS32R2
) {
11503 check_insn(env
, ctx
, ISA_MIPS3
);
11504 check_mips_64(ctx
);
11505 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
11508 generate_exception(ctx
, EXCP_RI
);
11513 switch ((ctx
->opcode
>> 21) & 0x1f) {
11515 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
11516 if (env
->insn_flags
& ISA_MIPS32R2
) {
11521 check_insn(env
, ctx
, ISA_MIPS3
);
11522 check_mips_64(ctx
);
11523 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
11526 generate_exception(ctx
, EXCP_RI
);
11530 case OPC_DADD
... OPC_DSUBU
:
11531 check_insn(env
, ctx
, ISA_MIPS3
);
11532 check_mips_64(ctx
);
11533 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
11537 check_insn(env
, ctx
, ISA_MIPS3
);
11538 check_mips_64(ctx
);
11539 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
11542 switch ((ctx
->opcode
>> 6) & 0x1f) {
11544 /* drotrv is decoded as dsrlv on non-R2 CPUs */
11545 if (env
->insn_flags
& ISA_MIPS32R2
) {
11550 check_insn(env
, ctx
, ISA_MIPS3
);
11551 check_mips_64(ctx
);
11552 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
11555 generate_exception(ctx
, EXCP_RI
);
11559 case OPC_DMULT
... OPC_DDIVU
:
11560 check_insn(env
, ctx
, ISA_MIPS3
);
11561 check_mips_64(ctx
);
11562 gen_muldiv(ctx
, op1
, rs
, rt
);
11565 default: /* Invalid */
11566 MIPS_INVAL("special");
11567 generate_exception(ctx
, EXCP_RI
);
11572 op1
= MASK_SPECIAL2(ctx
->opcode
);
11574 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
11575 case OPC_MSUB
... OPC_MSUBU
:
11576 check_insn(env
, ctx
, ISA_MIPS32
);
11577 gen_muldiv(ctx
, op1
, rs
, rt
);
11580 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
11584 check_insn(env
, ctx
, ISA_MIPS32
);
11585 gen_cl(ctx
, op1
, rd
, rs
);
11588 /* XXX: not clear which exception should be raised
11589 * when in debug mode...
11591 check_insn(env
, ctx
, ISA_MIPS32
);
11592 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
11593 generate_exception(ctx
, EXCP_DBp
);
11595 generate_exception(ctx
, EXCP_DBp
);
11597 /* Treat as NOP. */
11599 #if defined(TARGET_MIPS64)
11602 check_insn(env
, ctx
, ISA_MIPS64
);
11603 check_mips_64(ctx
);
11604 gen_cl(ctx
, op1
, rd
, rs
);
11607 default: /* Invalid */
11608 MIPS_INVAL("special2");
11609 generate_exception(ctx
, EXCP_RI
);
11614 op1
= MASK_SPECIAL3(ctx
->opcode
);
11618 check_insn(env
, ctx
, ISA_MIPS32R2
);
11619 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
11622 check_insn(env
, ctx
, ISA_MIPS32R2
);
11623 op2
= MASK_BSHFL(ctx
->opcode
);
11624 gen_bshfl(ctx
, op2
, rt
, rd
);
11627 gen_rdhwr(env
, ctx
, rt
, rd
);
11630 check_insn(env
, ctx
, ASE_MT
);
11632 TCGv t0
= tcg_temp_new();
11633 TCGv t1
= tcg_temp_new();
11635 gen_load_gpr(t0
, rt
);
11636 gen_load_gpr(t1
, rs
);
11637 gen_helper_fork(t0
, t1
);
11643 check_insn(env
, ctx
, ASE_MT
);
11645 TCGv t0
= tcg_temp_new();
11647 save_cpu_state(ctx
, 1);
11648 gen_load_gpr(t0
, rs
);
11649 gen_helper_yield(t0
, t0
);
11650 gen_store_gpr(t0
, rd
);
11654 #if defined(TARGET_MIPS64)
11655 case OPC_DEXTM
... OPC_DEXT
:
11656 case OPC_DINSM
... OPC_DINS
:
11657 check_insn(env
, ctx
, ISA_MIPS64R2
);
11658 check_mips_64(ctx
);
11659 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
11662 check_insn(env
, ctx
, ISA_MIPS64R2
);
11663 check_mips_64(ctx
);
11664 op2
= MASK_DBSHFL(ctx
->opcode
);
11665 gen_bshfl(ctx
, op2
, rt
, rd
);
11668 default: /* Invalid */
11669 MIPS_INVAL("special3");
11670 generate_exception(ctx
, EXCP_RI
);
11675 op1
= MASK_REGIMM(ctx
->opcode
);
11677 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
11678 case OPC_BLTZAL
... OPC_BGEZALL
:
11679 gen_compute_branch(ctx
, op1
, 4, rs
, -1, imm
<< 2);
11682 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
11684 gen_trap(ctx
, op1
, rs
, -1, imm
);
11687 check_insn(env
, ctx
, ISA_MIPS32R2
);
11688 /* Treat as NOP. */
11690 default: /* Invalid */
11691 MIPS_INVAL("regimm");
11692 generate_exception(ctx
, EXCP_RI
);
11697 check_cp0_enabled(ctx
);
11698 op1
= MASK_CP0(ctx
->opcode
);
11704 #if defined(TARGET_MIPS64)
11708 #ifndef CONFIG_USER_ONLY
11709 gen_cp0(env
, ctx
, op1
, rt
, rd
);
11710 #endif /* !CONFIG_USER_ONLY */
11712 case OPC_C0_FIRST
... OPC_C0_LAST
:
11713 #ifndef CONFIG_USER_ONLY
11714 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
11715 #endif /* !CONFIG_USER_ONLY */
11718 #ifndef CONFIG_USER_ONLY
11720 TCGv t0
= tcg_temp_new();
11722 op2
= MASK_MFMC0(ctx
->opcode
);
11725 check_insn(env
, ctx
, ASE_MT
);
11726 gen_helper_dmt(t0
, t0
);
11727 gen_store_gpr(t0
, rt
);
11730 check_insn(env
, ctx
, ASE_MT
);
11731 gen_helper_emt(t0
, t0
);
11732 gen_store_gpr(t0
, rt
);
11735 check_insn(env
, ctx
, ASE_MT
);
11736 gen_helper_dvpe(t0
, t0
);
11737 gen_store_gpr(t0
, rt
);
11740 check_insn(env
, ctx
, ASE_MT
);
11741 gen_helper_evpe(t0
, t0
);
11742 gen_store_gpr(t0
, rt
);
11745 check_insn(env
, ctx
, ISA_MIPS32R2
);
11746 save_cpu_state(ctx
, 1);
11748 gen_store_gpr(t0
, rt
);
11749 /* Stop translation as we may have switched the execution mode */
11750 ctx
->bstate
= BS_STOP
;
11753 check_insn(env
, ctx
, ISA_MIPS32R2
);
11754 save_cpu_state(ctx
, 1);
11756 gen_store_gpr(t0
, rt
);
11757 /* Stop translation as we may have switched the execution mode */
11758 ctx
->bstate
= BS_STOP
;
11760 default: /* Invalid */
11761 MIPS_INVAL("mfmc0");
11762 generate_exception(ctx
, EXCP_RI
);
11767 #endif /* !CONFIG_USER_ONLY */
11770 check_insn(env
, ctx
, ISA_MIPS32R2
);
11771 gen_load_srsgpr(rt
, rd
);
11774 check_insn(env
, ctx
, ISA_MIPS32R2
);
11775 gen_store_srsgpr(rt
, rd
);
11779 generate_exception(ctx
, EXCP_RI
);
11783 case OPC_ADDI
: /* Arithmetic with immediate opcode */
11785 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
11787 case OPC_SLTI
: /* Set on less than with immediate opcode */
11789 gen_slt_imm(env
, op
, rt
, rs
, imm
);
11791 case OPC_ANDI
: /* Arithmetic with immediate opcode */
11795 gen_logic_imm(env
, op
, rt
, rs
, imm
);
11797 case OPC_J
... OPC_JAL
: /* Jump */
11798 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
11799 gen_compute_branch(ctx
, op
, 4, rs
, rt
, offset
);
11802 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
11803 case OPC_BEQL
... OPC_BGTZL
:
11804 gen_compute_branch(ctx
, op
, 4, rs
, rt
, imm
<< 2);
11807 case OPC_LB
... OPC_LWR
: /* Load and stores */
11809 gen_ld(env
, ctx
, op
, rt
, rs
, imm
);
11811 case OPC_SB
... OPC_SW
:
11813 gen_st(ctx
, op
, rt
, rs
, imm
);
11816 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
11819 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
11820 /* Treat as NOP. */
11823 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
11824 /* Treat as NOP. */
11827 /* Floating point (COP1). */
11832 gen_cop1_ldst(env
, ctx
, op
, rt
, rs
, imm
);
11836 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
11837 check_cp1_enabled(ctx
);
11838 op1
= MASK_CP1(ctx
->opcode
);
11842 check_insn(env
, ctx
, ISA_MIPS32R2
);
11847 gen_cp1(ctx
, op1
, rt
, rd
);
11849 #if defined(TARGET_MIPS64)
11852 check_insn(env
, ctx
, ISA_MIPS3
);
11853 gen_cp1(ctx
, op1
, rt
, rd
);
11859 check_insn(env
, ctx
, ASE_MIPS3D
);
11862 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
11863 (rt
>> 2) & 0x7, imm
<< 2);
11871 gen_farith(ctx
, ctx
->opcode
& FOP(0x3f, 0x1f), rt
, rd
, sa
,
11876 generate_exception (ctx
, EXCP_RI
);
11880 generate_exception_err(ctx
, EXCP_CpU
, 1);
11890 /* COP2: Not implemented. */
11891 generate_exception_err(ctx
, EXCP_CpU
, 2);
11895 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
11896 check_cp1_enabled(ctx
);
11897 op1
= MASK_CP3(ctx
->opcode
);
11905 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
11908 /* Treat as NOP. */
11923 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
11927 generate_exception (ctx
, EXCP_RI
);
11931 generate_exception_err(ctx
, EXCP_CpU
, 1);
11935 #if defined(TARGET_MIPS64)
11936 /* MIPS64 opcodes */
11938 case OPC_LDL
... OPC_LDR
:
11941 check_insn(env
, ctx
, ISA_MIPS3
);
11942 check_mips_64(ctx
);
11943 gen_ld(env
, ctx
, op
, rt
, rs
, imm
);
11945 case OPC_SDL
... OPC_SDR
:
11947 check_insn(env
, ctx
, ISA_MIPS3
);
11948 check_mips_64(ctx
);
11949 gen_st(ctx
, op
, rt
, rs
, imm
);
11952 check_insn(env
, ctx
, ISA_MIPS3
);
11953 check_mips_64(ctx
);
11954 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
11958 check_insn(env
, ctx
, ISA_MIPS3
);
11959 check_mips_64(ctx
);
11960 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
11964 check_insn(env
, ctx
, ASE_MIPS16
| ASE_MICROMIPS
);
11965 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
11966 gen_compute_branch(ctx
, op
, 4, rs
, rt
, offset
);
11970 check_insn(env
, ctx
, ASE_MDMX
);
11971 /* MDMX: Not implemented. */
11972 default: /* Invalid */
11973 MIPS_INVAL("major opcode");
11974 generate_exception(ctx
, EXCP_RI
);
11980 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
11984 target_ulong pc_start
;
11985 uint16_t *gen_opc_end
;
11994 qemu_log("search pc %d\n", search_pc
);
11997 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
12000 ctx
.singlestep_enabled
= env
->singlestep_enabled
;
12002 ctx
.bstate
= BS_NONE
;
12003 /* Restore delay slot state from the tb context. */
12004 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
12005 restore_cpu_state(env
, &ctx
);
12006 #ifdef CONFIG_USER_ONLY
12007 ctx
.mem_idx
= MIPS_HFLAG_UM
;
12009 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
12012 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
12013 if (max_insns
== 0)
12014 max_insns
= CF_COUNT_MASK
;
12015 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb
, ctx
.mem_idx
, ctx
.hflags
);
12016 gen_icount_start();
12017 while (ctx
.bstate
== BS_NONE
) {
12018 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
12019 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
12020 if (bp
->pc
== ctx
.pc
) {
12021 save_cpu_state(&ctx
, 1);
12022 ctx
.bstate
= BS_BRANCH
;
12023 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
12024 /* Include the breakpoint location or the tb won't
12025 * be flushed when it must be. */
12027 goto done_generating
;
12033 j
= gen_opc_ptr
- gen_opc_buf
;
12037 gen_opc_instr_start
[lj
++] = 0;
12039 gen_opc_pc
[lj
] = ctx
.pc
;
12040 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
12041 gen_opc_instr_start
[lj
] = 1;
12042 gen_opc_icount
[lj
] = num_insns
;
12044 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
12048 if (!(ctx
.hflags
& MIPS_HFLAG_M16
)) {
12049 ctx
.opcode
= ldl_code(ctx
.pc
);
12051 decode_opc(env
, &ctx
, &is_branch
);
12052 } else if (env
->insn_flags
& ASE_MICROMIPS
) {
12053 ctx
.opcode
= lduw_code(ctx
.pc
);
12054 insn_bytes
= decode_micromips_opc(env
, &ctx
, &is_branch
);
12055 } else if (env
->insn_flags
& ASE_MIPS16
) {
12056 ctx
.opcode
= lduw_code(ctx
.pc
);
12057 insn_bytes
= decode_mips16_opc(env
, &ctx
, &is_branch
);
12059 generate_exception(&ctx
, EXCP_RI
);
12060 ctx
.bstate
= BS_STOP
;
12064 handle_delay_slot(env
, &ctx
, insn_bytes
);
12066 ctx
.pc
+= insn_bytes
;
12070 /* Execute a branch and its delay slot as a single instruction.
12071 This is what GDB expects and is consistent with what the
12072 hardware does (e.g. if a delay slot instruction faults, the
12073 reported PC is the PC of the branch). */
12074 if (env
->singlestep_enabled
&& (ctx
.hflags
& MIPS_HFLAG_BMASK
) == 0)
12077 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
12080 if (gen_opc_ptr
>= gen_opc_end
)
12083 if (num_insns
>= max_insns
)
12089 if (tb
->cflags
& CF_LAST_IO
)
12091 if (env
->singlestep_enabled
&& ctx
.bstate
!= BS_BRANCH
) {
12092 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
12093 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
12095 switch (ctx
.bstate
) {
12097 gen_helper_interrupt_restart();
12098 gen_goto_tb(&ctx
, 0, ctx
.pc
);
12101 save_cpu_state(&ctx
, 0);
12102 gen_goto_tb(&ctx
, 0, ctx
.pc
);
12105 gen_helper_interrupt_restart();
12106 tcg_gen_exit_tb(0);
12114 gen_icount_end(tb
, num_insns
);
12115 *gen_opc_ptr
= INDEX_op_end
;
12117 j
= gen_opc_ptr
- gen_opc_buf
;
12120 gen_opc_instr_start
[lj
++] = 0;
12122 tb
->size
= ctx
.pc
- pc_start
;
12123 tb
->icount
= num_insns
;
12127 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
12128 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
12129 log_target_disas(pc_start
, ctx
.pc
- pc_start
, 0);
12135 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
12137 gen_intermediate_code_internal(env
, tb
, 0);
12140 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
12142 gen_intermediate_code_internal(env
, tb
, 1);
12145 static void fpu_dump_state(CPUState
*env
, FILE *f
,
12146 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
12150 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
12152 #define printfpr(fp) \
12155 fpu_fprintf(f, "w:%08x d:%016" PRIx64 \
12156 " fd:%13g fs:%13g psu: %13g\n", \
12157 (fp)->w[FP_ENDIAN_IDX], (fp)->d, \
12158 (double)(fp)->fd, \
12159 (double)(fp)->fs[FP_ENDIAN_IDX], \
12160 (double)(fp)->fs[!FP_ENDIAN_IDX]); \
12163 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
12164 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
12165 fpu_fprintf(f, "w:%08x d:%016" PRIx64 \
12166 " fd:%13g fs:%13g psu:%13g\n", \
12167 tmp.w[FP_ENDIAN_IDX], tmp.d, \
12169 (double)tmp.fs[FP_ENDIAN_IDX], \
12170 (double)tmp.fs[!FP_ENDIAN_IDX]); \
12175 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
12176 env
->active_fpu
.fcr0
, env
->active_fpu
.fcr31
, is_fpu64
, env
->active_fpu
.fp_status
,
12177 get_float_exception_flags(&env
->active_fpu
.fp_status
));
12178 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
12179 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
12180 printfpr(&env
->active_fpu
.fpr
[i
]);
12186 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
12187 /* Debug help: The architecture requires 32bit code to maintain proper
12188 sign-extended values on 64bit machines. */
12190 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
12193 cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
12194 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
12199 if (!SIGN_EXT_P(env
->active_tc
.PC
))
12200 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->active_tc
.PC
);
12201 if (!SIGN_EXT_P(env
->active_tc
.HI
[0]))
12202 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->active_tc
.HI
[0]);
12203 if (!SIGN_EXT_P(env
->active_tc
.LO
[0]))
12204 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->active_tc
.LO
[0]);
12205 if (!SIGN_EXT_P(env
->btarget
))
12206 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
12208 for (i
= 0; i
< 32; i
++) {
12209 if (!SIGN_EXT_P(env
->active_tc
.gpr
[i
]))
12210 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->active_tc
.gpr
[i
]);
12213 if (!SIGN_EXT_P(env
->CP0_EPC
))
12214 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
12215 if (!SIGN_EXT_P(env
->lladdr
))
12216 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->lladdr
);
12220 void cpu_dump_state (CPUState
*env
, FILE *f
,
12221 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
12226 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
12227 " LO=0x" TARGET_FMT_lx
" ds %04x "
12228 TARGET_FMT_lx
" " TARGET_FMT_ld
"\n",
12229 env
->active_tc
.PC
, env
->active_tc
.HI
[0], env
->active_tc
.LO
[0],
12230 env
->hflags
, env
->btarget
, env
->bcond
);
12231 for (i
= 0; i
< 32; i
++) {
12233 cpu_fprintf(f
, "GPR%02d:", i
);
12234 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->active_tc
.gpr
[i
]);
12236 cpu_fprintf(f
, "\n");
12239 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
12240 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
12241 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
12242 env
->CP0_Config0
, env
->CP0_Config1
, env
->lladdr
);
12243 if (env
->hflags
& MIPS_HFLAG_FPU
)
12244 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
12245 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
12246 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
12250 static void mips_tcg_init(void)
12255 /* Initialize various static tables. */
12259 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
12260 TCGV_UNUSED(cpu_gpr
[0]);
12261 for (i
= 1; i
< 32; i
++)
12262 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
12263 offsetof(CPUState
, active_tc
.gpr
[i
]),
12265 cpu_PC
= tcg_global_mem_new(TCG_AREG0
,
12266 offsetof(CPUState
, active_tc
.PC
), "PC");
12267 for (i
= 0; i
< MIPS_DSP_ACC
; i
++) {
12268 cpu_HI
[i
] = tcg_global_mem_new(TCG_AREG0
,
12269 offsetof(CPUState
, active_tc
.HI
[i
]),
12271 cpu_LO
[i
] = tcg_global_mem_new(TCG_AREG0
,
12272 offsetof(CPUState
, active_tc
.LO
[i
]),
12274 cpu_ACX
[i
] = tcg_global_mem_new(TCG_AREG0
,
12275 offsetof(CPUState
, active_tc
.ACX
[i
]),
12278 cpu_dspctrl
= tcg_global_mem_new(TCG_AREG0
,
12279 offsetof(CPUState
, active_tc
.DSPControl
),
12281 bcond
= tcg_global_mem_new(TCG_AREG0
,
12282 offsetof(CPUState
, bcond
), "bcond");
12283 btarget
= tcg_global_mem_new(TCG_AREG0
,
12284 offsetof(CPUState
, btarget
), "btarget");
12285 hflags
= tcg_global_mem_new_i32(TCG_AREG0
,
12286 offsetof(CPUState
, hflags
), "hflags");
12288 fpu_fcr0
= tcg_global_mem_new_i32(TCG_AREG0
,
12289 offsetof(CPUState
, active_fpu
.fcr0
),
12291 fpu_fcr31
= tcg_global_mem_new_i32(TCG_AREG0
,
12292 offsetof(CPUState
, active_fpu
.fcr31
),
12295 /* register helpers */
12296 #define GEN_HELPER 2
12297 #include "helper.h"
12302 #include "translate_init.c"
12304 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
12307 const mips_def_t
*def
;
12309 def
= cpu_mips_find_by_name(cpu_model
);
12312 env
= qemu_mallocz(sizeof(CPUMIPSState
));
12313 env
->cpu_model
= def
;
12314 env
->cpu_model_str
= cpu_model
;
12316 cpu_exec_init(env
);
12317 #ifndef CONFIG_USER_ONLY
12318 mmu_init(env
, def
);
12320 fpu_init(env
, def
);
12321 mvp_init(env
, def
);
12324 qemu_init_vcpu(env
);
12328 void cpu_reset (CPUMIPSState
*env
)
12330 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
12331 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
12332 log_cpu_state(env
, 0);
12335 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
12338 /* Reset registers to their default values */
12339 env
->CP0_PRid
= env
->cpu_model
->CP0_PRid
;
12340 env
->CP0_Config0
= env
->cpu_model
->CP0_Config0
;
12341 #ifdef TARGET_WORDS_BIGENDIAN
12342 env
->CP0_Config0
|= (1 << CP0C0_BE
);
12344 env
->CP0_Config1
= env
->cpu_model
->CP0_Config1
;
12345 env
->CP0_Config2
= env
->cpu_model
->CP0_Config2
;
12346 env
->CP0_Config3
= env
->cpu_model
->CP0_Config3
;
12347 env
->CP0_Config6
= env
->cpu_model
->CP0_Config6
;
12348 env
->CP0_Config7
= env
->cpu_model
->CP0_Config7
;
12349 env
->CP0_LLAddr_rw_bitmask
= env
->cpu_model
->CP0_LLAddr_rw_bitmask
12350 << env
->cpu_model
->CP0_LLAddr_shift
;
12351 env
->CP0_LLAddr_shift
= env
->cpu_model
->CP0_LLAddr_shift
;
12352 env
->SYNCI_Step
= env
->cpu_model
->SYNCI_Step
;
12353 env
->CCRes
= env
->cpu_model
->CCRes
;
12354 env
->CP0_Status_rw_bitmask
= env
->cpu_model
->CP0_Status_rw_bitmask
;
12355 env
->CP0_TCStatus_rw_bitmask
= env
->cpu_model
->CP0_TCStatus_rw_bitmask
;
12356 env
->CP0_SRSCtl
= env
->cpu_model
->CP0_SRSCtl
;
12357 env
->current_tc
= 0;
12358 env
->SEGBITS
= env
->cpu_model
->SEGBITS
;
12359 env
->SEGMask
= (target_ulong
)((1ULL << env
->cpu_model
->SEGBITS
) - 1);
12360 #if defined(TARGET_MIPS64)
12361 if (env
->cpu_model
->insn_flags
& ISA_MIPS3
) {
12362 env
->SEGMask
|= 3ULL << 62;
12365 env
->PABITS
= env
->cpu_model
->PABITS
;
12366 env
->PAMask
= (target_ulong
)((1ULL << env
->cpu_model
->PABITS
) - 1);
12367 env
->CP0_SRSConf0_rw_bitmask
= env
->cpu_model
->CP0_SRSConf0_rw_bitmask
;
12368 env
->CP0_SRSConf0
= env
->cpu_model
->CP0_SRSConf0
;
12369 env
->CP0_SRSConf1_rw_bitmask
= env
->cpu_model
->CP0_SRSConf1_rw_bitmask
;
12370 env
->CP0_SRSConf1
= env
->cpu_model
->CP0_SRSConf1
;
12371 env
->CP0_SRSConf2_rw_bitmask
= env
->cpu_model
->CP0_SRSConf2_rw_bitmask
;
12372 env
->CP0_SRSConf2
= env
->cpu_model
->CP0_SRSConf2
;
12373 env
->CP0_SRSConf3_rw_bitmask
= env
->cpu_model
->CP0_SRSConf3_rw_bitmask
;
12374 env
->CP0_SRSConf3
= env
->cpu_model
->CP0_SRSConf3
;
12375 env
->CP0_SRSConf4_rw_bitmask
= env
->cpu_model
->CP0_SRSConf4_rw_bitmask
;
12376 env
->CP0_SRSConf4
= env
->cpu_model
->CP0_SRSConf4
;
12377 env
->insn_flags
= env
->cpu_model
->insn_flags
;
12379 #if defined(CONFIG_USER_ONLY)
12380 env
->hflags
= MIPS_HFLAG_UM
;
12381 /* Enable access to the SYNCI_Step register. */
12382 env
->CP0_HWREna
|= (1 << 1);
12383 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
12384 env
->hflags
|= MIPS_HFLAG_FPU
;
12386 #ifdef TARGET_MIPS64
12387 if (env
->active_fpu
.fcr0
& (1 << FCR0_F64
)) {
12388 env
->hflags
|= MIPS_HFLAG_F64
;
12392 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
12393 /* If the exception was raised from a delay slot,
12394 come back to the jump. */
12395 env
->CP0_ErrorEPC
= env
->active_tc
.PC
- 4;
12397 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
12399 env
->active_tc
.PC
= (int32_t)0xBFC00000;
12400 env
->CP0_Random
= env
->tlb
->nb_tlb
- 1;
12401 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
12402 env
->CP0_Wired
= 0;
12403 /* SMP not implemented */
12404 env
->CP0_EBase
= 0x80000000;
12405 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
12406 /* vectored interrupts not implemented, timer on int 7,
12407 no performance counters. */
12408 env
->CP0_IntCtl
= 0xe0000000;
12412 for (i
= 0; i
< 7; i
++) {
12413 env
->CP0_WatchLo
[i
] = 0;
12414 env
->CP0_WatchHi
[i
] = 0x80000000;
12416 env
->CP0_WatchLo
[7] = 0;
12417 env
->CP0_WatchHi
[7] = 0;
12419 /* Count register increments in debug mode, EJTAG version 1 */
12420 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
12421 env
->hflags
= MIPS_HFLAG_CP0
;
12423 #if defined(TARGET_MIPS64)
12424 if (env
->cpu_model
->insn_flags
& ISA_MIPS3
) {
12425 env
->hflags
|= MIPS_HFLAG_64
;
12428 env
->exception_index
= EXCP_NONE
;
12431 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
12432 unsigned long searched_pc
, int pc_pos
, void *puc
)
12434 env
->active_tc
.PC
= gen_opc_pc
[pc_pos
];
12435 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
12436 env
->hflags
|= gen_opc_hflags
[pc_pos
];