| commit | afa88c3ae5fb6b2dce4e6221b4cf2664b05adcc5 | |
| author | Aurelien Jarno <aurelien@aurel32.net> | |
| Thu, 1 Jul 2010 21:43:34 +0000 (1 23:43 +0200) | ||
| committer | Aurelien Jarno <aurelien@aurel32.net> | |
| Thu, 1 Jul 2010 21:45:28 +0000 (1 23:45 +0200) | ||
| tree | a191ba5c025fde087f19117c09a421ddc1b9a544 | treesnapshot (tar.gz zip) |
| parent | 5c13fdfd03f5763cf7f28978762ba714e2cfeb66 | commitdiff |
target-mips: add Loongson support prefetch
Loongson CPU uses a load to zero register for prefetch.
Emulate it as a NOP.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Loongson CPU uses a load to zero register for prefetch.
Emulate it as a NOP.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| target-mips/translate.c | diffblobblamehistory |