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block_int-common.h: split function pointers in BdrvChildClass
[qemu.git] / hw / net / e1000e_core.c
blob2c51089a82516f35bf1a88cb819107251962d815
1 /*
2 * Core code for QEMU e1000e emulation
3 *
4 * Software developer's manuals:
5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
6 *
7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
8 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 *
10 * Authors:
11 * Dmitry Fleytman <dmitry@daynix.com>
12 * Leonid Bloch <leonid@daynix.com>
13 * Yan Vugenfirer <yan@daynix.com>
14 *
15 * Based on work done by:
16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
17 * Copyright (c) 2008 Qumranet
18 * Based on work done by:
19 * Copyright (c) 2007 Dan Aloni
20 * Copyright (c) 2004 Antony T Curtis
21 *
22 * This library is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU Lesser General Public
24 * License as published by the Free Software Foundation; either
25 * version 2.1 of the License, or (at your option) any later version.
26 *
27 * This library is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
30 * Lesser General Public License for more details.
31 *
32 * You should have received a copy of the GNU Lesser General Public
33 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
34 */
35
36 #include "qemu/osdep.h"
37 #include "qemu/log.h"
38 #include "net/net.h"
39 #include "net/tap.h"
40 #include "hw/pci/msi.h"
41 #include "hw/pci/msix.h"
42 #include "sysemu/runstate.h"
43
44 #include "net_tx_pkt.h"
45 #include "net_rx_pkt.h"
46
47 #include "e1000x_common.h"
48 #include "e1000e_core.h"
49
50 #include "trace.h"
51
52 #define E1000E_MIN_XITR (500) /* No more then 7813 interrupts per
53 second according to spec 10.2.4.2 */
54 #define E1000E_MAX_TX_FRAGS (64)
55
56 static inline void
57 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val);
58
59 static inline void
60 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp)
61 {
62 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) {
63 trace_e1000e_wrn_no_ts_support();
64 }
65 }
66
67 static inline void
68 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length)
69 {
70 if (cmd_and_length & E1000_TXD_CMD_SNAP) {
71 trace_e1000e_wrn_no_snap_support();
72 }
73 }
74
75 static inline void
76 e1000e_raise_legacy_irq(E1000ECore *core)
77 {
78 trace_e1000e_irq_legacy_notify(true);
79 e1000x_inc_reg_if_not_full(core->mac, IAC);
80 pci_set_irq(core->owner, 1);
81 }
82
83 static inline void
84 e1000e_lower_legacy_irq(E1000ECore *core)
85 {
86 trace_e1000e_irq_legacy_notify(false);
87 pci_set_irq(core->owner, 0);
88 }
89
90 static inline void
91 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer)
92 {
93 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] *
94 timer->delay_resolution_ns;
95
96 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
97
98 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
99
100 timer->running = true;
101 }
102
103 static void
104 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer)
105 {
106 if (timer->running) {
107 e1000e_intrmgr_rearm_timer(timer);
108 }
109 }
110
111 static void
112 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer)
113 {
114 if (timer->running) {
115 timer_del(timer->timer);
116 }
117 }
118
119 static inline void
120 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer)
121 {
122 if (timer->running) {
123 timer_del(timer->timer);
124 timer->running = false;
125 }
126 }
127
128 static inline void
129 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core)
130 {
131 trace_e1000e_irq_fire_delayed_interrupts();
132 e1000e_set_interrupt_cause(core, 0);
133 }
134
135 static void
136 e1000e_intrmgr_on_timer(void *opaque)
137 {
138 E1000IntrDelayTimer *timer = opaque;
139
140 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2);
141
142 timer->running = false;
143 e1000e_intrmgr_fire_delayed_interrupts(timer->core);
144 }
145
146 static void
147 e1000e_intrmgr_on_throttling_timer(void *opaque)
148 {
149 E1000IntrDelayTimer *timer = opaque;
150
151 assert(!msix_enabled(timer->core->owner));
152
153 timer->running = false;
154
155 if (!timer->core->itr_intr_pending) {
156 trace_e1000e_irq_throttling_no_pending_interrupts();
157 return;
158 }
159
160 if (msi_enabled(timer->core->owner)) {
161 trace_e1000e_irq_msi_notify_postponed();
162 e1000e_set_interrupt_cause(timer->core, 0);
163 } else {
164 trace_e1000e_irq_legacy_notify_postponed();
165 e1000e_set_interrupt_cause(timer->core, 0);
166 }
167 }
168
169 static void
170 e1000e_intrmgr_on_msix_throttling_timer(void *opaque)
171 {
172 E1000IntrDelayTimer *timer = opaque;
173 int idx = timer - &timer->core->eitr[0];
174
175 assert(msix_enabled(timer->core->owner));
176
177 timer->running = false;
178
179 if (!timer->core->eitr_intr_pending[idx]) {
180 trace_e1000e_irq_throttling_no_pending_vec(idx);
181 return;
182 }
183
184 trace_e1000e_irq_msix_notify_postponed_vec(idx);
185 msix_notify(timer->core->owner, idx);
186 }
187
188 static void
189 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create)
190 {
191 int i;
192
193 core->radv.delay_reg = RADV;
194 core->rdtr.delay_reg = RDTR;
195 core->raid.delay_reg = RAID;
196 core->tadv.delay_reg = TADV;
197 core->tidv.delay_reg = TIDV;
198
199 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
200 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
201 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
202 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
203 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
204
205 core->radv.core = core;
206 core->rdtr.core = core;
207 core->raid.core = core;
208 core->tadv.core = core;
209 core->tidv.core = core;
210
211 core->itr.core = core;
212 core->itr.delay_reg = ITR;
213 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
214
215 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
216 core->eitr[i].core = core;
217 core->eitr[i].delay_reg = EITR + i;
218 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
219 }
220
221 if (!create) {
222 return;
223 }
224
225 core->radv.timer =
226 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv);
227 core->rdtr.timer =
228 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr);
229 core->raid.timer =
230 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid);
231
232 core->tadv.timer =
233 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv);
234 core->tidv.timer =
235 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv);
236
237 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
238 e1000e_intrmgr_on_throttling_timer,
239 &core->itr);
240
241 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
242 core->eitr[i].timer =
243 timer_new_ns(QEMU_CLOCK_VIRTUAL,
244 e1000e_intrmgr_on_msix_throttling_timer,
245 &core->eitr[i]);
246 }
247 }
248
249 static inline void
250 e1000e_intrmgr_stop_delay_timers(E1000ECore *core)
251 {
252 e1000e_intrmgr_stop_timer(&core->radv);
253 e1000e_intrmgr_stop_timer(&core->rdtr);
254 e1000e_intrmgr_stop_timer(&core->raid);
255 e1000e_intrmgr_stop_timer(&core->tidv);
256 e1000e_intrmgr_stop_timer(&core->tadv);
257 }
258
259 static bool
260 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes)
261 {
262 uint32_t delayable_causes;
263 uint32_t rdtr = core->mac[RDTR];
264 uint32_t radv = core->mac[RADV];
265 uint32_t raid = core->mac[RAID];
266
267 if (msix_enabled(core->owner)) {
268 return false;
269 }
270
271 delayable_causes = E1000_ICR_RXQ0 |
272 E1000_ICR_RXQ1 |
273 E1000_ICR_RXT0;
274
275 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) {
276 delayable_causes |= E1000_ICR_ACK;
277 }
278
279 /* Clean up all causes that may be delayed */
280 core->delayed_causes |= *causes & delayable_causes;
281 *causes &= ~delayable_causes;
282
283 /* Check if delayed RX interrupts disabled by client
284 or if there are causes that cannot be delayed */
285 if ((rdtr == 0) || (*causes != 0)) {
286 return false;
287 }
288
289 /* Check if delayed RX ACK interrupts disabled by client
290 and there is an ACK packet received */
291 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) {
292 return false;
293 }
294
295 /* All causes delayed */
296 e1000e_intrmgr_rearm_timer(&core->rdtr);
297
298 if (!core->radv.running && (radv != 0)) {
299 e1000e_intrmgr_rearm_timer(&core->radv);
300 }
301
302 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) {
303 e1000e_intrmgr_rearm_timer(&core->raid);
304 }
305
306 return true;
307 }
308
309 static bool
310 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes)
311 {
312 static const uint32_t delayable_causes = E1000_ICR_TXQ0 |
313 E1000_ICR_TXQ1 |
314 E1000_ICR_TXQE |
315 E1000_ICR_TXDW;
316
317 if (msix_enabled(core->owner)) {
318 return false;
319 }
320
321 /* Clean up all causes that may be delayed */
322 core->delayed_causes |= *causes & delayable_causes;
323 *causes &= ~delayable_causes;
324
325 /* If there are causes that cannot be delayed */
326 if (*causes != 0) {
327 return false;
328 }
329
330 /* All causes delayed */
331 e1000e_intrmgr_rearm_timer(&core->tidv);
332
333 if (!core->tadv.running && (core->mac[TADV] != 0)) {
334 e1000e_intrmgr_rearm_timer(&core->tadv);
335 }
336
337 return true;
338 }
339
340 static uint32_t
341 e1000e_intmgr_collect_delayed_causes(E1000ECore *core)
342 {
343 uint32_t res;
344
345 if (msix_enabled(core->owner)) {
346 assert(core->delayed_causes == 0);
347 return 0;
348 }
349
350 res = core->delayed_causes;
351 core->delayed_causes = 0;
352
353 e1000e_intrmgr_stop_delay_timers(core);
354
355 return res;
356 }
357
358 static void
359 e1000e_intrmgr_fire_all_timers(E1000ECore *core)
360 {
361 int i;
362 uint32_t val = e1000e_intmgr_collect_delayed_causes(core);
363
364 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]);
365 core->mac[ICR] |= val;
366
367 if (core->itr.running) {
368 timer_del(core->itr.timer);
369 e1000e_intrmgr_on_throttling_timer(&core->itr);
370 }
371
372 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
373 if (core->eitr[i].running) {
374 timer_del(core->eitr[i].timer);
375 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]);
376 }
377 }
378 }
379
380 static void
381 e1000e_intrmgr_resume(E1000ECore *core)
382 {
383 int i;
384
385 e1000e_intmgr_timer_resume(&core->radv);
386 e1000e_intmgr_timer_resume(&core->rdtr);
387 e1000e_intmgr_timer_resume(&core->raid);
388 e1000e_intmgr_timer_resume(&core->tidv);
389 e1000e_intmgr_timer_resume(&core->tadv);
390
391 e1000e_intmgr_timer_resume(&core->itr);
392
393 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
394 e1000e_intmgr_timer_resume(&core->eitr[i]);
395 }
396 }
397
398 static void
399 e1000e_intrmgr_pause(E1000ECore *core)
400 {
401 int i;
402
403 e1000e_intmgr_timer_pause(&core->radv);
404 e1000e_intmgr_timer_pause(&core->rdtr);
405 e1000e_intmgr_timer_pause(&core->raid);
406 e1000e_intmgr_timer_pause(&core->tidv);
407 e1000e_intmgr_timer_pause(&core->tadv);
408
409 e1000e_intmgr_timer_pause(&core->itr);
410
411 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
412 e1000e_intmgr_timer_pause(&core->eitr[i]);
413 }
414 }
415
416 static void
417 e1000e_intrmgr_reset(E1000ECore *core)
418 {
419 int i;
420
421 core->delayed_causes = 0;
422
423 e1000e_intrmgr_stop_delay_timers(core);
424
425 e1000e_intrmgr_stop_timer(&core->itr);
426
427 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
428 e1000e_intrmgr_stop_timer(&core->eitr[i]);
429 }
430 }
431
432 static void
433 e1000e_intrmgr_pci_unint(E1000ECore *core)
434 {
435 int i;
436
437 timer_free(core->radv.timer);
438 timer_free(core->rdtr.timer);
439 timer_free(core->raid.timer);
440
441 timer_free(core->tadv.timer);
442 timer_free(core->tidv.timer);
443
444 timer_free(core->itr.timer);
445
446 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
447 timer_free(core->eitr[i].timer);
448 }
449 }
450
451 static void
452 e1000e_intrmgr_pci_realize(E1000ECore *core)
453 {
454 e1000e_intrmgr_initialize_all_timers(core, true);
455 }
456
457 static inline bool
458 e1000e_rx_csum_enabled(E1000ECore *core)
459 {
460 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true;
461 }
462
463 static inline bool
464 e1000e_rx_use_legacy_descriptor(E1000ECore *core)
465 {
466 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true;
467 }
468
469 static inline bool
470 e1000e_rx_use_ps_descriptor(E1000ECore *core)
471 {
472 return !e1000e_rx_use_legacy_descriptor(core) &&
473 (core->mac[RCTL] & E1000_RCTL_DTYP_PS);
474 }
475
476 static inline bool
477 e1000e_rss_enabled(E1000ECore *core)
478 {
479 return E1000_MRQC_ENABLED(core->mac[MRQC]) &&
480 !e1000e_rx_csum_enabled(core) &&
481 !e1000e_rx_use_legacy_descriptor(core);
482 }
483
484 typedef struct E1000E_RSSInfo_st {
485 bool enabled;
486 uint32_t hash;
487 uint32_t queue;
488 uint32_t type;
489 } E1000E_RSSInfo;
490
491 static uint32_t
492 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt)
493 {
494 bool isip4, isip6, isudp, istcp;
495
496 assert(e1000e_rss_enabled(core));
497
498 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
499
500 if (isip4) {
501 bool fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
502
503 trace_e1000e_rx_rss_ip4(fragment, istcp, core->mac[MRQC],
504 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]),
505 E1000_MRQC_EN_IPV4(core->mac[MRQC]));
506
507 if (!fragment && istcp && E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) {
508 return E1000_MRQ_RSS_TYPE_IPV4TCP;
509 }
510
511 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
512 return E1000_MRQ_RSS_TYPE_IPV4;
513 }
514 } else if (isip6) {
515 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt);
516
517 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS;
518 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS;
519
520 /*
521 * Following two traces must not be combined because resulting
522 * event will have 11 arguments totally and some trace backends
523 * (at least "ust") have limitation of maximum 10 arguments per
524 * event. Events with more arguments fail to compile for
525 * backends like these.
526 */
527 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]);
528 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, istcp,
529 ip6info->has_ext_hdrs,
530 ip6info->rss_ex_dst_valid,
531 ip6info->rss_ex_src_valid,
532 core->mac[MRQC],
533 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]),
534 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
535 E1000_MRQC_EN_IPV6(core->mac[MRQC]));
536
537 if ((!ex_dis || !ip6info->has_ext_hdrs) &&
538 (!new_ex_dis || !(ip6info->rss_ex_dst_valid ||
539 ip6info->rss_ex_src_valid))) {
540
541 if (istcp && !ip6info->fragment &&
542 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) {
543 return E1000_MRQ_RSS_TYPE_IPV6TCP;
544 }
545
546 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
547 return E1000_MRQ_RSS_TYPE_IPV6EX;
548 }
549
550 }
551
552 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) {
553 return E1000_MRQ_RSS_TYPE_IPV6;
554 }
555
556 }
557
558 return E1000_MRQ_RSS_TYPE_NONE;
559 }
560
561 static uint32_t
562 e1000e_rss_calc_hash(E1000ECore *core,
563 struct NetRxPkt *pkt,
564 E1000E_RSSInfo *info)
565 {
566 NetRxPktRssType type;
567
568 assert(e1000e_rss_enabled(core));
569
570 switch (info->type) {
571 case E1000_MRQ_RSS_TYPE_IPV4:
572 type = NetPktRssIpV4;
573 break;
574 case E1000_MRQ_RSS_TYPE_IPV4TCP:
575 type = NetPktRssIpV4Tcp;
576 break;
577 case E1000_MRQ_RSS_TYPE_IPV6TCP:
578 type = NetPktRssIpV6TcpEx;
579 break;
580 case E1000_MRQ_RSS_TYPE_IPV6:
581 type = NetPktRssIpV6;
582 break;
583 case E1000_MRQ_RSS_TYPE_IPV6EX:
584 type = NetPktRssIpV6Ex;
585 break;
586 default:
587 assert(false);
588 return 0;
589 }
590
591 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]);
592 }
593
594 static void
595 e1000e_rss_parse_packet(E1000ECore *core,
596 struct NetRxPkt *pkt,
597 E1000E_RSSInfo *info)
598 {
599 trace_e1000e_rx_rss_started();
600
601 if (!e1000e_rss_enabled(core)) {
602 info->enabled = false;
603 info->hash = 0;
604 info->queue = 0;
605 info->type = 0;
606 trace_e1000e_rx_rss_disabled();
607 return;
608 }
609
610 info->enabled = true;
611
612 info->type = e1000e_rss_get_hash_type(core, pkt);
613
614 trace_e1000e_rx_rss_type(info->type);
615
616 if (info->type == E1000_MRQ_RSS_TYPE_NONE) {
617 info->hash = 0;
618 info->queue = 0;
619 return;
620 }
621
622 info->hash = e1000e_rss_calc_hash(core, pkt, info);
623 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
624 }
625
626 static void
627 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx)
628 {
629 if (tx->props.tse && tx->cptse) {
630 net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss);
631 net_tx_pkt_update_ip_checksums(tx->tx_pkt);
632 e1000x_inc_reg_if_not_full(core->mac, TSCTC);
633 return;
634 }
635
636 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) {
637 net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0);
638 }
639
640 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) {
641 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
642 }
643 }
644
645 static bool
646 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index)
647 {
648 int target_queue = MIN(core->max_queue_num, queue_index);
649 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue);
650
651 e1000e_setup_tx_offloads(core, tx);
652
653 net_tx_pkt_dump(tx->tx_pkt);
654
655 if ((core->phy[0][PHY_CTRL] & MII_CR_LOOPBACK) ||
656 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) {
657 return net_tx_pkt_send_loopback(tx->tx_pkt, queue);
658 } else {
659 return net_tx_pkt_send(tx->tx_pkt, queue);
660 }
661 }
662
663 static void
664 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt)
665 {
666 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
667 PTC1023, PTC1522 };
668
669 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt);
670
671 e1000x_increase_size_stats(core->mac, PTCregs, tot_len);
672 e1000x_inc_reg_if_not_full(core->mac, TPT);
673 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len);
674
675 switch (net_tx_pkt_get_packet_type(tx_pkt)) {
676 case ETH_PKT_BCAST:
677 e1000x_inc_reg_if_not_full(core->mac, BPTC);
678 break;
679 case ETH_PKT_MCAST:
680 e1000x_inc_reg_if_not_full(core->mac, MPTC);
681 break;
682 case ETH_PKT_UCAST:
683 break;
684 default:
685 g_assert_not_reached();
686 }
687
688 core->mac[GPTC] = core->mac[TPT];
689 core->mac[GOTCL] = core->mac[TOTL];
690 core->mac[GOTCH] = core->mac[TOTH];
691 }
692
693 static void
694 e1000e_process_tx_desc(E1000ECore *core,
695 struct e1000e_tx *tx,
696 struct e1000_tx_desc *dp,
697 int queue_index)
698 {
699 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
700 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
701 unsigned int split_size = txd_lower & 0xffff;
702 uint64_t addr;
703 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
704 bool eop = txd_lower & E1000_TXD_CMD_EOP;
705
706 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
707 e1000x_read_tx_ctx_descr(xp, &tx->props);
708 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length));
709 return;
710 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
711 /* data descriptor */
712 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
713 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0;
714 e1000e_process_ts_option(core, dp);
715 } else {
716 /* legacy descriptor */
717 e1000e_process_ts_option(core, dp);
718 tx->cptse = 0;
719 }
720
721 addr = le64_to_cpu(dp->buffer_addr);
722
723 if (!tx->skip_cp) {
724 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, addr, split_size)) {
725 tx->skip_cp = true;
726 }
727 }
728
729 if (eop) {
730 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
731 if (e1000x_vlan_enabled(core->mac) &&
732 e1000x_is_vlan_txd(txd_lower)) {
733 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt,
734 le16_to_cpu(dp->upper.fields.special), core->mac[VET]);
735 }
736 if (e1000e_tx_pkt_send(core, tx, queue_index)) {
737 e1000e_on_tx_done_update_stats(core, tx->tx_pkt);
738 }
739 }
740
741 tx->skip_cp = false;
742 net_tx_pkt_reset(tx->tx_pkt);
743
744 tx->sum_needed = 0;
745 tx->cptse = 0;
746 }
747 }
748
749 static inline uint32_t
750 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx)
751 {
752 if (!msix_enabled(core->owner)) {
753 return E1000_ICR_TXDW;
754 }
755
756 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1;
757 }
758
759 static inline uint32_t
760 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx,
761 bool min_threshold_hit)
762 {
763 if (!msix_enabled(core->owner)) {
764 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0);
765 }
766
767 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1;
768 }
769
770 static uint32_t
771 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base,
772 struct e1000_tx_desc *dp, bool *ide, int queue_idx)
773 {
774 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
775
776 if (!(txd_lower & E1000_TXD_CMD_RS) &&
777 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) {
778 return 0;
779 }
780
781 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false;
782
783 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD;
784
785 dp->upper.data = cpu_to_le32(txd_upper);
786 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp),
787 &dp->upper, sizeof(dp->upper));
788 return e1000e_tx_wb_interrupt_cause(core, queue_idx);
789 }
790
791 typedef struct E1000E_RingInfo_st {
792 int dbah;
793 int dbal;
794 int dlen;
795 int dh;
796 int dt;
797 int idx;
798 } E1000E_RingInfo;
799
800 static inline bool
801 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r)
802 {
803 return core->mac[r->dh] == core->mac[r->dt] ||
804 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN;
805 }
806
807 static inline uint64_t
808 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r)
809 {
810 uint64_t bah = core->mac[r->dbah];
811 uint64_t bal = core->mac[r->dbal];
812
813 return (bah << 32) + bal;
814 }
815
816 static inline uint64_t
817 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r)
818 {
819 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh];
820 }
821
822 static inline void
823 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count)
824 {
825 core->mac[r->dh] += count;
826
827 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) {
828 core->mac[r->dh] = 0;
829 }
830 }
831
832 static inline uint32_t
833 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r)
834 {
835 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen],
836 core->mac[r->dh], core->mac[r->dt]);
837
838 if (core->mac[r->dh] <= core->mac[r->dt]) {
839 return core->mac[r->dt] - core->mac[r->dh];
840 }
841
842 if (core->mac[r->dh] > core->mac[r->dt]) {
843 return core->mac[r->dlen] / E1000_RING_DESC_LEN +
844 core->mac[r->dt] - core->mac[r->dh];
845 }
846
847 g_assert_not_reached();
848 return 0;
849 }
850
851 static inline bool
852 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r)
853 {
854 return core->mac[r->dlen] > 0;
855 }
856
857 static inline uint32_t
858 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r)
859 {
860 return core->mac[r->dlen];
861 }
862
863 typedef struct E1000E_TxRing_st {
864 const E1000E_RingInfo *i;
865 struct e1000e_tx *tx;
866 } E1000E_TxRing;
867
868 static inline int
869 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx)
870 {
871 return (reg_idx - base_reg_idx) / (0x100 >> 2);
872 }
873
874 static inline void
875 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx)
876 {
877 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
878 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 },
879 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 }
880 };
881
882 assert(idx < ARRAY_SIZE(i));
883
884 txr->i = &i[idx];
885 txr->tx = &core->tx[idx];
886 }
887
888 typedef struct E1000E_RxRing_st {
889 const E1000E_RingInfo *i;
890 } E1000E_RxRing;
891
892 static inline void
893 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx)
894 {
895 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
896 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 },
897 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 }
898 };
899
900 assert(idx < ARRAY_SIZE(i));
901
902 rxr->i = &i[idx];
903 }
904
905 static void
906 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr)
907 {
908 dma_addr_t base;
909 struct e1000_tx_desc desc;
910 bool ide = false;
911 const E1000E_RingInfo *txi = txr->i;
912 uint32_t cause = E1000_ICS_TXQE;
913
914 if (!(core->mac[TCTL] & E1000_TCTL_EN)) {
915 trace_e1000e_tx_disabled();
916 return;
917 }
918
919 while (!e1000e_ring_empty(core, txi)) {
920 base = e1000e_ring_head_descr(core, txi);
921
922 pci_dma_read(core->owner, base, &desc, sizeof(desc));
923
924 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr,
925 desc.lower.data, desc.upper.data);
926
927 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx);
928 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx);
929
930 e1000e_ring_advance(core, txi, 1);
931 }
932
933 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) {
934 e1000e_set_interrupt_cause(core, cause);
935 }
936 }
937
938 static bool
939 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r,
940 size_t total_size)
941 {
942 uint32_t bufs = e1000e_ring_free_descr_num(core, r);
943
944 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size,
945 core->rx_desc_buf_size);
946
947 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) *
948 core->rx_desc_buf_size;
949 }
950
951 void
952 e1000e_start_recv(E1000ECore *core)
953 {
954 int i;
955
956 trace_e1000e_rx_start_recv();
957
958 for (i = 0; i <= core->max_queue_num; i++) {
959 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i));
960 }
961 }
962
963 bool
964 e1000e_can_receive(E1000ECore *core)
965 {
966 int i;
967
968 if (!e1000x_rx_ready(core->owner, core->mac)) {
969 return false;
970 }
971
972 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
973 E1000E_RxRing rxr;
974
975 e1000e_rx_ring_init(core, &rxr, i);
976 if (e1000e_ring_enabled(core, rxr.i) &&
977 e1000e_has_rxbufs(core, rxr.i, 1)) {
978 trace_e1000e_rx_can_recv();
979 return true;
980 }
981 }
982
983 trace_e1000e_rx_can_recv_rings_full();
984 return false;
985 }
986
987 ssize_t
988 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size)
989 {
990 const struct iovec iov = {
991 .iov_base = (uint8_t *)buf,
992 .iov_len = size
993 };
994
995 return e1000e_receive_iov(core, &iov, 1);
996 }
997
998 static inline bool
999 e1000e_rx_l3_cso_enabled(E1000ECore *core)
1000 {
1001 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD);
1002 }
1003
1004 static inline bool
1005 e1000e_rx_l4_cso_enabled(E1000ECore *core)
1006 {
1007 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
1008 }
1009
1010 static bool
1011 e1000e_receive_filter(E1000ECore *core, const uint8_t *buf, int size)
1012 {
1013 uint32_t rctl = core->mac[RCTL];
1014
1015 if (e1000x_is_vlan_packet(buf, core->mac[VET]) &&
1016 e1000x_vlan_rx_filter_enabled(core->mac)) {
1017 uint16_t vid = lduw_be_p(buf + 14);
1018 uint32_t vfta = ldl_le_p((uint32_t *)(core->mac + VFTA) +
1019 ((vid >> 5) & 0x7f));
1020 if ((vfta & (1 << (vid & 0x1f))) == 0) {
1021 trace_e1000e_rx_flt_vlan_mismatch(vid);
1022 return false;
1023 } else {
1024 trace_e1000e_rx_flt_vlan_match(vid);
1025 }
1026 }
1027
1028 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1029 case ETH_PKT_UCAST:
1030 if (rctl & E1000_RCTL_UPE) {
1031 return true; /* promiscuous ucast */
1032 }
1033 break;
1034
1035 case ETH_PKT_BCAST:
1036 if (rctl & E1000_RCTL_BAM) {
1037 return true; /* broadcast enabled */
1038 }
1039 break;
1040
1041 case ETH_PKT_MCAST:
1042 if (rctl & E1000_RCTL_MPE) {
1043 return true; /* promiscuous mcast */
1044 }
1045 break;
1046
1047 default:
1048 g_assert_not_reached();
1049 }
1050
1051 return e1000x_rx_group_filter(core->mac, buf);
1052 }
1053
1054 static inline void
1055 e1000e_read_lgcy_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr)
1056 {
1057 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc;
1058 *buff_addr = le64_to_cpu(d->buffer_addr);
1059 }
1060
1061 static inline void
1062 e1000e_read_ext_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr)
1063 {
1064 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc;
1065 *buff_addr = le64_to_cpu(d->read.buffer_addr);
1066 }
1067
1068 static inline void
1069 e1000e_read_ps_rx_descr(E1000ECore *core, uint8_t *desc,
1070 hwaddr (*buff_addr)[MAX_PS_BUFFERS])
1071 {
1072 int i;
1073 union e1000_rx_desc_packet_split *d =
1074 (union e1000_rx_desc_packet_split *) desc;
1075
1076 for (i = 0; i < MAX_PS_BUFFERS; i++) {
1077 (*buff_addr)[i] = le64_to_cpu(d->read.buffer_addr[i]);
1078 }
1079
1080 trace_e1000e_rx_desc_ps_read((*buff_addr)[0], (*buff_addr)[1],
1081 (*buff_addr)[2], (*buff_addr)[3]);
1082 }
1083
1084 static inline void
1085 e1000e_read_rx_descr(E1000ECore *core, uint8_t *desc,
1086 hwaddr (*buff_addr)[MAX_PS_BUFFERS])
1087 {
1088 if (e1000e_rx_use_legacy_descriptor(core)) {
1089 e1000e_read_lgcy_rx_descr(core, desc, &(*buff_addr)[0]);
1090 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0;
1091 } else {
1092 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1093 e1000e_read_ps_rx_descr(core, desc, buff_addr);
1094 } else {
1095 e1000e_read_ext_rx_descr(core, desc, &(*buff_addr)[0]);
1096 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0;
1097 }
1098 }
1099 }
1100
1101 static void
1102 e1000e_verify_csum_in_sw(E1000ECore *core,
1103 struct NetRxPkt *pkt,
1104 uint32_t *status_flags,
1105 bool istcp, bool isudp)
1106 {
1107 bool csum_valid;
1108 uint32_t csum_error;
1109
1110 if (e1000e_rx_l3_cso_enabled(core)) {
1111 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) {
1112 trace_e1000e_rx_metadata_l3_csum_validation_failed();
1113 } else {
1114 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE;
1115 *status_flags |= E1000_RXD_STAT_IPCS | csum_error;
1116 }
1117 } else {
1118 trace_e1000e_rx_metadata_l3_cso_disabled();
1119 }
1120
1121 if (!e1000e_rx_l4_cso_enabled(core)) {
1122 trace_e1000e_rx_metadata_l4_cso_disabled();
1123 return;
1124 }
1125
1126 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1127 trace_e1000e_rx_metadata_l4_csum_validation_failed();
1128 return;
1129 }
1130
1131 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE;
1132
1133 if (istcp) {
1134 *status_flags |= E1000_RXD_STAT_TCPCS |
1135 csum_error;
1136 } else if (isudp) {
1137 *status_flags |= E1000_RXD_STAT_TCPCS |
1138 E1000_RXD_STAT_UDPCS |
1139 csum_error;
1140 }
1141 }
1142
1143 static inline bool
1144 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt)
1145 {
1146 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) {
1147 return false;
1148 }
1149
1150 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) {
1151 return !net_rx_pkt_has_tcp_data(rx_pkt);
1152 }
1153
1154 return true;
1155 }
1156
1157 static void
1158 e1000e_build_rx_metadata(E1000ECore *core,
1159 struct NetRxPkt *pkt,
1160 bool is_eop,
1161 const E1000E_RSSInfo *rss_info,
1162 uint32_t *rss, uint32_t *mrq,
1163 uint32_t *status_flags,
1164 uint16_t *ip_id,
1165 uint16_t *vlan_tag)
1166 {
1167 struct virtio_net_hdr *vhdr;
1168 bool isip4, isip6, istcp, isudp;
1169 uint32_t pkt_type;
1170
1171 *status_flags = E1000_RXD_STAT_DD;
1172
1173 /* No additional metadata needed for non-EOP descriptors */
1174 if (!is_eop) {
1175 goto func_exit;
1176 }
1177
1178 *status_flags |= E1000_RXD_STAT_EOP;
1179
1180 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
1181 trace_e1000e_rx_metadata_protocols(isip4, isip6, isudp, istcp);
1182
1183 /* VLAN state */
1184 if (net_rx_pkt_is_vlan_stripped(pkt)) {
1185 *status_flags |= E1000_RXD_STAT_VP;
1186 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
1187 trace_e1000e_rx_metadata_vlan(*vlan_tag);
1188 }
1189
1190 /* Packet parsing results */
1191 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) {
1192 if (rss_info->enabled) {
1193 *rss = cpu_to_le32(rss_info->hash);
1194 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8));
1195 trace_e1000e_rx_metadata_rss(*rss, *mrq);
1196 }
1197 } else if (isip4) {
1198 *status_flags |= E1000_RXD_STAT_IPIDV;
1199 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt));
1200 trace_e1000e_rx_metadata_ip_id(*ip_id);
1201 }
1202
1203 if (istcp && e1000e_is_tcp_ack(core, pkt)) {
1204 *status_flags |= E1000_RXD_STAT_ACK;
1205 trace_e1000e_rx_metadata_ack();
1206 }
1207
1208 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) {
1209 trace_e1000e_rx_metadata_ipv6_filtering_disabled();
1210 pkt_type = E1000_RXD_PKT_MAC;
1211 } else if (istcp || isudp) {
1212 pkt_type = isip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP;
1213 } else if (isip4 || isip6) {
1214 pkt_type = isip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6;
1215 } else {
1216 pkt_type = E1000_RXD_PKT_MAC;
1217 }
1218
1219 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type);
1220 trace_e1000e_rx_metadata_pkt_type(pkt_type);
1221
1222 /* RX CSO information */
1223 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
1224 trace_e1000e_rx_metadata_ipv6_sum_disabled();
1225 goto func_exit;
1226 }
1227
1228 if (!net_rx_pkt_has_virt_hdr(pkt)) {
1229 trace_e1000e_rx_metadata_no_virthdr();
1230 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp);
1231 goto func_exit;
1232 }
1233
1234 vhdr = net_rx_pkt_get_vhdr(pkt);
1235
1236 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
1237 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
1238 trace_e1000e_rx_metadata_virthdr_no_csum_info();
1239 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp);
1240 goto func_exit;
1241 }
1242
1243 if (e1000e_rx_l3_cso_enabled(core)) {
1244 *status_flags |= isip4 ? E1000_RXD_STAT_IPCS : 0;
1245 } else {
1246 trace_e1000e_rx_metadata_l3_cso_disabled();
1247 }
1248
1249 if (e1000e_rx_l4_cso_enabled(core)) {
1250 if (istcp) {
1251 *status_flags |= E1000_RXD_STAT_TCPCS;
1252 } else if (isudp) {
1253 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
1254 }
1255 } else {
1256 trace_e1000e_rx_metadata_l4_cso_disabled();
1257 }
1258
1259 trace_e1000e_rx_metadata_status_flags(*status_flags);
1260
1261 func_exit:
1262 *status_flags = cpu_to_le32(*status_flags);
1263 }
1264
1265 static inline void
1266 e1000e_write_lgcy_rx_descr(E1000ECore *core, uint8_t *desc,
1267 struct NetRxPkt *pkt,
1268 const E1000E_RSSInfo *rss_info,
1269 uint16_t length)
1270 {
1271 uint32_t status_flags, rss, mrq;
1272 uint16_t ip_id;
1273
1274 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc;
1275
1276 assert(!rss_info->enabled);
1277
1278 d->length = cpu_to_le16(length);
1279 d->csum = 0;
1280
1281 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1282 rss_info,
1283 &rss, &mrq,
1284 &status_flags, &ip_id,
1285 &d->special);
1286 d->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24);
1287 d->status = (uint8_t) le32_to_cpu(status_flags);
1288 }
1289
1290 static inline void
1291 e1000e_write_ext_rx_descr(E1000ECore *core, uint8_t *desc,
1292 struct NetRxPkt *pkt,
1293 const E1000E_RSSInfo *rss_info,
1294 uint16_t length)
1295 {
1296 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc;
1297
1298 memset(&d->wb, 0, sizeof(d->wb));
1299
1300 d->wb.upper.length = cpu_to_le16(length);
1301
1302 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1303 rss_info,
1304 &d->wb.lower.hi_dword.rss,
1305 &d->wb.lower.mrq,
1306 &d->wb.upper.status_error,
1307 &d->wb.lower.hi_dword.csum_ip.ip_id,
1308 &d->wb.upper.vlan);
1309 }
1310
1311 static inline void
1312 e1000e_write_ps_rx_descr(E1000ECore *core, uint8_t *desc,
1313 struct NetRxPkt *pkt,
1314 const E1000E_RSSInfo *rss_info,
1315 size_t ps_hdr_len,
1316 uint16_t(*written)[MAX_PS_BUFFERS])
1317 {
1318 int i;
1319 union e1000_rx_desc_packet_split *d =
1320 (union e1000_rx_desc_packet_split *) desc;
1321
1322 memset(&d->wb, 0, sizeof(d->wb));
1323
1324 d->wb.middle.length0 = cpu_to_le16((*written)[0]);
1325
1326 for (i = 0; i < PS_PAGE_BUFFERS; i++) {
1327 d->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]);
1328 }
1329
1330 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1331 rss_info,
1332 &d->wb.lower.hi_dword.rss,
1333 &d->wb.lower.mrq,
1334 &d->wb.middle.status_error,
1335 &d->wb.lower.hi_dword.csum_ip.ip_id,
1336 &d->wb.middle.vlan);
1337
1338 d->wb.upper.header_status =
1339 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0));
1340
1341 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1],
1342 (*written)[2], (*written)[3]);
1343 }
1344
1345 static inline void
1346 e1000e_write_rx_descr(E1000ECore *core, uint8_t *desc,
1347 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info,
1348 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS])
1349 {
1350 if (e1000e_rx_use_legacy_descriptor(core)) {
1351 assert(ps_hdr_len == 0);
1352 e1000e_write_lgcy_rx_descr(core, desc, pkt, rss_info, (*written)[0]);
1353 } else {
1354 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1355 e1000e_write_ps_rx_descr(core, desc, pkt, rss_info,
1356 ps_hdr_len, written);
1357 } else {
1358 assert(ps_hdr_len == 0);
1359 e1000e_write_ext_rx_descr(core, desc, pkt, rss_info,
1360 (*written)[0]);
1361 }
1362 }
1363 }
1364
1365 typedef struct e1000e_ba_state_st {
1366 uint16_t written[MAX_PS_BUFFERS];
1367 uint8_t cur_idx;
1368 } e1000e_ba_state;
1369
1370 static inline void
1371 e1000e_write_hdr_to_rx_buffers(E1000ECore *core,
1372 hwaddr (*ba)[MAX_PS_BUFFERS],
1373 e1000e_ba_state *bastate,
1374 const char *data,
1375 dma_addr_t data_len)
1376 {
1377 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]);
1378
1379 pci_dma_write(core->owner, (*ba)[0] + bastate->written[0], data, data_len);
1380 bastate->written[0] += data_len;
1381
1382 bastate->cur_idx = 1;
1383 }
1384
1385 static void
1386 e1000e_write_to_rx_buffers(E1000ECore *core,
1387 hwaddr (*ba)[MAX_PS_BUFFERS],
1388 e1000e_ba_state *bastate,
1389 const char *data,
1390 dma_addr_t data_len)
1391 {
1392 while (data_len > 0) {
1393 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx];
1394 uint32_t cur_buf_bytes_left = cur_buf_len -
1395 bastate->written[bastate->cur_idx];
1396 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left);
1397
1398 trace_e1000e_rx_desc_buff_write(bastate->cur_idx,
1399 (*ba)[bastate->cur_idx],
1400 bastate->written[bastate->cur_idx],
1401 data,
1402 bytes_to_write);
1403
1404 pci_dma_write(core->owner,
1405 (*ba)[bastate->cur_idx] + bastate->written[bastate->cur_idx],
1406 data, bytes_to_write);
1407
1408 bastate->written[bastate->cur_idx] += bytes_to_write;
1409 data += bytes_to_write;
1410 data_len -= bytes_to_write;
1411
1412 if (bastate->written[bastate->cur_idx] == cur_buf_len) {
1413 bastate->cur_idx++;
1414 }
1415
1416 assert(bastate->cur_idx < MAX_PS_BUFFERS);
1417 }
1418 }
1419
1420 static void
1421 e1000e_update_rx_stats(E1000ECore *core,
1422 size_t data_size,
1423 size_t data_fcs_size)
1424 {
1425 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size);
1426
1427 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1428 case ETH_PKT_BCAST:
1429 e1000x_inc_reg_if_not_full(core->mac, BPRC);
1430 break;
1431
1432 case ETH_PKT_MCAST:
1433 e1000x_inc_reg_if_not_full(core->mac, MPRC);
1434 break;
1435
1436 default:
1437 break;
1438 }
1439 }
1440
1441 static inline bool
1442 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi)
1443 {
1444 return e1000e_ring_free_descr_num(core, rxi) ==
1445 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift;
1446 }
1447
1448 static bool
1449 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len)
1450 {
1451 bool isip4, isip6, isudp, istcp;
1452 bool fragment;
1453
1454 if (!e1000e_rx_use_ps_descriptor(core)) {
1455 return false;
1456 }
1457
1458 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
1459
1460 if (isip4) {
1461 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
1462 } else if (isip6) {
1463 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment;
1464 } else {
1465 return false;
1466 }
1467
1468 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) {
1469 return false;
1470 }
1471
1472 if (!fragment && (isudp || istcp)) {
1473 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt);
1474 } else {
1475 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt);
1476 }
1477
1478 if ((*hdr_len > core->rxbuf_sizes[0]) ||
1479 (*hdr_len > net_rx_pkt_get_total_len(pkt))) {
1480 return false;
1481 }
1482
1483 return true;
1484 }
1485
1486 static void
1487 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt,
1488 const E1000E_RxRing *rxr,
1489 const E1000E_RSSInfo *rss_info)
1490 {
1491 PCIDevice *d = core->owner;
1492 dma_addr_t base;
1493 uint8_t desc[E1000_MAX_RX_DESC_LEN];
1494 size_t desc_size;
1495 size_t desc_offset = 0;
1496 size_t iov_ofs = 0;
1497
1498 struct iovec *iov = net_rx_pkt_get_iovec(pkt);
1499 size_t size = net_rx_pkt_get_total_len(pkt);
1500 size_t total_size = size + e1000x_fcs_len(core->mac);
1501 const E1000E_RingInfo *rxi;
1502 size_t ps_hdr_len = 0;
1503 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len);
1504 bool is_first = true;
1505
1506 rxi = rxr->i;
1507
1508 do {
1509 hwaddr ba[MAX_PS_BUFFERS];
1510 e1000e_ba_state bastate = { { 0 } };
1511 bool is_last = false;
1512
1513 desc_size = total_size - desc_offset;
1514
1515 if (desc_size > core->rx_desc_buf_size) {
1516 desc_size = core->rx_desc_buf_size;
1517 }
1518
1519 if (e1000e_ring_empty(core, rxi)) {
1520 return;
1521 }
1522
1523 base = e1000e_ring_head_descr(core, rxi);
1524
1525 pci_dma_read(d, base, &desc, core->rx_desc_len);
1526
1527 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len);
1528
1529 e1000e_read_rx_descr(core, desc, &ba);
1530
1531 if (ba[0]) {
1532 if (desc_offset < size) {
1533 static const uint32_t fcs_pad;
1534 size_t iov_copy;
1535 size_t copy_size = size - desc_offset;
1536 if (copy_size > core->rx_desc_buf_size) {
1537 copy_size = core->rx_desc_buf_size;
1538 }
1539
1540 /* For PS mode copy the packet header first */
1541 if (do_ps) {
1542 if (is_first) {
1543 size_t ps_hdr_copied = 0;
1544 do {
1545 iov_copy = MIN(ps_hdr_len - ps_hdr_copied,
1546 iov->iov_len - iov_ofs);
1547
1548 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate,
1549 iov->iov_base, iov_copy);
1550
1551 copy_size -= iov_copy;
1552 ps_hdr_copied += iov_copy;
1553
1554 iov_ofs += iov_copy;
1555 if (iov_ofs == iov->iov_len) {
1556 iov++;
1557 iov_ofs = 0;
1558 }
1559 } while (ps_hdr_copied < ps_hdr_len);
1560
1561 is_first = false;
1562 } else {
1563 /* Leave buffer 0 of each descriptor except first */
1564 /* empty as per spec 7.1.5.1 */
1565 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate,
1566 NULL, 0);
1567 }
1568 }
1569
1570 /* Copy packet payload */
1571 while (copy_size) {
1572 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
1573
1574 e1000e_write_to_rx_buffers(core, &ba, &bastate,
1575 iov->iov_base + iov_ofs, iov_copy);
1576
1577 copy_size -= iov_copy;
1578 iov_ofs += iov_copy;
1579 if (iov_ofs == iov->iov_len) {
1580 iov++;
1581 iov_ofs = 0;
1582 }
1583 }
1584
1585 if (desc_offset + desc_size >= total_size) {
1586 /* Simulate FCS checksum presence in the last descriptor */
1587 e1000e_write_to_rx_buffers(core, &ba, &bastate,
1588 (const char *) &fcs_pad, e1000x_fcs_len(core->mac));
1589 }
1590 }
1591 } else { /* as per intel docs; skip descriptors with null buf addr */
1592 trace_e1000e_rx_null_descriptor();
1593 }
1594 desc_offset += desc_size;
1595 if (desc_offset >= total_size) {
1596 is_last = true;
1597 }
1598
1599 e1000e_write_rx_descr(core, desc, is_last ? core->rx_pkt : NULL,
1600 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written);
1601 pci_dma_write(d, base, &desc, core->rx_desc_len);
1602
1603 e1000e_ring_advance(core, rxi,
1604 core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
1605
1606 } while (desc_offset < total_size);
1607
1608 e1000e_update_rx_stats(core, size, total_size);
1609 }
1610
1611 static inline void
1612 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt)
1613 {
1614 if (net_rx_pkt_has_virt_hdr(pkt)) {
1615 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt);
1616
1617 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
1618 net_rx_pkt_fix_l4_csum(pkt);
1619 }
1620 }
1621 }
1622
1623 ssize_t
1624 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt)
1625 {
1626 static const int maximum_ethernet_hdr_len = (14 + 4);
1627 /* Min. octets in an ethernet frame sans FCS */
1628 static const int min_buf_size = 60;
1629
1630 uint32_t n = 0;
1631 uint8_t min_buf[min_buf_size];
1632 struct iovec min_iov;
1633 uint8_t *filter_buf;
1634 size_t size, orig_size;
1635 size_t iov_ofs = 0;
1636 E1000E_RxRing rxr;
1637 E1000E_RSSInfo rss_info;
1638 size_t total_size;
1639 ssize_t retval;
1640 bool rdmts_hit;
1641
1642 trace_e1000e_rx_receive_iov(iovcnt);
1643
1644 if (!e1000x_hw_rx_enabled(core->mac)) {
1645 return -1;
1646 }
1647
1648 /* Pull virtio header in */
1649 if (core->has_vnet) {
1650 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt);
1651 iov_ofs = sizeof(struct virtio_net_hdr);
1652 }
1653
1654 filter_buf = iov->iov_base + iov_ofs;
1655 orig_size = iov_size(iov, iovcnt);
1656 size = orig_size - iov_ofs;
1657
1658 /* Pad to minimum Ethernet frame length */
1659 if (size < sizeof(min_buf)) {
1660 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size);
1661 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1662 e1000x_inc_reg_if_not_full(core->mac, RUC);
1663 min_iov.iov_base = filter_buf = min_buf;
1664 min_iov.iov_len = size = sizeof(min_buf);
1665 iovcnt = 1;
1666 iov = &min_iov;
1667 iov_ofs = 0;
1668 } else if (iov->iov_len < maximum_ethernet_hdr_len) {
1669 /* This is very unlikely, but may happen. */
1670 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len);
1671 filter_buf = min_buf;
1672 }
1673
1674 /* Discard oversized packets if !LPE and !SBP. */
1675 if (e1000x_is_oversized(core->mac, size)) {
1676 return orig_size;
1677 }
1678
1679 net_rx_pkt_set_packet_type(core->rx_pkt,
1680 get_eth_packet_type(PKT_GET_ETH_HDR(filter_buf)));
1681
1682 if (!e1000e_receive_filter(core, filter_buf, size)) {
1683 trace_e1000e_rx_flt_dropped();
1684 return orig_size;
1685 }
1686
1687 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
1688 e1000x_vlan_enabled(core->mac), core->mac[VET]);
1689
1690 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info);
1691 e1000e_rx_ring_init(core, &rxr, rss_info.queue);
1692
1693 trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx);
1694
1695 total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
1696 e1000x_fcs_len(core->mac);
1697
1698 if (e1000e_has_rxbufs(core, rxr.i, total_size)) {
1699 e1000e_rx_fix_l4_csum(core, core->rx_pkt);
1700
1701 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
1702
1703 retval = orig_size;
1704
1705 /* Perform small receive detection (RSRPD) */
1706 if (total_size < core->mac[RSRPD]) {
1707 n |= E1000_ICS_SRPD;
1708 }
1709
1710 /* Perform ACK receive detection */
1711 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) &&
1712 (e1000e_is_tcp_ack(core, core->rx_pkt))) {
1713 n |= E1000_ICS_ACK;
1714 }
1715
1716 /* Check if receive descriptor minimum threshold hit */
1717 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i);
1718 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit);
1719
1720 trace_e1000e_rx_written_to_guest(n);
1721 } else {
1722 n |= E1000_ICS_RXO;
1723 retval = 0;
1724
1725 trace_e1000e_rx_not_written_to_guest(n);
1726 }
1727
1728 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) {
1729 trace_e1000e_rx_interrupt_set(n);
1730 e1000e_set_interrupt_cause(core, n);
1731 } else {
1732 trace_e1000e_rx_interrupt_delayed(n);
1733 }
1734
1735 return retval;
1736 }
1737
1738 static inline bool
1739 e1000e_have_autoneg(E1000ECore *core)
1740 {
1741 return core->phy[0][PHY_CTRL] & MII_CR_AUTO_NEG_EN;
1742 }
1743
1744 static void e1000e_update_flowctl_status(E1000ECore *core)
1745 {
1746 if (e1000e_have_autoneg(core) &&
1747 core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE) {
1748 trace_e1000e_link_autoneg_flowctl(true);
1749 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE;
1750 } else {
1751 trace_e1000e_link_autoneg_flowctl(false);
1752 }
1753 }
1754
1755 static inline void
1756 e1000e_link_down(E1000ECore *core)
1757 {
1758 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1759 e1000e_update_flowctl_status(core);
1760 }
1761
1762 static inline void
1763 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val)
1764 {
1765 /* bits 0-5 reserved; MII_CR_[RESTART_AUTO_NEG,RESET] are self clearing */
1766 core->phy[0][PHY_CTRL] = val & ~(0x3f |
1767 MII_CR_RESET |
1768 MII_CR_RESTART_AUTO_NEG);
1769
1770 if ((val & MII_CR_RESTART_AUTO_NEG) &&
1771 e1000e_have_autoneg(core)) {
1772 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1773 }
1774 }
1775
1776 static void
1777 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val)
1778 {
1779 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10);
1780
1781 if (val & BIT(10)) {
1782 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1783 }
1784 }
1785
1786 static void
1787 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val)
1788 {
1789 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK;
1790 }
1791
1792 void
1793 e1000e_core_set_link_status(E1000ECore *core)
1794 {
1795 NetClientState *nc = qemu_get_queue(core->owner_nic);
1796 uint32_t old_status = core->mac[STATUS];
1797
1798 trace_e1000e_link_status_changed(nc->link_down ? false : true);
1799
1800 if (nc->link_down) {
1801 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1802 } else {
1803 if (e1000e_have_autoneg(core) &&
1804 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
1805 e1000x_restart_autoneg(core->mac, core->phy[0],
1806 core->autoneg_timer);
1807 } else {
1808 e1000x_update_regs_on_link_up(core->mac, core->phy[0]);
1809 e1000e_start_recv(core);
1810 }
1811 }
1812
1813 if (core->mac[STATUS] != old_status) {
1814 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
1815 }
1816 }
1817
1818 static void
1819 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val)
1820 {
1821 trace_e1000e_core_ctrl_write(index, val);
1822
1823 /* RST is self clearing */
1824 core->mac[CTRL] = val & ~E1000_CTRL_RST;
1825 core->mac[CTRL_DUP] = core->mac[CTRL];
1826
1827 trace_e1000e_link_set_params(
1828 !!(val & E1000_CTRL_ASDE),
1829 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1830 !!(val & E1000_CTRL_FRCSPD),
1831 !!(val & E1000_CTRL_FRCDPX),
1832 !!(val & E1000_CTRL_RFCE),
1833 !!(val & E1000_CTRL_TFCE));
1834
1835 if (val & E1000_CTRL_RST) {
1836 trace_e1000e_core_ctrl_sw_reset();
1837 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
1838 }
1839
1840 if (val & E1000_CTRL_PHY_RST) {
1841 trace_e1000e_core_ctrl_phy_reset();
1842 core->mac[STATUS] |= E1000_STATUS_PHYRA;
1843 }
1844 }
1845
1846 static void
1847 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val)
1848 {
1849 trace_e1000e_rx_set_rfctl(val);
1850
1851 if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1852 trace_e1000e_wrn_iscsi_filtering_not_supported();
1853 }
1854
1855 if (!(val & E1000_RFCTL_NFSW_DIS)) {
1856 trace_e1000e_wrn_nfsw_filtering_not_supported();
1857 }
1858
1859 if (!(val & E1000_RFCTL_NFSR_DIS)) {
1860 trace_e1000e_wrn_nfsr_filtering_not_supported();
1861 }
1862
1863 core->mac[RFCTL] = val;
1864 }
1865
1866 static void
1867 e1000e_calc_per_desc_buf_size(E1000ECore *core)
1868 {
1869 int i;
1870 core->rx_desc_buf_size = 0;
1871
1872 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) {
1873 core->rx_desc_buf_size += core->rxbuf_sizes[i];
1874 }
1875 }
1876
1877 static void
1878 e1000e_parse_rxbufsize(E1000ECore *core)
1879 {
1880 uint32_t rctl = core->mac[RCTL];
1881
1882 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes));
1883
1884 if (rctl & E1000_RCTL_DTYP_MASK) {
1885 uint32_t bsize;
1886
1887 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK;
1888 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128;
1889
1890 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK;
1891 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024;
1892
1893 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK;
1894 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024;
1895
1896 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK;
1897 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024;
1898 } else if (rctl & E1000_RCTL_FLXBUF_MASK) {
1899 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK;
1900 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024;
1901 } else {
1902 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl);
1903 }
1904
1905 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1],
1906 core->rxbuf_sizes[2], core->rxbuf_sizes[3]);
1907
1908 e1000e_calc_per_desc_buf_size(core);
1909 }
1910
1911 static void
1912 e1000e_calc_rxdesclen(E1000ECore *core)
1913 {
1914 if (e1000e_rx_use_legacy_descriptor(core)) {
1915 core->rx_desc_len = sizeof(struct e1000_rx_desc);
1916 } else {
1917 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1918 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split);
1919 } else {
1920 core->rx_desc_len = sizeof(union e1000_rx_desc_extended);
1921 }
1922 }
1923 trace_e1000e_rx_desc_len(core->rx_desc_len);
1924 }
1925
1926 static void
1927 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val)
1928 {
1929 core->mac[RCTL] = val;
1930 trace_e1000e_rx_set_rctl(core->mac[RCTL]);
1931
1932 if (val & E1000_RCTL_EN) {
1933 e1000e_parse_rxbufsize(core);
1934 e1000e_calc_rxdesclen(core);
1935 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 +
1936 E1000_RING_DESC_LEN_SHIFT;
1937
1938 e1000e_start_recv(core);
1939 }
1940 }
1941
1942 static
1943 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE])
1944 (E1000ECore *, int, uint16_t) = {
1945 [0] = {
1946 [PHY_CTRL] = e1000e_set_phy_ctrl,
1947 [PHY_PAGE] = e1000e_set_phy_page,
1948 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits
1949 }
1950 };
1951
1952 static inline void
1953 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits)
1954 {
1955 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits);
1956 core->mac[IMS] &= ~bits;
1957 }
1958
1959 static inline bool
1960 e1000e_postpone_interrupt(bool *interrupt_pending,
1961 E1000IntrDelayTimer *timer)
1962 {
1963 if (timer->running) {
1964 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2);
1965
1966 *interrupt_pending = true;
1967 return true;
1968 }
1969
1970 if (timer->core->mac[timer->delay_reg] != 0) {
1971 e1000e_intrmgr_rearm_timer(timer);
1972 }
1973
1974 return false;
1975 }
1976
1977 static inline bool
1978 e1000e_itr_should_postpone(E1000ECore *core)
1979 {
1980 return e1000e_postpone_interrupt(&core->itr_intr_pending, &core->itr);
1981 }
1982
1983 static inline bool
1984 e1000e_eitr_should_postpone(E1000ECore *core, int idx)
1985 {
1986 return e1000e_postpone_interrupt(&core->eitr_intr_pending[idx],
1987 &core->eitr[idx]);
1988 }
1989
1990 static void
1991 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
1992 {
1993 uint32_t effective_eiac;
1994
1995 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
1996 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
1997 if (vec < E1000E_MSIX_VEC_NUM) {
1998 if (!e1000e_eitr_should_postpone(core, vec)) {
1999 trace_e1000e_irq_msix_notify_vec(vec);
2000 msix_notify(core->owner, vec);
2001 }
2002 } else {
2003 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2004 }
2005 } else {
2006 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2007 }
2008
2009 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) {
2010 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause);
2011 core->mac[IAM] &= ~cause;
2012 }
2013
2014 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]);
2015
2016 effective_eiac = core->mac[EIAC] & cause;
2017
2018 core->mac[ICR] &= ~effective_eiac;
2019 core->msi_causes_pending &= ~effective_eiac;
2020
2021 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2022 core->mac[IMS] &= ~effective_eiac;
2023 }
2024 }
2025
2026 static void
2027 e1000e_msix_notify(E1000ECore *core, uint32_t causes)
2028 {
2029 if (causes & E1000_ICR_RXQ0) {
2030 e1000e_msix_notify_one(core, E1000_ICR_RXQ0,
2031 E1000_IVAR_RXQ0(core->mac[IVAR]));
2032 }
2033
2034 if (causes & E1000_ICR_RXQ1) {
2035 e1000e_msix_notify_one(core, E1000_ICR_RXQ1,
2036 E1000_IVAR_RXQ1(core->mac[IVAR]));
2037 }
2038
2039 if (causes & E1000_ICR_TXQ0) {
2040 e1000e_msix_notify_one(core, E1000_ICR_TXQ0,
2041 E1000_IVAR_TXQ0(core->mac[IVAR]));
2042 }
2043
2044 if (causes & E1000_ICR_TXQ1) {
2045 e1000e_msix_notify_one(core, E1000_ICR_TXQ1,
2046 E1000_IVAR_TXQ1(core->mac[IVAR]));
2047 }
2048
2049 if (causes & E1000_ICR_OTHER) {
2050 e1000e_msix_notify_one(core, E1000_ICR_OTHER,
2051 E1000_IVAR_OTHER(core->mac[IVAR]));
2052 }
2053 }
2054
2055 static void
2056 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2057 {
2058 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2059 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2060 if (vec < E1000E_MSIX_VEC_NUM) {
2061 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec);
2062 msix_clr_pending(core->owner, vec);
2063 } else {
2064 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2065 }
2066 } else {
2067 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2068 }
2069 }
2070
2071 static void
2072 e1000e_msix_clear(E1000ECore *core, uint32_t causes)
2073 {
2074 if (causes & E1000_ICR_RXQ0) {
2075 e1000e_msix_clear_one(core, E1000_ICR_RXQ0,
2076 E1000_IVAR_RXQ0(core->mac[IVAR]));
2077 }
2078
2079 if (causes & E1000_ICR_RXQ1) {
2080 e1000e_msix_clear_one(core, E1000_ICR_RXQ1,
2081 E1000_IVAR_RXQ1(core->mac[IVAR]));
2082 }
2083
2084 if (causes & E1000_ICR_TXQ0) {
2085 e1000e_msix_clear_one(core, E1000_ICR_TXQ0,
2086 E1000_IVAR_TXQ0(core->mac[IVAR]));
2087 }
2088
2089 if (causes & E1000_ICR_TXQ1) {
2090 e1000e_msix_clear_one(core, E1000_ICR_TXQ1,
2091 E1000_IVAR_TXQ1(core->mac[IVAR]));
2092 }
2093
2094 if (causes & E1000_ICR_OTHER) {
2095 e1000e_msix_clear_one(core, E1000_ICR_OTHER,
2096 E1000_IVAR_OTHER(core->mac[IVAR]));
2097 }
2098 }
2099
2100 static inline void
2101 e1000e_fix_icr_asserted(E1000ECore *core)
2102 {
2103 core->mac[ICR] &= ~E1000_ICR_ASSERTED;
2104 if (core->mac[ICR]) {
2105 core->mac[ICR] |= E1000_ICR_ASSERTED;
2106 }
2107
2108 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
2109 }
2110
2111 static void
2112 e1000e_send_msi(E1000ECore *core, bool msix)
2113 {
2114 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED;
2115
2116 core->msi_causes_pending &= causes;
2117 causes ^= core->msi_causes_pending;
2118 if (causes == 0) {
2119 return;
2120 }
2121 core->msi_causes_pending |= causes;
2122
2123 if (msix) {
2124 e1000e_msix_notify(core, causes);
2125 } else {
2126 if (!e1000e_itr_should_postpone(core)) {
2127 trace_e1000e_irq_msi_notify(causes);
2128 msi_notify(core->owner, 0);
2129 }
2130 }
2131 }
2132
2133 static void
2134 e1000e_update_interrupt_state(E1000ECore *core)
2135 {
2136 bool interrupts_pending;
2137 bool is_msix = msix_enabled(core->owner);
2138
2139 /* Set ICR[OTHER] for MSI-X */
2140 if (is_msix) {
2141 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) {
2142 core->mac[ICR] |= E1000_ICR_OTHER;
2143 trace_e1000e_irq_add_msi_other(core->mac[ICR]);
2144 }
2145 }
2146
2147 e1000e_fix_icr_asserted(core);
2148
2149 /*
2150 * Make sure ICR and ICS registers have the same value.
2151 * The spec says that the ICS register is write-only. However in practice,
2152 * on real hardware ICS is readable, and for reads it has the same value as
2153 * ICR (except that ICS does not have the clear on read behaviour of ICR).
2154 *
2155 * The VxWorks PRO/1000 driver uses this behaviour.
2156 */
2157 core->mac[ICS] = core->mac[ICR];
2158
2159 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false;
2160 if (!interrupts_pending) {
2161 core->msi_causes_pending = 0;
2162 }
2163
2164 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
2165 core->mac[ICR], core->mac[IMS]);
2166
2167 if (is_msix || msi_enabled(core->owner)) {
2168 if (interrupts_pending) {
2169 e1000e_send_msi(core, is_msix);
2170 }
2171 } else {
2172 if (interrupts_pending) {
2173 if (!e1000e_itr_should_postpone(core)) {
2174 e1000e_raise_legacy_irq(core);
2175 }
2176 } else {
2177 e1000e_lower_legacy_irq(core);
2178 }
2179 }
2180 }
2181
2182 static void
2183 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val)
2184 {
2185 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]);
2186
2187 val |= e1000e_intmgr_collect_delayed_causes(core);
2188 core->mac[ICR] |= val;
2189
2190 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]);
2191
2192 e1000e_update_interrupt_state(core);
2193 }
2194
2195 static inline void
2196 e1000e_autoneg_timer(void *opaque)
2197 {
2198 E1000ECore *core = opaque;
2199 if (!qemu_get_queue(core->owner_nic)->link_down) {
2200 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]);
2201 e1000e_start_recv(core);
2202
2203 e1000e_update_flowctl_status(core);
2204 /* signal link status change to the guest */
2205 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
2206 }
2207 }
2208
2209 static inline uint16_t
2210 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)
2211 {
2212 uint16_t index = (addr & 0x1ffff) >> 2;
2213 return index + (mac_reg_access[index] & 0xfffe);
2214 }
2215
2216 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = {
2217 [0] = {
2218 [PHY_CTRL] = PHY_ANYPAGE | PHY_RW,
2219 [PHY_STATUS] = PHY_ANYPAGE | PHY_R,
2220 [PHY_ID1] = PHY_ANYPAGE | PHY_R,
2221 [PHY_ID2] = PHY_ANYPAGE | PHY_R,
2222 [PHY_AUTONEG_ADV] = PHY_ANYPAGE | PHY_RW,
2223 [PHY_LP_ABILITY] = PHY_ANYPAGE | PHY_R,
2224 [PHY_AUTONEG_EXP] = PHY_ANYPAGE | PHY_R,
2225 [PHY_NEXT_PAGE_TX] = PHY_ANYPAGE | PHY_RW,
2226 [PHY_LP_NEXT_PAGE] = PHY_ANYPAGE | PHY_R,
2227 [PHY_1000T_CTRL] = PHY_ANYPAGE | PHY_RW,
2228 [PHY_1000T_STATUS] = PHY_ANYPAGE | PHY_R,
2229 [PHY_EXT_STATUS] = PHY_ANYPAGE | PHY_R,
2230 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW,
2231
2232 [PHY_COPPER_CTRL1] = PHY_RW,
2233 [PHY_COPPER_STAT1] = PHY_R,
2234 [PHY_COPPER_CTRL3] = PHY_RW,
2235 [PHY_RX_ERR_CNTR] = PHY_R,
2236 [PHY_OEM_BITS] = PHY_RW,
2237 [PHY_BIAS_1] = PHY_RW,
2238 [PHY_BIAS_2] = PHY_RW,
2239 [PHY_COPPER_INT_ENABLE] = PHY_RW,
2240 [PHY_COPPER_STAT2] = PHY_R,
2241 [PHY_COPPER_CTRL2] = PHY_RW
2242 },
2243 [2] = {
2244 [PHY_MAC_CTRL1] = PHY_RW,
2245 [PHY_MAC_INT_ENABLE] = PHY_RW,
2246 [PHY_MAC_STAT] = PHY_R,
2247 [PHY_MAC_CTRL2] = PHY_RW
2248 },
2249 [3] = {
2250 [PHY_LED_03_FUNC_CTRL1] = PHY_RW,
2251 [PHY_LED_03_POL_CTRL] = PHY_RW,
2252 [PHY_LED_TIMER_CTRL] = PHY_RW,
2253 [PHY_LED_45_CTRL] = PHY_RW
2254 },
2255 [5] = {
2256 [PHY_1000T_SKEW] = PHY_R,
2257 [PHY_1000T_SWAP] = PHY_R
2258 },
2259 [6] = {
2260 [PHY_CRC_COUNTERS] = PHY_R
2261 }
2262 };
2263
2264 static bool
2265 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr,
2266 char cap, uint8_t *page)
2267 {
2268 *page =
2269 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0
2270 : core->phy[0][PHY_PAGE];
2271
2272 if (*page >= E1000E_PHY_PAGES) {
2273 return false;
2274 }
2275
2276 return e1000e_phy_regcap[*page][addr] & cap;
2277 }
2278
2279 static void
2280 e1000e_phy_reg_write(E1000ECore *core, uint8_t page,
2281 uint32_t addr, uint16_t data)
2282 {
2283 assert(page < E1000E_PHY_PAGES);
2284 assert(addr < E1000E_PHY_PAGE_SIZE);
2285
2286 if (e1000e_phyreg_writeops[page][addr]) {
2287 e1000e_phyreg_writeops[page][addr](core, addr, data);
2288 } else {
2289 core->phy[page][addr] = data;
2290 }
2291 }
2292
2293 static void
2294 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val)
2295 {
2296 uint32_t data = val & E1000_MDIC_DATA_MASK;
2297 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2298 uint8_t page;
2299
2300 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2301 val = core->mac[MDIC] | E1000_MDIC_ERROR;
2302 } else if (val & E1000_MDIC_OP_READ) {
2303 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) {
2304 trace_e1000e_core_mdic_read_unhandled(page, addr);
2305 val |= E1000_MDIC_ERROR;
2306 } else {
2307 val = (val ^ data) | core->phy[page][addr];
2308 trace_e1000e_core_mdic_read(page, addr, val);
2309 }
2310 } else if (val & E1000_MDIC_OP_WRITE) {
2311 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) {
2312 trace_e1000e_core_mdic_write_unhandled(page, addr);
2313 val |= E1000_MDIC_ERROR;
2314 } else {
2315 trace_e1000e_core_mdic_write(page, addr, data);
2316 e1000e_phy_reg_write(core, page, addr, data);
2317 }
2318 }
2319 core->mac[MDIC] = val | E1000_MDIC_READY;
2320
2321 if (val & E1000_MDIC_INT_EN) {
2322 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC);
2323 }
2324 }
2325
2326 static void
2327 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val)
2328 {
2329 core->mac[index] = val & 0xffff;
2330 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val);
2331 e1000e_start_recv(core);
2332 }
2333
2334 static void
2335 e1000e_set_status(E1000ECore *core, int index, uint32_t val)
2336 {
2337 if ((val & E1000_STATUS_PHYRA) == 0) {
2338 core->mac[index] &= ~E1000_STATUS_PHYRA;
2339 }
2340 }
2341
2342 static void
2343 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val)
2344 {
2345 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2346 !!(val & E1000_CTRL_EXT_SPD_BYPS));
2347
2348 /* Zero self-clearing bits */
2349 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
2350 core->mac[CTRL_EXT] = val;
2351 }
2352
2353 static void
2354 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val)
2355 {
2356 int i;
2357
2358 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2359
2360 if (!msix_enabled(core->owner)) {
2361 return;
2362 }
2363
2364 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
2365 if (core->mac[PBACLR] & BIT(i)) {
2366 msix_clr_pending(core->owner, i);
2367 }
2368 }
2369 }
2370
2371 static void
2372 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val)
2373 {
2374 core->mac[FCRTH] = val & 0xFFF8;
2375 }
2376
2377 static void
2378 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val)
2379 {
2380 core->mac[FCRTL] = val & 0x8000FFF8;
2381 }
2382
2383 static inline void
2384 e1000e_set_16bit(E1000ECore *core, int index, uint32_t val)
2385 {
2386 core->mac[index] = val & 0xffff;
2387 }
2388
2389 static void
2390 e1000e_set_12bit(E1000ECore *core, int index, uint32_t val)
2391 {
2392 core->mac[index] = val & 0xfff;
2393 }
2394
2395 static void
2396 e1000e_set_vet(E1000ECore *core, int index, uint32_t val)
2397 {
2398 core->mac[VET] = val & 0xffff;
2399 trace_e1000e_vlan_vet(core->mac[VET]);
2400 }
2401
2402 static void
2403 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val)
2404 {
2405 core->mac[index] = val & E1000_XDLEN_MASK;
2406 }
2407
2408 static void
2409 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val)
2410 {
2411 core->mac[index] = val & E1000_XDBAL_MASK;
2412 }
2413
2414 static void
2415 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val)
2416 {
2417 E1000E_TxRing txr;
2418 core->mac[index] = val;
2419
2420 if (core->mac[TARC0] & E1000_TARC_ENABLE) {
2421 e1000e_tx_ring_init(core, &txr, 0);
2422 e1000e_start_xmit(core, &txr);
2423 }
2424
2425 if (core->mac[TARC1] & E1000_TARC_ENABLE) {
2426 e1000e_tx_ring_init(core, &txr, 1);
2427 e1000e_start_xmit(core, &txr);
2428 }
2429 }
2430
2431 static void
2432 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val)
2433 {
2434 E1000E_TxRing txr;
2435 int qidx = e1000e_mq_queue_idx(TDT, index);
2436 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1;
2437
2438 core->mac[index] = val & 0xffff;
2439
2440 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) {
2441 e1000e_tx_ring_init(core, &txr, qidx);
2442 e1000e_start_xmit(core, &txr);
2443 }
2444 }
2445
2446 static void
2447 e1000e_set_ics(E1000ECore *core, int index, uint32_t val)
2448 {
2449 trace_e1000e_irq_write_ics(val);
2450 e1000e_set_interrupt_cause(core, val);
2451 }
2452
2453 static void
2454 e1000e_set_icr(E1000ECore *core, int index, uint32_t val)
2455 {
2456 uint32_t icr = 0;
2457 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2458 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2459 trace_e1000e_irq_icr_process_iame();
2460 e1000e_clear_ims_bits(core, core->mac[IAM]);
2461 }
2462
2463 icr = core->mac[ICR] & ~val;
2464 /* Windows driver expects that the "receive overrun" bit and other
2465 * ones to be cleared when the "Other" bit (#24) is cleared.
2466 */
2467 icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr;
2468 trace_e1000e_irq_icr_write(val, core->mac[ICR], icr);
2469 core->mac[ICR] = icr;
2470 e1000e_update_interrupt_state(core);
2471 }
2472
2473 static void
2474 e1000e_set_imc(E1000ECore *core, int index, uint32_t val)
2475 {
2476 trace_e1000e_irq_ims_clear_set_imc(val);
2477 e1000e_clear_ims_bits(core, val);
2478 e1000e_update_interrupt_state(core);
2479 }
2480
2481 static void
2482 e1000e_set_ims(E1000ECore *core, int index, uint32_t val)
2483 {
2484 static const uint32_t ims_ext_mask =
2485 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 |
2486 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2487 E1000_IMS_OTHER;
2488
2489 static const uint32_t ims_valid_mask =
2490 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC |
2491 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 |
2492 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD |
2493 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 |
2494 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2495 E1000_IMS_OTHER;
2496
2497 uint32_t valid_val = val & ims_valid_mask;
2498
2499 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val);
2500 core->mac[IMS] |= valid_val;
2501
2502 if ((valid_val & ims_ext_mask) &&
2503 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) &&
2504 msix_enabled(core->owner)) {
2505 e1000e_msix_clear(core, valid_val);
2506 }
2507
2508 if ((valid_val == ims_valid_mask) &&
2509 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) {
2510 trace_e1000e_irq_fire_all_timers(val);
2511 e1000e_intrmgr_fire_all_timers(core);
2512 }
2513
2514 e1000e_update_interrupt_state(core);
2515 }
2516
2517 static void
2518 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val)
2519 {
2520 e1000e_set_16bit(core, index, val);
2521
2522 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) {
2523 trace_e1000e_irq_rdtr_fpd_running();
2524 e1000e_intrmgr_fire_delayed_interrupts(core);
2525 } else {
2526 trace_e1000e_irq_rdtr_fpd_not_running();
2527 }
2528 }
2529
2530 static void
2531 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val)
2532 {
2533 e1000e_set_16bit(core, index, val);
2534
2535 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) {
2536 trace_e1000e_irq_tidv_fpd_running();
2537 e1000e_intrmgr_fire_delayed_interrupts(core);
2538 } else {
2539 trace_e1000e_irq_tidv_fpd_not_running();
2540 }
2541 }
2542
2543 static uint32_t
2544 e1000e_mac_readreg(E1000ECore *core, int index)
2545 {
2546 return core->mac[index];
2547 }
2548
2549 static uint32_t
2550 e1000e_mac_ics_read(E1000ECore *core, int index)
2551 {
2552 trace_e1000e_irq_read_ics(core->mac[ICS]);
2553 return core->mac[ICS];
2554 }
2555
2556 static uint32_t
2557 e1000e_mac_ims_read(E1000ECore *core, int index)
2558 {
2559 trace_e1000e_irq_read_ims(core->mac[IMS]);
2560 return core->mac[IMS];
2561 }
2562
2563 #define E1000E_LOW_BITS_READ_FUNC(num) \
2564 static uint32_t \
2565 e1000e_mac_low##num##_read(E1000ECore *core, int index) \
2566 { \
2567 return core->mac[index] & (BIT(num) - 1); \
2568 } \
2569
2570 #define E1000E_LOW_BITS_READ(num) \
2571 e1000e_mac_low##num##_read
2572
2573 E1000E_LOW_BITS_READ_FUNC(4);
2574 E1000E_LOW_BITS_READ_FUNC(6);
2575 E1000E_LOW_BITS_READ_FUNC(11);
2576 E1000E_LOW_BITS_READ_FUNC(13);
2577 E1000E_LOW_BITS_READ_FUNC(16);
2578
2579 static uint32_t
2580 e1000e_mac_swsm_read(E1000ECore *core, int index)
2581 {
2582 uint32_t val = core->mac[SWSM];
2583 core->mac[SWSM] = val | 1;
2584 return val;
2585 }
2586
2587 static uint32_t
2588 e1000e_mac_itr_read(E1000ECore *core, int index)
2589 {
2590 return core->itr_guest_value;
2591 }
2592
2593 static uint32_t
2594 e1000e_mac_eitr_read(E1000ECore *core, int index)
2595 {
2596 return core->eitr_guest_value[index - EITR];
2597 }
2598
2599 static uint32_t
2600 e1000e_mac_icr_read(E1000ECore *core, int index)
2601 {
2602 uint32_t ret = core->mac[ICR];
2603 trace_e1000e_irq_icr_read_entry(ret);
2604
2605 if (core->mac[IMS] == 0) {
2606 trace_e1000e_irq_icr_clear_zero_ims();
2607 core->mac[ICR] = 0;
2608 }
2609
2610 if (!msix_enabled(core->owner)) {
2611 trace_e1000e_irq_icr_clear_nonmsix_icr_read();
2612 core->mac[ICR] = 0;
2613 }
2614
2615 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2616 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2617 trace_e1000e_irq_icr_clear_iame();
2618 core->mac[ICR] = 0;
2619 trace_e1000e_irq_icr_process_iame();
2620 e1000e_clear_ims_bits(core, core->mac[IAM]);
2621 }
2622
2623 trace_e1000e_irq_icr_read_exit(core->mac[ICR]);
2624 e1000e_update_interrupt_state(core);
2625 return ret;
2626 }
2627
2628 static uint32_t
2629 e1000e_mac_read_clr4(E1000ECore *core, int index)
2630 {
2631 uint32_t ret = core->mac[index];
2632
2633 core->mac[index] = 0;
2634 return ret;
2635 }
2636
2637 static uint32_t
2638 e1000e_mac_read_clr8(E1000ECore *core, int index)
2639 {
2640 uint32_t ret = core->mac[index];
2641
2642 core->mac[index] = 0;
2643 core->mac[index - 1] = 0;
2644 return ret;
2645 }
2646
2647 static uint32_t
2648 e1000e_get_ctrl(E1000ECore *core, int index)
2649 {
2650 uint32_t val = core->mac[CTRL];
2651
2652 trace_e1000e_link_read_params(
2653 !!(val & E1000_CTRL_ASDE),
2654 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2655 !!(val & E1000_CTRL_FRCSPD),
2656 !!(val & E1000_CTRL_FRCDPX),
2657 !!(val & E1000_CTRL_RFCE),
2658 !!(val & E1000_CTRL_TFCE));
2659
2660 return val;
2661 }
2662
2663 static uint32_t
2664 e1000e_get_status(E1000ECore *core, int index)
2665 {
2666 uint32_t res = core->mac[STATUS];
2667
2668 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) {
2669 res |= E1000_STATUS_GIO_MASTER_ENABLE;
2670 }
2671
2672 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) {
2673 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0;
2674 } else {
2675 res |= E1000_STATUS_FD;
2676 }
2677
2678 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) ||
2679 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) {
2680 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) {
2681 case E1000_CTRL_SPD_10:
2682 res |= E1000_STATUS_SPEED_10;
2683 break;
2684 case E1000_CTRL_SPD_100:
2685 res |= E1000_STATUS_SPEED_100;
2686 break;
2687 case E1000_CTRL_SPD_1000:
2688 default:
2689 res |= E1000_STATUS_SPEED_1000;
2690 break;
2691 }
2692 } else {
2693 res |= E1000_STATUS_SPEED_1000;
2694 }
2695
2696 trace_e1000e_link_status(
2697 !!(res & E1000_STATUS_LU),
2698 !!(res & E1000_STATUS_FD),
2699 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT,
2700 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT);
2701
2702 return res;
2703 }
2704
2705 static uint32_t
2706 e1000e_get_tarc(E1000ECore *core, int index)
2707 {
2708 return core->mac[index] & ((BIT(11) - 1) |
2709 BIT(27) |
2710 BIT(28) |
2711 BIT(29) |
2712 BIT(30));
2713 }
2714
2715 static void
2716 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val)
2717 {
2718 core->mac[index] = val;
2719 }
2720
2721 static void
2722 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val)
2723 {
2724 uint32_t macaddr[2];
2725
2726 core->mac[index] = val;
2727
2728 macaddr[0] = cpu_to_le32(core->mac[RA]);
2729 macaddr[1] = cpu_to_le32(core->mac[RA + 1]);
2730 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic),
2731 (uint8_t *) macaddr);
2732
2733 trace_e1000e_mac_set_sw(MAC_ARG(macaddr));
2734 }
2735
2736 static void
2737 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val)
2738 {
2739 static const uint32_t ro_bits = E1000_EECD_PRES |
2740 E1000_EECD_AUTO_RD |
2741 E1000_EECD_SIZE_EX_MASK;
2742
2743 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);
2744 }
2745
2746 static void
2747 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val)
2748 {
2749 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2750 uint32_t flags = 0;
2751 uint32_t data = 0;
2752
2753 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2754 data = core->eeprom[addr];
2755 flags = E1000_EERW_DONE;
2756 }
2757
2758 core->mac[EERD] = flags |
2759 (addr << E1000_EERW_ADDR_SHIFT) |
2760 (data << E1000_EERW_DATA_SHIFT);
2761 }
2762
2763 static void
2764 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val)
2765 {
2766 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2767 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK;
2768 uint32_t flags = 0;
2769
2770 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2771 core->eeprom[addr] = data;
2772 flags = E1000_EERW_DONE;
2773 }
2774
2775 core->mac[EERD] = flags |
2776 (addr << E1000_EERW_ADDR_SHIFT) |
2777 (data << E1000_EERW_DATA_SHIFT);
2778 }
2779
2780 static void
2781 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val)
2782 {
2783 core->mac[RXDCTL] = core->mac[RXDCTL1] = val;
2784 }
2785
2786 static void
2787 e1000e_set_itr(E1000ECore *core, int index, uint32_t val)
2788 {
2789 uint32_t interval = val & 0xffff;
2790
2791 trace_e1000e_irq_itr_set(val);
2792
2793 core->itr_guest_value = interval;
2794 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2795 }
2796
2797 static void
2798 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val)
2799 {
2800 uint32_t interval = val & 0xffff;
2801 uint32_t eitr_num = index - EITR;
2802
2803 trace_e1000e_irq_eitr_set(eitr_num, val);
2804
2805 core->eitr_guest_value[eitr_num] = interval;
2806 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2807 }
2808
2809 static void
2810 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val)
2811 {
2812 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) {
2813
2814 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) {
2815 qemu_log_mask(LOG_GUEST_ERROR,
2816 "e1000e: PSRCTL.BSIZE0 cannot be zero");
2817 return;
2818 }
2819
2820 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) {
2821 qemu_log_mask(LOG_GUEST_ERROR,
2822 "e1000e: PSRCTL.BSIZE1 cannot be zero");
2823 return;
2824 }
2825 }
2826
2827 core->mac[PSRCTL] = val;
2828 }
2829
2830 static void
2831 e1000e_update_rx_offloads(E1000ECore *core)
2832 {
2833 int cso_state = e1000e_rx_l4_cso_enabled(core);
2834
2835 trace_e1000e_rx_set_cso(cso_state);
2836
2837 if (core->has_vnet) {
2838 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer,
2839 cso_state, 0, 0, 0, 0);
2840 }
2841 }
2842
2843 static void
2844 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val)
2845 {
2846 core->mac[RXCSUM] = val;
2847 e1000e_update_rx_offloads(core);
2848 }
2849
2850 static void
2851 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val)
2852 {
2853 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS;
2854 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits;
2855 }
2856
2857 #define e1000e_getreg(x) [x] = e1000e_mac_readreg
2858 typedef uint32_t (*readops)(E1000ECore *, int);
2859 static const readops e1000e_macreg_readops[] = {
2860 e1000e_getreg(PBA),
2861 e1000e_getreg(WUFC),
2862 e1000e_getreg(MANC),
2863 e1000e_getreg(TOTL),
2864 e1000e_getreg(RDT0),
2865 e1000e_getreg(RDBAH0),
2866 e1000e_getreg(TDBAL1),
2867 e1000e_getreg(RDLEN0),
2868 e1000e_getreg(RDH1),
2869 e1000e_getreg(LATECOL),
2870 e1000e_getreg(SEQEC),
2871 e1000e_getreg(XONTXC),
2872 e1000e_getreg(WUS),
2873 e1000e_getreg(GORCL),
2874 e1000e_getreg(MGTPRC),
2875 e1000e_getreg(EERD),
2876 e1000e_getreg(EIAC),
2877 e1000e_getreg(PSRCTL),
2878 e1000e_getreg(MANC2H),
2879 e1000e_getreg(RXCSUM),
2880 e1000e_getreg(GSCL_3),
2881 e1000e_getreg(GSCN_2),
2882 e1000e_getreg(RSRPD),
2883 e1000e_getreg(RDBAL1),
2884 e1000e_getreg(FCAH),
2885 e1000e_getreg(FCRTH),
2886 e1000e_getreg(FLOP),
2887 e1000e_getreg(FLASHT),
2888 e1000e_getreg(RXSTMPH),
2889 e1000e_getreg(TXSTMPL),
2890 e1000e_getreg(TIMADJL),
2891 e1000e_getreg(TXDCTL),
2892 e1000e_getreg(RDH0),
2893 e1000e_getreg(TDT1),
2894 e1000e_getreg(TNCRS),
2895 e1000e_getreg(RJC),
2896 e1000e_getreg(IAM),
2897 e1000e_getreg(GSCL_2),
2898 e1000e_getreg(RDBAH1),
2899 e1000e_getreg(FLSWDATA),
2900 e1000e_getreg(RXSATRH),
2901 e1000e_getreg(TIPG),
2902 e1000e_getreg(FLMNGCTL),
2903 e1000e_getreg(FLMNGCNT),
2904 e1000e_getreg(TSYNCTXCTL),
2905 e1000e_getreg(EXTCNF_SIZE),
2906 e1000e_getreg(EXTCNF_CTRL),
2907 e1000e_getreg(EEMNGDATA),
2908 e1000e_getreg(CTRL_EXT),
2909 e1000e_getreg(SYSTIMH),
2910 e1000e_getreg(EEMNGCTL),
2911 e1000e_getreg(FLMNGDATA),
2912 e1000e_getreg(TSYNCRXCTL),
2913 e1000e_getreg(TDH),
2914 e1000e_getreg(LEDCTL),
2915 e1000e_getreg(TCTL),
2916 e1000e_getreg(TDBAL),
2917 e1000e_getreg(TDLEN),
2918 e1000e_getreg(TDH1),
2919 e1000e_getreg(RADV),
2920 e1000e_getreg(ECOL),
2921 e1000e_getreg(DC),
2922 e1000e_getreg(RLEC),
2923 e1000e_getreg(XOFFTXC),
2924 e1000e_getreg(RFC),
2925 e1000e_getreg(RNBC),
2926 e1000e_getreg(MGTPTC),
2927 e1000e_getreg(TIMINCA),
2928 e1000e_getreg(RXCFGL),
2929 e1000e_getreg(MFUTP01),
2930 e1000e_getreg(FACTPS),
2931 e1000e_getreg(GSCL_1),
2932 e1000e_getreg(GSCN_0),
2933 e1000e_getreg(GCR2),
2934 e1000e_getreg(RDT1),
2935 e1000e_getreg(PBACLR),
2936 e1000e_getreg(FCTTV),
2937 e1000e_getreg(EEWR),
2938 e1000e_getreg(FLSWCTL),
2939 e1000e_getreg(RXDCTL1),
2940 e1000e_getreg(RXSATRL),
2941 e1000e_getreg(SYSTIML),
2942 e1000e_getreg(RXUDP),
2943 e1000e_getreg(TORL),
2944 e1000e_getreg(TDLEN1),
2945 e1000e_getreg(MCC),
2946 e1000e_getreg(WUC),
2947 e1000e_getreg(EECD),
2948 e1000e_getreg(MFUTP23),
2949 e1000e_getreg(RAID),
2950 e1000e_getreg(FCRTV),
2951 e1000e_getreg(TXDCTL1),
2952 e1000e_getreg(RCTL),
2953 e1000e_getreg(TDT),
2954 e1000e_getreg(MDIC),
2955 e1000e_getreg(FCRUC),
2956 e1000e_getreg(VET),
2957 e1000e_getreg(RDBAL0),
2958 e1000e_getreg(TDBAH1),
2959 e1000e_getreg(RDTR),
2960 e1000e_getreg(SCC),
2961 e1000e_getreg(COLC),
2962 e1000e_getreg(CEXTERR),
2963 e1000e_getreg(XOFFRXC),
2964 e1000e_getreg(IPAV),
2965 e1000e_getreg(GOTCL),
2966 e1000e_getreg(MGTPDC),
2967 e1000e_getreg(GCR),
2968 e1000e_getreg(IVAR),
2969 e1000e_getreg(POEMB),
2970 e1000e_getreg(MFVAL),
2971 e1000e_getreg(FUNCTAG),
2972 e1000e_getreg(GSCL_4),
2973 e1000e_getreg(GSCN_3),
2974 e1000e_getreg(MRQC),
2975 e1000e_getreg(RDLEN1),
2976 e1000e_getreg(FCT),
2977 e1000e_getreg(FLA),
2978 e1000e_getreg(FLOL),
2979 e1000e_getreg(RXDCTL),
2980 e1000e_getreg(RXSTMPL),
2981 e1000e_getreg(TXSTMPH),
2982 e1000e_getreg(TIMADJH),
2983 e1000e_getreg(FCRTL),
2984 e1000e_getreg(TDBAH),
2985 e1000e_getreg(TADV),
2986 e1000e_getreg(XONRXC),
2987 e1000e_getreg(TSCTFC),
2988 e1000e_getreg(RFCTL),
2989 e1000e_getreg(GSCN_1),
2990 e1000e_getreg(FCAL),
2991 e1000e_getreg(FLSWCNT),
2992
2993 [TOTH] = e1000e_mac_read_clr8,
2994 [GOTCH] = e1000e_mac_read_clr8,
2995 [PRC64] = e1000e_mac_read_clr4,
2996 [PRC255] = e1000e_mac_read_clr4,
2997 [PRC1023] = e1000e_mac_read_clr4,
2998 [PTC64] = e1000e_mac_read_clr4,
2999 [PTC255] = e1000e_mac_read_clr4,
3000 [PTC1023] = e1000e_mac_read_clr4,
3001 [GPRC] = e1000e_mac_read_clr4,
3002 [TPT] = e1000e_mac_read_clr4,
3003 [RUC] = e1000e_mac_read_clr4,
3004 [BPRC] = e1000e_mac_read_clr4,
3005 [MPTC] = e1000e_mac_read_clr4,
3006 [IAC] = e1000e_mac_read_clr4,
3007 [ICR] = e1000e_mac_icr_read,
3008 [RDFH] = E1000E_LOW_BITS_READ(13),
3009 [RDFHS] = E1000E_LOW_BITS_READ(13),
3010 [RDFPC] = E1000E_LOW_BITS_READ(13),
3011 [TDFH] = E1000E_LOW_BITS_READ(13),
3012 [TDFHS] = E1000E_LOW_BITS_READ(13),
3013 [STATUS] = e1000e_get_status,
3014 [TARC0] = e1000e_get_tarc,
3015 [PBS] = E1000E_LOW_BITS_READ(6),
3016 [ICS] = e1000e_mac_ics_read,
3017 [AIT] = E1000E_LOW_BITS_READ(16),
3018 [TORH] = e1000e_mac_read_clr8,
3019 [GORCH] = e1000e_mac_read_clr8,
3020 [PRC127] = e1000e_mac_read_clr4,
3021 [PRC511] = e1000e_mac_read_clr4,
3022 [PRC1522] = e1000e_mac_read_clr4,
3023 [PTC127] = e1000e_mac_read_clr4,
3024 [PTC511] = e1000e_mac_read_clr4,
3025 [PTC1522] = e1000e_mac_read_clr4,
3026 [GPTC] = e1000e_mac_read_clr4,
3027 [TPR] = e1000e_mac_read_clr4,
3028 [ROC] = e1000e_mac_read_clr4,
3029 [MPRC] = e1000e_mac_read_clr4,
3030 [BPTC] = e1000e_mac_read_clr4,
3031 [TSCTC] = e1000e_mac_read_clr4,
3032 [ITR] = e1000e_mac_itr_read,
3033 [RDFT] = E1000E_LOW_BITS_READ(13),
3034 [RDFTS] = E1000E_LOW_BITS_READ(13),
3035 [TDFPC] = E1000E_LOW_BITS_READ(13),
3036 [TDFT] = E1000E_LOW_BITS_READ(13),
3037 [TDFTS] = E1000E_LOW_BITS_READ(13),
3038 [CTRL] = e1000e_get_ctrl,
3039 [TARC1] = e1000e_get_tarc,
3040 [SWSM] = e1000e_mac_swsm_read,
3041 [IMS] = e1000e_mac_ims_read,
3042
3043 [CRCERRS ... MPC] = e1000e_mac_readreg,
3044 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg,
3045 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg,
3046 [RA ... RA + 31] = e1000e_mac_readreg,
3047 [WUPM ... WUPM + 31] = e1000e_mac_readreg,
3048 [MTA ... MTA + 127] = e1000e_mac_readreg,
3049 [VFTA ... VFTA + 127] = e1000e_mac_readreg,
3050 [FFMT ... FFMT + 254] = E1000E_LOW_BITS_READ(4),
3051 [FFVT ... FFVT + 254] = e1000e_mac_readreg,
3052 [MDEF ... MDEF + 7] = e1000e_mac_readreg,
3053 [FFLT ... FFLT + 10] = E1000E_LOW_BITS_READ(11),
3054 [FTFT ... FTFT + 254] = e1000e_mac_readreg,
3055 [PBM ... PBM + 10239] = e1000e_mac_readreg,
3056 [RETA ... RETA + 31] = e1000e_mac_readreg,
3057 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg,
3058 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg,
3059 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read
3060 };
3061 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) };
3062
3063 #define e1000e_putreg(x) [x] = e1000e_mac_writereg
3064 typedef void (*writeops)(E1000ECore *, int, uint32_t);
3065 static const writeops e1000e_macreg_writeops[] = {
3066 e1000e_putreg(PBA),
3067 e1000e_putreg(SWSM),
3068 e1000e_putreg(WUFC),
3069 e1000e_putreg(RDBAH1),
3070 e1000e_putreg(TDBAH),
3071 e1000e_putreg(TXDCTL),
3072 e1000e_putreg(RDBAH0),
3073 e1000e_putreg(LEDCTL),
3074 e1000e_putreg(FCAL),
3075 e1000e_putreg(FCRUC),
3076 e1000e_putreg(AIT),
3077 e1000e_putreg(TDFH),
3078 e1000e_putreg(TDFT),
3079 e1000e_putreg(TDFHS),
3080 e1000e_putreg(TDFTS),
3081 e1000e_putreg(TDFPC),
3082 e1000e_putreg(WUC),
3083 e1000e_putreg(WUS),
3084 e1000e_putreg(RDFH),
3085 e1000e_putreg(RDFT),
3086 e1000e_putreg(RDFHS),
3087 e1000e_putreg(RDFTS),
3088 e1000e_putreg(RDFPC),
3089 e1000e_putreg(IPAV),
3090 e1000e_putreg(TDBAH1),
3091 e1000e_putreg(TIMINCA),
3092 e1000e_putreg(IAM),
3093 e1000e_putreg(EIAC),
3094 e1000e_putreg(IVAR),
3095 e1000e_putreg(TARC0),
3096 e1000e_putreg(TARC1),
3097 e1000e_putreg(FLSWDATA),
3098 e1000e_putreg(POEMB),
3099 e1000e_putreg(PBS),
3100 e1000e_putreg(MFUTP01),
3101 e1000e_putreg(MFUTP23),
3102 e1000e_putreg(MANC),
3103 e1000e_putreg(MANC2H),
3104 e1000e_putreg(MFVAL),
3105 e1000e_putreg(EXTCNF_CTRL),
3106 e1000e_putreg(FACTPS),
3107 e1000e_putreg(FUNCTAG),
3108 e1000e_putreg(GSCL_1),
3109 e1000e_putreg(GSCL_2),
3110 e1000e_putreg(GSCL_3),
3111 e1000e_putreg(GSCL_4),
3112 e1000e_putreg(GSCN_0),
3113 e1000e_putreg(GSCN_1),
3114 e1000e_putreg(GSCN_2),
3115 e1000e_putreg(GSCN_3),
3116 e1000e_putreg(GCR2),
3117 e1000e_putreg(MRQC),
3118 e1000e_putreg(FLOP),
3119 e1000e_putreg(FLOL),
3120 e1000e_putreg(FLSWCTL),
3121 e1000e_putreg(FLSWCNT),
3122 e1000e_putreg(FLA),
3123 e1000e_putreg(RXDCTL1),
3124 e1000e_putreg(TXDCTL1),
3125 e1000e_putreg(TIPG),
3126 e1000e_putreg(RXSTMPH),
3127 e1000e_putreg(RXSTMPL),
3128 e1000e_putreg(RXSATRL),
3129 e1000e_putreg(RXSATRH),
3130 e1000e_putreg(TXSTMPL),
3131 e1000e_putreg(TXSTMPH),
3132 e1000e_putreg(SYSTIML),
3133 e1000e_putreg(SYSTIMH),
3134 e1000e_putreg(TIMADJL),
3135 e1000e_putreg(TIMADJH),
3136 e1000e_putreg(RXUDP),
3137 e1000e_putreg(RXCFGL),
3138 e1000e_putreg(TSYNCRXCTL),
3139 e1000e_putreg(TSYNCTXCTL),
3140 e1000e_putreg(EXTCNF_SIZE),
3141 e1000e_putreg(EEMNGCTL),
3142 e1000e_putreg(RA),
3143
3144 [TDH1] = e1000e_set_16bit,
3145 [TDT1] = e1000e_set_tdt,
3146 [TCTL] = e1000e_set_tctl,
3147 [TDT] = e1000e_set_tdt,
3148 [MDIC] = e1000e_set_mdic,
3149 [ICS] = e1000e_set_ics,
3150 [TDH] = e1000e_set_16bit,
3151 [RDH0] = e1000e_set_16bit,
3152 [RDT0] = e1000e_set_rdt,
3153 [IMC] = e1000e_set_imc,
3154 [IMS] = e1000e_set_ims,
3155 [ICR] = e1000e_set_icr,
3156 [EECD] = e1000e_set_eecd,
3157 [RCTL] = e1000e_set_rx_control,
3158 [CTRL] = e1000e_set_ctrl,
3159 [RDTR] = e1000e_set_rdtr,
3160 [RADV] = e1000e_set_16bit,
3161 [TADV] = e1000e_set_16bit,
3162 [ITR] = e1000e_set_itr,
3163 [EERD] = e1000e_set_eerd,
3164 [GCR] = e1000e_set_gcr,
3165 [PSRCTL] = e1000e_set_psrctl,
3166 [RXCSUM] = e1000e_set_rxcsum,
3167 [RAID] = e1000e_set_16bit,
3168 [RSRPD] = e1000e_set_12bit,
3169 [TIDV] = e1000e_set_tidv,
3170 [TDLEN1] = e1000e_set_dlen,
3171 [TDLEN] = e1000e_set_dlen,
3172 [RDLEN0] = e1000e_set_dlen,
3173 [RDLEN1] = e1000e_set_dlen,
3174 [TDBAL] = e1000e_set_dbal,
3175 [TDBAL1] = e1000e_set_dbal,
3176 [RDBAL0] = e1000e_set_dbal,
3177 [RDBAL1] = e1000e_set_dbal,
3178 [RDH1] = e1000e_set_16bit,
3179 [RDT1] = e1000e_set_rdt,
3180 [STATUS] = e1000e_set_status,
3181 [PBACLR] = e1000e_set_pbaclr,
3182 [CTRL_EXT] = e1000e_set_ctrlext,
3183 [FCAH] = e1000e_set_16bit,
3184 [FCT] = e1000e_set_16bit,
3185 [FCTTV] = e1000e_set_16bit,
3186 [FCRTV] = e1000e_set_16bit,
3187 [FCRTH] = e1000e_set_fcrth,
3188 [FCRTL] = e1000e_set_fcrtl,
3189 [VET] = e1000e_set_vet,
3190 [RXDCTL] = e1000e_set_rxdctl,
3191 [FLASHT] = e1000e_set_16bit,
3192 [EEWR] = e1000e_set_eewr,
3193 [CTRL_DUP] = e1000e_set_ctrl,
3194 [RFCTL] = e1000e_set_rfctl,
3195 [RA + 1] = e1000e_mac_setmacaddr,
3196
3197 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg,
3198 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg,
3199 [RA + 2 ... RA + 31] = e1000e_mac_writereg,
3200 [WUPM ... WUPM + 31] = e1000e_mac_writereg,
3201 [MTA ... MTA + 127] = e1000e_mac_writereg,
3202 [VFTA ... VFTA + 127] = e1000e_mac_writereg,
3203 [FFMT ... FFMT + 254] = e1000e_mac_writereg,
3204 [FFVT ... FFVT + 254] = e1000e_mac_writereg,
3205 [PBM ... PBM + 10239] = e1000e_mac_writereg,
3206 [MDEF ... MDEF + 7] = e1000e_mac_writereg,
3207 [FFLT ... FFLT + 10] = e1000e_mac_writereg,
3208 [FTFT ... FTFT + 254] = e1000e_mac_writereg,
3209 [RETA ... RETA + 31] = e1000e_mac_writereg,
3210 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg,
3211 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg,
3212 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr
3213 };
3214 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) };
3215
3216 enum { MAC_ACCESS_PARTIAL = 1 };
3217
3218 /* The array below combines alias offsets of the index values for the
3219 * MAC registers that have aliases, with the indication of not fully
3220 * implemented registers (lowest bit). This combination is possible
3221 * because all of the offsets are even. */
3222 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = {
3223 /* Alias index offsets */
3224 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802,
3225 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6,
3226 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904,
3227 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8,
3228 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00,
3229 [RA_A ... RA_A + 31] = 0x14f0,
3230 [VFTA_A ... VFTA_A + 127] = 0x1400,
3231 [RDBAL0_A ... RDLEN0_A] = 0x09bc,
3232 [TDBAL_A ... TDLEN_A] = 0x0cf8,
3233 /* Access options */
3234 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL,
3235 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL,
3236 [RDFPC] = MAC_ACCESS_PARTIAL,
3237 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL,
3238 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL,
3239 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL,
3240 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL,
3241 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL,
3242 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL,
3243 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL,
3244 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL,
3245 [TXDCTL1] = MAC_ACCESS_PARTIAL,
3246 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL
3247 };
3248
3249 void
3250 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size)
3251 {
3252 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3253
3254 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) {
3255 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3256 trace_e1000e_wrn_regs_write_trivial(index << 2);
3257 }
3258 trace_e1000e_core_write(index << 2, size, val);
3259 e1000e_macreg_writeops[index](core, index, val);
3260 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3261 trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3262 } else {
3263 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3264 }
3265 }
3266
3267 uint64_t
3268 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size)
3269 {
3270 uint64_t val;
3271 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3272
3273 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3274 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3275 trace_e1000e_wrn_regs_read_trivial(index << 2);
3276 }
3277 val = e1000e_macreg_readops[index](core, index);
3278 trace_e1000e_core_read(index << 2, size, val);
3279 return val;
3280 } else {
3281 trace_e1000e_wrn_regs_read_unknown(index << 2, size);
3282 }
3283 return 0;
3284 }
3285
3286 static inline void
3287 e1000e_autoneg_pause(E1000ECore *core)
3288 {
3289 timer_del(core->autoneg_timer);
3290 }
3291
3292 static void
3293 e1000e_autoneg_resume(E1000ECore *core)
3294 {
3295 if (e1000e_have_autoneg(core) &&
3296 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
3297 qemu_get_queue(core->owner_nic)->link_down = false;
3298 timer_mod(core->autoneg_timer,
3299 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
3300 }
3301 }
3302
3303 static void
3304 e1000e_vm_state_change(void *opaque, bool running, RunState state)
3305 {
3306 E1000ECore *core = opaque;
3307
3308 if (running) {
3309 trace_e1000e_vm_state_running();
3310 e1000e_intrmgr_resume(core);
3311 e1000e_autoneg_resume(core);
3312 } else {
3313 trace_e1000e_vm_state_stopped();
3314 e1000e_autoneg_pause(core);
3315 e1000e_intrmgr_pause(core);
3316 }
3317 }
3318
3319 void
3320 e1000e_core_pci_realize(E1000ECore *core,
3321 const uint16_t *eeprom_templ,
3322 uint32_t eeprom_size,
3323 const uint8_t *macaddr)
3324 {
3325 int i;
3326
3327 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3328 e1000e_autoneg_timer, core);
3329 e1000e_intrmgr_pci_realize(core);
3330
3331 core->vmstate =
3332 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core);
3333
3334 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3335 net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner,
3336 E1000E_MAX_TX_FRAGS, core->has_vnet);
3337 }
3338
3339 net_rx_pkt_init(&core->rx_pkt, core->has_vnet);
3340
3341 e1000x_core_prepare_eeprom(core->eeprom,
3342 eeprom_templ,
3343 eeprom_size,
3344 PCI_DEVICE_GET_CLASS(core->owner)->device_id,
3345 macaddr);
3346 e1000e_update_rx_offloads(core);
3347 }
3348
3349 void
3350 e1000e_core_pci_uninit(E1000ECore *core)
3351 {
3352 int i;
3353
3354 timer_free(core->autoneg_timer);
3355
3356 e1000e_intrmgr_pci_unint(core);
3357
3358 qemu_del_vm_change_state_handler(core->vmstate);
3359
3360 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3361 net_tx_pkt_reset(core->tx[i].tx_pkt);
3362 net_tx_pkt_uninit(core->tx[i].tx_pkt);
3363 }
3364
3365 net_rx_pkt_uninit(core->rx_pkt);
3366 }
3367
3368 static const uint16_t
3369 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {
3370 [0] = {
3371 [PHY_CTRL] = MII_CR_SPEED_SELECT_MSB |
3372 MII_CR_FULL_DUPLEX |
3373 MII_CR_AUTO_NEG_EN,
3374
3375 [PHY_STATUS] = MII_SR_EXTENDED_CAPS |
3376 MII_SR_LINK_STATUS |
3377 MII_SR_AUTONEG_CAPS |
3378 MII_SR_PREAMBLE_SUPPRESS |
3379 MII_SR_EXTENDED_STATUS |
3380 MII_SR_10T_HD_CAPS |
3381 MII_SR_10T_FD_CAPS |
3382 MII_SR_100X_HD_CAPS |
3383 MII_SR_100X_FD_CAPS,
3384
3385 [PHY_ID1] = 0x141,
3386 [PHY_ID2] = E1000_PHY_ID2_82574x,
3387 [PHY_AUTONEG_ADV] = 0xde1,
3388 [PHY_LP_ABILITY] = 0x7e0,
3389 [PHY_AUTONEG_EXP] = BIT(2),
3390 [PHY_NEXT_PAGE_TX] = BIT(0) | BIT(13),
3391 [PHY_1000T_CTRL] = BIT(8) | BIT(9) | BIT(10) | BIT(11),
3392 [PHY_1000T_STATUS] = 0x3c00,
3393 [PHY_EXT_STATUS] = BIT(12) | BIT(13),
3394
3395 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) |
3396 BIT(12) | BIT(13),
3397 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15)
3398 },
3399 [2] = {
3400 [PHY_MAC_CTRL1] = BIT(3) | BIT(7),
3401 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12)
3402 },
3403 [3] = {
3404 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14)
3405 }
3406 };
3407
3408 static const uint32_t e1000e_mac_reg_init[] = {
3409 [PBA] = 0x00140014,
3410 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18),
3411 [EXTCNF_CTRL] = BIT(3),
3412 [EEMNGCTL] = BIT(31),
3413 [FLASHT] = 0x2,
3414 [FLSWCTL] = BIT(30) | BIT(31),
3415 [FLOL] = BIT(0),
3416 [RXDCTL] = BIT(16),
3417 [RXDCTL1] = BIT(16),
3418 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20),
3419 [RXCFGL] = 0x88F7,
3420 [RXUDP] = 0x319,
3421 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
3422 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU |
3423 E1000_CTRL_ADVD3WUC,
3424 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU,
3425 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) |
3426 (4 << E1000_PSRCTL_BSIZE1_SHIFT) |
3427 (4 << E1000_PSRCTL_BSIZE2_SHIFT),
3428 [TARC0] = 0x3 | E1000_TARC_ENABLE,
3429 [TARC1] = 0x3 | E1000_TARC_ENABLE,
3430 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES,
3431 [EERD] = E1000_EERW_DONE,
3432 [EEWR] = E1000_EERW_DONE,
3433 [GCR] = E1000_L0S_ADJUST |
3434 E1000_L1_ENTRY_LATENCY_MSB |
3435 E1000_L1_ENTRY_LATENCY_LSB,
3436 [TDFH] = 0x600,
3437 [TDFT] = 0x600,
3438 [TDFHS] = 0x600,
3439 [TDFTS] = 0x600,
3440 [POEMB] = 0x30D,
3441 [PBS] = 0x028,
3442 [MANC] = E1000_MANC_DIS_IP_CHK_ARP,
3443 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000,
3444 [SWSM] = 1,
3445 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD,
3446 [ITR] = E1000E_MIN_XITR,
3447 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR,
3448 };
3449
3450 void
3451 e1000e_core_reset(E1000ECore *core)
3452 {
3453 int i;
3454
3455 timer_del(core->autoneg_timer);
3456
3457 e1000e_intrmgr_reset(core);
3458
3459 memset(core->phy, 0, sizeof core->phy);
3460 memmove(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init);
3461 memset(core->mac, 0, sizeof core->mac);
3462 memmove(core->mac, e1000e_mac_reg_init, sizeof e1000e_mac_reg_init);
3463
3464 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT;
3465
3466 if (qemu_get_queue(core->owner_nic)->link_down) {
3467 e1000e_link_down(core);
3468 }
3469
3470 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
3471
3472 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3473 net_tx_pkt_reset(core->tx[i].tx_pkt);
3474 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props));
3475 core->tx[i].skip_cp = false;
3476 }
3477 }
3478
3479 void e1000e_core_pre_save(E1000ECore *core)
3480 {
3481 int i;
3482 NetClientState *nc = qemu_get_queue(core->owner_nic);
3483
3484 /*
3485 * If link is down and auto-negotiation is supported and ongoing,
3486 * complete auto-negotiation immediately. This allows us to look
3487 * at MII_SR_AUTONEG_COMPLETE to infer link status on load.
3488 */
3489 if (nc->link_down && e1000e_have_autoneg(core)) {
3490 core->phy[0][PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE;
3491 e1000e_update_flowctl_status(core);
3492 }
3493
3494 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3495 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) {
3496 core->tx[i].skip_cp = true;
3497 }
3498 }
3499 }
3500
3501 int
3502 e1000e_core_post_load(E1000ECore *core)
3503 {
3504 NetClientState *nc = qemu_get_queue(core->owner_nic);
3505
3506 /* nc.link_down can't be migrated, so infer link_down according
3507 * to link status bit in core.mac[STATUS].
3508 */
3509 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
3510
3511 return 0;
3512 }
QEmu