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Merge tag 'qemu-macppc-20230206' of https://github.com/mcayland/qemu into staging
[qemu.git] / hw / net / e1000e_core.c
blobfc9cdb4528d9ab3b87f47e70b6ae7ebb19dca1c5
1 /*
2 * Core code for QEMU e1000e emulation
3 *
4 * Software developer's manuals:
5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
6 *
7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
8 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 *
10 * Authors:
11 * Dmitry Fleytman <dmitry@daynix.com>
12 * Leonid Bloch <leonid@daynix.com>
13 * Yan Vugenfirer <yan@daynix.com>
14 *
15 * Based on work done by:
16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
17 * Copyright (c) 2008 Qumranet
18 * Based on work done by:
19 * Copyright (c) 2007 Dan Aloni
20 * Copyright (c) 2004 Antony T Curtis
21 *
22 * This library is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU Lesser General Public
24 * License as published by the Free Software Foundation; either
25 * version 2.1 of the License, or (at your option) any later version.
26 *
27 * This library is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
30 * Lesser General Public License for more details.
31 *
32 * You should have received a copy of the GNU Lesser General Public
33 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
34 */
35
36 #include "qemu/osdep.h"
37 #include "qemu/log.h"
38 #include "net/net.h"
39 #include "net/tap.h"
40 #include "hw/pci/msi.h"
41 #include "hw/pci/msix.h"
42 #include "sysemu/runstate.h"
43
44 #include "net_tx_pkt.h"
45 #include "net_rx_pkt.h"
46
47 #include "e1000x_common.h"
48 #include "e1000e_core.h"
49
50 #include "trace.h"
51
52 #define E1000E_MIN_XITR (500) /* No more then 7813 interrupts per
53 second according to spec 10.2.4.2 */
54 #define E1000E_MAX_TX_FRAGS (64)
55
56 static inline void
57 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val);
58
59 static inline void
60 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp)
61 {
62 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) {
63 trace_e1000e_wrn_no_ts_support();
64 }
65 }
66
67 static inline void
68 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length)
69 {
70 if (cmd_and_length & E1000_TXD_CMD_SNAP) {
71 trace_e1000e_wrn_no_snap_support();
72 }
73 }
74
75 static inline void
76 e1000e_raise_legacy_irq(E1000ECore *core)
77 {
78 trace_e1000e_irq_legacy_notify(true);
79 e1000x_inc_reg_if_not_full(core->mac, IAC);
80 pci_set_irq(core->owner, 1);
81 }
82
83 static inline void
84 e1000e_lower_legacy_irq(E1000ECore *core)
85 {
86 trace_e1000e_irq_legacy_notify(false);
87 pci_set_irq(core->owner, 0);
88 }
89
90 static inline void
91 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer)
92 {
93 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] *
94 timer->delay_resolution_ns;
95
96 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
97
98 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
99
100 timer->running = true;
101 }
102
103 static void
104 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer)
105 {
106 if (timer->running) {
107 e1000e_intrmgr_rearm_timer(timer);
108 }
109 }
110
111 static void
112 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer)
113 {
114 if (timer->running) {
115 timer_del(timer->timer);
116 }
117 }
118
119 static inline void
120 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer)
121 {
122 if (timer->running) {
123 timer_del(timer->timer);
124 timer->running = false;
125 }
126 }
127
128 static inline void
129 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core)
130 {
131 trace_e1000e_irq_fire_delayed_interrupts();
132 e1000e_set_interrupt_cause(core, 0);
133 }
134
135 static void
136 e1000e_intrmgr_on_timer(void *opaque)
137 {
138 E1000IntrDelayTimer *timer = opaque;
139
140 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2);
141
142 timer->running = false;
143 e1000e_intrmgr_fire_delayed_interrupts(timer->core);
144 }
145
146 static void
147 e1000e_intrmgr_on_throttling_timer(void *opaque)
148 {
149 E1000IntrDelayTimer *timer = opaque;
150
151 assert(!msix_enabled(timer->core->owner));
152
153 timer->running = false;
154
155 if (!timer->core->itr_intr_pending) {
156 trace_e1000e_irq_throttling_no_pending_interrupts();
157 return;
158 }
159
160 if (msi_enabled(timer->core->owner)) {
161 trace_e1000e_irq_msi_notify_postponed();
162 /* Clear msi_causes_pending to fire MSI eventually */
163 timer->core->msi_causes_pending = 0;
164 e1000e_set_interrupt_cause(timer->core, 0);
165 } else {
166 trace_e1000e_irq_legacy_notify_postponed();
167 e1000e_set_interrupt_cause(timer->core, 0);
168 }
169 }
170
171 static void
172 e1000e_intrmgr_on_msix_throttling_timer(void *opaque)
173 {
174 E1000IntrDelayTimer *timer = opaque;
175 int idx = timer - &timer->core->eitr[0];
176
177 assert(msix_enabled(timer->core->owner));
178
179 timer->running = false;
180
181 if (!timer->core->eitr_intr_pending[idx]) {
182 trace_e1000e_irq_throttling_no_pending_vec(idx);
183 return;
184 }
185
186 trace_e1000e_irq_msix_notify_postponed_vec(idx);
187 msix_notify(timer->core->owner, idx);
188 }
189
190 static void
191 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create)
192 {
193 int i;
194
195 core->radv.delay_reg = RADV;
196 core->rdtr.delay_reg = RDTR;
197 core->raid.delay_reg = RAID;
198 core->tadv.delay_reg = TADV;
199 core->tidv.delay_reg = TIDV;
200
201 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
202 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
203 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
204 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
205 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
206
207 core->radv.core = core;
208 core->rdtr.core = core;
209 core->raid.core = core;
210 core->tadv.core = core;
211 core->tidv.core = core;
212
213 core->itr.core = core;
214 core->itr.delay_reg = ITR;
215 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
216
217 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
218 core->eitr[i].core = core;
219 core->eitr[i].delay_reg = EITR + i;
220 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
221 }
222
223 if (!create) {
224 return;
225 }
226
227 core->radv.timer =
228 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv);
229 core->rdtr.timer =
230 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr);
231 core->raid.timer =
232 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid);
233
234 core->tadv.timer =
235 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv);
236 core->tidv.timer =
237 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv);
238
239 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
240 e1000e_intrmgr_on_throttling_timer,
241 &core->itr);
242
243 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
244 core->eitr[i].timer =
245 timer_new_ns(QEMU_CLOCK_VIRTUAL,
246 e1000e_intrmgr_on_msix_throttling_timer,
247 &core->eitr[i]);
248 }
249 }
250
251 static inline void
252 e1000e_intrmgr_stop_delay_timers(E1000ECore *core)
253 {
254 e1000e_intrmgr_stop_timer(&core->radv);
255 e1000e_intrmgr_stop_timer(&core->rdtr);
256 e1000e_intrmgr_stop_timer(&core->raid);
257 e1000e_intrmgr_stop_timer(&core->tidv);
258 e1000e_intrmgr_stop_timer(&core->tadv);
259 }
260
261 static bool
262 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes)
263 {
264 uint32_t delayable_causes;
265 uint32_t rdtr = core->mac[RDTR];
266 uint32_t radv = core->mac[RADV];
267 uint32_t raid = core->mac[RAID];
268
269 if (msix_enabled(core->owner)) {
270 return false;
271 }
272
273 delayable_causes = E1000_ICR_RXQ0 |
274 E1000_ICR_RXQ1 |
275 E1000_ICR_RXT0;
276
277 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) {
278 delayable_causes |= E1000_ICR_ACK;
279 }
280
281 /* Clean up all causes that may be delayed */
282 core->delayed_causes |= *causes & delayable_causes;
283 *causes &= ~delayable_causes;
284
285 /* Check if delayed RX interrupts disabled by client
286 or if there are causes that cannot be delayed */
287 if ((rdtr == 0) || (*causes != 0)) {
288 return false;
289 }
290
291 /* Check if delayed RX ACK interrupts disabled by client
292 and there is an ACK packet received */
293 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) {
294 return false;
295 }
296
297 /* All causes delayed */
298 e1000e_intrmgr_rearm_timer(&core->rdtr);
299
300 if (!core->radv.running && (radv != 0)) {
301 e1000e_intrmgr_rearm_timer(&core->radv);
302 }
303
304 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) {
305 e1000e_intrmgr_rearm_timer(&core->raid);
306 }
307
308 return true;
309 }
310
311 static bool
312 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes)
313 {
314 static const uint32_t delayable_causes = E1000_ICR_TXQ0 |
315 E1000_ICR_TXQ1 |
316 E1000_ICR_TXQE |
317 E1000_ICR_TXDW;
318
319 if (msix_enabled(core->owner)) {
320 return false;
321 }
322
323 /* Clean up all causes that may be delayed */
324 core->delayed_causes |= *causes & delayable_causes;
325 *causes &= ~delayable_causes;
326
327 /* If there are causes that cannot be delayed */
328 if (*causes != 0) {
329 return false;
330 }
331
332 /* All causes delayed */
333 e1000e_intrmgr_rearm_timer(&core->tidv);
334
335 if (!core->tadv.running && (core->mac[TADV] != 0)) {
336 e1000e_intrmgr_rearm_timer(&core->tadv);
337 }
338
339 return true;
340 }
341
342 static uint32_t
343 e1000e_intmgr_collect_delayed_causes(E1000ECore *core)
344 {
345 uint32_t res;
346
347 if (msix_enabled(core->owner)) {
348 assert(core->delayed_causes == 0);
349 return 0;
350 }
351
352 res = core->delayed_causes;
353 core->delayed_causes = 0;
354
355 e1000e_intrmgr_stop_delay_timers(core);
356
357 return res;
358 }
359
360 static void
361 e1000e_intrmgr_fire_all_timers(E1000ECore *core)
362 {
363 int i;
364 uint32_t val = e1000e_intmgr_collect_delayed_causes(core);
365
366 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]);
367 core->mac[ICR] |= val;
368
369 if (core->itr.running) {
370 timer_del(core->itr.timer);
371 e1000e_intrmgr_on_throttling_timer(&core->itr);
372 }
373
374 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
375 if (core->eitr[i].running) {
376 timer_del(core->eitr[i].timer);
377 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]);
378 }
379 }
380 }
381
382 static void
383 e1000e_intrmgr_resume(E1000ECore *core)
384 {
385 int i;
386
387 e1000e_intmgr_timer_resume(&core->radv);
388 e1000e_intmgr_timer_resume(&core->rdtr);
389 e1000e_intmgr_timer_resume(&core->raid);
390 e1000e_intmgr_timer_resume(&core->tidv);
391 e1000e_intmgr_timer_resume(&core->tadv);
392
393 e1000e_intmgr_timer_resume(&core->itr);
394
395 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
396 e1000e_intmgr_timer_resume(&core->eitr[i]);
397 }
398 }
399
400 static void
401 e1000e_intrmgr_pause(E1000ECore *core)
402 {
403 int i;
404
405 e1000e_intmgr_timer_pause(&core->radv);
406 e1000e_intmgr_timer_pause(&core->rdtr);
407 e1000e_intmgr_timer_pause(&core->raid);
408 e1000e_intmgr_timer_pause(&core->tidv);
409 e1000e_intmgr_timer_pause(&core->tadv);
410
411 e1000e_intmgr_timer_pause(&core->itr);
412
413 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
414 e1000e_intmgr_timer_pause(&core->eitr[i]);
415 }
416 }
417
418 static void
419 e1000e_intrmgr_reset(E1000ECore *core)
420 {
421 int i;
422
423 core->delayed_causes = 0;
424
425 e1000e_intrmgr_stop_delay_timers(core);
426
427 e1000e_intrmgr_stop_timer(&core->itr);
428
429 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
430 e1000e_intrmgr_stop_timer(&core->eitr[i]);
431 }
432 }
433
434 static void
435 e1000e_intrmgr_pci_unint(E1000ECore *core)
436 {
437 int i;
438
439 timer_free(core->radv.timer);
440 timer_free(core->rdtr.timer);
441 timer_free(core->raid.timer);
442
443 timer_free(core->tadv.timer);
444 timer_free(core->tidv.timer);
445
446 timer_free(core->itr.timer);
447
448 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
449 timer_free(core->eitr[i].timer);
450 }
451 }
452
453 static void
454 e1000e_intrmgr_pci_realize(E1000ECore *core)
455 {
456 e1000e_intrmgr_initialize_all_timers(core, true);
457 }
458
459 static inline bool
460 e1000e_rx_csum_enabled(E1000ECore *core)
461 {
462 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true;
463 }
464
465 static inline bool
466 e1000e_rx_use_legacy_descriptor(E1000ECore *core)
467 {
468 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true;
469 }
470
471 static inline bool
472 e1000e_rx_use_ps_descriptor(E1000ECore *core)
473 {
474 return !e1000e_rx_use_legacy_descriptor(core) &&
475 (core->mac[RCTL] & E1000_RCTL_DTYP_PS);
476 }
477
478 static inline bool
479 e1000e_rss_enabled(E1000ECore *core)
480 {
481 return E1000_MRQC_ENABLED(core->mac[MRQC]) &&
482 !e1000e_rx_csum_enabled(core) &&
483 !e1000e_rx_use_legacy_descriptor(core);
484 }
485
486 typedef struct E1000E_RSSInfo_st {
487 bool enabled;
488 uint32_t hash;
489 uint32_t queue;
490 uint32_t type;
491 } E1000E_RSSInfo;
492
493 static uint32_t
494 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt)
495 {
496 bool isip4, isip6, isudp, istcp;
497
498 assert(e1000e_rss_enabled(core));
499
500 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
501
502 if (isip4) {
503 bool fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
504
505 trace_e1000e_rx_rss_ip4(fragment, istcp, core->mac[MRQC],
506 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]),
507 E1000_MRQC_EN_IPV4(core->mac[MRQC]));
508
509 if (!fragment && istcp && E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) {
510 return E1000_MRQ_RSS_TYPE_IPV4TCP;
511 }
512
513 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
514 return E1000_MRQ_RSS_TYPE_IPV4;
515 }
516 } else if (isip6) {
517 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt);
518
519 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS;
520 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS;
521
522 /*
523 * Following two traces must not be combined because resulting
524 * event will have 11 arguments totally and some trace backends
525 * (at least "ust") have limitation of maximum 10 arguments per
526 * event. Events with more arguments fail to compile for
527 * backends like these.
528 */
529 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]);
530 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, istcp,
531 ip6info->has_ext_hdrs,
532 ip6info->rss_ex_dst_valid,
533 ip6info->rss_ex_src_valid,
534 core->mac[MRQC],
535 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]),
536 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
537 E1000_MRQC_EN_IPV6(core->mac[MRQC]));
538
539 if ((!ex_dis || !ip6info->has_ext_hdrs) &&
540 (!new_ex_dis || !(ip6info->rss_ex_dst_valid ||
541 ip6info->rss_ex_src_valid))) {
542
543 if (istcp && !ip6info->fragment &&
544 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) {
545 return E1000_MRQ_RSS_TYPE_IPV6TCP;
546 }
547
548 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
549 return E1000_MRQ_RSS_TYPE_IPV6EX;
550 }
551
552 }
553
554 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) {
555 return E1000_MRQ_RSS_TYPE_IPV6;
556 }
557
558 }
559
560 return E1000_MRQ_RSS_TYPE_NONE;
561 }
562
563 static uint32_t
564 e1000e_rss_calc_hash(E1000ECore *core,
565 struct NetRxPkt *pkt,
566 E1000E_RSSInfo *info)
567 {
568 NetRxPktRssType type;
569
570 assert(e1000e_rss_enabled(core));
571
572 switch (info->type) {
573 case E1000_MRQ_RSS_TYPE_IPV4:
574 type = NetPktRssIpV4;
575 break;
576 case E1000_MRQ_RSS_TYPE_IPV4TCP:
577 type = NetPktRssIpV4Tcp;
578 break;
579 case E1000_MRQ_RSS_TYPE_IPV6TCP:
580 type = NetPktRssIpV6TcpEx;
581 break;
582 case E1000_MRQ_RSS_TYPE_IPV6:
583 type = NetPktRssIpV6;
584 break;
585 case E1000_MRQ_RSS_TYPE_IPV6EX:
586 type = NetPktRssIpV6Ex;
587 break;
588 default:
589 assert(false);
590 return 0;
591 }
592
593 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]);
594 }
595
596 static void
597 e1000e_rss_parse_packet(E1000ECore *core,
598 struct NetRxPkt *pkt,
599 E1000E_RSSInfo *info)
600 {
601 trace_e1000e_rx_rss_started();
602
603 if (!e1000e_rss_enabled(core)) {
604 info->enabled = false;
605 info->hash = 0;
606 info->queue = 0;
607 info->type = 0;
608 trace_e1000e_rx_rss_disabled();
609 return;
610 }
611
612 info->enabled = true;
613
614 info->type = e1000e_rss_get_hash_type(core, pkt);
615
616 trace_e1000e_rx_rss_type(info->type);
617
618 if (info->type == E1000_MRQ_RSS_TYPE_NONE) {
619 info->hash = 0;
620 info->queue = 0;
621 return;
622 }
623
624 info->hash = e1000e_rss_calc_hash(core, pkt, info);
625 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
626 }
627
628 static void
629 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx)
630 {
631 if (tx->props.tse && tx->cptse) {
632 net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss);
633 net_tx_pkt_update_ip_checksums(tx->tx_pkt);
634 e1000x_inc_reg_if_not_full(core->mac, TSCTC);
635 return;
636 }
637
638 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) {
639 net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0);
640 }
641
642 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) {
643 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
644 }
645 }
646
647 static bool
648 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index)
649 {
650 int target_queue = MIN(core->max_queue_num, queue_index);
651 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue);
652
653 e1000e_setup_tx_offloads(core, tx);
654
655 net_tx_pkt_dump(tx->tx_pkt);
656
657 if ((core->phy[0][PHY_CTRL] & MII_CR_LOOPBACK) ||
658 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) {
659 return net_tx_pkt_send_loopback(tx->tx_pkt, queue);
660 } else {
661 return net_tx_pkt_send(tx->tx_pkt, queue);
662 }
663 }
664
665 static void
666 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt)
667 {
668 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
669 PTC1023, PTC1522 };
670
671 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt);
672
673 e1000x_increase_size_stats(core->mac, PTCregs, tot_len);
674 e1000x_inc_reg_if_not_full(core->mac, TPT);
675 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len);
676
677 switch (net_tx_pkt_get_packet_type(tx_pkt)) {
678 case ETH_PKT_BCAST:
679 e1000x_inc_reg_if_not_full(core->mac, BPTC);
680 break;
681 case ETH_PKT_MCAST:
682 e1000x_inc_reg_if_not_full(core->mac, MPTC);
683 break;
684 case ETH_PKT_UCAST:
685 break;
686 default:
687 g_assert_not_reached();
688 }
689
690 core->mac[GPTC] = core->mac[TPT];
691 core->mac[GOTCL] = core->mac[TOTL];
692 core->mac[GOTCH] = core->mac[TOTH];
693 }
694
695 static void
696 e1000e_process_tx_desc(E1000ECore *core,
697 struct e1000e_tx *tx,
698 struct e1000_tx_desc *dp,
699 int queue_index)
700 {
701 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
702 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
703 unsigned int split_size = txd_lower & 0xffff;
704 uint64_t addr;
705 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
706 bool eop = txd_lower & E1000_TXD_CMD_EOP;
707
708 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
709 e1000x_read_tx_ctx_descr(xp, &tx->props);
710 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length));
711 return;
712 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
713 /* data descriptor */
714 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
715 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0;
716 e1000e_process_ts_option(core, dp);
717 } else {
718 /* legacy descriptor */
719 e1000e_process_ts_option(core, dp);
720 tx->cptse = 0;
721 }
722
723 addr = le64_to_cpu(dp->buffer_addr);
724
725 if (!tx->skip_cp) {
726 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, addr, split_size)) {
727 tx->skip_cp = true;
728 }
729 }
730
731 if (eop) {
732 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
733 if (e1000x_vlan_enabled(core->mac) &&
734 e1000x_is_vlan_txd(txd_lower)) {
735 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt,
736 le16_to_cpu(dp->upper.fields.special), core->mac[VET]);
737 }
738 if (e1000e_tx_pkt_send(core, tx, queue_index)) {
739 e1000e_on_tx_done_update_stats(core, tx->tx_pkt);
740 }
741 }
742
743 tx->skip_cp = false;
744 net_tx_pkt_reset(tx->tx_pkt);
745
746 tx->sum_needed = 0;
747 tx->cptse = 0;
748 }
749 }
750
751 static inline uint32_t
752 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx)
753 {
754 if (!msix_enabled(core->owner)) {
755 return E1000_ICR_TXDW;
756 }
757
758 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1;
759 }
760
761 static inline uint32_t
762 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx,
763 bool min_threshold_hit)
764 {
765 if (!msix_enabled(core->owner)) {
766 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0);
767 }
768
769 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1;
770 }
771
772 static uint32_t
773 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base,
774 struct e1000_tx_desc *dp, bool *ide, int queue_idx)
775 {
776 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
777
778 if (!(txd_lower & E1000_TXD_CMD_RS) &&
779 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) {
780 return 0;
781 }
782
783 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false;
784
785 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD;
786
787 dp->upper.data = cpu_to_le32(txd_upper);
788 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp),
789 &dp->upper, sizeof(dp->upper));
790 return e1000e_tx_wb_interrupt_cause(core, queue_idx);
791 }
792
793 typedef struct E1000E_RingInfo_st {
794 int dbah;
795 int dbal;
796 int dlen;
797 int dh;
798 int dt;
799 int idx;
800 } E1000E_RingInfo;
801
802 static inline bool
803 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r)
804 {
805 return core->mac[r->dh] == core->mac[r->dt] ||
806 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN;
807 }
808
809 static inline uint64_t
810 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r)
811 {
812 uint64_t bah = core->mac[r->dbah];
813 uint64_t bal = core->mac[r->dbal];
814
815 return (bah << 32) + bal;
816 }
817
818 static inline uint64_t
819 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r)
820 {
821 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh];
822 }
823
824 static inline void
825 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count)
826 {
827 core->mac[r->dh] += count;
828
829 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) {
830 core->mac[r->dh] = 0;
831 }
832 }
833
834 static inline uint32_t
835 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r)
836 {
837 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen],
838 core->mac[r->dh], core->mac[r->dt]);
839
840 if (core->mac[r->dh] <= core->mac[r->dt]) {
841 return core->mac[r->dt] - core->mac[r->dh];
842 }
843
844 if (core->mac[r->dh] > core->mac[r->dt]) {
845 return core->mac[r->dlen] / E1000_RING_DESC_LEN +
846 core->mac[r->dt] - core->mac[r->dh];
847 }
848
849 g_assert_not_reached();
850 return 0;
851 }
852
853 static inline bool
854 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r)
855 {
856 return core->mac[r->dlen] > 0;
857 }
858
859 static inline uint32_t
860 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r)
861 {
862 return core->mac[r->dlen];
863 }
864
865 typedef struct E1000E_TxRing_st {
866 const E1000E_RingInfo *i;
867 struct e1000e_tx *tx;
868 } E1000E_TxRing;
869
870 static inline int
871 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx)
872 {
873 return (reg_idx - base_reg_idx) / (0x100 >> 2);
874 }
875
876 static inline void
877 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx)
878 {
879 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
880 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 },
881 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 }
882 };
883
884 assert(idx < ARRAY_SIZE(i));
885
886 txr->i = &i[idx];
887 txr->tx = &core->tx[idx];
888 }
889
890 typedef struct E1000E_RxRing_st {
891 const E1000E_RingInfo *i;
892 } E1000E_RxRing;
893
894 static inline void
895 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx)
896 {
897 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
898 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 },
899 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 }
900 };
901
902 assert(idx < ARRAY_SIZE(i));
903
904 rxr->i = &i[idx];
905 }
906
907 static void
908 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr)
909 {
910 dma_addr_t base;
911 struct e1000_tx_desc desc;
912 bool ide = false;
913 const E1000E_RingInfo *txi = txr->i;
914 uint32_t cause = E1000_ICS_TXQE;
915
916 if (!(core->mac[TCTL] & E1000_TCTL_EN)) {
917 trace_e1000e_tx_disabled();
918 return;
919 }
920
921 while (!e1000e_ring_empty(core, txi)) {
922 base = e1000e_ring_head_descr(core, txi);
923
924 pci_dma_read(core->owner, base, &desc, sizeof(desc));
925
926 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr,
927 desc.lower.data, desc.upper.data);
928
929 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx);
930 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx);
931
932 e1000e_ring_advance(core, txi, 1);
933 }
934
935 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) {
936 e1000e_set_interrupt_cause(core, cause);
937 }
938 }
939
940 static bool
941 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r,
942 size_t total_size)
943 {
944 uint32_t bufs = e1000e_ring_free_descr_num(core, r);
945
946 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size,
947 core->rx_desc_buf_size);
948
949 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) *
950 core->rx_desc_buf_size;
951 }
952
953 void
954 e1000e_start_recv(E1000ECore *core)
955 {
956 int i;
957
958 trace_e1000e_rx_start_recv();
959
960 for (i = 0; i <= core->max_queue_num; i++) {
961 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i));
962 }
963 }
964
965 bool
966 e1000e_can_receive(E1000ECore *core)
967 {
968 int i;
969
970 if (!e1000x_rx_ready(core->owner, core->mac)) {
971 return false;
972 }
973
974 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
975 E1000E_RxRing rxr;
976
977 e1000e_rx_ring_init(core, &rxr, i);
978 if (e1000e_ring_enabled(core, rxr.i) &&
979 e1000e_has_rxbufs(core, rxr.i, 1)) {
980 trace_e1000e_rx_can_recv();
981 return true;
982 }
983 }
984
985 trace_e1000e_rx_can_recv_rings_full();
986 return false;
987 }
988
989 ssize_t
990 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size)
991 {
992 const struct iovec iov = {
993 .iov_base = (uint8_t *)buf,
994 .iov_len = size
995 };
996
997 return e1000e_receive_iov(core, &iov, 1);
998 }
999
1000 static inline bool
1001 e1000e_rx_l3_cso_enabled(E1000ECore *core)
1002 {
1003 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD);
1004 }
1005
1006 static inline bool
1007 e1000e_rx_l4_cso_enabled(E1000ECore *core)
1008 {
1009 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
1010 }
1011
1012 static bool
1013 e1000e_receive_filter(E1000ECore *core, const uint8_t *buf, int size)
1014 {
1015 uint32_t rctl = core->mac[RCTL];
1016
1017 if (e1000x_is_vlan_packet(buf, core->mac[VET]) &&
1018 e1000x_vlan_rx_filter_enabled(core->mac)) {
1019 uint16_t vid = lduw_be_p(buf + 14);
1020 uint32_t vfta = ldl_le_p((uint32_t *)(core->mac + VFTA) +
1021 ((vid >> 5) & 0x7f));
1022 if ((vfta & (1 << (vid & 0x1f))) == 0) {
1023 trace_e1000e_rx_flt_vlan_mismatch(vid);
1024 return false;
1025 } else {
1026 trace_e1000e_rx_flt_vlan_match(vid);
1027 }
1028 }
1029
1030 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1031 case ETH_PKT_UCAST:
1032 if (rctl & E1000_RCTL_UPE) {
1033 return true; /* promiscuous ucast */
1034 }
1035 break;
1036
1037 case ETH_PKT_BCAST:
1038 if (rctl & E1000_RCTL_BAM) {
1039 return true; /* broadcast enabled */
1040 }
1041 break;
1042
1043 case ETH_PKT_MCAST:
1044 if (rctl & E1000_RCTL_MPE) {
1045 return true; /* promiscuous mcast */
1046 }
1047 break;
1048
1049 default:
1050 g_assert_not_reached();
1051 }
1052
1053 return e1000x_rx_group_filter(core->mac, buf);
1054 }
1055
1056 static inline void
1057 e1000e_read_lgcy_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr)
1058 {
1059 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc;
1060 *buff_addr = le64_to_cpu(d->buffer_addr);
1061 }
1062
1063 static inline void
1064 e1000e_read_ext_rx_descr(E1000ECore *core, uint8_t *desc, hwaddr *buff_addr)
1065 {
1066 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc;
1067 *buff_addr = le64_to_cpu(d->read.buffer_addr);
1068 }
1069
1070 static inline void
1071 e1000e_read_ps_rx_descr(E1000ECore *core, uint8_t *desc,
1072 hwaddr (*buff_addr)[MAX_PS_BUFFERS])
1073 {
1074 int i;
1075 union e1000_rx_desc_packet_split *d =
1076 (union e1000_rx_desc_packet_split *) desc;
1077
1078 for (i = 0; i < MAX_PS_BUFFERS; i++) {
1079 (*buff_addr)[i] = le64_to_cpu(d->read.buffer_addr[i]);
1080 }
1081
1082 trace_e1000e_rx_desc_ps_read((*buff_addr)[0], (*buff_addr)[1],
1083 (*buff_addr)[2], (*buff_addr)[3]);
1084 }
1085
1086 static inline void
1087 e1000e_read_rx_descr(E1000ECore *core, uint8_t *desc,
1088 hwaddr (*buff_addr)[MAX_PS_BUFFERS])
1089 {
1090 if (e1000e_rx_use_legacy_descriptor(core)) {
1091 e1000e_read_lgcy_rx_descr(core, desc, &(*buff_addr)[0]);
1092 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0;
1093 } else {
1094 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1095 e1000e_read_ps_rx_descr(core, desc, buff_addr);
1096 } else {
1097 e1000e_read_ext_rx_descr(core, desc, &(*buff_addr)[0]);
1098 (*buff_addr)[1] = (*buff_addr)[2] = (*buff_addr)[3] = 0;
1099 }
1100 }
1101 }
1102
1103 static void
1104 e1000e_verify_csum_in_sw(E1000ECore *core,
1105 struct NetRxPkt *pkt,
1106 uint32_t *status_flags,
1107 bool istcp, bool isudp)
1108 {
1109 bool csum_valid;
1110 uint32_t csum_error;
1111
1112 if (e1000e_rx_l3_cso_enabled(core)) {
1113 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) {
1114 trace_e1000e_rx_metadata_l3_csum_validation_failed();
1115 } else {
1116 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE;
1117 *status_flags |= E1000_RXD_STAT_IPCS | csum_error;
1118 }
1119 } else {
1120 trace_e1000e_rx_metadata_l3_cso_disabled();
1121 }
1122
1123 if (!e1000e_rx_l4_cso_enabled(core)) {
1124 trace_e1000e_rx_metadata_l4_cso_disabled();
1125 return;
1126 }
1127
1128 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1129 trace_e1000e_rx_metadata_l4_csum_validation_failed();
1130 return;
1131 }
1132
1133 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE;
1134
1135 if (istcp) {
1136 *status_flags |= E1000_RXD_STAT_TCPCS |
1137 csum_error;
1138 } else if (isudp) {
1139 *status_flags |= E1000_RXD_STAT_TCPCS |
1140 E1000_RXD_STAT_UDPCS |
1141 csum_error;
1142 }
1143 }
1144
1145 static inline bool
1146 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt)
1147 {
1148 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) {
1149 return false;
1150 }
1151
1152 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) {
1153 return !net_rx_pkt_has_tcp_data(rx_pkt);
1154 }
1155
1156 return true;
1157 }
1158
1159 static void
1160 e1000e_build_rx_metadata(E1000ECore *core,
1161 struct NetRxPkt *pkt,
1162 bool is_eop,
1163 const E1000E_RSSInfo *rss_info,
1164 uint32_t *rss, uint32_t *mrq,
1165 uint32_t *status_flags,
1166 uint16_t *ip_id,
1167 uint16_t *vlan_tag)
1168 {
1169 struct virtio_net_hdr *vhdr;
1170 bool isip4, isip6, istcp, isudp;
1171 uint32_t pkt_type;
1172
1173 *status_flags = E1000_RXD_STAT_DD;
1174
1175 /* No additional metadata needed for non-EOP descriptors */
1176 if (!is_eop) {
1177 goto func_exit;
1178 }
1179
1180 *status_flags |= E1000_RXD_STAT_EOP;
1181
1182 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
1183 trace_e1000e_rx_metadata_protocols(isip4, isip6, isudp, istcp);
1184
1185 /* VLAN state */
1186 if (net_rx_pkt_is_vlan_stripped(pkt)) {
1187 *status_flags |= E1000_RXD_STAT_VP;
1188 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
1189 trace_e1000e_rx_metadata_vlan(*vlan_tag);
1190 }
1191
1192 /* Packet parsing results */
1193 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) {
1194 if (rss_info->enabled) {
1195 *rss = cpu_to_le32(rss_info->hash);
1196 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8));
1197 trace_e1000e_rx_metadata_rss(*rss, *mrq);
1198 }
1199 } else if (isip4) {
1200 *status_flags |= E1000_RXD_STAT_IPIDV;
1201 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt));
1202 trace_e1000e_rx_metadata_ip_id(*ip_id);
1203 }
1204
1205 if (istcp && e1000e_is_tcp_ack(core, pkt)) {
1206 *status_flags |= E1000_RXD_STAT_ACK;
1207 trace_e1000e_rx_metadata_ack();
1208 }
1209
1210 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) {
1211 trace_e1000e_rx_metadata_ipv6_filtering_disabled();
1212 pkt_type = E1000_RXD_PKT_MAC;
1213 } else if (istcp || isudp) {
1214 pkt_type = isip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP;
1215 } else if (isip4 || isip6) {
1216 pkt_type = isip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6;
1217 } else {
1218 pkt_type = E1000_RXD_PKT_MAC;
1219 }
1220
1221 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type);
1222 trace_e1000e_rx_metadata_pkt_type(pkt_type);
1223
1224 /* RX CSO information */
1225 if (isip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
1226 trace_e1000e_rx_metadata_ipv6_sum_disabled();
1227 goto func_exit;
1228 }
1229
1230 if (!net_rx_pkt_has_virt_hdr(pkt)) {
1231 trace_e1000e_rx_metadata_no_virthdr();
1232 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp);
1233 goto func_exit;
1234 }
1235
1236 vhdr = net_rx_pkt_get_vhdr(pkt);
1237
1238 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
1239 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
1240 trace_e1000e_rx_metadata_virthdr_no_csum_info();
1241 e1000e_verify_csum_in_sw(core, pkt, status_flags, istcp, isudp);
1242 goto func_exit;
1243 }
1244
1245 if (e1000e_rx_l3_cso_enabled(core)) {
1246 *status_flags |= isip4 ? E1000_RXD_STAT_IPCS : 0;
1247 } else {
1248 trace_e1000e_rx_metadata_l3_cso_disabled();
1249 }
1250
1251 if (e1000e_rx_l4_cso_enabled(core)) {
1252 if (istcp) {
1253 *status_flags |= E1000_RXD_STAT_TCPCS;
1254 } else if (isudp) {
1255 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
1256 }
1257 } else {
1258 trace_e1000e_rx_metadata_l4_cso_disabled();
1259 }
1260
1261 trace_e1000e_rx_metadata_status_flags(*status_flags);
1262
1263 func_exit:
1264 *status_flags = cpu_to_le32(*status_flags);
1265 }
1266
1267 static inline void
1268 e1000e_write_lgcy_rx_descr(E1000ECore *core, uint8_t *desc,
1269 struct NetRxPkt *pkt,
1270 const E1000E_RSSInfo *rss_info,
1271 uint16_t length)
1272 {
1273 uint32_t status_flags, rss, mrq;
1274 uint16_t ip_id;
1275
1276 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc;
1277
1278 assert(!rss_info->enabled);
1279
1280 d->length = cpu_to_le16(length);
1281 d->csum = 0;
1282
1283 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1284 rss_info,
1285 &rss, &mrq,
1286 &status_flags, &ip_id,
1287 &d->special);
1288 d->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24);
1289 d->status = (uint8_t) le32_to_cpu(status_flags);
1290 }
1291
1292 static inline void
1293 e1000e_write_ext_rx_descr(E1000ECore *core, uint8_t *desc,
1294 struct NetRxPkt *pkt,
1295 const E1000E_RSSInfo *rss_info,
1296 uint16_t length)
1297 {
1298 union e1000_rx_desc_extended *d = (union e1000_rx_desc_extended *) desc;
1299
1300 memset(&d->wb, 0, sizeof(d->wb));
1301
1302 d->wb.upper.length = cpu_to_le16(length);
1303
1304 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1305 rss_info,
1306 &d->wb.lower.hi_dword.rss,
1307 &d->wb.lower.mrq,
1308 &d->wb.upper.status_error,
1309 &d->wb.lower.hi_dword.csum_ip.ip_id,
1310 &d->wb.upper.vlan);
1311 }
1312
1313 static inline void
1314 e1000e_write_ps_rx_descr(E1000ECore *core, uint8_t *desc,
1315 struct NetRxPkt *pkt,
1316 const E1000E_RSSInfo *rss_info,
1317 size_t ps_hdr_len,
1318 uint16_t(*written)[MAX_PS_BUFFERS])
1319 {
1320 int i;
1321 union e1000_rx_desc_packet_split *d =
1322 (union e1000_rx_desc_packet_split *) desc;
1323
1324 memset(&d->wb, 0, sizeof(d->wb));
1325
1326 d->wb.middle.length0 = cpu_to_le16((*written)[0]);
1327
1328 for (i = 0; i < PS_PAGE_BUFFERS; i++) {
1329 d->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]);
1330 }
1331
1332 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1333 rss_info,
1334 &d->wb.lower.hi_dword.rss,
1335 &d->wb.lower.mrq,
1336 &d->wb.middle.status_error,
1337 &d->wb.lower.hi_dword.csum_ip.ip_id,
1338 &d->wb.middle.vlan);
1339
1340 d->wb.upper.header_status =
1341 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0));
1342
1343 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1],
1344 (*written)[2], (*written)[3]);
1345 }
1346
1347 static inline void
1348 e1000e_write_rx_descr(E1000ECore *core, uint8_t *desc,
1349 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info,
1350 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS])
1351 {
1352 if (e1000e_rx_use_legacy_descriptor(core)) {
1353 assert(ps_hdr_len == 0);
1354 e1000e_write_lgcy_rx_descr(core, desc, pkt, rss_info, (*written)[0]);
1355 } else {
1356 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1357 e1000e_write_ps_rx_descr(core, desc, pkt, rss_info,
1358 ps_hdr_len, written);
1359 } else {
1360 assert(ps_hdr_len == 0);
1361 e1000e_write_ext_rx_descr(core, desc, pkt, rss_info,
1362 (*written)[0]);
1363 }
1364 }
1365 }
1366
1367 static inline void
1368 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr,
1369 uint8_t *desc, dma_addr_t len)
1370 {
1371 PCIDevice *dev = core->owner;
1372
1373 if (e1000e_rx_use_legacy_descriptor(core)) {
1374 struct e1000_rx_desc *d = (struct e1000_rx_desc *) desc;
1375 size_t offset = offsetof(struct e1000_rx_desc, status);
1376 uint8_t status = d->status;
1377
1378 d->status &= ~E1000_RXD_STAT_DD;
1379 pci_dma_write(dev, addr, desc, len);
1380
1381 if (status & E1000_RXD_STAT_DD) {
1382 d->status = status;
1383 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1384 }
1385 } else {
1386 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1387 union e1000_rx_desc_packet_split *d =
1388 (union e1000_rx_desc_packet_split *) desc;
1389 size_t offset = offsetof(union e1000_rx_desc_packet_split,
1390 wb.middle.status_error);
1391 uint32_t status = d->wb.middle.status_error;
1392
1393 d->wb.middle.status_error &= ~E1000_RXD_STAT_DD;
1394 pci_dma_write(dev, addr, desc, len);
1395
1396 if (status & E1000_RXD_STAT_DD) {
1397 d->wb.middle.status_error = status;
1398 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1399 }
1400 } else {
1401 union e1000_rx_desc_extended *d =
1402 (union e1000_rx_desc_extended *) desc;
1403 size_t offset = offsetof(union e1000_rx_desc_extended,
1404 wb.upper.status_error);
1405 uint32_t status = d->wb.upper.status_error;
1406
1407 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD;
1408 pci_dma_write(dev, addr, desc, len);
1409
1410 if (status & E1000_RXD_STAT_DD) {
1411 d->wb.upper.status_error = status;
1412 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1413 }
1414 }
1415 }
1416 }
1417
1418 typedef struct e1000e_ba_state_st {
1419 uint16_t written[MAX_PS_BUFFERS];
1420 uint8_t cur_idx;
1421 } e1000e_ba_state;
1422
1423 static inline void
1424 e1000e_write_hdr_to_rx_buffers(E1000ECore *core,
1425 hwaddr (*ba)[MAX_PS_BUFFERS],
1426 e1000e_ba_state *bastate,
1427 const char *data,
1428 dma_addr_t data_len)
1429 {
1430 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]);
1431
1432 pci_dma_write(core->owner, (*ba)[0] + bastate->written[0], data, data_len);
1433 bastate->written[0] += data_len;
1434
1435 bastate->cur_idx = 1;
1436 }
1437
1438 static void
1439 e1000e_write_to_rx_buffers(E1000ECore *core,
1440 hwaddr (*ba)[MAX_PS_BUFFERS],
1441 e1000e_ba_state *bastate,
1442 const char *data,
1443 dma_addr_t data_len)
1444 {
1445 while (data_len > 0) {
1446 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx];
1447 uint32_t cur_buf_bytes_left = cur_buf_len -
1448 bastate->written[bastate->cur_idx];
1449 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left);
1450
1451 trace_e1000e_rx_desc_buff_write(bastate->cur_idx,
1452 (*ba)[bastate->cur_idx],
1453 bastate->written[bastate->cur_idx],
1454 data,
1455 bytes_to_write);
1456
1457 pci_dma_write(core->owner,
1458 (*ba)[bastate->cur_idx] + bastate->written[bastate->cur_idx],
1459 data, bytes_to_write);
1460
1461 bastate->written[bastate->cur_idx] += bytes_to_write;
1462 data += bytes_to_write;
1463 data_len -= bytes_to_write;
1464
1465 if (bastate->written[bastate->cur_idx] == cur_buf_len) {
1466 bastate->cur_idx++;
1467 }
1468
1469 assert(bastate->cur_idx < MAX_PS_BUFFERS);
1470 }
1471 }
1472
1473 static void
1474 e1000e_update_rx_stats(E1000ECore *core,
1475 size_t data_size,
1476 size_t data_fcs_size)
1477 {
1478 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size);
1479
1480 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1481 case ETH_PKT_BCAST:
1482 e1000x_inc_reg_if_not_full(core->mac, BPRC);
1483 break;
1484
1485 case ETH_PKT_MCAST:
1486 e1000x_inc_reg_if_not_full(core->mac, MPRC);
1487 break;
1488
1489 default:
1490 break;
1491 }
1492 }
1493
1494 static inline bool
1495 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi)
1496 {
1497 return e1000e_ring_free_descr_num(core, rxi) ==
1498 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift;
1499 }
1500
1501 static bool
1502 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len)
1503 {
1504 bool isip4, isip6, isudp, istcp;
1505 bool fragment;
1506
1507 if (!e1000e_rx_use_ps_descriptor(core)) {
1508 return false;
1509 }
1510
1511 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
1512
1513 if (isip4) {
1514 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
1515 } else if (isip6) {
1516 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment;
1517 } else {
1518 return false;
1519 }
1520
1521 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) {
1522 return false;
1523 }
1524
1525 if (!fragment && (isudp || istcp)) {
1526 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt);
1527 } else {
1528 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt);
1529 }
1530
1531 if ((*hdr_len > core->rxbuf_sizes[0]) ||
1532 (*hdr_len > net_rx_pkt_get_total_len(pkt))) {
1533 return false;
1534 }
1535
1536 return true;
1537 }
1538
1539 static void
1540 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt,
1541 const E1000E_RxRing *rxr,
1542 const E1000E_RSSInfo *rss_info)
1543 {
1544 PCIDevice *d = core->owner;
1545 dma_addr_t base;
1546 uint8_t desc[E1000_MAX_RX_DESC_LEN];
1547 size_t desc_size;
1548 size_t desc_offset = 0;
1549 size_t iov_ofs = 0;
1550
1551 struct iovec *iov = net_rx_pkt_get_iovec(pkt);
1552 size_t size = net_rx_pkt_get_total_len(pkt);
1553 size_t total_size = size + e1000x_fcs_len(core->mac);
1554 const E1000E_RingInfo *rxi;
1555 size_t ps_hdr_len = 0;
1556 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len);
1557 bool is_first = true;
1558
1559 rxi = rxr->i;
1560
1561 do {
1562 hwaddr ba[MAX_PS_BUFFERS];
1563 e1000e_ba_state bastate = { { 0 } };
1564 bool is_last = false;
1565
1566 desc_size = total_size - desc_offset;
1567
1568 if (desc_size > core->rx_desc_buf_size) {
1569 desc_size = core->rx_desc_buf_size;
1570 }
1571
1572 if (e1000e_ring_empty(core, rxi)) {
1573 return;
1574 }
1575
1576 base = e1000e_ring_head_descr(core, rxi);
1577
1578 pci_dma_read(d, base, &desc, core->rx_desc_len);
1579
1580 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len);
1581
1582 e1000e_read_rx_descr(core, desc, &ba);
1583
1584 if (ba[0]) {
1585 if (desc_offset < size) {
1586 static const uint32_t fcs_pad;
1587 size_t iov_copy;
1588 size_t copy_size = size - desc_offset;
1589 if (copy_size > core->rx_desc_buf_size) {
1590 copy_size = core->rx_desc_buf_size;
1591 }
1592
1593 /* For PS mode copy the packet header first */
1594 if (do_ps) {
1595 if (is_first) {
1596 size_t ps_hdr_copied = 0;
1597 do {
1598 iov_copy = MIN(ps_hdr_len - ps_hdr_copied,
1599 iov->iov_len - iov_ofs);
1600
1601 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate,
1602 iov->iov_base, iov_copy);
1603
1604 copy_size -= iov_copy;
1605 ps_hdr_copied += iov_copy;
1606
1607 iov_ofs += iov_copy;
1608 if (iov_ofs == iov->iov_len) {
1609 iov++;
1610 iov_ofs = 0;
1611 }
1612 } while (ps_hdr_copied < ps_hdr_len);
1613
1614 is_first = false;
1615 } else {
1616 /* Leave buffer 0 of each descriptor except first */
1617 /* empty as per spec 7.1.5.1 */
1618 e1000e_write_hdr_to_rx_buffers(core, &ba, &bastate,
1619 NULL, 0);
1620 }
1621 }
1622
1623 /* Copy packet payload */
1624 while (copy_size) {
1625 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
1626
1627 e1000e_write_to_rx_buffers(core, &ba, &bastate,
1628 iov->iov_base + iov_ofs, iov_copy);
1629
1630 copy_size -= iov_copy;
1631 iov_ofs += iov_copy;
1632 if (iov_ofs == iov->iov_len) {
1633 iov++;
1634 iov_ofs = 0;
1635 }
1636 }
1637
1638 if (desc_offset + desc_size >= total_size) {
1639 /* Simulate FCS checksum presence in the last descriptor */
1640 e1000e_write_to_rx_buffers(core, &ba, &bastate,
1641 (const char *) &fcs_pad, e1000x_fcs_len(core->mac));
1642 }
1643 }
1644 } else { /* as per intel docs; skip descriptors with null buf addr */
1645 trace_e1000e_rx_null_descriptor();
1646 }
1647 desc_offset += desc_size;
1648 if (desc_offset >= total_size) {
1649 is_last = true;
1650 }
1651
1652 e1000e_write_rx_descr(core, desc, is_last ? core->rx_pkt : NULL,
1653 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written);
1654 e1000e_pci_dma_write_rx_desc(core, base, desc, core->rx_desc_len);
1655
1656 e1000e_ring_advance(core, rxi,
1657 core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
1658
1659 } while (desc_offset < total_size);
1660
1661 e1000e_update_rx_stats(core, size, total_size);
1662 }
1663
1664 static inline void
1665 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt)
1666 {
1667 if (net_rx_pkt_has_virt_hdr(pkt)) {
1668 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt);
1669
1670 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
1671 net_rx_pkt_fix_l4_csum(pkt);
1672 }
1673 }
1674 }
1675
1676 /* Min. octets in an ethernet frame sans FCS */
1677 #define MIN_BUF_SIZE 60
1678
1679 ssize_t
1680 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt)
1681 {
1682 static const int maximum_ethernet_hdr_len = (14 + 4);
1683
1684 uint32_t n = 0;
1685 uint8_t min_buf[MIN_BUF_SIZE];
1686 struct iovec min_iov;
1687 uint8_t *filter_buf;
1688 size_t size, orig_size;
1689 size_t iov_ofs = 0;
1690 E1000E_RxRing rxr;
1691 E1000E_RSSInfo rss_info;
1692 size_t total_size;
1693 ssize_t retval;
1694 bool rdmts_hit;
1695
1696 trace_e1000e_rx_receive_iov(iovcnt);
1697
1698 if (!e1000x_hw_rx_enabled(core->mac)) {
1699 return -1;
1700 }
1701
1702 /* Pull virtio header in */
1703 if (core->has_vnet) {
1704 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt);
1705 iov_ofs = sizeof(struct virtio_net_hdr);
1706 }
1707
1708 filter_buf = iov->iov_base + iov_ofs;
1709 orig_size = iov_size(iov, iovcnt);
1710 size = orig_size - iov_ofs;
1711
1712 /* Pad to minimum Ethernet frame length */
1713 if (size < sizeof(min_buf)) {
1714 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size);
1715 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1716 e1000x_inc_reg_if_not_full(core->mac, RUC);
1717 min_iov.iov_base = filter_buf = min_buf;
1718 min_iov.iov_len = size = sizeof(min_buf);
1719 iovcnt = 1;
1720 iov = &min_iov;
1721 iov_ofs = 0;
1722 } else if (iov->iov_len < maximum_ethernet_hdr_len) {
1723 /* This is very unlikely, but may happen. */
1724 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len);
1725 filter_buf = min_buf;
1726 }
1727
1728 /* Discard oversized packets if !LPE and !SBP. */
1729 if (e1000x_is_oversized(core->mac, size)) {
1730 return orig_size;
1731 }
1732
1733 net_rx_pkt_set_packet_type(core->rx_pkt,
1734 get_eth_packet_type(PKT_GET_ETH_HDR(filter_buf)));
1735
1736 if (!e1000e_receive_filter(core, filter_buf, size)) {
1737 trace_e1000e_rx_flt_dropped();
1738 return orig_size;
1739 }
1740
1741 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
1742 e1000x_vlan_enabled(core->mac), core->mac[VET]);
1743
1744 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info);
1745 e1000e_rx_ring_init(core, &rxr, rss_info.queue);
1746
1747 trace_e1000e_rx_rss_dispatched_to_queue(rxr.i->idx);
1748
1749 total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
1750 e1000x_fcs_len(core->mac);
1751
1752 if (e1000e_has_rxbufs(core, rxr.i, total_size)) {
1753 e1000e_rx_fix_l4_csum(core, core->rx_pkt);
1754
1755 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
1756
1757 retval = orig_size;
1758
1759 /* Perform small receive detection (RSRPD) */
1760 if (total_size < core->mac[RSRPD]) {
1761 n |= E1000_ICS_SRPD;
1762 }
1763
1764 /* Perform ACK receive detection */
1765 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) &&
1766 (e1000e_is_tcp_ack(core, core->rx_pkt))) {
1767 n |= E1000_ICS_ACK;
1768 }
1769
1770 /* Check if receive descriptor minimum threshold hit */
1771 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i);
1772 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit);
1773
1774 trace_e1000e_rx_written_to_guest(n);
1775 } else {
1776 n |= E1000_ICS_RXO;
1777 retval = 0;
1778
1779 trace_e1000e_rx_not_written_to_guest(n);
1780 }
1781
1782 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) {
1783 trace_e1000e_rx_interrupt_set(n);
1784 e1000e_set_interrupt_cause(core, n);
1785 } else {
1786 trace_e1000e_rx_interrupt_delayed(n);
1787 }
1788
1789 return retval;
1790 }
1791
1792 static inline bool
1793 e1000e_have_autoneg(E1000ECore *core)
1794 {
1795 return core->phy[0][PHY_CTRL] & MII_CR_AUTO_NEG_EN;
1796 }
1797
1798 static void e1000e_update_flowctl_status(E1000ECore *core)
1799 {
1800 if (e1000e_have_autoneg(core) &&
1801 core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE) {
1802 trace_e1000e_link_autoneg_flowctl(true);
1803 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE;
1804 } else {
1805 trace_e1000e_link_autoneg_flowctl(false);
1806 }
1807 }
1808
1809 static inline void
1810 e1000e_link_down(E1000ECore *core)
1811 {
1812 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1813 e1000e_update_flowctl_status(core);
1814 }
1815
1816 static inline void
1817 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val)
1818 {
1819 /* bits 0-5 reserved; MII_CR_[RESTART_AUTO_NEG,RESET] are self clearing */
1820 core->phy[0][PHY_CTRL] = val & ~(0x3f |
1821 MII_CR_RESET |
1822 MII_CR_RESTART_AUTO_NEG);
1823
1824 if ((val & MII_CR_RESTART_AUTO_NEG) &&
1825 e1000e_have_autoneg(core)) {
1826 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1827 }
1828 }
1829
1830 static void
1831 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val)
1832 {
1833 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10);
1834
1835 if (val & BIT(10)) {
1836 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1837 }
1838 }
1839
1840 static void
1841 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val)
1842 {
1843 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK;
1844 }
1845
1846 void
1847 e1000e_core_set_link_status(E1000ECore *core)
1848 {
1849 NetClientState *nc = qemu_get_queue(core->owner_nic);
1850 uint32_t old_status = core->mac[STATUS];
1851
1852 trace_e1000e_link_status_changed(nc->link_down ? false : true);
1853
1854 if (nc->link_down) {
1855 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1856 } else {
1857 if (e1000e_have_autoneg(core) &&
1858 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
1859 e1000x_restart_autoneg(core->mac, core->phy[0],
1860 core->autoneg_timer);
1861 } else {
1862 e1000x_update_regs_on_link_up(core->mac, core->phy[0]);
1863 e1000e_start_recv(core);
1864 }
1865 }
1866
1867 if (core->mac[STATUS] != old_status) {
1868 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
1869 }
1870 }
1871
1872 static void
1873 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val)
1874 {
1875 trace_e1000e_core_ctrl_write(index, val);
1876
1877 /* RST is self clearing */
1878 core->mac[CTRL] = val & ~E1000_CTRL_RST;
1879 core->mac[CTRL_DUP] = core->mac[CTRL];
1880
1881 trace_e1000e_link_set_params(
1882 !!(val & E1000_CTRL_ASDE),
1883 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1884 !!(val & E1000_CTRL_FRCSPD),
1885 !!(val & E1000_CTRL_FRCDPX),
1886 !!(val & E1000_CTRL_RFCE),
1887 !!(val & E1000_CTRL_TFCE));
1888
1889 if (val & E1000_CTRL_RST) {
1890 trace_e1000e_core_ctrl_sw_reset();
1891 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
1892 }
1893
1894 if (val & E1000_CTRL_PHY_RST) {
1895 trace_e1000e_core_ctrl_phy_reset();
1896 core->mac[STATUS] |= E1000_STATUS_PHYRA;
1897 }
1898 }
1899
1900 static void
1901 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val)
1902 {
1903 trace_e1000e_rx_set_rfctl(val);
1904
1905 if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1906 trace_e1000e_wrn_iscsi_filtering_not_supported();
1907 }
1908
1909 if (!(val & E1000_RFCTL_NFSW_DIS)) {
1910 trace_e1000e_wrn_nfsw_filtering_not_supported();
1911 }
1912
1913 if (!(val & E1000_RFCTL_NFSR_DIS)) {
1914 trace_e1000e_wrn_nfsr_filtering_not_supported();
1915 }
1916
1917 core->mac[RFCTL] = val;
1918 }
1919
1920 static void
1921 e1000e_calc_per_desc_buf_size(E1000ECore *core)
1922 {
1923 int i;
1924 core->rx_desc_buf_size = 0;
1925
1926 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) {
1927 core->rx_desc_buf_size += core->rxbuf_sizes[i];
1928 }
1929 }
1930
1931 static void
1932 e1000e_parse_rxbufsize(E1000ECore *core)
1933 {
1934 uint32_t rctl = core->mac[RCTL];
1935
1936 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes));
1937
1938 if (rctl & E1000_RCTL_DTYP_MASK) {
1939 uint32_t bsize;
1940
1941 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK;
1942 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128;
1943
1944 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK;
1945 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024;
1946
1947 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK;
1948 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024;
1949
1950 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK;
1951 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024;
1952 } else if (rctl & E1000_RCTL_FLXBUF_MASK) {
1953 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK;
1954 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024;
1955 } else {
1956 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl);
1957 }
1958
1959 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1],
1960 core->rxbuf_sizes[2], core->rxbuf_sizes[3]);
1961
1962 e1000e_calc_per_desc_buf_size(core);
1963 }
1964
1965 static void
1966 e1000e_calc_rxdesclen(E1000ECore *core)
1967 {
1968 if (e1000e_rx_use_legacy_descriptor(core)) {
1969 core->rx_desc_len = sizeof(struct e1000_rx_desc);
1970 } else {
1971 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1972 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split);
1973 } else {
1974 core->rx_desc_len = sizeof(union e1000_rx_desc_extended);
1975 }
1976 }
1977 trace_e1000e_rx_desc_len(core->rx_desc_len);
1978 }
1979
1980 static void
1981 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val)
1982 {
1983 core->mac[RCTL] = val;
1984 trace_e1000e_rx_set_rctl(core->mac[RCTL]);
1985
1986 if (val & E1000_RCTL_EN) {
1987 e1000e_parse_rxbufsize(core);
1988 e1000e_calc_rxdesclen(core);
1989 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 +
1990 E1000_RING_DESC_LEN_SHIFT;
1991
1992 e1000e_start_recv(core);
1993 }
1994 }
1995
1996 static
1997 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE])
1998 (E1000ECore *, int, uint16_t) = {
1999 [0] = {
2000 [PHY_CTRL] = e1000e_set_phy_ctrl,
2001 [PHY_PAGE] = e1000e_set_phy_page,
2002 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits
2003 }
2004 };
2005
2006 static inline void
2007 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits)
2008 {
2009 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits);
2010 core->mac[IMS] &= ~bits;
2011 }
2012
2013 static inline bool
2014 e1000e_postpone_interrupt(bool *interrupt_pending,
2015 E1000IntrDelayTimer *timer)
2016 {
2017 if (timer->running) {
2018 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2);
2019
2020 *interrupt_pending = true;
2021 return true;
2022 }
2023
2024 if (timer->core->mac[timer->delay_reg] != 0) {
2025 e1000e_intrmgr_rearm_timer(timer);
2026 }
2027
2028 return false;
2029 }
2030
2031 static inline bool
2032 e1000e_itr_should_postpone(E1000ECore *core)
2033 {
2034 return e1000e_postpone_interrupt(&core->itr_intr_pending, &core->itr);
2035 }
2036
2037 static inline bool
2038 e1000e_eitr_should_postpone(E1000ECore *core, int idx)
2039 {
2040 return e1000e_postpone_interrupt(&core->eitr_intr_pending[idx],
2041 &core->eitr[idx]);
2042 }
2043
2044 static void
2045 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2046 {
2047 uint32_t effective_eiac;
2048
2049 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2050 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2051 if (vec < E1000E_MSIX_VEC_NUM) {
2052 if (!e1000e_eitr_should_postpone(core, vec)) {
2053 trace_e1000e_irq_msix_notify_vec(vec);
2054 msix_notify(core->owner, vec);
2055 }
2056 } else {
2057 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2058 }
2059 } else {
2060 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2061 }
2062
2063 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) {
2064 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause);
2065 core->mac[IAM] &= ~cause;
2066 }
2067
2068 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]);
2069
2070 effective_eiac = core->mac[EIAC] & cause;
2071
2072 core->mac[ICR] &= ~effective_eiac;
2073 core->msi_causes_pending &= ~effective_eiac;
2074
2075 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2076 core->mac[IMS] &= ~effective_eiac;
2077 }
2078 }
2079
2080 static void
2081 e1000e_msix_notify(E1000ECore *core, uint32_t causes)
2082 {
2083 if (causes & E1000_ICR_RXQ0) {
2084 e1000e_msix_notify_one(core, E1000_ICR_RXQ0,
2085 E1000_IVAR_RXQ0(core->mac[IVAR]));
2086 }
2087
2088 if (causes & E1000_ICR_RXQ1) {
2089 e1000e_msix_notify_one(core, E1000_ICR_RXQ1,
2090 E1000_IVAR_RXQ1(core->mac[IVAR]));
2091 }
2092
2093 if (causes & E1000_ICR_TXQ0) {
2094 e1000e_msix_notify_one(core, E1000_ICR_TXQ0,
2095 E1000_IVAR_TXQ0(core->mac[IVAR]));
2096 }
2097
2098 if (causes & E1000_ICR_TXQ1) {
2099 e1000e_msix_notify_one(core, E1000_ICR_TXQ1,
2100 E1000_IVAR_TXQ1(core->mac[IVAR]));
2101 }
2102
2103 if (causes & E1000_ICR_OTHER) {
2104 e1000e_msix_notify_one(core, E1000_ICR_OTHER,
2105 E1000_IVAR_OTHER(core->mac[IVAR]));
2106 }
2107 }
2108
2109 static void
2110 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2111 {
2112 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2113 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2114 if (vec < E1000E_MSIX_VEC_NUM) {
2115 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec);
2116 msix_clr_pending(core->owner, vec);
2117 } else {
2118 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2119 }
2120 } else {
2121 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2122 }
2123 }
2124
2125 static void
2126 e1000e_msix_clear(E1000ECore *core, uint32_t causes)
2127 {
2128 if (causes & E1000_ICR_RXQ0) {
2129 e1000e_msix_clear_one(core, E1000_ICR_RXQ0,
2130 E1000_IVAR_RXQ0(core->mac[IVAR]));
2131 }
2132
2133 if (causes & E1000_ICR_RXQ1) {
2134 e1000e_msix_clear_one(core, E1000_ICR_RXQ1,
2135 E1000_IVAR_RXQ1(core->mac[IVAR]));
2136 }
2137
2138 if (causes & E1000_ICR_TXQ0) {
2139 e1000e_msix_clear_one(core, E1000_ICR_TXQ0,
2140 E1000_IVAR_TXQ0(core->mac[IVAR]));
2141 }
2142
2143 if (causes & E1000_ICR_TXQ1) {
2144 e1000e_msix_clear_one(core, E1000_ICR_TXQ1,
2145 E1000_IVAR_TXQ1(core->mac[IVAR]));
2146 }
2147
2148 if (causes & E1000_ICR_OTHER) {
2149 e1000e_msix_clear_one(core, E1000_ICR_OTHER,
2150 E1000_IVAR_OTHER(core->mac[IVAR]));
2151 }
2152 }
2153
2154 static inline void
2155 e1000e_fix_icr_asserted(E1000ECore *core)
2156 {
2157 core->mac[ICR] &= ~E1000_ICR_ASSERTED;
2158 if (core->mac[ICR]) {
2159 core->mac[ICR] |= E1000_ICR_ASSERTED;
2160 }
2161
2162 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
2163 }
2164
2165 static void
2166 e1000e_send_msi(E1000ECore *core, bool msix)
2167 {
2168 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED;
2169
2170 core->msi_causes_pending &= causes;
2171 causes ^= core->msi_causes_pending;
2172 if (causes == 0) {
2173 return;
2174 }
2175 core->msi_causes_pending |= causes;
2176
2177 if (msix) {
2178 e1000e_msix_notify(core, causes);
2179 } else {
2180 if (!e1000e_itr_should_postpone(core)) {
2181 trace_e1000e_irq_msi_notify(causes);
2182 msi_notify(core->owner, 0);
2183 }
2184 }
2185 }
2186
2187 static void
2188 e1000e_update_interrupt_state(E1000ECore *core)
2189 {
2190 bool interrupts_pending;
2191 bool is_msix = msix_enabled(core->owner);
2192
2193 /* Set ICR[OTHER] for MSI-X */
2194 if (is_msix) {
2195 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) {
2196 core->mac[ICR] |= E1000_ICR_OTHER;
2197 trace_e1000e_irq_add_msi_other(core->mac[ICR]);
2198 }
2199 }
2200
2201 e1000e_fix_icr_asserted(core);
2202
2203 /*
2204 * Make sure ICR and ICS registers have the same value.
2205 * The spec says that the ICS register is write-only. However in practice,
2206 * on real hardware ICS is readable, and for reads it has the same value as
2207 * ICR (except that ICS does not have the clear on read behaviour of ICR).
2208 *
2209 * The VxWorks PRO/1000 driver uses this behaviour.
2210 */
2211 core->mac[ICS] = core->mac[ICR];
2212
2213 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false;
2214 if (!interrupts_pending) {
2215 core->msi_causes_pending = 0;
2216 }
2217
2218 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
2219 core->mac[ICR], core->mac[IMS]);
2220
2221 if (is_msix || msi_enabled(core->owner)) {
2222 if (interrupts_pending) {
2223 e1000e_send_msi(core, is_msix);
2224 }
2225 } else {
2226 if (interrupts_pending) {
2227 if (!e1000e_itr_should_postpone(core)) {
2228 e1000e_raise_legacy_irq(core);
2229 }
2230 } else {
2231 e1000e_lower_legacy_irq(core);
2232 }
2233 }
2234 }
2235
2236 static void
2237 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val)
2238 {
2239 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]);
2240
2241 val |= e1000e_intmgr_collect_delayed_causes(core);
2242 core->mac[ICR] |= val;
2243
2244 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]);
2245
2246 e1000e_update_interrupt_state(core);
2247 }
2248
2249 static inline void
2250 e1000e_autoneg_timer(void *opaque)
2251 {
2252 E1000ECore *core = opaque;
2253 if (!qemu_get_queue(core->owner_nic)->link_down) {
2254 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]);
2255 e1000e_start_recv(core);
2256
2257 e1000e_update_flowctl_status(core);
2258 /* signal link status change to the guest */
2259 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
2260 }
2261 }
2262
2263 static inline uint16_t
2264 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)
2265 {
2266 uint16_t index = (addr & 0x1ffff) >> 2;
2267 return index + (mac_reg_access[index] & 0xfffe);
2268 }
2269
2270 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = {
2271 [0] = {
2272 [PHY_CTRL] = PHY_ANYPAGE | PHY_RW,
2273 [PHY_STATUS] = PHY_ANYPAGE | PHY_R,
2274 [PHY_ID1] = PHY_ANYPAGE | PHY_R,
2275 [PHY_ID2] = PHY_ANYPAGE | PHY_R,
2276 [PHY_AUTONEG_ADV] = PHY_ANYPAGE | PHY_RW,
2277 [PHY_LP_ABILITY] = PHY_ANYPAGE | PHY_R,
2278 [PHY_AUTONEG_EXP] = PHY_ANYPAGE | PHY_R,
2279 [PHY_NEXT_PAGE_TX] = PHY_ANYPAGE | PHY_RW,
2280 [PHY_LP_NEXT_PAGE] = PHY_ANYPAGE | PHY_R,
2281 [PHY_1000T_CTRL] = PHY_ANYPAGE | PHY_RW,
2282 [PHY_1000T_STATUS] = PHY_ANYPAGE | PHY_R,
2283 [PHY_EXT_STATUS] = PHY_ANYPAGE | PHY_R,
2284 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW,
2285
2286 [PHY_COPPER_CTRL1] = PHY_RW,
2287 [PHY_COPPER_STAT1] = PHY_R,
2288 [PHY_COPPER_CTRL3] = PHY_RW,
2289 [PHY_RX_ERR_CNTR] = PHY_R,
2290 [PHY_OEM_BITS] = PHY_RW,
2291 [PHY_BIAS_1] = PHY_RW,
2292 [PHY_BIAS_2] = PHY_RW,
2293 [PHY_COPPER_INT_ENABLE] = PHY_RW,
2294 [PHY_COPPER_STAT2] = PHY_R,
2295 [PHY_COPPER_CTRL2] = PHY_RW
2296 },
2297 [2] = {
2298 [PHY_MAC_CTRL1] = PHY_RW,
2299 [PHY_MAC_INT_ENABLE] = PHY_RW,
2300 [PHY_MAC_STAT] = PHY_R,
2301 [PHY_MAC_CTRL2] = PHY_RW
2302 },
2303 [3] = {
2304 [PHY_LED_03_FUNC_CTRL1] = PHY_RW,
2305 [PHY_LED_03_POL_CTRL] = PHY_RW,
2306 [PHY_LED_TIMER_CTRL] = PHY_RW,
2307 [PHY_LED_45_CTRL] = PHY_RW
2308 },
2309 [5] = {
2310 [PHY_1000T_SKEW] = PHY_R,
2311 [PHY_1000T_SWAP] = PHY_R
2312 },
2313 [6] = {
2314 [PHY_CRC_COUNTERS] = PHY_R
2315 }
2316 };
2317
2318 static bool
2319 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr,
2320 char cap, uint8_t *page)
2321 {
2322 *page =
2323 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0
2324 : core->phy[0][PHY_PAGE];
2325
2326 if (*page >= E1000E_PHY_PAGES) {
2327 return false;
2328 }
2329
2330 return e1000e_phy_regcap[*page][addr] & cap;
2331 }
2332
2333 static void
2334 e1000e_phy_reg_write(E1000ECore *core, uint8_t page,
2335 uint32_t addr, uint16_t data)
2336 {
2337 assert(page < E1000E_PHY_PAGES);
2338 assert(addr < E1000E_PHY_PAGE_SIZE);
2339
2340 if (e1000e_phyreg_writeops[page][addr]) {
2341 e1000e_phyreg_writeops[page][addr](core, addr, data);
2342 } else {
2343 core->phy[page][addr] = data;
2344 }
2345 }
2346
2347 static void
2348 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val)
2349 {
2350 uint32_t data = val & E1000_MDIC_DATA_MASK;
2351 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2352 uint8_t page;
2353
2354 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2355 val = core->mac[MDIC] | E1000_MDIC_ERROR;
2356 } else if (val & E1000_MDIC_OP_READ) {
2357 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) {
2358 trace_e1000e_core_mdic_read_unhandled(page, addr);
2359 val |= E1000_MDIC_ERROR;
2360 } else {
2361 val = (val ^ data) | core->phy[page][addr];
2362 trace_e1000e_core_mdic_read(page, addr, val);
2363 }
2364 } else if (val & E1000_MDIC_OP_WRITE) {
2365 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) {
2366 trace_e1000e_core_mdic_write_unhandled(page, addr);
2367 val |= E1000_MDIC_ERROR;
2368 } else {
2369 trace_e1000e_core_mdic_write(page, addr, data);
2370 e1000e_phy_reg_write(core, page, addr, data);
2371 }
2372 }
2373 core->mac[MDIC] = val | E1000_MDIC_READY;
2374
2375 if (val & E1000_MDIC_INT_EN) {
2376 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC);
2377 }
2378 }
2379
2380 static void
2381 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val)
2382 {
2383 core->mac[index] = val & 0xffff;
2384 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val);
2385 e1000e_start_recv(core);
2386 }
2387
2388 static void
2389 e1000e_set_status(E1000ECore *core, int index, uint32_t val)
2390 {
2391 if ((val & E1000_STATUS_PHYRA) == 0) {
2392 core->mac[index] &= ~E1000_STATUS_PHYRA;
2393 }
2394 }
2395
2396 static void
2397 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val)
2398 {
2399 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2400 !!(val & E1000_CTRL_EXT_SPD_BYPS));
2401
2402 /* Zero self-clearing bits */
2403 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
2404 core->mac[CTRL_EXT] = val;
2405 }
2406
2407 static void
2408 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val)
2409 {
2410 int i;
2411
2412 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2413
2414 if (!msix_enabled(core->owner)) {
2415 return;
2416 }
2417
2418 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
2419 if (core->mac[PBACLR] & BIT(i)) {
2420 msix_clr_pending(core->owner, i);
2421 }
2422 }
2423 }
2424
2425 static void
2426 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val)
2427 {
2428 core->mac[FCRTH] = val & 0xFFF8;
2429 }
2430
2431 static void
2432 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val)
2433 {
2434 core->mac[FCRTL] = val & 0x8000FFF8;
2435 }
2436
2437 static inline void
2438 e1000e_set_16bit(E1000ECore *core, int index, uint32_t val)
2439 {
2440 core->mac[index] = val & 0xffff;
2441 }
2442
2443 static void
2444 e1000e_set_12bit(E1000ECore *core, int index, uint32_t val)
2445 {
2446 core->mac[index] = val & 0xfff;
2447 }
2448
2449 static void
2450 e1000e_set_vet(E1000ECore *core, int index, uint32_t val)
2451 {
2452 core->mac[VET] = val & 0xffff;
2453 trace_e1000e_vlan_vet(core->mac[VET]);
2454 }
2455
2456 static void
2457 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val)
2458 {
2459 core->mac[index] = val & E1000_XDLEN_MASK;
2460 }
2461
2462 static void
2463 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val)
2464 {
2465 core->mac[index] = val & E1000_XDBAL_MASK;
2466 }
2467
2468 static void
2469 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val)
2470 {
2471 E1000E_TxRing txr;
2472 core->mac[index] = val;
2473
2474 if (core->mac[TARC0] & E1000_TARC_ENABLE) {
2475 e1000e_tx_ring_init(core, &txr, 0);
2476 e1000e_start_xmit(core, &txr);
2477 }
2478
2479 if (core->mac[TARC1] & E1000_TARC_ENABLE) {
2480 e1000e_tx_ring_init(core, &txr, 1);
2481 e1000e_start_xmit(core, &txr);
2482 }
2483 }
2484
2485 static void
2486 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val)
2487 {
2488 E1000E_TxRing txr;
2489 int qidx = e1000e_mq_queue_idx(TDT, index);
2490 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1;
2491
2492 core->mac[index] = val & 0xffff;
2493
2494 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) {
2495 e1000e_tx_ring_init(core, &txr, qidx);
2496 e1000e_start_xmit(core, &txr);
2497 }
2498 }
2499
2500 static void
2501 e1000e_set_ics(E1000ECore *core, int index, uint32_t val)
2502 {
2503 trace_e1000e_irq_write_ics(val);
2504 e1000e_set_interrupt_cause(core, val);
2505 }
2506
2507 static void
2508 e1000e_set_icr(E1000ECore *core, int index, uint32_t val)
2509 {
2510 uint32_t icr = 0;
2511 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2512 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2513 trace_e1000e_irq_icr_process_iame();
2514 e1000e_clear_ims_bits(core, core->mac[IAM]);
2515 }
2516
2517 icr = core->mac[ICR] & ~val;
2518 /* Windows driver expects that the "receive overrun" bit and other
2519 * ones to be cleared when the "Other" bit (#24) is cleared.
2520 */
2521 icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr;
2522 trace_e1000e_irq_icr_write(val, core->mac[ICR], icr);
2523 core->mac[ICR] = icr;
2524 e1000e_update_interrupt_state(core);
2525 }
2526
2527 static void
2528 e1000e_set_imc(E1000ECore *core, int index, uint32_t val)
2529 {
2530 trace_e1000e_irq_ims_clear_set_imc(val);
2531 e1000e_clear_ims_bits(core, val);
2532 e1000e_update_interrupt_state(core);
2533 }
2534
2535 static void
2536 e1000e_set_ims(E1000ECore *core, int index, uint32_t val)
2537 {
2538 static const uint32_t ims_ext_mask =
2539 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 |
2540 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2541 E1000_IMS_OTHER;
2542
2543 static const uint32_t ims_valid_mask =
2544 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC |
2545 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 |
2546 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD |
2547 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 |
2548 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2549 E1000_IMS_OTHER;
2550
2551 uint32_t valid_val = val & ims_valid_mask;
2552
2553 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val);
2554 core->mac[IMS] |= valid_val;
2555
2556 if ((valid_val & ims_ext_mask) &&
2557 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) &&
2558 msix_enabled(core->owner)) {
2559 e1000e_msix_clear(core, valid_val);
2560 }
2561
2562 if ((valid_val == ims_valid_mask) &&
2563 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) {
2564 trace_e1000e_irq_fire_all_timers(val);
2565 e1000e_intrmgr_fire_all_timers(core);
2566 }
2567
2568 e1000e_update_interrupt_state(core);
2569 }
2570
2571 static void
2572 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val)
2573 {
2574 e1000e_set_16bit(core, index, val);
2575
2576 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) {
2577 trace_e1000e_irq_rdtr_fpd_running();
2578 e1000e_intrmgr_fire_delayed_interrupts(core);
2579 } else {
2580 trace_e1000e_irq_rdtr_fpd_not_running();
2581 }
2582 }
2583
2584 static void
2585 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val)
2586 {
2587 e1000e_set_16bit(core, index, val);
2588
2589 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) {
2590 trace_e1000e_irq_tidv_fpd_running();
2591 e1000e_intrmgr_fire_delayed_interrupts(core);
2592 } else {
2593 trace_e1000e_irq_tidv_fpd_not_running();
2594 }
2595 }
2596
2597 static uint32_t
2598 e1000e_mac_readreg(E1000ECore *core, int index)
2599 {
2600 return core->mac[index];
2601 }
2602
2603 static uint32_t
2604 e1000e_mac_ics_read(E1000ECore *core, int index)
2605 {
2606 trace_e1000e_irq_read_ics(core->mac[ICS]);
2607 return core->mac[ICS];
2608 }
2609
2610 static uint32_t
2611 e1000e_mac_ims_read(E1000ECore *core, int index)
2612 {
2613 trace_e1000e_irq_read_ims(core->mac[IMS]);
2614 return core->mac[IMS];
2615 }
2616
2617 #define E1000E_LOW_BITS_READ_FUNC(num) \
2618 static uint32_t \
2619 e1000e_mac_low##num##_read(E1000ECore *core, int index) \
2620 { \
2621 return core->mac[index] & (BIT(num) - 1); \
2622 } \
2623
2624 #define E1000E_LOW_BITS_READ(num) \
2625 e1000e_mac_low##num##_read
2626
2627 E1000E_LOW_BITS_READ_FUNC(4);
2628 E1000E_LOW_BITS_READ_FUNC(6);
2629 E1000E_LOW_BITS_READ_FUNC(11);
2630 E1000E_LOW_BITS_READ_FUNC(13);
2631 E1000E_LOW_BITS_READ_FUNC(16);
2632
2633 static uint32_t
2634 e1000e_mac_swsm_read(E1000ECore *core, int index)
2635 {
2636 uint32_t val = core->mac[SWSM];
2637 core->mac[SWSM] = val | 1;
2638 return val;
2639 }
2640
2641 static uint32_t
2642 e1000e_mac_itr_read(E1000ECore *core, int index)
2643 {
2644 return core->itr_guest_value;
2645 }
2646
2647 static uint32_t
2648 e1000e_mac_eitr_read(E1000ECore *core, int index)
2649 {
2650 return core->eitr_guest_value[index - EITR];
2651 }
2652
2653 static uint32_t
2654 e1000e_mac_icr_read(E1000ECore *core, int index)
2655 {
2656 uint32_t ret = core->mac[ICR];
2657 trace_e1000e_irq_icr_read_entry(ret);
2658
2659 if (core->mac[IMS] == 0) {
2660 trace_e1000e_irq_icr_clear_zero_ims();
2661 core->mac[ICR] = 0;
2662 }
2663
2664 if (!msix_enabled(core->owner)) {
2665 trace_e1000e_irq_icr_clear_nonmsix_icr_read();
2666 core->mac[ICR] = 0;
2667 }
2668
2669 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2670 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2671 trace_e1000e_irq_icr_clear_iame();
2672 core->mac[ICR] = 0;
2673 trace_e1000e_irq_icr_process_iame();
2674 e1000e_clear_ims_bits(core, core->mac[IAM]);
2675 }
2676
2677 trace_e1000e_irq_icr_read_exit(core->mac[ICR]);
2678 e1000e_update_interrupt_state(core);
2679 return ret;
2680 }
2681
2682 static uint32_t
2683 e1000e_mac_read_clr4(E1000ECore *core, int index)
2684 {
2685 uint32_t ret = core->mac[index];
2686
2687 core->mac[index] = 0;
2688 return ret;
2689 }
2690
2691 static uint32_t
2692 e1000e_mac_read_clr8(E1000ECore *core, int index)
2693 {
2694 uint32_t ret = core->mac[index];
2695
2696 core->mac[index] = 0;
2697 core->mac[index - 1] = 0;
2698 return ret;
2699 }
2700
2701 static uint32_t
2702 e1000e_get_ctrl(E1000ECore *core, int index)
2703 {
2704 uint32_t val = core->mac[CTRL];
2705
2706 trace_e1000e_link_read_params(
2707 !!(val & E1000_CTRL_ASDE),
2708 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2709 !!(val & E1000_CTRL_FRCSPD),
2710 !!(val & E1000_CTRL_FRCDPX),
2711 !!(val & E1000_CTRL_RFCE),
2712 !!(val & E1000_CTRL_TFCE));
2713
2714 return val;
2715 }
2716
2717 static uint32_t
2718 e1000e_get_status(E1000ECore *core, int index)
2719 {
2720 uint32_t res = core->mac[STATUS];
2721
2722 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) {
2723 res |= E1000_STATUS_GIO_MASTER_ENABLE;
2724 }
2725
2726 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) {
2727 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0;
2728 } else {
2729 res |= E1000_STATUS_FD;
2730 }
2731
2732 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) ||
2733 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) {
2734 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) {
2735 case E1000_CTRL_SPD_10:
2736 res |= E1000_STATUS_SPEED_10;
2737 break;
2738 case E1000_CTRL_SPD_100:
2739 res |= E1000_STATUS_SPEED_100;
2740 break;
2741 case E1000_CTRL_SPD_1000:
2742 default:
2743 res |= E1000_STATUS_SPEED_1000;
2744 break;
2745 }
2746 } else {
2747 res |= E1000_STATUS_SPEED_1000;
2748 }
2749
2750 trace_e1000e_link_status(
2751 !!(res & E1000_STATUS_LU),
2752 !!(res & E1000_STATUS_FD),
2753 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT,
2754 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT);
2755
2756 return res;
2757 }
2758
2759 static uint32_t
2760 e1000e_get_tarc(E1000ECore *core, int index)
2761 {
2762 return core->mac[index] & ((BIT(11) - 1) |
2763 BIT(27) |
2764 BIT(28) |
2765 BIT(29) |
2766 BIT(30));
2767 }
2768
2769 static void
2770 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val)
2771 {
2772 core->mac[index] = val;
2773 }
2774
2775 static void
2776 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val)
2777 {
2778 uint32_t macaddr[2];
2779
2780 core->mac[index] = val;
2781
2782 macaddr[0] = cpu_to_le32(core->mac[RA]);
2783 macaddr[1] = cpu_to_le32(core->mac[RA + 1]);
2784 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic),
2785 (uint8_t *) macaddr);
2786
2787 trace_e1000e_mac_set_sw(MAC_ARG(macaddr));
2788 }
2789
2790 static void
2791 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val)
2792 {
2793 static const uint32_t ro_bits = E1000_EECD_PRES |
2794 E1000_EECD_AUTO_RD |
2795 E1000_EECD_SIZE_EX_MASK;
2796
2797 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);
2798 }
2799
2800 static void
2801 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val)
2802 {
2803 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2804 uint32_t flags = 0;
2805 uint32_t data = 0;
2806
2807 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2808 data = core->eeprom[addr];
2809 flags = E1000_EERW_DONE;
2810 }
2811
2812 core->mac[EERD] = flags |
2813 (addr << E1000_EERW_ADDR_SHIFT) |
2814 (data << E1000_EERW_DATA_SHIFT);
2815 }
2816
2817 static void
2818 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val)
2819 {
2820 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2821 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK;
2822 uint32_t flags = 0;
2823
2824 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2825 core->eeprom[addr] = data;
2826 flags = E1000_EERW_DONE;
2827 }
2828
2829 core->mac[EERD] = flags |
2830 (addr << E1000_EERW_ADDR_SHIFT) |
2831 (data << E1000_EERW_DATA_SHIFT);
2832 }
2833
2834 static void
2835 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val)
2836 {
2837 core->mac[RXDCTL] = core->mac[RXDCTL1] = val;
2838 }
2839
2840 static void
2841 e1000e_set_itr(E1000ECore *core, int index, uint32_t val)
2842 {
2843 uint32_t interval = val & 0xffff;
2844
2845 trace_e1000e_irq_itr_set(val);
2846
2847 core->itr_guest_value = interval;
2848 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2849 }
2850
2851 static void
2852 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val)
2853 {
2854 uint32_t interval = val & 0xffff;
2855 uint32_t eitr_num = index - EITR;
2856
2857 trace_e1000e_irq_eitr_set(eitr_num, val);
2858
2859 core->eitr_guest_value[eitr_num] = interval;
2860 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2861 }
2862
2863 static void
2864 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val)
2865 {
2866 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) {
2867
2868 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) {
2869 qemu_log_mask(LOG_GUEST_ERROR,
2870 "e1000e: PSRCTL.BSIZE0 cannot be zero");
2871 return;
2872 }
2873
2874 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) {
2875 qemu_log_mask(LOG_GUEST_ERROR,
2876 "e1000e: PSRCTL.BSIZE1 cannot be zero");
2877 return;
2878 }
2879 }
2880
2881 core->mac[PSRCTL] = val;
2882 }
2883
2884 static void
2885 e1000e_update_rx_offloads(E1000ECore *core)
2886 {
2887 int cso_state = e1000e_rx_l4_cso_enabled(core);
2888
2889 trace_e1000e_rx_set_cso(cso_state);
2890
2891 if (core->has_vnet) {
2892 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer,
2893 cso_state, 0, 0, 0, 0);
2894 }
2895 }
2896
2897 static void
2898 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val)
2899 {
2900 core->mac[RXCSUM] = val;
2901 e1000e_update_rx_offloads(core);
2902 }
2903
2904 static void
2905 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val)
2906 {
2907 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS;
2908 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits;
2909 }
2910
2911 #define e1000e_getreg(x) [x] = e1000e_mac_readreg
2912 typedef uint32_t (*readops)(E1000ECore *, int);
2913 static const readops e1000e_macreg_readops[] = {
2914 e1000e_getreg(PBA),
2915 e1000e_getreg(WUFC),
2916 e1000e_getreg(MANC),
2917 e1000e_getreg(TOTL),
2918 e1000e_getreg(RDT0),
2919 e1000e_getreg(RDBAH0),
2920 e1000e_getreg(TDBAL1),
2921 e1000e_getreg(RDLEN0),
2922 e1000e_getreg(RDH1),
2923 e1000e_getreg(LATECOL),
2924 e1000e_getreg(SEQEC),
2925 e1000e_getreg(XONTXC),
2926 e1000e_getreg(WUS),
2927 e1000e_getreg(GORCL),
2928 e1000e_getreg(MGTPRC),
2929 e1000e_getreg(EERD),
2930 e1000e_getreg(EIAC),
2931 e1000e_getreg(PSRCTL),
2932 e1000e_getreg(MANC2H),
2933 e1000e_getreg(RXCSUM),
2934 e1000e_getreg(GSCL_3),
2935 e1000e_getreg(GSCN_2),
2936 e1000e_getreg(RSRPD),
2937 e1000e_getreg(RDBAL1),
2938 e1000e_getreg(FCAH),
2939 e1000e_getreg(FCRTH),
2940 e1000e_getreg(FLOP),
2941 e1000e_getreg(FLASHT),
2942 e1000e_getreg(RXSTMPH),
2943 e1000e_getreg(TXSTMPL),
2944 e1000e_getreg(TIMADJL),
2945 e1000e_getreg(TXDCTL),
2946 e1000e_getreg(RDH0),
2947 e1000e_getreg(TDT1),
2948 e1000e_getreg(TNCRS),
2949 e1000e_getreg(RJC),
2950 e1000e_getreg(IAM),
2951 e1000e_getreg(GSCL_2),
2952 e1000e_getreg(RDBAH1),
2953 e1000e_getreg(FLSWDATA),
2954 e1000e_getreg(RXSATRH),
2955 e1000e_getreg(TIPG),
2956 e1000e_getreg(FLMNGCTL),
2957 e1000e_getreg(FLMNGCNT),
2958 e1000e_getreg(TSYNCTXCTL),
2959 e1000e_getreg(EXTCNF_SIZE),
2960 e1000e_getreg(EXTCNF_CTRL),
2961 e1000e_getreg(EEMNGDATA),
2962 e1000e_getreg(CTRL_EXT),
2963 e1000e_getreg(SYSTIMH),
2964 e1000e_getreg(EEMNGCTL),
2965 e1000e_getreg(FLMNGDATA),
2966 e1000e_getreg(TSYNCRXCTL),
2967 e1000e_getreg(TDH),
2968 e1000e_getreg(LEDCTL),
2969 e1000e_getreg(TCTL),
2970 e1000e_getreg(TDBAL),
2971 e1000e_getreg(TDLEN),
2972 e1000e_getreg(TDH1),
2973 e1000e_getreg(RADV),
2974 e1000e_getreg(ECOL),
2975 e1000e_getreg(DC),
2976 e1000e_getreg(RLEC),
2977 e1000e_getreg(XOFFTXC),
2978 e1000e_getreg(RFC),
2979 e1000e_getreg(RNBC),
2980 e1000e_getreg(MGTPTC),
2981 e1000e_getreg(TIMINCA),
2982 e1000e_getreg(RXCFGL),
2983 e1000e_getreg(MFUTP01),
2984 e1000e_getreg(FACTPS),
2985 e1000e_getreg(GSCL_1),
2986 e1000e_getreg(GSCN_0),
2987 e1000e_getreg(GCR2),
2988 e1000e_getreg(RDT1),
2989 e1000e_getreg(PBACLR),
2990 e1000e_getreg(FCTTV),
2991 e1000e_getreg(EEWR),
2992 e1000e_getreg(FLSWCTL),
2993 e1000e_getreg(RXDCTL1),
2994 e1000e_getreg(RXSATRL),
2995 e1000e_getreg(SYSTIML),
2996 e1000e_getreg(RXUDP),
2997 e1000e_getreg(TORL),
2998 e1000e_getreg(TDLEN1),
2999 e1000e_getreg(MCC),
3000 e1000e_getreg(WUC),
3001 e1000e_getreg(EECD),
3002 e1000e_getreg(MFUTP23),
3003 e1000e_getreg(RAID),
3004 e1000e_getreg(FCRTV),
3005 e1000e_getreg(TXDCTL1),
3006 e1000e_getreg(RCTL),
3007 e1000e_getreg(TDT),
3008 e1000e_getreg(MDIC),
3009 e1000e_getreg(FCRUC),
3010 e1000e_getreg(VET),
3011 e1000e_getreg(RDBAL0),
3012 e1000e_getreg(TDBAH1),
3013 e1000e_getreg(RDTR),
3014 e1000e_getreg(SCC),
3015 e1000e_getreg(COLC),
3016 e1000e_getreg(CEXTERR),
3017 e1000e_getreg(XOFFRXC),
3018 e1000e_getreg(IPAV),
3019 e1000e_getreg(GOTCL),
3020 e1000e_getreg(MGTPDC),
3021 e1000e_getreg(GCR),
3022 e1000e_getreg(IVAR),
3023 e1000e_getreg(POEMB),
3024 e1000e_getreg(MFVAL),
3025 e1000e_getreg(FUNCTAG),
3026 e1000e_getreg(GSCL_4),
3027 e1000e_getreg(GSCN_3),
3028 e1000e_getreg(MRQC),
3029 e1000e_getreg(RDLEN1),
3030 e1000e_getreg(FCT),
3031 e1000e_getreg(FLA),
3032 e1000e_getreg(FLOL),
3033 e1000e_getreg(RXDCTL),
3034 e1000e_getreg(RXSTMPL),
3035 e1000e_getreg(TXSTMPH),
3036 e1000e_getreg(TIMADJH),
3037 e1000e_getreg(FCRTL),
3038 e1000e_getreg(TDBAH),
3039 e1000e_getreg(TADV),
3040 e1000e_getreg(XONRXC),
3041 e1000e_getreg(TSCTFC),
3042 e1000e_getreg(RFCTL),
3043 e1000e_getreg(GSCN_1),
3044 e1000e_getreg(FCAL),
3045 e1000e_getreg(FLSWCNT),
3046
3047 [TOTH] = e1000e_mac_read_clr8,
3048 [GOTCH] = e1000e_mac_read_clr8,
3049 [PRC64] = e1000e_mac_read_clr4,
3050 [PRC255] = e1000e_mac_read_clr4,
3051 [PRC1023] = e1000e_mac_read_clr4,
3052 [PTC64] = e1000e_mac_read_clr4,
3053 [PTC255] = e1000e_mac_read_clr4,
3054 [PTC1023] = e1000e_mac_read_clr4,
3055 [GPRC] = e1000e_mac_read_clr4,
3056 [TPT] = e1000e_mac_read_clr4,
3057 [RUC] = e1000e_mac_read_clr4,
3058 [BPRC] = e1000e_mac_read_clr4,
3059 [MPTC] = e1000e_mac_read_clr4,
3060 [IAC] = e1000e_mac_read_clr4,
3061 [ICR] = e1000e_mac_icr_read,
3062 [RDFH] = E1000E_LOW_BITS_READ(13),
3063 [RDFHS] = E1000E_LOW_BITS_READ(13),
3064 [RDFPC] = E1000E_LOW_BITS_READ(13),
3065 [TDFH] = E1000E_LOW_BITS_READ(13),
3066 [TDFHS] = E1000E_LOW_BITS_READ(13),
3067 [STATUS] = e1000e_get_status,
3068 [TARC0] = e1000e_get_tarc,
3069 [PBS] = E1000E_LOW_BITS_READ(6),
3070 [ICS] = e1000e_mac_ics_read,
3071 [AIT] = E1000E_LOW_BITS_READ(16),
3072 [TORH] = e1000e_mac_read_clr8,
3073 [GORCH] = e1000e_mac_read_clr8,
3074 [PRC127] = e1000e_mac_read_clr4,
3075 [PRC511] = e1000e_mac_read_clr4,
3076 [PRC1522] = e1000e_mac_read_clr4,
3077 [PTC127] = e1000e_mac_read_clr4,
3078 [PTC511] = e1000e_mac_read_clr4,
3079 [PTC1522] = e1000e_mac_read_clr4,
3080 [GPTC] = e1000e_mac_read_clr4,
3081 [TPR] = e1000e_mac_read_clr4,
3082 [ROC] = e1000e_mac_read_clr4,
3083 [MPRC] = e1000e_mac_read_clr4,
3084 [BPTC] = e1000e_mac_read_clr4,
3085 [TSCTC] = e1000e_mac_read_clr4,
3086 [ITR] = e1000e_mac_itr_read,
3087 [RDFT] = E1000E_LOW_BITS_READ(13),
3088 [RDFTS] = E1000E_LOW_BITS_READ(13),
3089 [TDFPC] = E1000E_LOW_BITS_READ(13),
3090 [TDFT] = E1000E_LOW_BITS_READ(13),
3091 [TDFTS] = E1000E_LOW_BITS_READ(13),
3092 [CTRL] = e1000e_get_ctrl,
3093 [TARC1] = e1000e_get_tarc,
3094 [SWSM] = e1000e_mac_swsm_read,
3095 [IMS] = e1000e_mac_ims_read,
3096
3097 [CRCERRS ... MPC] = e1000e_mac_readreg,
3098 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg,
3099 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg,
3100 [RA ... RA + 31] = e1000e_mac_readreg,
3101 [WUPM ... WUPM + 31] = e1000e_mac_readreg,
3102 [MTA ... MTA + 127] = e1000e_mac_readreg,
3103 [VFTA ... VFTA + 127] = e1000e_mac_readreg,
3104 [FFMT ... FFMT + 254] = E1000E_LOW_BITS_READ(4),
3105 [FFVT ... FFVT + 254] = e1000e_mac_readreg,
3106 [MDEF ... MDEF + 7] = e1000e_mac_readreg,
3107 [FFLT ... FFLT + 10] = E1000E_LOW_BITS_READ(11),
3108 [FTFT ... FTFT + 254] = e1000e_mac_readreg,
3109 [PBM ... PBM + 10239] = e1000e_mac_readreg,
3110 [RETA ... RETA + 31] = e1000e_mac_readreg,
3111 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg,
3112 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg,
3113 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read
3114 };
3115 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) };
3116
3117 #define e1000e_putreg(x) [x] = e1000e_mac_writereg
3118 typedef void (*writeops)(E1000ECore *, int, uint32_t);
3119 static const writeops e1000e_macreg_writeops[] = {
3120 e1000e_putreg(PBA),
3121 e1000e_putreg(SWSM),
3122 e1000e_putreg(WUFC),
3123 e1000e_putreg(RDBAH1),
3124 e1000e_putreg(TDBAH),
3125 e1000e_putreg(TXDCTL),
3126 e1000e_putreg(RDBAH0),
3127 e1000e_putreg(LEDCTL),
3128 e1000e_putreg(FCAL),
3129 e1000e_putreg(FCRUC),
3130 e1000e_putreg(AIT),
3131 e1000e_putreg(TDFH),
3132 e1000e_putreg(TDFT),
3133 e1000e_putreg(TDFHS),
3134 e1000e_putreg(TDFTS),
3135 e1000e_putreg(TDFPC),
3136 e1000e_putreg(WUC),
3137 e1000e_putreg(WUS),
3138 e1000e_putreg(RDFH),
3139 e1000e_putreg(RDFT),
3140 e1000e_putreg(RDFHS),
3141 e1000e_putreg(RDFTS),
3142 e1000e_putreg(RDFPC),
3143 e1000e_putreg(IPAV),
3144 e1000e_putreg(TDBAH1),
3145 e1000e_putreg(TIMINCA),
3146 e1000e_putreg(IAM),
3147 e1000e_putreg(EIAC),
3148 e1000e_putreg(IVAR),
3149 e1000e_putreg(TARC0),
3150 e1000e_putreg(TARC1),
3151 e1000e_putreg(FLSWDATA),
3152 e1000e_putreg(POEMB),
3153 e1000e_putreg(PBS),
3154 e1000e_putreg(MFUTP01),
3155 e1000e_putreg(MFUTP23),
3156 e1000e_putreg(MANC),
3157 e1000e_putreg(MANC2H),
3158 e1000e_putreg(MFVAL),
3159 e1000e_putreg(EXTCNF_CTRL),
3160 e1000e_putreg(FACTPS),
3161 e1000e_putreg(FUNCTAG),
3162 e1000e_putreg(GSCL_1),
3163 e1000e_putreg(GSCL_2),
3164 e1000e_putreg(GSCL_3),
3165 e1000e_putreg(GSCL_4),
3166 e1000e_putreg(GSCN_0),
3167 e1000e_putreg(GSCN_1),
3168 e1000e_putreg(GSCN_2),
3169 e1000e_putreg(GSCN_3),
3170 e1000e_putreg(GCR2),
3171 e1000e_putreg(MRQC),
3172 e1000e_putreg(FLOP),
3173 e1000e_putreg(FLOL),
3174 e1000e_putreg(FLSWCTL),
3175 e1000e_putreg(FLSWCNT),
3176 e1000e_putreg(FLA),
3177 e1000e_putreg(RXDCTL1),
3178 e1000e_putreg(TXDCTL1),
3179 e1000e_putreg(TIPG),
3180 e1000e_putreg(RXSTMPH),
3181 e1000e_putreg(RXSTMPL),
3182 e1000e_putreg(RXSATRL),
3183 e1000e_putreg(RXSATRH),
3184 e1000e_putreg(TXSTMPL),
3185 e1000e_putreg(TXSTMPH),
3186 e1000e_putreg(SYSTIML),
3187 e1000e_putreg(SYSTIMH),
3188 e1000e_putreg(TIMADJL),
3189 e1000e_putreg(TIMADJH),
3190 e1000e_putreg(RXUDP),
3191 e1000e_putreg(RXCFGL),
3192 e1000e_putreg(TSYNCRXCTL),
3193 e1000e_putreg(TSYNCTXCTL),
3194 e1000e_putreg(EXTCNF_SIZE),
3195 e1000e_putreg(EEMNGCTL),
3196 e1000e_putreg(RA),
3197
3198 [TDH1] = e1000e_set_16bit,
3199 [TDT1] = e1000e_set_tdt,
3200 [TCTL] = e1000e_set_tctl,
3201 [TDT] = e1000e_set_tdt,
3202 [MDIC] = e1000e_set_mdic,
3203 [ICS] = e1000e_set_ics,
3204 [TDH] = e1000e_set_16bit,
3205 [RDH0] = e1000e_set_16bit,
3206 [RDT0] = e1000e_set_rdt,
3207 [IMC] = e1000e_set_imc,
3208 [IMS] = e1000e_set_ims,
3209 [ICR] = e1000e_set_icr,
3210 [EECD] = e1000e_set_eecd,
3211 [RCTL] = e1000e_set_rx_control,
3212 [CTRL] = e1000e_set_ctrl,
3213 [RDTR] = e1000e_set_rdtr,
3214 [RADV] = e1000e_set_16bit,
3215 [TADV] = e1000e_set_16bit,
3216 [ITR] = e1000e_set_itr,
3217 [EERD] = e1000e_set_eerd,
3218 [GCR] = e1000e_set_gcr,
3219 [PSRCTL] = e1000e_set_psrctl,
3220 [RXCSUM] = e1000e_set_rxcsum,
3221 [RAID] = e1000e_set_16bit,
3222 [RSRPD] = e1000e_set_12bit,
3223 [TIDV] = e1000e_set_tidv,
3224 [TDLEN1] = e1000e_set_dlen,
3225 [TDLEN] = e1000e_set_dlen,
3226 [RDLEN0] = e1000e_set_dlen,
3227 [RDLEN1] = e1000e_set_dlen,
3228 [TDBAL] = e1000e_set_dbal,
3229 [TDBAL1] = e1000e_set_dbal,
3230 [RDBAL0] = e1000e_set_dbal,
3231 [RDBAL1] = e1000e_set_dbal,
3232 [RDH1] = e1000e_set_16bit,
3233 [RDT1] = e1000e_set_rdt,
3234 [STATUS] = e1000e_set_status,
3235 [PBACLR] = e1000e_set_pbaclr,
3236 [CTRL_EXT] = e1000e_set_ctrlext,
3237 [FCAH] = e1000e_set_16bit,
3238 [FCT] = e1000e_set_16bit,
3239 [FCTTV] = e1000e_set_16bit,
3240 [FCRTV] = e1000e_set_16bit,
3241 [FCRTH] = e1000e_set_fcrth,
3242 [FCRTL] = e1000e_set_fcrtl,
3243 [VET] = e1000e_set_vet,
3244 [RXDCTL] = e1000e_set_rxdctl,
3245 [FLASHT] = e1000e_set_16bit,
3246 [EEWR] = e1000e_set_eewr,
3247 [CTRL_DUP] = e1000e_set_ctrl,
3248 [RFCTL] = e1000e_set_rfctl,
3249 [RA + 1] = e1000e_mac_setmacaddr,
3250
3251 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg,
3252 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg,
3253 [RA + 2 ... RA + 31] = e1000e_mac_writereg,
3254 [WUPM ... WUPM + 31] = e1000e_mac_writereg,
3255 [MTA ... MTA + 127] = e1000e_mac_writereg,
3256 [VFTA ... VFTA + 127] = e1000e_mac_writereg,
3257 [FFMT ... FFMT + 254] = e1000e_mac_writereg,
3258 [FFVT ... FFVT + 254] = e1000e_mac_writereg,
3259 [PBM ... PBM + 10239] = e1000e_mac_writereg,
3260 [MDEF ... MDEF + 7] = e1000e_mac_writereg,
3261 [FFLT ... FFLT + 10] = e1000e_mac_writereg,
3262 [FTFT ... FTFT + 254] = e1000e_mac_writereg,
3263 [RETA ... RETA + 31] = e1000e_mac_writereg,
3264 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg,
3265 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg,
3266 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr
3267 };
3268 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) };
3269
3270 enum { MAC_ACCESS_PARTIAL = 1 };
3271
3272 /* The array below combines alias offsets of the index values for the
3273 * MAC registers that have aliases, with the indication of not fully
3274 * implemented registers (lowest bit). This combination is possible
3275 * because all of the offsets are even. */
3276 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = {
3277 /* Alias index offsets */
3278 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802,
3279 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6,
3280 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904,
3281 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8,
3282 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00,
3283 [RA_A ... RA_A + 31] = 0x14f0,
3284 [VFTA_A ... VFTA_A + 127] = 0x1400,
3285 [RDBAL0_A ... RDLEN0_A] = 0x09bc,
3286 [TDBAL_A ... TDLEN_A] = 0x0cf8,
3287 /* Access options */
3288 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL,
3289 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL,
3290 [RDFPC] = MAC_ACCESS_PARTIAL,
3291 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL,
3292 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL,
3293 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL,
3294 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL,
3295 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL,
3296 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL,
3297 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL,
3298 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL,
3299 [TXDCTL1] = MAC_ACCESS_PARTIAL,
3300 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL
3301 };
3302
3303 void
3304 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size)
3305 {
3306 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3307
3308 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) {
3309 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3310 trace_e1000e_wrn_regs_write_trivial(index << 2);
3311 }
3312 trace_e1000e_core_write(index << 2, size, val);
3313 e1000e_macreg_writeops[index](core, index, val);
3314 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3315 trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3316 } else {
3317 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3318 }
3319 }
3320
3321 uint64_t
3322 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size)
3323 {
3324 uint64_t val;
3325 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3326
3327 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3328 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3329 trace_e1000e_wrn_regs_read_trivial(index << 2);
3330 }
3331 val = e1000e_macreg_readops[index](core, index);
3332 trace_e1000e_core_read(index << 2, size, val);
3333 return val;
3334 } else {
3335 trace_e1000e_wrn_regs_read_unknown(index << 2, size);
3336 }
3337 return 0;
3338 }
3339
3340 static inline void
3341 e1000e_autoneg_pause(E1000ECore *core)
3342 {
3343 timer_del(core->autoneg_timer);
3344 }
3345
3346 static void
3347 e1000e_autoneg_resume(E1000ECore *core)
3348 {
3349 if (e1000e_have_autoneg(core) &&
3350 !(core->phy[0][PHY_STATUS] & MII_SR_AUTONEG_COMPLETE)) {
3351 qemu_get_queue(core->owner_nic)->link_down = false;
3352 timer_mod(core->autoneg_timer,
3353 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
3354 }
3355 }
3356
3357 static void
3358 e1000e_vm_state_change(void *opaque, bool running, RunState state)
3359 {
3360 E1000ECore *core = opaque;
3361
3362 if (running) {
3363 trace_e1000e_vm_state_running();
3364 e1000e_intrmgr_resume(core);
3365 e1000e_autoneg_resume(core);
3366 } else {
3367 trace_e1000e_vm_state_stopped();
3368 e1000e_autoneg_pause(core);
3369 e1000e_intrmgr_pause(core);
3370 }
3371 }
3372
3373 void
3374 e1000e_core_pci_realize(E1000ECore *core,
3375 const uint16_t *eeprom_templ,
3376 uint32_t eeprom_size,
3377 const uint8_t *macaddr)
3378 {
3379 int i;
3380
3381 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3382 e1000e_autoneg_timer, core);
3383 e1000e_intrmgr_pci_realize(core);
3384
3385 core->vmstate =
3386 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core);
3387
3388 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3389 net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner,
3390 E1000E_MAX_TX_FRAGS, core->has_vnet);
3391 }
3392
3393 net_rx_pkt_init(&core->rx_pkt, core->has_vnet);
3394
3395 e1000x_core_prepare_eeprom(core->eeprom,
3396 eeprom_templ,
3397 eeprom_size,
3398 PCI_DEVICE_GET_CLASS(core->owner)->device_id,
3399 macaddr);
3400 e1000e_update_rx_offloads(core);
3401 }
3402
3403 void
3404 e1000e_core_pci_uninit(E1000ECore *core)
3405 {
3406 int i;
3407
3408 timer_free(core->autoneg_timer);
3409
3410 e1000e_intrmgr_pci_unint(core);
3411
3412 qemu_del_vm_change_state_handler(core->vmstate);
3413
3414 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3415 net_tx_pkt_reset(core->tx[i].tx_pkt);
3416 net_tx_pkt_uninit(core->tx[i].tx_pkt);
3417 }
3418
3419 net_rx_pkt_uninit(core->rx_pkt);
3420 }
3421
3422 static const uint16_t
3423 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {
3424 [0] = {
3425 [PHY_CTRL] = MII_CR_SPEED_SELECT_MSB |
3426 MII_CR_FULL_DUPLEX |
3427 MII_CR_AUTO_NEG_EN,
3428
3429 [PHY_STATUS] = MII_SR_EXTENDED_CAPS |
3430 MII_SR_LINK_STATUS |
3431 MII_SR_AUTONEG_CAPS |
3432 MII_SR_PREAMBLE_SUPPRESS |
3433 MII_SR_EXTENDED_STATUS |
3434 MII_SR_10T_HD_CAPS |
3435 MII_SR_10T_FD_CAPS |
3436 MII_SR_100X_HD_CAPS |
3437 MII_SR_100X_FD_CAPS,
3438
3439 [PHY_ID1] = 0x141,
3440 [PHY_ID2] = E1000_PHY_ID2_82574x,
3441 [PHY_AUTONEG_ADV] = 0xde1,
3442 [PHY_LP_ABILITY] = 0x7e0,
3443 [PHY_AUTONEG_EXP] = BIT(2),
3444 [PHY_NEXT_PAGE_TX] = BIT(0) | BIT(13),
3445 [PHY_1000T_CTRL] = BIT(8) | BIT(9) | BIT(10) | BIT(11),
3446 [PHY_1000T_STATUS] = 0x3c00,
3447 [PHY_EXT_STATUS] = BIT(12) | BIT(13),
3448
3449 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) |
3450 BIT(12) | BIT(13),
3451 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15)
3452 },
3453 [2] = {
3454 [PHY_MAC_CTRL1] = BIT(3) | BIT(7),
3455 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12)
3456 },
3457 [3] = {
3458 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14)
3459 }
3460 };
3461
3462 static const uint32_t e1000e_mac_reg_init[] = {
3463 [PBA] = 0x00140014,
3464 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18),
3465 [EXTCNF_CTRL] = BIT(3),
3466 [EEMNGCTL] = BIT(31),
3467 [FLASHT] = 0x2,
3468 [FLSWCTL] = BIT(30) | BIT(31),
3469 [FLOL] = BIT(0),
3470 [RXDCTL] = BIT(16),
3471 [RXDCTL1] = BIT(16),
3472 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20),
3473 [RXCFGL] = 0x88F7,
3474 [RXUDP] = 0x319,
3475 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
3476 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU |
3477 E1000_CTRL_ADVD3WUC,
3478 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU,
3479 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) |
3480 (4 << E1000_PSRCTL_BSIZE1_SHIFT) |
3481 (4 << E1000_PSRCTL_BSIZE2_SHIFT),
3482 [TARC0] = 0x3 | E1000_TARC_ENABLE,
3483 [TARC1] = 0x3 | E1000_TARC_ENABLE,
3484 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES,
3485 [EERD] = E1000_EERW_DONE,
3486 [EEWR] = E1000_EERW_DONE,
3487 [GCR] = E1000_L0S_ADJUST |
3488 E1000_L1_ENTRY_LATENCY_MSB |
3489 E1000_L1_ENTRY_LATENCY_LSB,
3490 [TDFH] = 0x600,
3491 [TDFT] = 0x600,
3492 [TDFHS] = 0x600,
3493 [TDFTS] = 0x600,
3494 [POEMB] = 0x30D,
3495 [PBS] = 0x028,
3496 [MANC] = E1000_MANC_DIS_IP_CHK_ARP,
3497 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000,
3498 [SWSM] = 1,
3499 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD,
3500 [ITR] = E1000E_MIN_XITR,
3501 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR,
3502 };
3503
3504 void
3505 e1000e_core_reset(E1000ECore *core)
3506 {
3507 int i;
3508
3509 timer_del(core->autoneg_timer);
3510
3511 e1000e_intrmgr_reset(core);
3512
3513 memset(core->phy, 0, sizeof core->phy);
3514 memmove(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init);
3515 memset(core->mac, 0, sizeof core->mac);
3516 memmove(core->mac, e1000e_mac_reg_init, sizeof e1000e_mac_reg_init);
3517
3518 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT;
3519
3520 if (qemu_get_queue(core->owner_nic)->link_down) {
3521 e1000e_link_down(core);
3522 }
3523
3524 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
3525
3526 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3527 net_tx_pkt_reset(core->tx[i].tx_pkt);
3528 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props));
3529 core->tx[i].skip_cp = false;
3530 }
3531 }
3532
3533 void e1000e_core_pre_save(E1000ECore *core)
3534 {
3535 int i;
3536 NetClientState *nc = qemu_get_queue(core->owner_nic);
3537
3538 /*
3539 * If link is down and auto-negotiation is supported and ongoing,
3540 * complete auto-negotiation immediately. This allows us to look
3541 * at MII_SR_AUTONEG_COMPLETE to infer link status on load.
3542 */
3543 if (nc->link_down && e1000e_have_autoneg(core)) {
3544 core->phy[0][PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE;
3545 e1000e_update_flowctl_status(core);
3546 }
3547
3548 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3549 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) {
3550 core->tx[i].skip_cp = true;
3551 }
3552 }
3553 }
3554
3555 int
3556 e1000e_core_post_load(E1000ECore *core)
3557 {
3558 NetClientState *nc = qemu_get_queue(core->owner_nic);
3559
3560 /* nc.link_down can't be migrated, so infer link_down according
3561 * to link status bit in core.mac[STATUS].
3562 */
3563 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
3564
3565 return 0;
3566 }
QEmu