tcg/arm: optimize register allocation order
[qemu.git] / poison.h
blobd7db7f43b6804bbc36f52bd8197d590bea60f813
1 /* Poison identifiers that should not be used when building
2 target independent device code. */
4 #ifndef HW_POISON_H
5 #define HW_POISON_H
6 #ifdef __GNUC__
8 #pragma GCC poison TARGET_I386
9 #pragma GCC poison TARGET_X86_64
10 #pragma GCC poison TARGET_ALPHA
11 #pragma GCC poison TARGET_ARM
12 #pragma GCC poison TARGET_CRIS
13 #pragma GCC poison TARGET_M68K
14 #pragma GCC poison TARGET_MIPS
15 #pragma GCC poison TARGET_MIPS64
16 #pragma GCC poison TARGET_PPC
17 #pragma GCC poison TARGET_PPCEMB
18 #pragma GCC poison TARGET_PPC64
19 #pragma GCC poison TARGET_ABI32
20 #pragma GCC poison TARGET_SH4
21 #pragma GCC poison TARGET_SPARC
22 #pragma GCC poison TARGET_SPARC64
24 #pragma GCC poison TARGET_WORDS_BIGENDIAN
25 #pragma GCC poison BSWAP_NEEDED
27 #pragma GCC poison TARGET_LONG_BITS
28 #pragma GCC poison TARGET_FMT_lx
29 #pragma GCC poison TARGET_FMT_ld
31 #pragma GCC poison TARGET_PAGE_SIZE
32 #pragma GCC poison TARGET_PAGE_MASK
33 #pragma GCC poison TARGET_PAGE_BITS
34 #pragma GCC poison TARGET_PAGE_ALIGN
36 #pragma GCC poison CPUState
37 #pragma GCC poison env
39 #pragma GCC poison CPU_INTERRUPT_HARD
40 #pragma GCC poison CPU_INTERRUPT_EXITTB
41 #pragma GCC poison CPU_INTERRUPT_TIMER
42 #pragma GCC poison CPU_INTERRUPT_FIQ
43 #pragma GCC poison CPU_INTERRUPT_HALT
44 #pragma GCC poison CPU_INTERRUPT_SMI
45 #pragma GCC poison CPU_INTERRUPT_DEBUG
46 #pragma GCC poison CPU_INTERRUPT_VIRQ
47 #pragma GCC poison CPU_INTERRUPT_NMI
49 #endif
50 #endif