| commit | 914ccf51b07af860021863e0f8e46eac9ffbcb68 | |
| author | Aurelien Jarno <aurelien@aurel32.net> | |
| Fri, 9 Apr 2010 18:52:48 +0000 (9 20:52 +0200) | ||
| committer | Aurelien Jarno <aurelien@aurel32.net> | |
| Mon, 19 Apr 2010 05:03:06 +0000 (19 07:03 +0200) | ||
| tree | a879811d8bc42a82063741d8c1817347bd6d559a | treesnapshot (tar.gz zip) |
| parent | bf5675efe33888fe058210be98259a34faf4d4e5 | commitdiff |
tcg/arm: optimize register allocation order
The beginning of the register allocation order list on the TCG arm
target matches the list of clobbered registers. This means that when an
helper is called, there is almost always clobbered registers that have
to be spilled.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The beginning of the register allocation order list on the TCG arm
target matches the list of clobbered registers. This means that when an
helper is called, there is almost always clobbered registers that have
to be spilled.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| tcg/arm/tcg-target.c | diffblobblamehistory |