target/openrisc/sys_helper.c

   1 /*
   2  * OpenRISC system instructions helper routines
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *                         Zhizhou Zhang <etouzh@gmail.com>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "exec/exec-all.h"
  24 #include "exec/helper-proto.h"
  25 #include "exception.h"
  26 #include "sysemu/sysemu.h"
  27
  28 #define TO_SPR(group, number) (((group) << 11) + (number))
  29
  30 void HELPER(mtspr)(CPUOpenRISCState *env,
  31                    target_ulong ra, target_ulong rb, target_ulong offset)
  32 {
  33 #ifndef CONFIG_USER_ONLY
  34     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
  35     CPUState *cs = CPU(cpu);
  36     int spr = (ra | offset);
  37     int idx;
  38
  39     switch (spr) {
  40     case TO_SPR(0, 0): /* VR */
  41         env->vr = rb;
  42         break;
  43
  44     case TO_SPR(0, 11): /* EVBAR */
  45         env->evbar = rb;
  46         break;
  47
  48     case TO_SPR(0, 16): /* NPC */
  49         cpu_restore_state(cs, GETPC(), true);
  50         /* ??? Mirror or1ksim in not trashing delayed branch state
  51            when "jumping" to the current instruction.  */
  52         if (env->pc != rb) {
  53             env->pc = rb;
  54             env->dflag = 0;
  55             cpu_loop_exit(cs);
  56         }
  57         break;
  58
  59     case TO_SPR(0, 17): /* SR */
  60         if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
  61             (rb & (SR_IME | SR_DME | SR_SM))) {
  62             tlb_flush(cs);
  63         }
  64         cpu_set_sr(env, rb);
  65         if (env->sr & SR_DME) {
  66             env->tlb->cpu_openrisc_map_address_data =
  67                 &cpu_openrisc_get_phys_data;
  68         } else {
  69             env->tlb->cpu_openrisc_map_address_data =
  70                 &cpu_openrisc_get_phys_nommu;
  71         }
  72
  73         if (env->sr & SR_IME) {
  74             env->tlb->cpu_openrisc_map_address_code =
  75                 &cpu_openrisc_get_phys_code;
  76         } else {
  77             env->tlb->cpu_openrisc_map_address_code =
  78                 &cpu_openrisc_get_phys_nommu;
  79         }
  80         break;
  81
  82     case TO_SPR(0, 18): /* PPC */
  83         env->ppc = rb;
  84         break;
  85
  86     case TO_SPR(0, 32): /* EPCR */
  87         env->epcr = rb;
  88         break;
  89
  90     case TO_SPR(0, 48): /* EEAR */
  91         env->eear = rb;
  92         break;
  93
  94     case TO_SPR(0, 64): /* ESR */
  95         env->esr = rb;
  96         break;
  97
  98     case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
  99         idx = (spr - 1024);
 100         env->shadow_gpr[idx / 32][idx % 32] = rb;
 101
 102     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
 103         idx = spr - TO_SPR(1, 512);
 104         if (!(rb & 1)) {
 105             tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
 106         }
 107         env->tlb->dtlb[0][idx].mr = rb;
 108         break;
 109
 110     case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
 111         idx = spr - TO_SPR(1, 640);
 112         env->tlb->dtlb[0][idx].tr = rb;
 113         break;
 114     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
 115     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
 116     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
 117     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 118     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 119     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 120         break;
 121     case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1):   /* ITLBW0MR 0-127 */
 122         idx = spr - TO_SPR(2, 512);
 123         if (!(rb & 1)) {
 124             tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
 125         }
 126         env->tlb->itlb[0][idx].mr = rb;
 127         break;
 128
 129     case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
 130         idx = spr - TO_SPR(2, 640);
 131         env->tlb->itlb[0][idx].tr = rb;
 132         break;
 133     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 134     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 135     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 136     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 137     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 138     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 139         break;
 140     case TO_SPR(5, 1):  /* MACLO */
 141         env->mac = deposit64(env->mac, 0, 32, rb);
 142         break;
 143     case TO_SPR(5, 2):  /* MACHI */
 144         env->mac = deposit64(env->mac, 32, 32, rb);
 145         break;
 146     case TO_SPR(8, 0):  /* PMR */
 147         env->pmr = rb;
 148         if (env->pmr & PMR_DME || env->pmr & PMR_SME) {
 149             cpu_restore_state(cs, GETPC(), true);
 150             env->pc += 4;
 151             cs->halted = 1;
 152             raise_exception(cpu, EXCP_HALTED);
 153         }
 154         break;
 155     case TO_SPR(9, 0):  /* PICMR */
 156         env->picmr |= rb;
 157         break;
 158     case TO_SPR(9, 2):  /* PICSR */
 159         env->picsr &= ~rb;
 160         break;
 161     case TO_SPR(10, 0): /* TTMR */
 162         {
 163             if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
 164                 switch (rb & TTMR_M) {
 165                 case TIMER_NONE:
 166                     cpu_openrisc_count_stop(cpu);
 167                     break;
 168                 case TIMER_INTR:
 169                 case TIMER_SHOT:
 170                 case TIMER_CONT:
 171                     cpu_openrisc_count_start(cpu);
 172                     break;
 173                 default:
 174                     break;
 175                 }
 176             }
 177
 178             int ip = env->ttmr & TTMR_IP;
 179
 180             if (rb & TTMR_IP) {    /* Keep IP bit.  */
 181                 env->ttmr = (rb & ~TTMR_IP) | ip;
 182             } else {    /* Clear IP bit.  */
 183                 env->ttmr = rb & ~TTMR_IP;
 184                 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 185             }
 186
 187             cpu_openrisc_timer_update(cpu);
 188         }
 189         break;
 190
 191     case TO_SPR(10, 1): /* TTCR */
 192         cpu_openrisc_count_set(cpu, rb);
 193         if (env->ttmr & TIMER_NONE) {
 194             return;
 195         }
 196         cpu_openrisc_timer_update(cpu);
 197         break;
 198     default:
 199         break;
 200     }
 201 #endif
 202 }
 203
 204 target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
 205                            target_ulong rd, target_ulong ra, uint32_t offset)
 206 {
 207 #ifndef CONFIG_USER_ONLY
 208     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
 209     CPUState *cs = CPU(cpu);
 210     int spr = (ra | offset);
 211     int idx;
 212
 213     switch (spr) {
 214     case TO_SPR(0, 0): /* VR */
 215         return env->vr & SPR_VR;
 216
 217     case TO_SPR(0, 1): /* UPR */
 218         return env->upr;    /* TT, DM, IM, UP present */
 219
 220     case TO_SPR(0, 2): /* CPUCFGR */
 221         return env->cpucfgr;
 222
 223     case TO_SPR(0, 3): /* DMMUCFGR */
 224         return env->dmmucfgr;    /* 1Way, 64 entries */
 225
 226     case TO_SPR(0, 4): /* IMMUCFGR */
 227         return env->immucfgr;
 228
 229     case TO_SPR(0, 11): /* EVBAR */
 230         return env->evbar;
 231
 232     case TO_SPR(0, 16): /* NPC (equals PC) */
 233         cpu_restore_state(cs, GETPC(), false);
 234         return env->pc;
 235
 236     case TO_SPR(0, 17): /* SR */
 237         return cpu_get_sr(env);
 238
 239     case TO_SPR(0, 18): /* PPC */
 240         cpu_restore_state(cs, GETPC(), false);
 241         return env->ppc;
 242
 243     case TO_SPR(0, 32): /* EPCR */
 244         return env->epcr;
 245
 246     case TO_SPR(0, 48): /* EEAR */
 247         return env->eear;
 248
 249     case TO_SPR(0, 64): /* ESR */
 250         return env->esr;
 251
 252     case TO_SPR(0, 128): /* COREID */
 253         return cpu->parent_obj.cpu_index;
 254
 255     case TO_SPR(0, 129): /* NUMCORES */
 256         return max_cpus;
 257
 258     case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
 259         idx = (spr - 1024);
 260         return env->shadow_gpr[idx / 32][idx % 32];
 261
 262     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
 263         idx = spr - TO_SPR(1, 512);
 264         return env->tlb->dtlb[0][idx].mr;
 265
 266     case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
 267         idx = spr - TO_SPR(1, 640);
 268         return env->tlb->dtlb[0][idx].tr;
 269
 270     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
 271     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
 272     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
 273     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 274     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 275     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 276         break;
 277
 278     case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
 279         idx = spr - TO_SPR(2, 512);
 280         return env->tlb->itlb[0][idx].mr;
 281
 282     case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
 283         idx = spr - TO_SPR(2, 640);
 284         return env->tlb->itlb[0][idx].tr;
 285
 286     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 287     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 288     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 289     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 290     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 291     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 292         break;
 293
 294     case TO_SPR(5, 1):  /* MACLO */
 295         return (uint32_t)env->mac;
 296         break;
 297     case TO_SPR(5, 2):  /* MACHI */
 298         return env->mac >> 32;
 299         break;
 300
 301     case TO_SPR(8, 0):  /* PMR */
 302         return env->pmr;
 303
 304     case TO_SPR(9, 0):  /* PICMR */
 305         return env->picmr;
 306
 307     case TO_SPR(9, 2):  /* PICSR */
 308         return env->picsr;
 309
 310     case TO_SPR(10, 0): /* TTMR */
 311         return env->ttmr;
 312
 313     case TO_SPR(10, 1): /* TTCR */
 314         cpu_openrisc_count_update(cpu);
 315         return cpu_openrisc_count_get(cpu);
 316
 317     default:
 318         break;
 319     }
 320 #endif
 321
 322     /* for rd is passed in, if rd unchanged, just keep it back.  */
 323     return rd;
 324 }