2 * OpenRISC system instructions helper routines
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Zhizhou Zhang <etouzh@gmail.com>
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25 #include "exception.h"
26 #ifndef CONFIG_USER_ONLY
27 #include "hw/boards.h"
30 #define TO_SPR(group, number) (((group) << 11) + (number))
32 void HELPER(mtspr
)(CPUOpenRISCState
*env
, target_ulong spr
, target_ulong rb
)
34 #ifndef CONFIG_USER_ONLY
35 OpenRISCCPU
*cpu
= env_archcpu(env
);
36 CPUState
*cs
= env_cpu(env
);
42 #ifndef CONFIG_USER_ONLY
43 case TO_SPR(0, 11): /* EVBAR */
47 case TO_SPR(0, 16): /* NPC */
48 cpu_restore_state(cs
, GETPC());
49 /* ??? Mirror or1ksim in not trashing delayed branch state
50 when "jumping" to the current instruction. */
58 case TO_SPR(0, 17): /* SR */
62 case TO_SPR(0, 32): /* EPCR */
66 case TO_SPR(0, 48): /* EEAR */
70 case TO_SPR(0, 64): /* ESR */
74 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
76 env
->shadow_gpr
[idx
/ 32][idx
% 32] = rb
;
79 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE
- 1): /* DTLBW0MR 0-127 */
80 idx
= spr
- TO_SPR(1, 512);
81 mr
= env
->tlb
.dtlb
[idx
].mr
;
83 tlb_flush_page(cs
, mr
& TARGET_PAGE_MASK
);
86 tlb_flush_page(cs
, rb
& TARGET_PAGE_MASK
);
88 env
->tlb
.dtlb
[idx
].mr
= rb
;
90 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE
- 1): /* DTLBW0TR 0-127 */
91 idx
= spr
- TO_SPR(1, 640);
92 env
->tlb
.dtlb
[idx
].tr
= rb
;
94 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
95 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
96 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
97 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
98 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
99 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
102 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE
- 1): /* ITLBW0MR 0-127 */
103 idx
= spr
- TO_SPR(2, 512);
104 mr
= env
->tlb
.itlb
[idx
].mr
;
106 tlb_flush_page(cs
, mr
& TARGET_PAGE_MASK
);
109 tlb_flush_page(cs
, rb
& TARGET_PAGE_MASK
);
111 env
->tlb
.itlb
[idx
].mr
= rb
;
113 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE
- 1): /* ITLBW0TR 0-127 */
114 idx
= spr
- TO_SPR(2, 640);
115 env
->tlb
.itlb
[idx
].tr
= rb
;
117 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
118 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
119 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
120 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
121 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
122 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
125 case TO_SPR(5, 1): /* MACLO */
126 env
->mac
= deposit64(env
->mac
, 0, 32, rb
);
128 case TO_SPR(5, 2): /* MACHI */
129 env
->mac
= deposit64(env
->mac
, 32, 32, rb
);
131 case TO_SPR(8, 0): /* PMR */
133 if (env
->pmr
& PMR_DME
|| env
->pmr
& PMR_SME
) {
134 cpu_restore_state(cs
, GETPC());
137 raise_exception(cpu
, EXCP_HALTED
);
140 case TO_SPR(9, 0): /* PICMR */
142 qemu_mutex_lock_iothread();
143 if (env
->picsr
& env
->picmr
) {
144 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
146 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
148 qemu_mutex_unlock_iothread();
150 case TO_SPR(9, 2): /* PICSR */
153 case TO_SPR(10, 0): /* TTMR */
155 qemu_mutex_lock_iothread();
156 if ((env
->ttmr
& TTMR_M
) ^ (rb
& TTMR_M
)) {
157 switch (rb
& TTMR_M
) {
159 cpu_openrisc_count_stop(cpu
);
164 cpu_openrisc_count_start(cpu
);
171 int ip
= env
->ttmr
& TTMR_IP
;
173 if (rb
& TTMR_IP
) { /* Keep IP bit. */
174 env
->ttmr
= (rb
& ~TTMR_IP
) | ip
;
175 } else { /* Clear IP bit. */
176 env
->ttmr
= rb
& ~TTMR_IP
;
177 cs
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
179 cpu_openrisc_timer_update(cpu
);
180 qemu_mutex_unlock_iothread();
184 case TO_SPR(10, 1): /* TTCR */
185 qemu_mutex_lock_iothread();
186 cpu_openrisc_count_set(cpu
, rb
);
187 cpu_openrisc_timer_update(cpu
);
188 qemu_mutex_unlock_iothread();
192 case TO_SPR(0, 20): /* FPCSR */
193 cpu_set_fpcsr(env
, rb
);
198 target_ulong
HELPER(mfspr
)(CPUOpenRISCState
*env
, target_ulong rd
,
201 #ifndef CONFIG_USER_ONLY
202 uint64_t data
[TARGET_INSN_START_WORDS
];
203 MachineState
*ms
= MACHINE(qdev_get_machine());
204 OpenRISCCPU
*cpu
= env_archcpu(env
);
205 CPUState
*cs
= env_cpu(env
);
210 #ifndef CONFIG_USER_ONLY
211 case TO_SPR(0, 0): /* VR */
214 case TO_SPR(0, 1): /* UPR */
217 case TO_SPR(0, 2): /* CPUCFGR */
220 case TO_SPR(0, 3): /* DMMUCFGR */
221 return env
->dmmucfgr
;
223 case TO_SPR(0, 4): /* IMMUCFGR */
224 return env
->immucfgr
;
226 case TO_SPR(0, 9): /* VR2 */
229 case TO_SPR(0, 10): /* AVR */
232 case TO_SPR(0, 11): /* EVBAR */
235 case TO_SPR(0, 16): /* NPC (equals PC) */
236 if (cpu_unwind_state_data(cs
, GETPC(), data
)) {
241 case TO_SPR(0, 17): /* SR */
242 return cpu_get_sr(env
);
244 case TO_SPR(0, 18): /* PPC */
245 if (cpu_unwind_state_data(cs
, GETPC(), data
)) {
252 case TO_SPR(0, 32): /* EPCR */
255 case TO_SPR(0, 48): /* EEAR */
258 case TO_SPR(0, 64): /* ESR */
261 case TO_SPR(0, 128): /* COREID */
262 return cpu
->parent_obj
.cpu_index
;
264 case TO_SPR(0, 129): /* NUMCORES */
265 return ms
->smp
.max_cpus
;
267 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
269 return env
->shadow_gpr
[idx
/ 32][idx
% 32];
271 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE
- 1): /* DTLBW0MR 0-127 */
272 idx
= spr
- TO_SPR(1, 512);
273 return env
->tlb
.dtlb
[idx
].mr
;
275 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE
- 1): /* DTLBW0TR 0-127 */
276 idx
= spr
- TO_SPR(1, 640);
277 return env
->tlb
.dtlb
[idx
].tr
;
279 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
280 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
281 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
282 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
283 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
284 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
287 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE
- 1): /* ITLBW0MR 0-127 */
288 idx
= spr
- TO_SPR(2, 512);
289 return env
->tlb
.itlb
[idx
].mr
;
291 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE
- 1): /* ITLBW0TR 0-127 */
292 idx
= spr
- TO_SPR(2, 640);
293 return env
->tlb
.itlb
[idx
].tr
;
295 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
296 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
297 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
298 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
299 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
300 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
303 case TO_SPR(5, 1): /* MACLO */
304 return (uint32_t)env
->mac
;
306 case TO_SPR(5, 2): /* MACHI */
307 return env
->mac
>> 32;
310 case TO_SPR(8, 0): /* PMR */
313 case TO_SPR(9, 0): /* PICMR */
316 case TO_SPR(9, 2): /* PICSR */
319 case TO_SPR(10, 0): /* TTMR */
322 case TO_SPR(10, 1): /* TTCR */
323 qemu_mutex_lock_iothread();
324 cpu_openrisc_count_update(cpu
);
325 qemu_mutex_unlock_iothread();
326 return cpu_openrisc_count_get(cpu
);
329 case TO_SPR(0, 20): /* FPCSR */
333 /* for rd is passed in, if rd unchanged, just keep it back. */