target/hexagon/cpu.h

   1 /*
   2  *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_CPU_H
  19 #define HEXAGON_CPU_H
  20
  21 /* Forward declaration needed by some of the header files */
  22 typedef struct CPUHexagonState CPUHexagonState;
  23
  24 #include "fpu/softfloat-types.h"
  25
  26 #include "qemu-common.h"
  27 #include "exec/cpu-defs.h"
  28 #include "hex_regs.h"
  29 #include "mmvec/mmvec.h"
  30
  31 #define NUM_PREGS 4
  32 #define TOTAL_PER_THREAD_REGS 64
  33
  34 #define SLOTS_MAX 4
  35 #define STORES_MAX 2
  36 #define REG_WRITES_MAX 32
  37 #define PRED_WRITES_MAX 5                   /* 4 insns + endloop */
  38 #define VSTORES_MAX 2
  39
  40 #define TYPE_HEXAGON_CPU "hexagon-cpu"
  41
  42 #define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
  43 #define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
  44 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
  45
  46 #define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
  47
  48 #define MMU_USER_IDX 0
  49
  50 typedef struct {
  51     target_ulong va;
  52     uint8_t width;
  53     uint32_t data32;
  54     uint64_t data64;
  55 } MemLog;
  56
  57 typedef struct {
  58     target_ulong va;
  59     int size;
  60     DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16);
  61     MMVector data QEMU_ALIGNED(16);
  62 } VStoreLog;
  63
  64 #define EXEC_STATUS_OK          0x0000
  65 #define EXEC_STATUS_STOP        0x0002
  66 #define EXEC_STATUS_REPLAY      0x0010
  67 #define EXEC_STATUS_LOCKED      0x0020
  68 #define EXEC_STATUS_EXCEPTION   0x0100
  69
  70
  71 #define EXCEPTION_DETECTED      (env->status & EXEC_STATUS_EXCEPTION)
  72 #define REPLAY_DETECTED         (env->status & EXEC_STATUS_REPLAY)
  73 #define CLEAR_EXCEPTION         (env->status &= (~EXEC_STATUS_EXCEPTION))
  74 #define SET_EXCEPTION           (env->status |= EXEC_STATUS_EXCEPTION)
  75
  76 /* Maximum number of vector temps in a packet */
  77 #define VECTOR_TEMPS_MAX            4
  78
  79 struct CPUHexagonState {
  80     target_ulong gpr[TOTAL_PER_THREAD_REGS];
  81     target_ulong pred[NUM_PREGS];
  82     target_ulong branch_taken;
  83     target_ulong next_PC;
  84
  85     /* For comparing with LLDB on target - see adjust_stack_ptrs function */
  86     target_ulong last_pc_dumped;
  87     target_ulong stack_start;
  88
  89     uint8_t slot_cancelled;
  90     target_ulong new_value[TOTAL_PER_THREAD_REGS];
  91
  92     /*
  93      * Only used when HEX_DEBUG is on, but unconditionally included
  94      * to reduce recompile time when turning HEX_DEBUG on/off.
  95      */
  96     target_ulong this_PC;
  97     target_ulong reg_written[TOTAL_PER_THREAD_REGS];
  98
  99     target_ulong new_pred_value[NUM_PREGS];
 100     target_ulong pred_written;
 101
 102     MemLog mem_log_stores[STORES_MAX];
 103     target_ulong pkt_has_store_s1;
 104     target_ulong dczero_addr;
 105
 106     float_status fp_status;
 107
 108     target_ulong llsc_addr;
 109     target_ulong llsc_val;
 110     uint64_t     llsc_val_i64;
 111
 112     MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16);
 113     MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
 114     MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
 115
 116     VRegMask VRegs_updated;
 117
 118     MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16);
 119     MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16);
 120     QRegMask QRegs_updated;
 121
 122     /* Temporaries used within instructions */
 123     MMVectorPair VuuV QEMU_ALIGNED(16);
 124     MMVectorPair VvvV QEMU_ALIGNED(16);
 125     MMVectorPair VxxV QEMU_ALIGNED(16);
 126     MMVector     vtmp QEMU_ALIGNED(16);
 127     MMQReg       qtmp QEMU_ALIGNED(16);
 128
 129     VStoreLog vstore[VSTORES_MAX];
 130     target_ulong vstore_pending[VSTORES_MAX];
 131     bool vtcm_pending;
 132     VTCMStoreLog vtcm_log;
 133 };
 134
 135 #define HEXAGON_CPU_CLASS(klass) \
 136     OBJECT_CLASS_CHECK(HexagonCPUClass, (klass), TYPE_HEXAGON_CPU)
 137 #define HEXAGON_CPU(obj) \
 138     OBJECT_CHECK(HexagonCPU, (obj), TYPE_HEXAGON_CPU)
 139 #define HEXAGON_CPU_GET_CLASS(obj) \
 140     OBJECT_GET_CLASS(HexagonCPUClass, (obj), TYPE_HEXAGON_CPU)
 141
 142 typedef struct HexagonCPUClass {
 143     /*< private >*/
 144     CPUClass parent_class;
 145     /*< public >*/
 146     DeviceRealize parent_realize;
 147     DeviceReset parent_reset;
 148 } HexagonCPUClass;
 149
 150 typedef struct HexagonCPU {
 151     /*< private >*/
 152     CPUState parent_obj;
 153     /*< public >*/
 154     CPUNegativeOffsetState neg;
 155     CPUHexagonState env;
 156
 157     bool lldb_compat;
 158     target_ulong lldb_stack_adjust;
 159 } HexagonCPU;
 160
 161 #include "cpu_bits.h"
 162
 163 static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc,
 164                                         target_ulong *cs_base, uint32_t *flags)
 165 {
 166     *pc = env->gpr[HEX_REG_PC];
 167     *cs_base = 0;
 168 #ifdef CONFIG_USER_ONLY
 169     *flags = 0;
 170 #else
 171 #error System mode not supported on Hexagon yet
 172 #endif
 173 }
 174
 175 static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
 176 {
 177 #ifdef CONFIG_USER_ONLY
 178     return MMU_USER_IDX;
 179 #else
 180 #error System mode not supported on Hexagon yet
 181 #endif
 182 }
 183
 184 typedef struct CPUHexagonState CPUArchState;
 185 typedef HexagonCPU ArchCPU;
 186
 187 void hexagon_translate_init(void);
 188
 189 #include "exec/cpu-all.h"
 190
 191 #endif /* HEXAGON_CPU_H */