target/hexagon/cpu.h

   1 /*
   2  *  Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_CPU_H
  19 #define HEXAGON_CPU_H
  20
  21 #include "fpu/softfloat-types.h"
  22
  23 #include "exec/cpu-defs.h"
  24 #include "hex_regs.h"
  25 #include "mmvec/mmvec.h"
  26 #include "qom/object.h"
  27 #include "hw/core/cpu.h"
  28 #include "hw/registerfields.h"
  29
  30 #define NUM_PREGS 4
  31 #define TOTAL_PER_THREAD_REGS 64
  32
  33 #define SLOTS_MAX 4
  34 #define STORES_MAX 2
  35 #define REG_WRITES_MAX 32
  36 #define PRED_WRITES_MAX 5                   /* 4 insns + endloop */
  37 #define VSTORES_MAX 2
  38
  39 #define TYPE_HEXAGON_CPU "hexagon-cpu"
  40
  41 #define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
  42 #define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
  43 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
  44
  45 #define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
  46
  47 #define MMU_USER_IDX 0
  48
  49 typedef struct {
  50     target_ulong va;
  51     uint8_t width;
  52     uint32_t data32;
  53     uint64_t data64;
  54 } MemLog;
  55
  56 typedef struct {
  57     target_ulong va;
  58     int size;
  59     DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16);
  60     MMVector data QEMU_ALIGNED(16);
  61 } VStoreLog;
  62
  63 #define EXEC_STATUS_OK          0x0000
  64 #define EXEC_STATUS_STOP        0x0002
  65 #define EXEC_STATUS_REPLAY      0x0010
  66 #define EXEC_STATUS_LOCKED      0x0020
  67 #define EXEC_STATUS_EXCEPTION   0x0100
  68
  69
  70 #define EXCEPTION_DETECTED      (env->status & EXEC_STATUS_EXCEPTION)
  71 #define REPLAY_DETECTED         (env->status & EXEC_STATUS_REPLAY)
  72 #define CLEAR_EXCEPTION         (env->status &= (~EXEC_STATUS_EXCEPTION))
  73 #define SET_EXCEPTION           (env->status |= EXEC_STATUS_EXCEPTION)
  74
  75 /* Maximum number of vector temps in a packet */
  76 #define VECTOR_TEMPS_MAX            4
  77
  78 typedef struct CPUArchState {
  79     target_ulong gpr[TOTAL_PER_THREAD_REGS];
  80     target_ulong pred[NUM_PREGS];
  81     target_ulong branch_taken;
  82
  83     /* For comparing with LLDB on target - see adjust_stack_ptrs function */
  84     target_ulong last_pc_dumped;
  85     target_ulong stack_start;
  86
  87     uint8_t slot_cancelled;
  88     target_ulong new_value[TOTAL_PER_THREAD_REGS];
  89
  90     /*
  91      * Only used when HEX_DEBUG is on, but unconditionally included
  92      * to reduce recompile time when turning HEX_DEBUG on/off.
  93      */
  94     target_ulong this_PC;
  95     target_ulong reg_written[TOTAL_PER_THREAD_REGS];
  96
  97     target_ulong new_pred_value[NUM_PREGS];
  98     target_ulong pred_written;
  99
 100     MemLog mem_log_stores[STORES_MAX];
 101     target_ulong pkt_has_store_s1;
 102     target_ulong dczero_addr;
 103
 104     float_status fp_status;
 105
 106     target_ulong llsc_addr;
 107     target_ulong llsc_val;
 108     uint64_t     llsc_val_i64;
 109
 110     MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16);
 111     MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
 112     MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
 113
 114     VRegMask VRegs_updated;
 115
 116     MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16);
 117     MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16);
 118     QRegMask QRegs_updated;
 119
 120     /* Temporaries used within instructions */
 121     MMVectorPair VuuV QEMU_ALIGNED(16);
 122     MMVectorPair VvvV QEMU_ALIGNED(16);
 123     MMVectorPair VxxV QEMU_ALIGNED(16);
 124     MMVector     vtmp QEMU_ALIGNED(16);
 125     MMQReg       qtmp QEMU_ALIGNED(16);
 126
 127     VStoreLog vstore[VSTORES_MAX];
 128     target_ulong vstore_pending[VSTORES_MAX];
 129     bool vtcm_pending;
 130     VTCMStoreLog vtcm_log;
 131 } CPUHexagonState;
 132
 133 OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
 134
 135 typedef struct HexagonCPUClass {
 136     /*< private >*/
 137     CPUClass parent_class;
 138     /*< public >*/
 139     DeviceRealize parent_realize;
 140     ResettablePhases parent_phases;
 141 } HexagonCPUClass;
 142
 143 struct ArchCPU {
 144     /*< private >*/
 145     CPUState parent_obj;
 146     /*< public >*/
 147     CPUNegativeOffsetState neg;
 148     CPUHexagonState env;
 149
 150     bool lldb_compat;
 151     target_ulong lldb_stack_adjust;
 152 };
 153
 154 #include "cpu_bits.h"
 155
 156 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
 157
 158 static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc,
 159                                         target_ulong *cs_base, uint32_t *flags)
 160 {
 161     uint32_t hex_flags = 0;
 162     *pc = env->gpr[HEX_REG_PC];
 163     *cs_base = 0;
 164     if (*pc == env->gpr[HEX_REG_SA0]) {
 165         hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
 166     }
 167     *flags = hex_flags;
 168 }
 169
 170 static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
 171 {
 172 #ifdef CONFIG_USER_ONLY
 173     return MMU_USER_IDX;
 174 #else
 175 #error System mode not supported on Hexagon yet
 176 #endif
 177 }
 178
 179 typedef HexagonCPU ArchCPU;
 180
 181 void hexagon_translate_init(void);
 182
 183 #include "exec/cpu-all.h"
 184
 185 #endif /* HEXAGON_CPU_H */