target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)
[qemu.git] / hw / arm / allwinner-a10.c
blob01206f243c68c6e61ed2e10cc4fc2273b71ce1bf
1 /*
2 * Allwinner A10 SoC emulation
4 * Copyright (C) 2013 Li Guang
5 * Written by Li Guang <lig.fnst@cn.fujitsu.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
18 #include "hw/sysbus.h"
19 #include "hw/devices.h"
20 #include "hw/arm/allwinner-a10.h"
22 static void aw_a10_init(Object *obj)
24 AwA10State *s = AW_A10(obj);
26 object_initialize(&s->cpu, sizeof(s->cpu), "cortex-a8-" TYPE_ARM_CPU);
27 object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
29 object_initialize(&s->intc, sizeof(s->intc), TYPE_AW_A10_PIC);
30 qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default());
32 object_initialize(&s->timer, sizeof(s->timer), TYPE_AW_A10_PIT);
33 qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
35 object_initialize(&s->emac, sizeof(s->emac), TYPE_AW_EMAC);
36 qdev_set_parent_bus(DEVICE(&s->emac), sysbus_get_default());
37 if (nd_table[0].used) {
38 qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
39 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
43 static void aw_a10_realize(DeviceState *dev, Error **errp)
45 AwA10State *s = AW_A10(dev);
46 SysBusDevice *sysbusdev;
47 uint8_t i;
48 qemu_irq fiq, irq;
49 Error *err = NULL;
51 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
52 if (err != NULL) {
53 error_propagate(errp, err);
54 return;
56 irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
57 fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
59 object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
60 if (err != NULL) {
61 error_propagate(errp, err);
62 return;
64 sysbusdev = SYS_BUS_DEVICE(&s->intc);
65 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
66 sysbus_connect_irq(sysbusdev, 0, irq);
67 sysbus_connect_irq(sysbusdev, 1, fiq);
68 for (i = 0; i < AW_A10_PIC_INT_NR; i++) {
69 s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
72 object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
73 if (err != NULL) {
74 error_propagate(errp, err);
75 return;
77 sysbusdev = SYS_BUS_DEVICE(&s->timer);
78 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
79 sysbus_connect_irq(sysbusdev, 0, s->irq[22]);
80 sysbus_connect_irq(sysbusdev, 1, s->irq[23]);
81 sysbus_connect_irq(sysbusdev, 2, s->irq[24]);
82 sysbus_connect_irq(sysbusdev, 3, s->irq[25]);
83 sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
84 sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
86 object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
87 if (err != NULL) {
88 error_propagate(errp, err);
89 return;
91 sysbusdev = SYS_BUS_DEVICE(&s->emac);
92 sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
93 sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
95 serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
96 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
99 static void aw_a10_class_init(ObjectClass *oc, void *data)
101 DeviceClass *dc = DEVICE_CLASS(oc);
103 dc->realize = aw_a10_realize;
106 static const TypeInfo aw_a10_type_info = {
107 .name = TYPE_AW_A10,
108 .parent = TYPE_DEVICE,
109 .instance_size = sizeof(AwA10State),
110 .instance_init = aw_a10_init,
111 .class_init = aw_a10_class_init,
114 static void aw_a10_register_types(void)
116 type_register_static(&aw_a10_type_info);
119 type_init(aw_a10_register_types)