2 * Allwinner A10 SoC emulation
4 * Copyright (C) 2013 Li Guang
5 * Written by Li Guang <lig.fnst@cn.fujitsu.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu/module.h"
21 #include "hw/sysbus.h"
22 #include "hw/arm/allwinner-a10.h"
23 #include "hw/misc/unimp.h"
24 #include "sysemu/sysemu.h"
25 #include "hw/boards.h"
26 #include "hw/usb/hcd-ohci.h"
27 #include "hw/loader.h"
29 #define AW_A10_SRAM_A_BASE 0x00000000
30 #define AW_A10_DRAMC_BASE 0x01c01000
31 #define AW_A10_MMC0_BASE 0x01c0f000
32 #define AW_A10_CCM_BASE 0x01c20000
33 #define AW_A10_PIC_REG_BASE 0x01c20400
34 #define AW_A10_PIT_REG_BASE 0x01c20c00
35 #define AW_A10_UART0_REG_BASE 0x01c28000
36 #define AW_A10_EMAC_BASE 0x01c0b000
37 #define AW_A10_EHCI_BASE 0x01c14000
38 #define AW_A10_OHCI_BASE 0x01c14400
39 #define AW_A10_SATA_BASE 0x01c18000
40 #define AW_A10_RTC_BASE 0x01c20d00
41 #define AW_A10_I2C0_BASE 0x01c2ac00
43 void allwinner_a10_bootrom_setup(AwA10State
*s
, BlockBackend
*blk
)
45 const int64_t rom_size
= 32 * KiB
;
46 g_autofree
uint8_t *buffer
= g_new0(uint8_t, rom_size
);
48 if (blk_pread(blk
, 8 * KiB
, rom_size
, buffer
, 0) < 0) {
49 error_setg(&error_fatal
, "%s: failed to read BlockBackend data",
54 rom_add_blob("allwinner-a10.bootrom", buffer
, rom_size
,
55 rom_size
, AW_A10_SRAM_A_BASE
,
56 NULL
, NULL
, NULL
, NULL
, false);
59 static void aw_a10_init(Object
*obj
)
61 AwA10State
*s
= AW_A10(obj
);
63 object_initialize_child(obj
, "cpu", &s
->cpu
,
64 ARM_CPU_TYPE_NAME("cortex-a8"));
66 object_initialize_child(obj
, "intc", &s
->intc
, TYPE_AW_A10_PIC
);
68 object_initialize_child(obj
, "timer", &s
->timer
, TYPE_AW_A10_PIT
);
70 object_initialize_child(obj
, "ccm", &s
->ccm
, TYPE_AW_A10_CCM
);
72 object_initialize_child(obj
, "dramc", &s
->dramc
, TYPE_AW_A10_DRAMC
);
74 object_initialize_child(obj
, "emac", &s
->emac
, TYPE_AW_EMAC
);
76 object_initialize_child(obj
, "sata", &s
->sata
, TYPE_ALLWINNER_AHCI
);
78 object_initialize_child(obj
, "i2c0", &s
->i2c0
, TYPE_AW_I2C
);
80 if (machine_usb(current_machine
)) {
83 for (i
= 0; i
< AW_A10_NUM_USB
; i
++) {
84 object_initialize_child(obj
, "ehci[*]", &s
->ehci
[i
],
86 object_initialize_child(obj
, "ohci[*]", &s
->ohci
[i
],
91 object_initialize_child(obj
, "mmc0", &s
->mmc0
, TYPE_AW_SDHOST_SUN4I
);
93 object_initialize_child(obj
, "rtc", &s
->rtc
, TYPE_AW_RTC_SUN4I
);
96 static void aw_a10_realize(DeviceState
*dev
, Error
**errp
)
98 AwA10State
*s
= AW_A10(dev
);
99 SysBusDevice
*sysbusdev
;
101 if (!qdev_realize(DEVICE(&s
->cpu
), NULL
, errp
)) {
105 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->intc
), errp
)) {
108 sysbusdev
= SYS_BUS_DEVICE(&s
->intc
);
109 sysbus_mmio_map(sysbusdev
, 0, AW_A10_PIC_REG_BASE
);
110 sysbus_connect_irq(sysbusdev
, 0,
111 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_IRQ
));
112 sysbus_connect_irq(sysbusdev
, 1,
113 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_FIQ
));
114 qdev_pass_gpios(DEVICE(&s
->intc
), dev
, NULL
);
116 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->timer
), errp
)) {
119 sysbusdev
= SYS_BUS_DEVICE(&s
->timer
);
120 sysbus_mmio_map(sysbusdev
, 0, AW_A10_PIT_REG_BASE
);
121 sysbus_connect_irq(sysbusdev
, 0, qdev_get_gpio_in(dev
, 22));
122 sysbus_connect_irq(sysbusdev
, 1, qdev_get_gpio_in(dev
, 23));
123 sysbus_connect_irq(sysbusdev
, 2, qdev_get_gpio_in(dev
, 24));
124 sysbus_connect_irq(sysbusdev
, 3, qdev_get_gpio_in(dev
, 25));
125 sysbus_connect_irq(sysbusdev
, 4, qdev_get_gpio_in(dev
, 67));
126 sysbus_connect_irq(sysbusdev
, 5, qdev_get_gpio_in(dev
, 68));
128 memory_region_init_ram(&s
->sram_a
, OBJECT(dev
), "sram A", 48 * KiB
,
130 memory_region_add_subregion(get_system_memory(), 0x00000000, &s
->sram_a
);
131 create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB
);
133 /* Clock Control Module */
134 sysbus_realize(SYS_BUS_DEVICE(&s
->ccm
), &error_fatal
);
135 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ccm
), 0, AW_A10_CCM_BASE
);
137 /* DRAM Control Module */
138 sysbus_realize(SYS_BUS_DEVICE(&s
->dramc
), &error_fatal
);
139 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->dramc
), 0, AW_A10_DRAMC_BASE
);
141 /* FIXME use qdev NIC properties instead of nd_table[] */
142 if (nd_table
[0].used
) {
143 qemu_check_nic_model(&nd_table
[0], TYPE_AW_EMAC
);
144 qdev_set_nic_properties(DEVICE(&s
->emac
), &nd_table
[0]);
146 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->emac
), errp
)) {
149 sysbusdev
= SYS_BUS_DEVICE(&s
->emac
);
150 sysbus_mmio_map(sysbusdev
, 0, AW_A10_EMAC_BASE
);
151 sysbus_connect_irq(sysbusdev
, 0, qdev_get_gpio_in(dev
, 55));
153 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sata
), errp
)) {
156 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sata
), 0, AW_A10_SATA_BASE
);
157 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sata
), 0, qdev_get_gpio_in(dev
, 56));
159 /* FIXME use a qdev chardev prop instead of serial_hd() */
160 serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE
, 2,
161 qdev_get_gpio_in(dev
, 1),
162 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN
);
164 if (machine_usb(current_machine
)) {
167 for (i
= 0; i
< AW_A10_NUM_USB
; i
++) {
168 g_autofree
char *bus
= g_strdup_printf("usb-bus.%d", i
);
170 object_property_set_bool(OBJECT(&s
->ehci
[i
]), "companion-enable",
172 sysbus_realize(SYS_BUS_DEVICE(&s
->ehci
[i
]), &error_fatal
);
173 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ehci
[i
]), 0,
174 AW_A10_EHCI_BASE
+ i
* 0x8000);
175 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ehci
[i
]), 0,
176 qdev_get_gpio_in(dev
, 39 + i
));
178 object_property_set_str(OBJECT(&s
->ohci
[i
]), "masterbus", bus
,
180 sysbus_realize(SYS_BUS_DEVICE(&s
->ohci
[i
]), &error_fatal
);
181 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ohci
[i
]), 0,
182 AW_A10_OHCI_BASE
+ i
* 0x8000);
183 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ohci
[i
]), 0,
184 qdev_get_gpio_in(dev
, 64 + i
));
189 object_property_set_link(OBJECT(&s
->mmc0
), "dma-memory",
190 OBJECT(get_system_memory()), &error_fatal
);
191 sysbus_realize(SYS_BUS_DEVICE(&s
->mmc0
), &error_fatal
);
192 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->mmc0
), 0, AW_A10_MMC0_BASE
);
193 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->mmc0
), 0, qdev_get_gpio_in(dev
, 32));
194 object_property_add_alias(OBJECT(s
), "sd-bus", OBJECT(&s
->mmc0
),
198 sysbus_realize(SYS_BUS_DEVICE(&s
->rtc
), &error_fatal
);
199 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s
->rtc
), 0, AW_A10_RTC_BASE
, 10);
202 sysbus_realize(SYS_BUS_DEVICE(&s
->i2c0
), &error_fatal
);
203 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c0
), 0, AW_A10_I2C0_BASE
);
204 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c0
), 0, qdev_get_gpio_in(dev
, 7));
207 static void aw_a10_class_init(ObjectClass
*oc
, void *data
)
209 DeviceClass
*dc
= DEVICE_CLASS(oc
);
211 dc
->realize
= aw_a10_realize
;
212 /* Reason: Uses serial_hds and nd_table in realize function */
213 dc
->user_creatable
= false;
216 static const TypeInfo aw_a10_type_info
= {
218 .parent
= TYPE_DEVICE
,
219 .instance_size
= sizeof(AwA10State
),
220 .instance_init
= aw_a10_init
,
221 .class_init
= aw_a10_class_init
,
224 static void aw_a10_register_types(void)
226 type_register_static(&aw_a10_type_info
);
229 type_init(aw_a10_register_types
)